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authorKumar Gala <galak@kernel.crashing.org>2008-05-30 14:43:43 -0400
committerKumar Gala <galak@kernel.crashing.org>2008-06-02 15:44:25 -0400
commitc054065bc10a7ee2bcf78b5bc95f4b4d9bdc923a (patch)
tree023b60c1b55c04c2db08983a3aaef151d081fcac /arch/powerpc/boot/dts/mpc8568mds.dts
parentacd4b715ec83e451990bb82bdbf28ecaeab1b67d (diff)
[POWERPC] 85xx: Add next-level-cache property
Added next-level-cache to the L1 and a reference to the new L2 label. This is per the ePAPR 0.94 spec. Since we are't really dependent on this today we aren't supporting the "legacy" l2-cache phandle that is specified in the PPC v2.1 OF Binding spec. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/boot/dts/mpc8568mds.dts')
-rw-r--r--arch/powerpc/boot/dts/mpc8568mds.dts3
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/powerpc/boot/dts/mpc8568mds.dts b/arch/powerpc/boot/dts/mpc8568mds.dts
index d9064ee2d2d8..d7af8db1a22f 100644
--- a/arch/powerpc/boot/dts/mpc8568mds.dts
+++ b/arch/powerpc/boot/dts/mpc8568mds.dts
@@ -42,6 +42,7 @@
42 timebase-frequency = <0>; 42 timebase-frequency = <0>;
43 bus-frequency = <0>; 43 bus-frequency = <0>;
44 clock-frequency = <0>; 44 clock-frequency = <0>;
45 next-level-cache = <&L2>;
45 }; 46 };
46 }; 47 };
47 48
@@ -70,7 +71,7 @@
70 interrupts = <18 2>; 71 interrupts = <18 2>;
71 }; 72 };
72 73
73 l2-cache-controller@20000 { 74 L2: l2-cache-controller@20000 {
74 compatible = "fsl,8568-l2-cache-controller"; 75 compatible = "fsl,8568-l2-cache-controller";
75 reg = <0x20000 0x1000>; 76 reg = <0x20000 0x1000>;
76 cache-line-size = <32>; // 32 bytes 77 cache-line-size = <32>; // 32 bytes