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authorKumar Gala <galak@kernel.crashing.org>2007-07-03 03:35:35 -0400
committerKumar Gala <galak@kernel.crashing.org>2007-07-03 03:35:35 -0400
commitb533f8ae796d1ee0289bf04d4f1e72c02ad4a17d (patch)
tree4bec480194b251e18fee511df1cf4840a1995c88 /arch/powerpc/boot/dts/mpc8560ads.dts
parenteae98266e78e5659d75dbb62b4601960c15c7830 (diff)
[POWERPC] Reworked interrupt numbers for OpenPIC based Freescale chips
Make the interrupt numbers match the OpenPIC spec intead of the Freescale docs which distinguish between internal and external interrupts. Now we can use the interrupt number directly to find the register offset associated with it. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/boot/dts/mpc8560ads.dts')
-rw-r--r--arch/powerpc/boot/dts/mpc8560ads.dts116
1 files changed, 58 insertions, 58 deletions
diff --git a/arch/powerpc/boot/dts/mpc8560ads.dts b/arch/powerpc/boot/dts/mpc8560ads.dts
index 205ee3219ec6..2d41d549c213 100644
--- a/arch/powerpc/boot/dts/mpc8560ads.dts
+++ b/arch/powerpc/boot/dts/mpc8560ads.dts
@@ -52,7 +52,7 @@
52 compatible = "fsl,8540-memory-controller"; 52 compatible = "fsl,8540-memory-controller";
53 reg = <2000 1000>; 53 reg = <2000 1000>;
54 interrupt-parent = <&mpic>; 54 interrupt-parent = <&mpic>;
55 interrupts = <2 2>; 55 interrupts = <12 2>;
56 }; 56 };
57 57
58 l2-cache-controller@20000 { 58 l2-cache-controller@20000 {
@@ -61,7 +61,7 @@
61 cache-line-size = <20>; // 32 bytes 61 cache-line-size = <20>; // 32 bytes
62 cache-size = <40000>; // L2, 256K 62 cache-size = <40000>; // L2, 256K
63 interrupt-parent = <&mpic>; 63 interrupt-parent = <&mpic>;
64 interrupts = <0 2>; 64 interrupts = <10 2>;
65 }; 65 };
66 66
67 mdio@24520 { 67 mdio@24520 {
@@ -72,25 +72,25 @@
72 #size-cells = <0>; 72 #size-cells = <0>;
73 phy0: ethernet-phy@0 { 73 phy0: ethernet-phy@0 {
74 interrupt-parent = <&mpic>; 74 interrupt-parent = <&mpic>;
75 interrupts = <35 1>; 75 interrupts = <5 1>;
76 reg = <0>; 76 reg = <0>;
77 device_type = "ethernet-phy"; 77 device_type = "ethernet-phy";
78 }; 78 };
79 phy1: ethernet-phy@1 { 79 phy1: ethernet-phy@1 {
80 interrupt-parent = <&mpic>; 80 interrupt-parent = <&mpic>;
81 interrupts = <35 1>; 81 interrupts = <5 1>;
82 reg = <1>; 82 reg = <1>;
83 device_type = "ethernet-phy"; 83 device_type = "ethernet-phy";
84 }; 84 };
85 phy2: ethernet-phy@2 { 85 phy2: ethernet-phy@2 {
86 interrupt-parent = <&mpic>; 86 interrupt-parent = <&mpic>;
87 interrupts = <37 1>; 87 interrupts = <7 1>;
88 reg = <2>; 88 reg = <2>;
89 device_type = "ethernet-phy"; 89 device_type = "ethernet-phy";
90 }; 90 };
91 phy3: ethernet-phy@3 { 91 phy3: ethernet-phy@3 {
92 interrupt-parent = <&mpic>; 92 interrupt-parent = <&mpic>;
93 interrupts = <37 1>; 93 interrupts = <7 1>;
94 reg = <3>; 94 reg = <3>;
95 device_type = "ethernet-phy"; 95 device_type = "ethernet-phy";
96 }; 96 };
@@ -108,7 +108,7 @@
108 */ 108 */
109 address = [ 00 00 00 00 00 00 ]; 109 address = [ 00 00 00 00 00 00 ];
110 local-mac-address = [ 00 00 00 00 00 00 ]; 110 local-mac-address = [ 00 00 00 00 00 00 ];
111 interrupts = <d 2 e 2 12 2>; 111 interrupts = <1d 2 1e 2 22 2>;
112 interrupt-parent = <&mpic>; 112 interrupt-parent = <&mpic>;
113 phy-handle = <&phy0>; 113 phy-handle = <&phy0>;
114 }; 114 };
@@ -127,7 +127,7 @@
127 */ 127 */
128 address = [ 00 00 00 00 00 00 ]; 128 address = [ 00 00 00 00 00 00 ];
129 local-mac-address = [ 00 00 00 00 00 00 ]; 129 local-mac-address = [ 00 00 00 00 00 00 ];
130 interrupts = <13 2 14 2 18 2>; 130 interrupts = <23 2 24 2 28 2>;
131 interrupt-parent = <&mpic>; 131 interrupt-parent = <&mpic>;
132 phy-handle = <&phy1>; 132 phy-handle = <&phy1>;
133 }; 133 };
@@ -144,79 +144,79 @@
144 interrupt-map = < 144 interrupt-map = <
145 145
146 /* IDSEL 0x2 */ 146 /* IDSEL 0x2 */
147 1000 0 0 1 &mpic 31 1 147 1000 0 0 1 &mpic 1 1
148 1000 0 0 2 &mpic 32 1 148 1000 0 0 2 &mpic 2 1
149 1000 0 0 3 &mpic 33 1 149 1000 0 0 3 &mpic 3 1
150 1000 0 0 4 &mpic 34 1 150 1000 0 0 4 &mpic 4 1
151 151
152 /* IDSEL 0x3 */ 152 /* IDSEL 0x3 */
153 1800 0 0 1 &mpic 34 1 153 1800 0 0 1 &mpic 4 1
154 1800 0 0 2 &mpic 31 1 154 1800 0 0 2 &mpic 1 1
155 1800 0 0 3 &mpic 32 1 155 1800 0 0 3 &mpic 2 1
156 1800 0 0 4 &mpic 33 1 156 1800 0 0 4 &mpic 3 1
157 157
158 /* IDSEL 0x4 */ 158 /* IDSEL 0x4 */
159 2000 0 0 1 &mpic 33 1 159 2000 0 0 1 &mpic 3 1
160 2000 0 0 2 &mpic 34 1 160 2000 0 0 2 &mpic 4 1
161 2000 0 0 3 &mpic 31 1 161 2000 0 0 3 &mpic 1 1
162 2000 0 0 4 &mpic 32 1 162 2000 0 0 4 &mpic 2 1
163 163
164 /* IDSEL 0x5 */ 164 /* IDSEL 0x5 */
165 2800 0 0 1 &mpic 32 1 165 2800 0 0 1 &mpic 2 1
166 2800 0 0 2 &mpic 33 1 166 2800 0 0 2 &mpic 3 1
167 2800 0 0 3 &mpic 34 1 167 2800 0 0 3 &mpic 4 1
168 2800 0 0 4 &mpic 31 1 168 2800 0 0 4 &mpic 1 1
169 169
170 /* IDSEL 12 */ 170 /* IDSEL 12 */
171 6000 0 0 1 &mpic 31 1 171 6000 0 0 1 &mpic 1 1
172 6000 0 0 2 &mpic 32 1 172 6000 0 0 2 &mpic 2 1
173 6000 0 0 3 &mpic 33 1 173 6000 0 0 3 &mpic 3 1
174 6000 0 0 4 &mpic 34 1 174 6000 0 0 4 &mpic 4 1
175 175
176 /* IDSEL 13 */ 176 /* IDSEL 13 */
177 6800 0 0 1 &mpic 34 1 177 6800 0 0 1 &mpic 4 1
178 6800 0 0 2 &mpic 31 1 178 6800 0 0 2 &mpic 1 1
179 6800 0 0 3 &mpic 32 1 179 6800 0 0 3 &mpic 2 1
180 6800 0 0 4 &mpic 33 1 180 6800 0 0 4 &mpic 3 1
181 181
182 /* IDSEL 14*/ 182 /* IDSEL 14*/
183 7000 0 0 1 &mpic 33 1 183 7000 0 0 1 &mpic 3 1
184 7000 0 0 2 &mpic 34 1 184 7000 0 0 2 &mpic 4 1
185 7000 0 0 3 &mpic 31 1 185 7000 0 0 3 &mpic 1 1
186 7000 0 0 4 &mpic 32 1 186 7000 0 0 4 &mpic 2 1
187 187
188 /* IDSEL 15 */ 188 /* IDSEL 15 */
189 7800 0 0 1 &mpic 32 1 189 7800 0 0 1 &mpic 2 1
190 7800 0 0 2 &mpic 33 1 190 7800 0 0 2 &mpic 3 1
191 7800 0 0 3 &mpic 34 1 191 7800 0 0 3 &mpic 4 1
192 7800 0 0 4 &mpic 31 1 192 7800 0 0 4 &mpic 1 1
193 193
194 /* IDSEL 18 */ 194 /* IDSEL 18 */
195 9000 0 0 1 &mpic 31 1 195 9000 0 0 1 &mpic 1 1
196 9000 0 0 2 &mpic 32 1 196 9000 0 0 2 &mpic 2 1
197 9000 0 0 3 &mpic 33 1 197 9000 0 0 3 &mpic 3 1
198 9000 0 0 4 &mpic 34 1 198 9000 0 0 4 &mpic 4 1
199 199
200 /* IDSEL 19 */ 200 /* IDSEL 19 */
201 9800 0 0 1 &mpic 34 1 201 9800 0 0 1 &mpic 4 1
202 9800 0 0 2 &mpic 31 1 202 9800 0 0 2 &mpic 1 1
203 9800 0 0 3 &mpic 32 1 203 9800 0 0 3 &mpic 2 1
204 9800 0 0 4 &mpic 33 1 204 9800 0 0 4 &mpic 3 1
205 205
206 /* IDSEL 20 */ 206 /* IDSEL 20 */
207 a000 0 0 1 &mpic 33 1 207 a000 0 0 1 &mpic 3 1
208 a000 0 0 2 &mpic 34 1 208 a000 0 0 2 &mpic 4 1
209 a000 0 0 3 &mpic 31 1 209 a000 0 0 3 &mpic 1 1
210 a000 0 0 4 &mpic 32 1 210 a000 0 0 4 &mpic 2 1
211 211
212 /* IDSEL 21 */ 212 /* IDSEL 21 */
213 a800 0 0 1 &mpic 32 1 213 a800 0 0 1 &mpic 2 1
214 a800 0 0 2 &mpic 33 1 214 a800 0 0 2 &mpic 3 1
215 a800 0 0 3 &mpic 34 1 215 a800 0 0 3 &mpic 4 1
216 a800 0 0 4 &mpic 31 1>; 216 a800 0 0 4 &mpic 1 1>;
217 217
218 interrupt-parent = <&mpic>; 218 interrupt-parent = <&mpic>;
219 interrupts = <8 0>; 219 interrupts = <18 0>;
220 bus-range = <0 0>; 220 bus-range = <0 0>;
221 ranges = <02000000 0 80000000 80000000 0 20000000 221 ranges = <02000000 0 80000000 80000000 0 20000000
222 01000000 0 00000000 e2000000 0 01000000>; 222 01000000 0 00000000 e2000000 0 01000000>;
@@ -246,7 +246,7 @@
246 interrupt-controller; 246 interrupt-controller;
247 #address-cells = <0>; 247 #address-cells = <0>;
248 #interrupt-cells = <2>; 248 #interrupt-cells = <2>;
249 interrupts = <1e 0>; 249 interrupts = <2e 0>;
250 interrupt-parent = <&mpic>; 250 interrupt-parent = <&mpic>;
251 reg = <90c00 80>; 251 reg = <90c00 80>;
252 built-in; 252 built-in;
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-24 00:37:21 -0500