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authorKumar Gala <galak@kernel.crashing.org>2007-09-12 19:23:46 -0400
committerKumar Gala <galak@kernel.crashing.org>2007-09-14 09:53:22 -0400
commit1b3c5cdab49a605f0e048e1ccbf4cc61a2626485 (patch)
treeb81e6642588b00a7dbb42611614e745517b6a6b9 /arch/powerpc/boot/dts/mpc8555cds.dts
parentf0c8ac8083cbd9347b398bfddcca20f1e2786016 (diff)
[POWERPC] Move PCI nodes to be sibilings with SOC nodes
Updated the device trees to have the PCI nodes be at the same level as the SOC node. This is to make it so that the SOC nodes children address space is just on chip registers and not other bus memory as well. Also, for PCIe nodes added a P2P bridge to handle the virtual P2P bridge that exists in the PHB. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/boot/dts/mpc8555cds.dts')
-rw-r--r--arch/powerpc/boot/dts/mpc8555cds.dts190
1 files changed, 95 insertions, 95 deletions
diff --git a/arch/powerpc/boot/dts/mpc8555cds.dts b/arch/powerpc/boot/dts/mpc8555cds.dts
index ce11d11293d0..99199295147e 100644
--- a/arch/powerpc/boot/dts/mpc8555cds.dts
+++ b/arch/powerpc/boot/dts/mpc8555cds.dts
@@ -43,7 +43,7 @@
43 #size-cells = <1>; 43 #size-cells = <1>;
44 device_type = "soc"; 44 device_type = "soc";
45 ranges = <0 e0000000 00100000>; 45 ranges = <0 e0000000 00100000>;
46 reg = <e0000000 00100000>; // CCSRBAR 1M 46 reg = <e0000000 00001000>; // CCSRBAR 1M
47 bus-frequency = <0>; 47 bus-frequency = <0>;
48 48
49 memory-controller@2000 { 49 memory-controller@2000 {
@@ -135,100 +135,6 @@
135 interrupt-parent = <&mpic>; 135 interrupt-parent = <&mpic>;
136 }; 136 };
137 137
138 pci1: pci@8000 {
139 interrupt-map-mask = <1f800 0 0 7>;
140 interrupt-map = <
141
142 /* IDSEL 0x10 */
143 08000 0 0 1 &mpic 0 1
144 08000 0 0 2 &mpic 1 1
145 08000 0 0 3 &mpic 2 1
146 08000 0 0 4 &mpic 3 1
147
148 /* IDSEL 0x11 */
149 08800 0 0 1 &mpic 0 1
150 08800 0 0 2 &mpic 1 1
151 08800 0 0 3 &mpic 2 1
152 08800 0 0 4 &mpic 3 1
153
154 /* IDSEL 0x12 (Slot 1) */
155 09000 0 0 1 &mpic 0 1
156 09000 0 0 2 &mpic 1 1
157 09000 0 0 3 &mpic 2 1
158 09000 0 0 4 &mpic 3 1
159
160 /* IDSEL 0x13 (Slot 2) */
161 09800 0 0 1 &mpic 1 1
162 09800 0 0 2 &mpic 2 1
163 09800 0 0 3 &mpic 3 1
164 09800 0 0 4 &mpic 0 1
165
166 /* IDSEL 0x14 (Slot 3) */
167 0a000 0 0 1 &mpic 2 1
168 0a000 0 0 2 &mpic 3 1
169 0a000 0 0 3 &mpic 0 1
170 0a000 0 0 4 &mpic 1 1
171
172 /* IDSEL 0x15 (Slot 4) */
173 0a800 0 0 1 &mpic 3 1
174 0a800 0 0 2 &mpic 0 1
175 0a800 0 0 3 &mpic 1 1
176 0a800 0 0 4 &mpic 2 1
177
178 /* Bus 1 (Tundra Bridge) */
179 /* IDSEL 0x12 (ISA bridge) */
180 19000 0 0 1 &mpic 0 1
181 19000 0 0 2 &mpic 1 1
182 19000 0 0 3 &mpic 2 1
183 19000 0 0 4 &mpic 3 1>;
184 interrupt-parent = <&mpic>;
185 interrupts = <18 2>;
186 bus-range = <0 0>;
187 ranges = <02000000 0 80000000 80000000 0 20000000
188 01000000 0 00000000 e2000000 0 00100000>;
189 clock-frequency = <3f940aa>;
190 #interrupt-cells = <1>;
191 #size-cells = <2>;
192 #address-cells = <3>;
193 reg = <8000 1000>;
194 compatible = "fsl,mpc8540-pci";
195 device_type = "pci";
196
197 i8259@19000 {
198 interrupt-controller;
199 device_type = "interrupt-controller";
200 reg = <19000 0 0 0 1>;
201 #address-cells = <0>;
202 #interrupt-cells = <2>;
203 compatible = "chrp,iic";
204 interrupts = <1>;
205 interrupt-parent = <&pci1>;
206 };
207 };
208
209 pci@9000 {
210 interrupt-map-mask = <f800 0 0 7>;
211 interrupt-map = <
212
213 /* IDSEL 0x15 */
214 a800 0 0 1 &mpic b 1
215 a800 0 0 2 &mpic b 1
216 a800 0 0 3 &mpic b 1
217 a800 0 0 4 &mpic b 1>;
218 interrupt-parent = <&mpic>;
219 interrupts = <19 2>;
220 bus-range = <0 0>;
221 ranges = <02000000 0 a0000000 a0000000 0 20000000
222 01000000 0 00000000 e3000000 0 00100000>;
223 clock-frequency = <3f940aa>;
224 #interrupt-cells = <1>;
225 #size-cells = <2>;
226 #address-cells = <3>;
227 reg = <9000 1000>;
228 compatible = "fsl,mpc8540-pci";
229 device_type = "pci";
230 };
231
232 mpic: pic@40000 { 138 mpic: pic@40000 {
233 clock-frequency = <0>; 139 clock-frequency = <0>;
234 interrupt-controller; 140 interrupt-controller;
@@ -240,4 +146,98 @@
240 big-endian; 146 big-endian;
241 }; 147 };
242 }; 148 };
149
150 pci1: pci@e0008000 {
151 interrupt-map-mask = <1f800 0 0 7>;
152 interrupt-map = <
153
154 /* IDSEL 0x10 */
155 08000 0 0 1 &mpic 0 1
156 08000 0 0 2 &mpic 1 1
157 08000 0 0 3 &mpic 2 1
158 08000 0 0 4 &mpic 3 1
159
160 /* IDSEL 0x11 */
161 08800 0 0 1 &mpic 0 1
162 08800 0 0 2 &mpic 1 1
163 08800 0 0 3 &mpic 2 1
164 08800 0 0 4 &mpic 3 1
165
166 /* IDSEL 0x12 (Slot 1) */
167 09000 0 0 1 &mpic 0 1
168 09000 0 0 2 &mpic 1 1
169 09000 0 0 3 &mpic 2 1
170 09000 0 0 4 &mpic 3 1
171
172 /* IDSEL 0x13 (Slot 2) */
173 09800 0 0 1 &mpic 1 1
174 09800 0 0 2 &mpic 2 1
175 09800 0 0 3 &mpic 3 1
176 09800 0 0 4 &mpic 0 1
177
178 /* IDSEL 0x14 (Slot 3) */
179 0a000 0 0 1 &mpic 2 1
180 0a000 0 0 2 &mpic 3 1
181 0a000 0 0 3 &mpic 0 1
182 0a000 0 0 4 &mpic 1 1
183
184 /* IDSEL 0x15 (Slot 4) */
185 0a800 0 0 1 &mpic 3 1
186 0a800 0 0 2 &mpic 0 1
187 0a800 0 0 3 &mpic 1 1
188 0a800 0 0 4 &mpic 2 1
189
190 /* Bus 1 (Tundra Bridge) */
191 /* IDSEL 0x12 (ISA bridge) */
192 19000 0 0 1 &mpic 0 1
193 19000 0 0 2 &mpic 1 1
194 19000 0 0 3 &mpic 2 1
195 19000 0 0 4 &mpic 3 1>;
196 interrupt-parent = <&mpic>;
197 interrupts = <18 2>;
198 bus-range = <0 0>;
199 ranges = <02000000 0 80000000 80000000 0 20000000
200 01000000 0 00000000 e2000000 0 00100000>;
201 clock-frequency = <3f940aa>;
202 #interrupt-cells = <1>;
203 #size-cells = <2>;
204 #address-cells = <3>;
205 reg = <e0008000 1000>;
206 compatible = "fsl,mpc8540-pci";
207 device_type = "pci";
208
209 i8259@19000 {
210 interrupt-controller;
211 device_type = "interrupt-controller";
212 reg = <19000 0 0 0 1>;
213 #address-cells = <0>;
214 #interrupt-cells = <2>;
215 compatible = "chrp,iic";
216 interrupts = <1>;
217 interrupt-parent = <&pci1>;
218 };
219 };
220
221 pci@e0009000 {
222 interrupt-map-mask = <f800 0 0 7>;
223 interrupt-map = <
224
225 /* IDSEL 0x15 */
226 a800 0 0 1 &mpic b 1
227 a800 0 0 2 &mpic b 1
228 a800 0 0 3 &mpic b 1
229 a800 0 0 4 &mpic b 1>;
230 interrupt-parent = <&mpic>;
231 interrupts = <19 2>;
232 bus-range = <0 0>;
233 ranges = <02000000 0 a0000000 a0000000 0 20000000
234 01000000 0 00000000 e3000000 0 00100000>;
235 clock-frequency = <3f940aa>;
236 #interrupt-cells = <1>;
237 #size-cells = <2>;
238 #address-cells = <3>;
239 reg = <e0009000 1000>;
240 compatible = "fsl,mpc8540-pci";
241 device_type = "pci";
242 };
243}; 243};
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