diff options
author | Kumar Gala <galak@kernel.crashing.org> | 2008-05-30 14:43:43 -0400 |
---|---|---|
committer | Kumar Gala <galak@kernel.crashing.org> | 2008-06-02 15:44:25 -0400 |
commit | c054065bc10a7ee2bcf78b5bc95f4b4d9bdc923a (patch) | |
tree | 023b60c1b55c04c2db08983a3aaef151d081fcac /arch/powerpc/boot/dts/mpc8541cds.dts | |
parent | acd4b715ec83e451990bb82bdbf28ecaeab1b67d (diff) |
[POWERPC] 85xx: Add next-level-cache property
Added next-level-cache to the L1 and a reference to the new L2 label.
This is per the ePAPR 0.94 spec. Since we are't really dependent on this
today we aren't supporting the "legacy" l2-cache phandle that is specified
in the PPC v2.1 OF Binding spec.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/boot/dts/mpc8541cds.dts')
-rw-r--r-- | arch/powerpc/boot/dts/mpc8541cds.dts | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/powerpc/boot/dts/mpc8541cds.dts b/arch/powerpc/boot/dts/mpc8541cds.dts index 21ebe7cc454a..66192aa0f311 100644 --- a/arch/powerpc/boot/dts/mpc8541cds.dts +++ b/arch/powerpc/boot/dts/mpc8541cds.dts | |||
@@ -40,6 +40,7 @@ | |||
40 | timebase-frequency = <0>; // 33 MHz, from uboot | 40 | timebase-frequency = <0>; // 33 MHz, from uboot |
41 | bus-frequency = <0>; // 166 MHz | 41 | bus-frequency = <0>; // 166 MHz |
42 | clock-frequency = <0>; // 825 MHz, from uboot | 42 | clock-frequency = <0>; // 825 MHz, from uboot |
43 | next-level-cache = <&L2>; | ||
43 | }; | 44 | }; |
44 | }; | 45 | }; |
45 | 46 | ||
@@ -63,7 +64,7 @@ | |||
63 | interrupts = <18 2>; | 64 | interrupts = <18 2>; |
64 | }; | 65 | }; |
65 | 66 | ||
66 | l2-cache-controller@20000 { | 67 | L2: l2-cache-controller@20000 { |
67 | compatible = "fsl,8541-l2-cache-controller"; | 68 | compatible = "fsl,8541-l2-cache-controller"; |
68 | reg = <0x20000 0x1000>; | 69 | reg = <0x20000 0x1000>; |
69 | cache-line-size = <32>; // 32 bytes | 70 | cache-line-size = <32>; // 32 bytes |