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authorPaul Gortmaker <paul.gortmaker@windriver.com>2008-01-28 16:09:36 -0500
committerKumar Gala <galak@kernel.crashing.org>2008-01-28 17:16:38 -0500
commitcda13dd164f91df79ba797ab84848352b03de115 (patch)
treef366a541f2358c4b74b3e4c8b7ec04994c23d3e8 /arch/powerpc/boot/dts/mpc8378_mds.dts
parenta6f71745969d495d697d1ccd96385d2f7a963375 (diff)
[POWERPC] 83xx: Clean up / convert mpc83xx board DTS files to v1 format.
This patch converts the remaining 83xx boards to the dts-v1 format. This includes the mpc8313_rdb, mpc832x_mds, mpc8323_rdb, mpc8349emitx, mpc8349emitxgp and the mpc836x_mds. The mpc8315_rdb mpc834x_mds, mpc837[789]_*, and sbc8349 were already dts-v1 and only undergo minor changes for the sake of formatting consistency across the whole group of boards; i.e. the idea being that you can do a "diff -u board_A.dts board_B.dts" and see something meaningful. The general rule I've applied is that entries for values normally parsed by humans are left in decimal (i.e. IRQ, cache size, clock rates, basic counts and indexes) and all other data (i.e. reg and ranges, IRQ flags etc.) remain in hex. I've used dtc to confirm that the output prior to this changeset matches the output after this changeset is applied for all boards. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/boot/dts/mpc8378_mds.dts')
-rw-r--r--arch/powerpc/boot/dts/mpc8378_mds.dts130
1 files changed, 65 insertions, 65 deletions
diff --git a/arch/powerpc/boot/dts/mpc8378_mds.dts b/arch/powerpc/boot/dts/mpc8378_mds.dts
index 386f4a037b33..533e9b06cc8f 100644
--- a/arch/powerpc/boot/dts/mpc8378_mds.dts
+++ b/arch/powerpc/boot/dts/mpc8378_mds.dts
@@ -31,11 +31,11 @@
31 31
32 PowerPC,8378@0 { 32 PowerPC,8378@0 {
33 device_type = "cpu"; 33 device_type = "cpu";
34 reg = <0>; 34 reg = <0x0>;
35 d-cache-line-size = <0x20>; 35 d-cache-line-size = <32>;
36 i-cache-line-size = <0x20>; 36 i-cache-line-size = <32>;
37 d-cache-size = <0x8000>; // L1, 32K 37 d-cache-size = <32768>;
38 i-cache-size = <0x8000>; // L1, 32K 38 i-cache-size = <32768>;
39 timebase-frequency = <0>; 39 timebase-frequency = <0>;
40 bus-frequency = <0>; 40 bus-frequency = <0>;
41 clock-frequency = <0>; 41 clock-frequency = <0>;
@@ -66,8 +66,8 @@
66 cell-index = <0>; 66 cell-index = <0>;
67 compatible = "fsl-i2c"; 67 compatible = "fsl-i2c";
68 reg = <0x3000 0x100>; 68 reg = <0x3000 0x100>;
69 interrupts = <0xe 0x8>; 69 interrupts = <14 0x8>;
70 interrupt-parent = < &ipic >; 70 interrupt-parent = <&ipic>;
71 dfsrr; 71 dfsrr;
72 }; 72 };
73 73
@@ -77,8 +77,8 @@
77 cell-index = <1>; 77 cell-index = <1>;
78 compatible = "fsl-i2c"; 78 compatible = "fsl-i2c";
79 reg = <0x3100 0x100>; 79 reg = <0x3100 0x100>;
80 interrupts = <0xf 0x8>; 80 interrupts = <15 0x8>;
81 interrupt-parent = < &ipic >; 81 interrupt-parent = <&ipic>;
82 dfsrr; 82 dfsrr;
83 }; 83 };
84 84
@@ -86,8 +86,8 @@
86 cell-index = <0>; 86 cell-index = <0>;
87 compatible = "fsl,spi"; 87 compatible = "fsl,spi";
88 reg = <0x7000 0x1000>; 88 reg = <0x7000 0x1000>;
89 interrupts = <0x10 0x8>; 89 interrupts = <16 0x8>;
90 interrupt-parent = < &ipic >; 90 interrupt-parent = <&ipic>;
91 mode = "cpu"; 91 mode = "cpu";
92 }; 92 };
93 93
@@ -97,8 +97,8 @@
97 reg = <0x23000 0x1000>; 97 reg = <0x23000 0x1000>;
98 #address-cells = <1>; 98 #address-cells = <1>;
99 #size-cells = <0>; 99 #size-cells = <0>;
100 interrupt-parent = < &ipic >; 100 interrupt-parent = <&ipic>;
101 interrupts = <0x26 0x8>; 101 interrupts = <38 0x8>;
102 phy_type = "utmi_wide"; 102 phy_type = "utmi_wide";
103 }; 103 };
104 104
@@ -108,15 +108,15 @@
108 compatible = "fsl,gianfar-mdio"; 108 compatible = "fsl,gianfar-mdio";
109 reg = <0x24520 0x20>; 109 reg = <0x24520 0x20>;
110 phy2: ethernet-phy@2 { 110 phy2: ethernet-phy@2 {
111 interrupt-parent = < &ipic >; 111 interrupt-parent = <&ipic>;
112 interrupts = <0x11 0x8>; 112 interrupts = <17 0x8>;
113 reg = <2>; 113 reg = <0x2>;
114 device_type = "ethernet-phy"; 114 device_type = "ethernet-phy";
115 }; 115 };
116 phy3: ethernet-phy@3 { 116 phy3: ethernet-phy@3 {
117 interrupt-parent = < &ipic >; 117 interrupt-parent = <&ipic>;
118 interrupts = <0x12 0x8>; 118 interrupts = <18 0x8>;
119 reg = <3>; 119 reg = <0x3>;
120 device_type = "ethernet-phy"; 120 device_type = "ethernet-phy";
121 }; 121 };
122 }; 122 };
@@ -128,10 +128,10 @@
128 compatible = "gianfar"; 128 compatible = "gianfar";
129 reg = <0x24000 0x1000>; 129 reg = <0x24000 0x1000>;
130 local-mac-address = [ 00 00 00 00 00 00 ]; 130 local-mac-address = [ 00 00 00 00 00 00 ];
131 interrupts = <0x20 0x8 0x21 0x8 0x22 0x8>; 131 interrupts = <32 0x8 33 0x8 34 0x8>;
132 phy-connection-type = "mii"; 132 phy-connection-type = "mii";
133 interrupt-parent = < &ipic >; 133 interrupt-parent = <&ipic>;
134 phy-handle = < &phy2 >; 134 phy-handle = <&phy2>;
135 }; 135 };
136 136
137 enet1: ethernet@25000 { 137 enet1: ethernet@25000 {
@@ -141,10 +141,10 @@
141 compatible = "gianfar"; 141 compatible = "gianfar";
142 reg = <0x25000 0x1000>; 142 reg = <0x25000 0x1000>;
143 local-mac-address = [ 00 00 00 00 00 00 ]; 143 local-mac-address = [ 00 00 00 00 00 00 ];
144 interrupts = <0x23 0x8 0x24 0x8 0x25 0x8>; 144 interrupts = <35 0x8 36 0x8 37 0x8>;
145 phy-connection-type = "mii"; 145 phy-connection-type = "mii";
146 interrupt-parent = < &ipic >; 146 interrupt-parent = <&ipic>;
147 phy-handle = < &phy3 >; 147 phy-handle = <&phy3>;
148 }; 148 };
149 149
150 serial0: serial@4500 { 150 serial0: serial@4500 {
@@ -153,8 +153,8 @@
153 compatible = "ns16550"; 153 compatible = "ns16550";
154 reg = <0x4500 0x100>; 154 reg = <0x4500 0x100>;
155 clock-frequency = <0>; 155 clock-frequency = <0>;
156 interrupts = <0x9 0x8>; 156 interrupts = <9 0x8>;
157 interrupt-parent = < &ipic >; 157 interrupt-parent = <&ipic>;
158 }; 158 };
159 159
160 serial1: serial@4600 { 160 serial1: serial@4600 {
@@ -163,19 +163,19 @@
163 compatible = "ns16550"; 163 compatible = "ns16550";
164 reg = <0x4600 0x100>; 164 reg = <0x4600 0x100>;
165 clock-frequency = <0>; 165 clock-frequency = <0>;
166 interrupts = <0xa 0x8>; 166 interrupts = <10 0x8>;
167 interrupt-parent = < &ipic >; 167 interrupt-parent = <&ipic>;
168 }; 168 };
169 169
170 crypto@30000 { 170 crypto@30000 {
171 model = "SEC3"; 171 model = "SEC3";
172 compatible = "talitos"; 172 compatible = "talitos";
173 reg = <0x30000 0x10000>; 173 reg = <0x30000 0x10000>;
174 interrupts = <0xb 0x8>; 174 interrupts = <11 0x8>;
175 interrupt-parent = < &ipic >; 175 interrupt-parent = <&ipic>;
176 /* Rev. 3.0 geometry */ 176 /* Rev. 3.0 geometry */
177 num-channels = <4>; 177 num-channels = <4>;
178 channel-fifo-len = <0x18>; 178 channel-fifo-len = <24>;
179 exec-units-mask = <0x000001fe>; 179 exec-units-mask = <0x000001fe>;
180 descriptor-types-mask = <0x03ab0ebf>; 180 descriptor-types-mask = <0x03ab0ebf>;
181 }; 181 };
@@ -184,8 +184,8 @@
184 model = "eSDHC"; 184 model = "eSDHC";
185 compatible = "fsl,esdhc"; 185 compatible = "fsl,esdhc";
186 reg = <0x2e000 0x1000>; 186 reg = <0x2e000 0x1000>;
187 interrupts = <0x2a 0x8>; 187 interrupts = <42 0x8>;
188 interrupt-parent = < &ipic >; 188 interrupt-parent = <&ipic>;
189 }; 189 };
190 190
191 /* IPIC 191 /* IPIC
@@ -209,49 +209,49 @@
209 interrupt-map = < 209 interrupt-map = <
210 210
211 /* IDSEL 0x11 */ 211 /* IDSEL 0x11 */
212 0x8800 0x0 0x0 0x1 &ipic 0x14 0x8 212 0x8800 0x0 0x0 0x1 &ipic 20 0x8
213 0x8800 0x0 0x0 0x2 &ipic 0x15 0x8 213 0x8800 0x0 0x0 0x2 &ipic 21 0x8
214 0x8800 0x0 0x0 0x3 &ipic 0x16 0x8 214 0x8800 0x0 0x0 0x3 &ipic 22 0x8
215 0x8800 0x0 0x0 0x4 &ipic 0x17 0x8 215 0x8800 0x0 0x0 0x4 &ipic 23 0x8
216 216
217 /* IDSEL 0x12 */ 217 /* IDSEL 0x12 */
218 0x9000 0x0 0x0 0x1 &ipic 0x16 0x8 218 0x9000 0x0 0x0 0x1 &ipic 22 0x8
219 0x9000 0x0 0x0 0x2 &ipic 0x17 0x8 219 0x9000 0x0 0x0 0x2 &ipic 23 0x8
220 0x9000 0x0 0x0 0x3 &ipic 0x14 0x8 220 0x9000 0x0 0x0 0x3 &ipic 20 0x8
221 0x9000 0x0 0x0 0x4 &ipic 0x15 0x8 221 0x9000 0x0 0x0 0x4 &ipic 21 0x8
222 222
223 /* IDSEL 0x13 */ 223 /* IDSEL 0x13 */
224 0x9800 0x0 0x0 0x1 &ipic 0x17 0x8 224 0x9800 0x0 0x0 0x1 &ipic 23 0x8
225 0x9800 0x0 0x0 0x2 &ipic 0x14 0x8 225 0x9800 0x0 0x0 0x2 &ipic 20 0x8
226 0x9800 0x0 0x0 0x3 &ipic 0x15 0x8 226 0x9800 0x0 0x0 0x3 &ipic 21 0x8
227 0x9800 0x0 0x0 0x4 &ipic 0x16 0x8 227 0x9800 0x0 0x0 0x4 &ipic 22 0x8
228 228
229 /* IDSEL 0x15 */ 229 /* IDSEL 0x15 */
230 0xa800 0x0 0x0 0x1 &ipic 0x14 0x8 230 0xa800 0x0 0x0 0x1 &ipic 20 0x8
231 0xa800 0x0 0x0 0x2 &ipic 0x15 0x8 231 0xa800 0x0 0x0 0x2 &ipic 21 0x8
232 0xa800 0x0 0x0 0x3 &ipic 0x16 0x8 232 0xa800 0x0 0x0 0x3 &ipic 22 0x8
233 0xa800 0x0 0x0 0x4 &ipic 0x17 0x8 233 0xa800 0x0 0x0 0x4 &ipic 23 0x8
234 234
235 /* IDSEL 0x16 */ 235 /* IDSEL 0x16 */
236 0xb000 0x0 0x0 0x1 &ipic 0x17 0x8 236 0xb000 0x0 0x0 0x1 &ipic 23 0x8
237 0xb000 0x0 0x0 0x2 &ipic 0x14 0x8 237 0xb000 0x0 0x0 0x2 &ipic 20 0x8
238 0xb000 0x0 0x0 0x3 &ipic 0x15 0x8 238 0xb000 0x0 0x0 0x3 &ipic 21 0x8
239 0xb000 0x0 0x0 0x4 &ipic 0x16 0x8 239 0xb000 0x0 0x0 0x4 &ipic 22 0x8
240 240
241 /* IDSEL 0x17 */ 241 /* IDSEL 0x17 */
242 0xb800 0x0 0x0 0x1 &ipic 0x16 0x8 242 0xb800 0x0 0x0 0x1 &ipic 22 0x8
243 0xb800 0x0 0x0 0x2 &ipic 0x17 0x8 243 0xb800 0x0 0x0 0x2 &ipic 23 0x8
244 0xb800 0x0 0x0 0x3 &ipic 0x14 0x8 244 0xb800 0x0 0x0 0x3 &ipic 20 0x8
245 0xb800 0x0 0x0 0x4 &ipic 0x15 0x8 245 0xb800 0x0 0x0 0x4 &ipic 21 0x8
246 246
247 /* IDSEL 0x18 */ 247 /* IDSEL 0x18 */
248 0xc000 0x0 0x0 0x1 &ipic 0x15 0x8 248 0xc000 0x0 0x0 0x1 &ipic 21 0x8
249 0xc000 0x0 0x0 0x2 &ipic 0x16 0x8 249 0xc000 0x0 0x0 0x2 &ipic 22 0x8
250 0xc000 0x0 0x0 0x3 &ipic 0x17 0x8 250 0xc000 0x0 0x0 0x3 &ipic 23 0x8
251 0xc000 0x0 0x0 0x4 &ipic 0x14 0x8>; 251 0xc000 0x0 0x0 0x4 &ipic 20 0x8>;
252 interrupt-parent = < &ipic >; 252 interrupt-parent = <&ipic>;
253 interrupts = <0x42 0x8>; 253 interrupts = <66 0x8>;
254 bus-range = <0 0>; 254 bus-range = <0x0 0x0>;
255 ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000 255 ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
256 0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000 256 0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
257 0x01000000 0x0 0x00000000 0xe0300000 0x0 0x00100000>; 257 0x01000000 0x0 0x00000000 0xe0300000 0x0 0x00100000>;
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-21 10:15:35 -0500