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authorAnton Vorontsov <avorontsov@ru.mvista.com>2009-03-19 14:01:42 -0400
committerKumar Gala <galak@kernel.crashing.org>2009-03-24 09:34:19 -0400
commit125a00d74ea57a901fd4cc3d84baf2e825704b68 (patch)
treec35549d98bc50d1c791f28d769df630308beb0cc /arch/powerpc/boot/dts/mpc8378_mds.dts
parent757c74d298dc8438760b8dea275c4c6e0ac8a77f (diff)
powerpc/83xx: Add power management support for MPC837x boards
This patch adds pmc nodes to the device tree files so that the boards will able to use standby capability of MPC837x processors. The MPC837x PMC controllers are compatible with MPC8349 ones (i.e. no deep sleep). sleep = <> properties are used to specify SCCR masks as described in "Specifying Device Power Management Information (sleep property)" chapter in Documentation/powerpc/booting-without-of.txt. Since I2C1 and eSDHC controllers share the same clock source, they are now placed under sleep-nexus nodes. A processor is able to wakeup the boards on LAN events (Wake-On-Lan), console events (with no_console_suspend kernel command line), GPIO events and external IRQs (IRQ1 and IRQ2). The processor can also wakeup the boards by the fourth general purpose timer in GTM1 block, but the GTM wakeup support isn't yet implemented (it's tested to work, but it's unclear how can we use the quite short GTM timers, and how do we want to expose the GTM to userspace). Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/boot/dts/mpc8378_mds.dts')
-rw-r--r--arch/powerpc/boot/dts/mpc8378_mds.dts66
1 files changed, 45 insertions, 21 deletions
diff --git a/arch/powerpc/boot/dts/mpc8378_mds.dts b/arch/powerpc/boot/dts/mpc8378_mds.dts
index c3b212cf9025..155841d4db29 100644
--- a/arch/powerpc/boot/dts/mpc8378_mds.dts
+++ b/arch/powerpc/boot/dts/mpc8378_mds.dts
@@ -129,21 +129,38 @@
129 reg = <0x200 0x100>; 129 reg = <0x200 0x100>;
130 }; 130 };
131 131
132 i2c@3000 { 132 sleep-nexus {
133 #address-cells = <1>; 133 #address-cells = <1>;
134 #size-cells = <0>; 134 #size-cells = <1>;
135 cell-index = <0>; 135 compatible = "simple-bus";
136 compatible = "fsl-i2c"; 136 sleep = <&pmc 0x0c000000>;
137 reg = <0x3000 0x100>; 137 ranges;
138 interrupts = <14 0x8>;
139 interrupt-parent = <&ipic>;
140 dfsrr;
141 138
142 rtc@68 { 139 i2c@3000 {
143 compatible = "dallas,ds1374"; 140 #address-cells = <1>;
144 reg = <0x68>; 141 #size-cells = <0>;
145 interrupts = <19 0x8>; 142 cell-index = <0>;
143 compatible = "fsl-i2c";
144 reg = <0x3000 0x100>;
145 interrupts = <14 0x8>;
146 interrupt-parent = <&ipic>; 146 interrupt-parent = <&ipic>;
147 dfsrr;
148
149 rtc@68 {
150 compatible = "dallas,ds1374";
151 reg = <0x68>;
152 interrupts = <19 0x8>;
153 interrupt-parent = <&ipic>;
154 };
155 };
156
157 sdhci@2e000 {
158 compatible = "fsl,mpc8378-esdhc", "fsl,mpc8379-esdhc";
159 reg = <0x2e000 0x1000>;
160 interrupts = <42 0x8>;
161 interrupt-parent = <&ipic>;
162 /* Filled in by U-Boot */
163 clock-frequency = <0>;
147 }; 164 };
148 }; 165 };
149 166
@@ -215,6 +232,7 @@
215 interrupts = <38 0x8>; 232 interrupts = <38 0x8>;
216 dr_mode = "host"; 233 dr_mode = "host";
217 phy_type = "ulpi"; 234 phy_type = "ulpi";
235 sleep = <&pmc 0x00c00000>;
218 }; 236 };
219 237
220 mdio@24520 { 238 mdio@24520 {
@@ -265,6 +283,8 @@
265 interrupt-parent = <&ipic>; 283 interrupt-parent = <&ipic>;
266 tbi-handle = <&tbi0>; 284 tbi-handle = <&tbi0>;
267 phy-handle = <&phy2>; 285 phy-handle = <&phy2>;
286 sleep = <&pmc 0xc0000000>;
287 fsl,magic-packet;
268 }; 288 };
269 289
270 enet1: ethernet@25000 { 290 enet1: ethernet@25000 {
@@ -279,6 +299,8 @@
279 interrupt-parent = <&ipic>; 299 interrupt-parent = <&ipic>;
280 tbi-handle = <&tbi1>; 300 tbi-handle = <&tbi1>;
281 phy-handle = <&phy3>; 301 phy-handle = <&phy3>;
302 sleep = <&pmc 0x30000000>;
303 fsl,magic-packet;
282 }; 304 };
283 305
284 serial0: serial@4500 { 306 serial0: serial@4500 {
@@ -311,15 +333,7 @@
311 fsl,channel-fifo-len = <24>; 333 fsl,channel-fifo-len = <24>;
312 fsl,exec-units-mask = <0x9fe>; 334 fsl,exec-units-mask = <0x9fe>;
313 fsl,descriptor-types-mask = <0x3ab0ebf>; 335 fsl,descriptor-types-mask = <0x3ab0ebf>;
314 }; 336 sleep = <&pmc 0x03000000>;
315
316 sdhci@2e000 {
317 compatible = "fsl,mpc8378-esdhc", "fsl,mpc8379-esdhc";
318 reg = <0x2e000 0x1000>;
319 interrupts = <42 0x8>;
320 interrupt-parent = <&ipic>;
321 /* Filled in by U-Boot */
322 clock-frequency = <0>;
323 }; 337 };
324 338
325 /* IPIC 339 /* IPIC
@@ -335,6 +349,13 @@
335 #interrupt-cells = <2>; 349 #interrupt-cells = <2>;
336 reg = <0x700 0x100>; 350 reg = <0x700 0x100>;
337 }; 351 };
352
353 pmc: power@b00 {
354 compatible = "fsl,mpc8378-pmc", "fsl,mpc8349-pmc";
355 reg = <0xb00 0x100 0xa00 0x100>;
356 interrupts = <80 0x8>;
357 interrupt-parent = <&ipic>;
358 };
338 }; 359 };
339 360
340 pci0: pci@e0008500 { 361 pci0: pci@e0008500 {
@@ -390,6 +411,7 @@
390 0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000 411 0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
391 0x01000000 0x0 0x00000000 0xe0300000 0x0 0x00100000>; 412 0x01000000 0x0 0x00000000 0xe0300000 0x0 0x00100000>;
392 clock-frequency = <0>; 413 clock-frequency = <0>;
414 sleep = <&pmc 0x00010000>;
393 #interrupt-cells = <1>; 415 #interrupt-cells = <1>;
394 #size-cells = <2>; 416 #size-cells = <2>;
395 #address-cells = <3>; 417 #address-cells = <3>;
@@ -414,6 +436,7 @@
414 0 0 0 2 &ipic 1 8 436 0 0 0 2 &ipic 1 8
415 0 0 0 3 &ipic 1 8 437 0 0 0 3 &ipic 1 8
416 0 0 0 4 &ipic 1 8>; 438 0 0 0 4 &ipic 1 8>;
439 sleep = <&pmc 0x00300000>;
417 clock-frequency = <0>; 440 clock-frequency = <0>;
418 441
419 pcie@0 { 442 pcie@0 {
@@ -445,6 +468,7 @@
445 0 0 0 2 &ipic 2 8 468 0 0 0 2 &ipic 2 8
446 0 0 0 3 &ipic 2 8 469 0 0 0 3 &ipic 2 8
447 0 0 0 4 &ipic 2 8>; 470 0 0 0 4 &ipic 2 8>;
471 sleep = <&pmc 0x000c0000>;
448 clock-frequency = <0>; 472 clock-frequency = <0>;
449 473
450 pcie@0 { 474 pcie@0 {