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authorPaul Gortmaker <paul.gortmaker@windriver.com>2008-01-28 16:09:36 -0500
committerKumar Gala <galak@kernel.crashing.org>2008-01-28 17:16:38 -0500
commitcda13dd164f91df79ba797ab84848352b03de115 (patch)
treef366a541f2358c4b74b3e4c8b7ec04994c23d3e8 /arch/powerpc/boot/dts/mpc832x_mds.dts
parenta6f71745969d495d697d1ccd96385d2f7a963375 (diff)
[POWERPC] 83xx: Clean up / convert mpc83xx board DTS files to v1 format.
This patch converts the remaining 83xx boards to the dts-v1 format. This includes the mpc8313_rdb, mpc832x_mds, mpc8323_rdb, mpc8349emitx, mpc8349emitxgp and the mpc836x_mds. The mpc8315_rdb mpc834x_mds, mpc837[789]_*, and sbc8349 were already dts-v1 and only undergo minor changes for the sake of formatting consistency across the whole group of boards; i.e. the idea being that you can do a "diff -u board_A.dts board_B.dts" and see something meaningful. The general rule I've applied is that entries for values normally parsed by humans are left in decimal (i.e. IRQ, cache size, clock rates, basic counts and indexes) and all other data (i.e. reg and ranges, IRQ flags etc.) remain in hex. I've used dtc to confirm that the output prior to this changeset matches the output after this changeset is applied for all boards. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/boot/dts/mpc832x_mds.dts')
-rw-r--r--arch/powerpc/boot/dts/mpc832x_mds.dts252
1 files changed, 127 insertions, 125 deletions
diff --git a/arch/powerpc/boot/dts/mpc832x_mds.dts b/arch/powerpc/boot/dts/mpc832x_mds.dts
index 7c3c52cea75c..9bb408371bcd 100644
--- a/arch/powerpc/boot/dts/mpc832x_mds.dts
+++ b/arch/powerpc/boot/dts/mpc832x_mds.dts
@@ -21,6 +21,8 @@
21 * you're going by the schematic, the pin is called "P19J-K22". 21 * you're going by the schematic, the pin is called "P19J-K22".
22 */ 22 */
23 23
24/dts-v1/;
25
24/ { 26/ {
25 model = "MPC8323EMDS"; 27 model = "MPC8323EMDS";
26 compatible = "MPC8323EMDS", "MPC832xMDS", "MPC83xxMDS"; 28 compatible = "MPC8323EMDS", "MPC832xMDS", "MPC83xxMDS";
@@ -41,11 +43,11 @@
41 43
42 PowerPC,8323@0 { 44 PowerPC,8323@0 {
43 device_type = "cpu"; 45 device_type = "cpu";
44 reg = <0>; 46 reg = <0x0>;
45 d-cache-line-size = <20>; // 32 bytes 47 d-cache-line-size = <32>; // 32 bytes
46 i-cache-line-size = <20>; // 32 bytes 48 i-cache-line-size = <32>; // 32 bytes
47 d-cache-size = <4000>; // L1, 16K 49 d-cache-size = <16384>; // L1, 16K
48 i-cache-size = <4000>; // L1, 16K 50 i-cache-size = <16384>; // L1, 16K
49 timebase-frequency = <0>; 51 timebase-frequency = <0>;
50 bus-frequency = <0>; 52 bus-frequency = <0>;
51 clock-frequency = <0>; 53 clock-frequency = <0>;
@@ -54,26 +56,26 @@
54 56
55 memory { 57 memory {
56 device_type = "memory"; 58 device_type = "memory";
57 reg = <00000000 08000000>; 59 reg = <0x00000000 0x08000000>;
58 }; 60 };
59 61
60 bcsr@f8000000 { 62 bcsr@f8000000 {
61 device_type = "board-control"; 63 device_type = "board-control";
62 reg = <f8000000 8000>; 64 reg = <0xf8000000 0x8000>;
63 }; 65 };
64 66
65 soc8323@e0000000 { 67 soc8323@e0000000 {
66 #address-cells = <1>; 68 #address-cells = <1>;
67 #size-cells = <1>; 69 #size-cells = <1>;
68 device_type = "soc"; 70 device_type = "soc";
69 ranges = <0 e0000000 00100000>; 71 ranges = <0x0 0xe0000000 0x00100000>;
70 reg = <e0000000 00000200>; 72 reg = <0xe0000000 0x00000200>;
71 bus-frequency = <7DE2900>; 73 bus-frequency = <132000000>;
72 74
73 wdt@200 { 75 wdt@200 {
74 device_type = "watchdog"; 76 device_type = "watchdog";
75 compatible = "mpc83xx_wdt"; 77 compatible = "mpc83xx_wdt";
76 reg = <200 100>; 78 reg = <0x200 0x100>;
77 }; 79 };
78 80
79 i2c@3000 { 81 i2c@3000 {
@@ -81,14 +83,14 @@
81 #size-cells = <0>; 83 #size-cells = <0>;
82 cell-index = <0>; 84 cell-index = <0>;
83 compatible = "fsl-i2c"; 85 compatible = "fsl-i2c";
84 reg = <3000 100>; 86 reg = <0x3000 0x100>;
85 interrupts = <e 8>; 87 interrupts = <14 0x8>;
86 interrupt-parent = < &ipic >; 88 interrupt-parent = <&ipic>;
87 dfsrr; 89 dfsrr;
88 90
89 rtc@68 { 91 rtc@68 {
90 compatible = "dallas,ds1374"; 92 compatible = "dallas,ds1374";
91 reg = <68>; 93 reg = <0x68>;
92 }; 94 };
93 }; 95 };
94 96
@@ -96,46 +98,46 @@
96 cell-index = <0>; 98 cell-index = <0>;
97 device_type = "serial"; 99 device_type = "serial";
98 compatible = "ns16550"; 100 compatible = "ns16550";
99 reg = <4500 100>; 101 reg = <0x4500 0x100>;
100 clock-frequency = <0>; 102 clock-frequency = <0>;
101 interrupts = <9 8>; 103 interrupts = <9 0x8>;
102 interrupt-parent = < &ipic >; 104 interrupt-parent = <&ipic>;
103 }; 105 };
104 106
105 serial1: serial@4600 { 107 serial1: serial@4600 {
106 cell-index = <1>; 108 cell-index = <1>;
107 device_type = "serial"; 109 device_type = "serial";
108 compatible = "ns16550"; 110 compatible = "ns16550";
109 reg = <4600 100>; 111 reg = <0x4600 0x100>;
110 clock-frequency = <0>; 112 clock-frequency = <0>;
111 interrupts = <a 8>; 113 interrupts = <10 0x8>;
112 interrupt-parent = < &ipic >; 114 interrupt-parent = <&ipic>;
113 }; 115 };
114 116
115 crypto@30000 { 117 crypto@30000 {
116 device_type = "crypto"; 118 device_type = "crypto";
117 model = "SEC2"; 119 model = "SEC2";
118 compatible = "talitos"; 120 compatible = "talitos";
119 reg = <30000 7000>; 121 reg = <0x30000 0x7000>;
120 interrupts = <b 8>; 122 interrupts = <11 0x8>;
121 interrupt-parent = < &ipic >; 123 interrupt-parent = <&ipic>;
122 /* Rev. 2.2 */ 124 /* Rev. 2.2 */
123 num-channels = <1>; 125 num-channels = <1>;
124 channel-fifo-len = <18>; 126 channel-fifo-len = <24>;
125 exec-units-mask = <0000004c>; 127 exec-units-mask = <0x0000004c>;
126 descriptor-types-mask = <0122003f>; 128 descriptor-types-mask = <0x0122003f>;
127 }; 129 };
128 130
129 ipic: pic@700 { 131 ipic: pic@700 {
130 interrupt-controller; 132 interrupt-controller;
131 #address-cells = <0>; 133 #address-cells = <0>;
132 #interrupt-cells = <2>; 134 #interrupt-cells = <2>;
133 reg = <700 100>; 135 reg = <0x700 0x100>;
134 device_type = "ipic"; 136 device_type = "ipic";
135 }; 137 };
136 138
137 par_io@1400 { 139 par_io@1400 {
138 reg = <1400 100>; 140 reg = <0x1400 0x100>;
139 device_type = "par_io"; 141 device_type = "par_io";
140 num-ports = <7>; 142 num-ports = <7>;
141 143
@@ -144,8 +146,8 @@
144 /* port pin dir open_drain assignment has_irq */ 146 /* port pin dir open_drain assignment has_irq */
145 3 4 3 0 2 0 /* MDIO */ 147 3 4 3 0 2 0 /* MDIO */
146 3 5 1 0 2 0 /* MDC */ 148 3 5 1 0 2 0 /* MDC */
147 0 d 2 0 1 0 /* RX_CLK (CLK9) */ 149 0 13 2 0 1 0 /* RX_CLK (CLK9) */
148 3 18 2 0 1 0 /* TX_CLK (CLK10) */ 150 3 24 2 0 1 0 /* TX_CLK (CLK10) */
149 1 0 1 0 1 0 /* TxD0 */ 151 1 0 1 0 1 0 /* TxD0 */
150 1 1 1 0 1 0 /* TxD1 */ 152 1 1 1 0 1 0 /* TxD1 */
151 1 2 1 0 1 0 /* TxD2 */ 153 1 2 1 0 1 0 /* TxD2 */
@@ -156,30 +158,30 @@
156 1 7 2 0 1 0 /* RxD3 */ 158 1 7 2 0 1 0 /* RxD3 */
157 1 8 2 0 1 0 /* RX_ER */ 159 1 8 2 0 1 0 /* RX_ER */
158 1 9 1 0 1 0 /* TX_ER */ 160 1 9 1 0 1 0 /* TX_ER */
159 1 a 2 0 1 0 /* RX_DV */ 161 1 10 2 0 1 0 /* RX_DV */
160 1 b 2 0 1 0 /* COL */ 162 1 11 2 0 1 0 /* COL */
161 1 c 1 0 1 0 /* TX_EN */ 163 1 12 1 0 1 0 /* TX_EN */
162 1 d 2 0 1 0>;/* CRS */ 164 1 13 2 0 1 0>; /* CRS */
163 }; 165 };
164 pio4: ucc_pin@04 { 166 pio4: ucc_pin@04 {
165 pio-map = < 167 pio-map = <
166 /* port pin dir open_drain assignment has_irq */ 168 /* port pin dir open_drain assignment has_irq */
167 3 1f 2 0 1 0 /* RX_CLK (CLK7) */ 169 3 31 2 0 1 0 /* RX_CLK (CLK7) */
168 3 6 2 0 1 0 /* TX_CLK (CLK8) */ 170 3 6 2 0 1 0 /* TX_CLK (CLK8) */
169 1 12 1 0 1 0 /* TxD0 */ 171 1 18 1 0 1 0 /* TxD0 */
170 1 13 1 0 1 0 /* TxD1 */ 172 1 19 1 0 1 0 /* TxD1 */
171 1 14 1 0 1 0 /* TxD2 */ 173 1 20 1 0 1 0 /* TxD2 */
172 1 15 1 0 1 0 /* TxD3 */ 174 1 21 1 0 1 0 /* TxD3 */
173 1 16 2 0 1 0 /* RxD0 */ 175 1 22 2 0 1 0 /* RxD0 */
174 1 17 2 0 1 0 /* RxD1 */ 176 1 23 2 0 1 0 /* RxD1 */
175 1 18 2 0 1 0 /* RxD2 */ 177 1 24 2 0 1 0 /* RxD2 */
176 1 19 2 0 1 0 /* RxD3 */ 178 1 25 2 0 1 0 /* RxD3 */
177 1 1a 2 0 1 0 /* RX_ER */ 179 1 26 2 0 1 0 /* RX_ER */
178 1 1b 1 0 1 0 /* TX_ER */ 180 1 27 1 0 1 0 /* TX_ER */
179 1 1c 2 0 1 0 /* RX_DV */ 181 1 28 2 0 1 0 /* RX_DV */
180 1 1d 2 0 1 0 /* COL */ 182 1 29 2 0 1 0 /* COL */
181 1 1e 1 0 1 0 /* TX_EN */ 183 1 30 1 0 1 0 /* TX_EN */
182 1 1f 2 0 1 0>;/* CRS */ 184 1 31 2 0 1 0>; /* CRS */
183 }; 185 };
184 pio5: ucc_pin@05 { 186 pio5: ucc_pin@05 {
185 pio-map = < 187 pio-map = <
@@ -190,10 +192,10 @@
190 2 0 1 0 2 0 /* TxD5 */ 192 2 0 1 0 2 0 /* TxD5 */
191 2 8 2 0 2 0 /* RxD5 */ 193 2 8 2 0 2 0 /* RxD5 */
192 194
193 2 1d 2 0 0 0 /* CTS5 */ 195 2 29 2 0 0 0 /* CTS5 */
194 2 1f 1 0 2 0 /* RTS5 */ 196 2 31 1 0 2 0 /* RTS5 */
195 197
196 2 18 2 0 0 0 /* CD */ 198 2 24 2 0 0 0 /* CD */
197 199
198 >; 200 >;
199 }; 201 };
@@ -206,47 +208,47 @@
206 #size-cells = <1>; 208 #size-cells = <1>;
207 device_type = "qe"; 209 device_type = "qe";
208 compatible = "fsl,qe"; 210 compatible = "fsl,qe";
209 ranges = <0 e0100000 00100000>; 211 ranges = <0x0 0xe0100000 0x00100000>;
210 reg = <e0100000 480>; 212 reg = <0xe0100000 0x480>;
211 brg-frequency = <0>; 213 brg-frequency = <0>;
212 bus-frequency = <BCD3D80>; 214 bus-frequency = <198000000>;
213 215
214 muram@10000 { 216 muram@10000 {
215 #address-cells = <1>; 217 #address-cells = <1>;
216 #size-cells = <1>; 218 #size-cells = <1>;
217 compatible = "fsl,qe-muram", "fsl,cpm-muram"; 219 compatible = "fsl,qe-muram", "fsl,cpm-muram";
218 ranges = <0 00010000 00004000>; 220 ranges = <0x0 0x00010000 0x00004000>;
219 221
220 data-only@0 { 222 data-only@0 {
221 compatible = "fsl,qe-muram-data", 223 compatible = "fsl,qe-muram-data",
222 "fsl,cpm-muram-data"; 224 "fsl,cpm-muram-data";
223 reg = <0 4000>; 225 reg = <0x0 0x4000>;
224 }; 226 };
225 }; 227 };
226 228
227 spi@4c0 { 229 spi@4c0 {
228 cell-index = <0>; 230 cell-index = <0>;
229 compatible = "fsl,spi"; 231 compatible = "fsl,spi";
230 reg = <4c0 40>; 232 reg = <0x4c0 0x40>;
231 interrupts = <2>; 233 interrupts = <2>;
232 interrupt-parent = < &qeic >; 234 interrupt-parent = <&qeic>;
233 mode = "cpu"; 235 mode = "cpu";
234 }; 236 };
235 237
236 spi@500 { 238 spi@500 {
237 cell-index = <1>; 239 cell-index = <1>;
238 compatible = "fsl,spi"; 240 compatible = "fsl,spi";
239 reg = <500 40>; 241 reg = <0x500 0x40>;
240 interrupts = <1>; 242 interrupts = <1>;
241 interrupt-parent = < &qeic >; 243 interrupt-parent = <&qeic>;
242 mode = "cpu"; 244 mode = "cpu";
243 }; 245 };
244 246
245 usb@6c0 { 247 usb@6c0 {
246 compatible = "qe_udc"; 248 compatible = "qe_udc";
247 reg = <6c0 40 8B00 100>; 249 reg = <0x6c0 0x40 0x8b00 0x100>;
248 interrupts = <b>; 250 interrupts = <11>;
249 interrupt-parent = < &qeic >; 251 interrupt-parent = <&qeic>;
250 mode = "slave"; 252 mode = "slave";
251 }; 253 };
252 254
@@ -256,14 +258,14 @@
256 model = "UCC"; 258 model = "UCC";
257 cell-index = <3>; 259 cell-index = <3>;
258 device-id = <3>; 260 device-id = <3>;
259 reg = <2200 200>; 261 reg = <0x2200 0x200>;
260 interrupts = <22>; 262 interrupts = <34>;
261 interrupt-parent = < &qeic >; 263 interrupt-parent = <&qeic>;
262 local-mac-address = [ 00 00 00 00 00 00 ]; 264 local-mac-address = [ 00 00 00 00 00 00 ];
263 rx-clock-name = "clk9"; 265 rx-clock-name = "clk9";
264 tx-clock-name = "clk10"; 266 tx-clock-name = "clk10";
265 phy-handle = < &phy3 >; 267 phy-handle = <&phy3>;
266 pio-handle = < &pio3 >; 268 pio-handle = <&pio3>;
267 }; 269 };
268 270
269 enet1: ucc@3200 { 271 enet1: ucc@3200 {
@@ -272,14 +274,14 @@
272 model = "UCC"; 274 model = "UCC";
273 cell-index = <4>; 275 cell-index = <4>;
274 device-id = <4>; 276 device-id = <4>;
275 reg = <3200 200>; 277 reg = <0x3200 0x200>;
276 interrupts = <23>; 278 interrupts = <35>;
277 interrupt-parent = < &qeic >; 279 interrupt-parent = <&qeic>;
278 local-mac-address = [ 00 00 00 00 00 00 ]; 280 local-mac-address = [ 00 00 00 00 00 00 ];
279 rx-clock-name = "clk7"; 281 rx-clock-name = "clk7";
280 tx-clock-name = "clk8"; 282 tx-clock-name = "clk8";
281 phy-handle = < &phy4 >; 283 phy-handle = <&phy4>;
282 pio-handle = < &pio4 >; 284 pio-handle = <&pio4>;
283 }; 285 };
284 286
285 ucc@2400 { 287 ucc@2400 {
@@ -289,8 +291,8 @@
289 device-id = <5>; /* The UCC number, 1-7*/ 291 device-id = <5>; /* The UCC number, 1-7*/
290 port-number = <0>; /* Which ttyQEx device */ 292 port-number = <0>; /* Which ttyQEx device */
291 soft-uart; /* We need Soft-UART */ 293 soft-uart; /* We need Soft-UART */
292 reg = <2400 200>; 294 reg = <0x2400 0x200>;
293 interrupts = <28>; /* From Table 18-12 */ 295 interrupts = <40>; /* From Table 18-12 */
294 interrupt-parent = < &qeic >; 296 interrupt-parent = < &qeic >;
295 /* 297 /*
296 * For Soft-UART, we need to set TX to 1X, which 298 * For Soft-UART, we need to set TX to 1X, which
@@ -305,19 +307,19 @@
305 mdio@2320 { 307 mdio@2320 {
306 #address-cells = <1>; 308 #address-cells = <1>;
307 #size-cells = <0>; 309 #size-cells = <0>;
308 reg = <2320 18>; 310 reg = <0x2320 0x18>;
309 compatible = "fsl,ucc-mdio"; 311 compatible = "fsl,ucc-mdio";
310 312
311 phy3: ethernet-phy@03 { 313 phy3: ethernet-phy@03 {
312 interrupt-parent = < &ipic >; 314 interrupt-parent = <&ipic>;
313 interrupts = <11 8>; 315 interrupts = <17 0x8>;
314 reg = <3>; 316 reg = <0x3>;
315 device_type = "ethernet-phy"; 317 device_type = "ethernet-phy";
316 }; 318 };
317 phy4: ethernet-phy@04 { 319 phy4: ethernet-phy@04 {
318 interrupt-parent = < &ipic >; 320 interrupt-parent = <&ipic>;
319 interrupts = <12 8>; 321 interrupts = <18 0x8>;
320 reg = <4>; 322 reg = <0x4>;
321 device_type = "ethernet-phy"; 323 device_type = "ethernet-phy";
322 }; 324 };
323 }; 325 };
@@ -327,69 +329,69 @@
327 compatible = "fsl,qe-ic"; 329 compatible = "fsl,qe-ic";
328 #address-cells = <0>; 330 #address-cells = <0>;
329 #interrupt-cells = <1>; 331 #interrupt-cells = <1>;
330 reg = <80 80>; 332 reg = <0x80 0x80>;
331 big-endian; 333 big-endian;
332 interrupts = <20 8 21 8>; //high:32 low:33 334 interrupts = <32 0x8 33 0x8>; //high:32 low:33
333 interrupt-parent = < &ipic >; 335 interrupt-parent = <&ipic>;
334 }; 336 };
335 }; 337 };
336 338
337 pci0: pci@e0008500 { 339 pci0: pci@e0008500 {
338 cell-index = <1>; 340 cell-index = <1>;
339 interrupt-map-mask = <f800 0 0 7>; 341 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
340 interrupt-map = < 342 interrupt-map = <
341 /* IDSEL 0x11 AD17 */ 343 /* IDSEL 0x11 AD17 */
342 8800 0 0 1 &ipic 14 8 344 0x8800 0x0 0x0 0x1 &ipic 20 0x8
343 8800 0 0 2 &ipic 15 8 345 0x8800 0x0 0x0 0x2 &ipic 21 0x8
344 8800 0 0 3 &ipic 16 8 346 0x8800 0x0 0x0 0x3 &ipic 22 0x8
345 8800 0 0 4 &ipic 17 8 347 0x8800 0x0 0x0 0x4 &ipic 23 0x8
346 348
347 /* IDSEL 0x12 AD18 */ 349 /* IDSEL 0x12 AD18 */
348 9000 0 0 1 &ipic 16 8 350 0x9000 0x0 0x0 0x1 &ipic 22 0x8
349 9000 0 0 2 &ipic 17 8 351 0x9000 0x0 0x0 0x2 &ipic 23 0x8
350 9000 0 0 3 &ipic 14 8 352 0x9000 0x0 0x0 0x3 &ipic 20 0x8
351 9000 0 0 4 &ipic 15 8 353 0x9000 0x0 0x0 0x4 &ipic 21 0x8
352 354
353 /* IDSEL 0x13 AD19 */ 355 /* IDSEL 0x13 AD19 */
354 9800 0 0 1 &ipic 17 8 356 0x9800 0x0 0x0 0x1 &ipic 23 0x8
355 9800 0 0 2 &ipic 14 8 357 0x9800 0x0 0x0 0x2 &ipic 20 0x8
356 9800 0 0 3 &ipic 15 8 358 0x9800 0x0 0x0 0x3 &ipic 21 0x8
357 9800 0 0 4 &ipic 16 8 359 0x9800 0x0 0x0 0x4 &ipic 22 0x8
358 360
359 /* IDSEL 0x15 AD21*/ 361 /* IDSEL 0x15 AD21*/
360 a800 0 0 1 &ipic 14 8 362 0xa800 0x0 0x0 0x1 &ipic 20 0x8
361 a800 0 0 2 &ipic 15 8 363 0xa800 0x0 0x0 0x2 &ipic 21 0x8
362 a800 0 0 3 &ipic 16 8 364 0xa800 0x0 0x0 0x3 &ipic 22 0x8
363 a800 0 0 4 &ipic 17 8 365 0xa800 0x0 0x0 0x4 &ipic 23 0x8
364 366
365 /* IDSEL 0x16 AD22*/ 367 /* IDSEL 0x16 AD22*/
366 b000 0 0 1 &ipic 17 8 368 0xb000 0x0 0x0 0x1 &ipic 23 0x8
367 b000 0 0 2 &ipic 14 8 369 0xb000 0x0 0x0 0x2 &ipic 20 0x8
368 b000 0 0 3 &ipic 15 8 370 0xb000 0x0 0x0 0x3 &ipic 21 0x8
369 b000 0 0 4 &ipic 16 8 371 0xb000 0x0 0x0 0x4 &ipic 22 0x8
370 372
371 /* IDSEL 0x17 AD23*/ 373 /* IDSEL 0x17 AD23*/
372 b800 0 0 1 &ipic 16 8 374 0xb800 0x0 0x0 0x1 &ipic 22 0x8
373 b800 0 0 2 &ipic 17 8 375 0xb800 0x0 0x0 0x2 &ipic 23 0x8
374 b800 0 0 3 &ipic 14 8 376 0xb800 0x0 0x0 0x3 &ipic 20 0x8
375 b800 0 0 4 &ipic 15 8 377 0xb800 0x0 0x0 0x4 &ipic 21 0x8
376 378
377 /* IDSEL 0x18 AD24*/ 379 /* IDSEL 0x18 AD24*/
378 c000 0 0 1 &ipic 15 8 380 0xc000 0x0 0x0 0x1 &ipic 21 0x8
379 c000 0 0 2 &ipic 16 8 381 0xc000 0x0 0x0 0x2 &ipic 22 0x8
380 c000 0 0 3 &ipic 17 8 382 0xc000 0x0 0x0 0x3 &ipic 23 0x8
381 c000 0 0 4 &ipic 14 8>; 383 0xc000 0x0 0x0 0x4 &ipic 20 0x8>;
382 interrupt-parent = < &ipic >; 384 interrupt-parent = <&ipic>;
383 interrupts = <42 8>; 385 interrupts = <66 0x8>;
384 bus-range = <0 0>; 386 bus-range = <0x0 0x0>;
385 ranges = <02000000 0 90000000 90000000 0 10000000 387 ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
386 42000000 0 80000000 80000000 0 10000000 388 0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
387 01000000 0 00000000 d0000000 0 00100000>; 389 0x01000000 0x0 0x00000000 0xd0000000 0x0 0x00100000>;
388 clock-frequency = <0>; 390 clock-frequency = <0>;
389 #interrupt-cells = <1>; 391 #interrupt-cells = <1>;
390 #size-cells = <2>; 392 #size-cells = <2>;
391 #address-cells = <3>; 393 #address-cells = <3>;
392 reg = <e0008500 100>; 394 reg = <0xe0008500 0x100>;
393 compatible = "fsl,mpc8349-pci"; 395 compatible = "fsl,mpc8349-pci";
394 device_type = "pci"; 396 device_type = "pci";
395 }; 397 };
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-04 04:37:39 -0500