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authorPaul Gortmaker <paul.gortmaker@windriver.com>2008-01-28 16:09:36 -0500
committerKumar Gala <galak@kernel.crashing.org>2008-01-28 17:16:38 -0500
commitcda13dd164f91df79ba797ab84848352b03de115 (patch)
treef366a541f2358c4b74b3e4c8b7ec04994c23d3e8 /arch/powerpc/boot/dts/mpc8315erdb.dts
parenta6f71745969d495d697d1ccd96385d2f7a963375 (diff)
[POWERPC] 83xx: Clean up / convert mpc83xx board DTS files to v1 format.
This patch converts the remaining 83xx boards to the dts-v1 format. This includes the mpc8313_rdb, mpc832x_mds, mpc8323_rdb, mpc8349emitx, mpc8349emitxgp and the mpc836x_mds. The mpc8315_rdb mpc834x_mds, mpc837[789]_*, and sbc8349 were already dts-v1 and only undergo minor changes for the sake of formatting consistency across the whole group of boards; i.e. the idea being that you can do a "diff -u board_A.dts board_B.dts" and see something meaningful. The general rule I've applied is that entries for values normally parsed by humans are left in decimal (i.e. IRQ, cache size, clock rates, basic counts and indexes) and all other data (i.e. reg and ranges, IRQ flags etc.) remain in hex. I've used dtc to confirm that the output prior to this changeset matches the output after this changeset is applied for all boards. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/boot/dts/mpc8315erdb.dts')
-rw-r--r--arch/powerpc/boot/dts/mpc8315erdb.dts100
1 files changed, 50 insertions, 50 deletions
diff --git a/arch/powerpc/boot/dts/mpc8315erdb.dts b/arch/powerpc/boot/dts/mpc8315erdb.dts
index e157f2342ea0..b582032ba3d6 100644
--- a/arch/powerpc/boot/dts/mpc8315erdb.dts
+++ b/arch/powerpc/boot/dts/mpc8315erdb.dts
@@ -30,7 +30,7 @@
30 30
31 PowerPC,8315@0 { 31 PowerPC,8315@0 {
32 device_type = "cpu"; 32 device_type = "cpu";
33 reg = <0>; 33 reg = <0x0>;
34 d-cache-line-size = <32>; 34 d-cache-line-size = <32>;
35 i-cache-line-size = <32>; 35 i-cache-line-size = <32>;
36 d-cache-size = <16384>; 36 d-cache-size = <16384>;
@@ -51,22 +51,22 @@
51 #size-cells = <1>; 51 #size-cells = <1>;
52 compatible = "fsl,mpc8315-elbc", "fsl,elbc", "simple-bus"; 52 compatible = "fsl,mpc8315-elbc", "fsl,elbc", "simple-bus";
53 reg = <0xe0005000 0x1000>; 53 reg = <0xe0005000 0x1000>;
54 interrupts = <77 8>; 54 interrupts = <77 0x8>;
55 interrupt-parent = <&ipic>; 55 interrupt-parent = <&ipic>;
56 56
57 // CS0 and CS1 are swapped when 57 // CS0 and CS1 are swapped when
58 // booting from nand, but the 58 // booting from nand, but the
59 // addresses are the same. 59 // addresses are the same.
60 ranges = <0 0 0xfe000000 0x00800000 60 ranges = <0x0 0x0 0xfe000000 0x00800000
61 1 0 0xe0600000 0x00002000 61 0x1 0x0 0xe0600000 0x00002000
62 2 0 0xf0000000 0x00020000 62 0x2 0x0 0xf0000000 0x00020000
63 3 0 0xfa000000 0x00008000>; 63 0x3 0x0 0xfa000000 0x00008000>;
64 64
65 flash@0,0 { 65 flash@0,0 {
66 #address-cells = <1>; 66 #address-cells = <1>;
67 #size-cells = <1>; 67 #size-cells = <1>;
68 compatible = "cfi-flash"; 68 compatible = "cfi-flash";
69 reg = <0 0 0x800000>; 69 reg = <0x0 0x0 0x800000>;
70 bank-width = <2>; 70 bank-width = <2>;
71 device-width = <1>; 71 device-width = <1>;
72 }; 72 };
@@ -76,7 +76,7 @@
76 #size-cells = <1>; 76 #size-cells = <1>;
77 compatible = "fsl,mpc8315-fcm-nand", 77 compatible = "fsl,mpc8315-fcm-nand",
78 "fsl,elbc-fcm-nand"; 78 "fsl,elbc-fcm-nand";
79 reg = <1 0 0x2000>; 79 reg = <0x1 0x0 0x2000>;
80 80
81 u-boot@0 { 81 u-boot@0 {
82 reg = <0x0 0x100000>; 82 reg = <0x0 0x100000>;
@@ -113,8 +113,8 @@
113 cell-index = <0>; 113 cell-index = <0>;
114 compatible = "fsl-i2c"; 114 compatible = "fsl-i2c";
115 reg = <0x3000 0x100>; 115 reg = <0x3000 0x100>;
116 interrupts = <14 8>; 116 interrupts = <14 0x8>;
117 interrupt-parent = < &ipic >; 117 interrupt-parent = <&ipic>;
118 dfsrr; 118 dfsrr;
119 rtc@68 { 119 rtc@68 {
120 device_type = "rtc"; 120 device_type = "rtc";
@@ -127,8 +127,8 @@
127 cell-index = <0>; 127 cell-index = <0>;
128 compatible = "fsl,spi"; 128 compatible = "fsl,spi";
129 reg = <0x7000 0x1000>; 129 reg = <0x7000 0x1000>;
130 interrupts = <16 8>; 130 interrupts = <16 0x8>;
131 interrupt-parent = < &ipic >; 131 interrupt-parent = <&ipic>;
132 mode = "cpu"; 132 mode = "cpu";
133 }; 133 };
134 134
@@ -137,8 +137,8 @@
137 reg = <0x23000 0x1000>; 137 reg = <0x23000 0x1000>;
138 #address-cells = <1>; 138 #address-cells = <1>;
139 #size-cells = <0>; 139 #size-cells = <0>;
140 interrupt-parent = < &ipic >; 140 interrupt-parent = <&ipic>;
141 interrupts = <38 8>; 141 interrupts = <38 0x8>;
142 phy_type = "utmi"; 142 phy_type = "utmi";
143 }; 143 };
144 144
@@ -148,15 +148,15 @@
148 compatible = "fsl,gianfar-mdio"; 148 compatible = "fsl,gianfar-mdio";
149 reg = <0x24520 0x20>; 149 reg = <0x24520 0x20>;
150 phy0: ethernet-phy@0 { 150 phy0: ethernet-phy@0 {
151 interrupt-parent = < &ipic >; 151 interrupt-parent = <&ipic>;
152 interrupts = <20 8>; 152 interrupts = <20 0x8>;
153 reg = <0>; 153 reg = <0x0>;
154 device_type = "ethernet-phy"; 154 device_type = "ethernet-phy";
155 }; 155 };
156 phy1: ethernet-phy@1 { 156 phy1: ethernet-phy@1 {
157 interrupt-parent = < &ipic >; 157 interrupt-parent = <&ipic>;
158 interrupts = <19 8>; 158 interrupts = <19 0x8>;
159 reg = <1>; 159 reg = <0x1>;
160 device_type = "ethernet-phy"; 160 device_type = "ethernet-phy";
161 }; 161 };
162 }; 162 };
@@ -168,8 +168,8 @@
168 compatible = "gianfar"; 168 compatible = "gianfar";
169 reg = <0x24000 0x1000>; 169 reg = <0x24000 0x1000>;
170 local-mac-address = [ 00 00 00 00 00 00 ]; 170 local-mac-address = [ 00 00 00 00 00 00 ];
171 interrupts = <32 8 33 8 34 8>; 171 interrupts = <32 0x8 33 0x8 34 0x8>;
172 interrupt-parent = < &ipic >; 172 interrupt-parent = <&ipic>;
173 phy-handle = < &phy0 >; 173 phy-handle = < &phy0 >;
174 }; 174 };
175 175
@@ -180,8 +180,8 @@
180 compatible = "gianfar"; 180 compatible = "gianfar";
181 reg = <0x25000 0x1000>; 181 reg = <0x25000 0x1000>;
182 local-mac-address = [ 00 00 00 00 00 00 ]; 182 local-mac-address = [ 00 00 00 00 00 00 ];
183 interrupts = <35 8 36 8 37 8>; 183 interrupts = <35 0x8 36 0x8 37 0x8>;
184 interrupt-parent = < &ipic >; 184 interrupt-parent = <&ipic>;
185 phy-handle = < &phy1 >; 185 phy-handle = < &phy1 >;
186 }; 186 };
187 187
@@ -191,8 +191,8 @@
191 compatible = "ns16550"; 191 compatible = "ns16550";
192 reg = <0x4500 0x100>; 192 reg = <0x4500 0x100>;
193 clock-frequency = <0>; 193 clock-frequency = <0>;
194 interrupts = <9 8>; 194 interrupts = <9 0x8>;
195 interrupt-parent = < &ipic >; 195 interrupt-parent = <&ipic>;
196 }; 196 };
197 197
198 serial1: serial@4600 { 198 serial1: serial@4600 {
@@ -201,8 +201,8 @@
201 compatible = "ns16550"; 201 compatible = "ns16550";
202 reg = <0x4600 0x100>; 202 reg = <0x4600 0x100>;
203 clock-frequency = <0>; 203 clock-frequency = <0>;
204 interrupts = <10 8>; 204 interrupts = <10 0x8>;
205 interrupt-parent = < &ipic >; 205 interrupt-parent = <&ipic>;
206 }; 206 };
207 207
208 crypto@30000 { 208 crypto@30000 {
@@ -210,8 +210,8 @@
210 device_type = "crypto"; 210 device_type = "crypto";
211 compatible = "talitos"; 211 compatible = "talitos";
212 reg = <0x30000 0x10000>; 212 reg = <0x30000 0x10000>;
213 interrupts = <11 8>; 213 interrupts = <11 0x8>;
214 interrupt-parent = < &ipic >; 214 interrupt-parent = <&ipic>;
215 /* Rev. 3.0 geometry */ 215 /* Rev. 3.0 geometry */
216 num-channels = <4>; 216 num-channels = <4>;
217 channel-fifo-len = <24>; 217 channel-fifo-len = <24>;
@@ -223,16 +223,16 @@
223 compatible = "fsl,mpc8315-sata", "fsl,pq-sata"; 223 compatible = "fsl,mpc8315-sata", "fsl,pq-sata";
224 reg = <0x18000 0x1000>; 224 reg = <0x18000 0x1000>;
225 cell-index = <1>; 225 cell-index = <1>;
226 interrupts = <44 8>; 226 interrupts = <44 0x8>;
227 interrupt-parent = < &ipic >; 227 interrupt-parent = <&ipic>;
228 }; 228 };
229 229
230 sata@19000 { 230 sata@19000 {
231 compatible = "fsl,mpc8315-sata", "fsl,pq-sata"; 231 compatible = "fsl,mpc8315-sata", "fsl,pq-sata";
232 reg = <0x19000 0x1000>; 232 reg = <0x19000 0x1000>;
233 cell-index = <2>; 233 cell-index = <2>;
234 interrupts = <45 8>; 234 interrupts = <45 0x8>;
235 interrupt-parent = < &ipic >; 235 interrupt-parent = <&ipic>;
236 }; 236 };
237 237
238 /* IPIC 238 /* IPIC
@@ -251,28 +251,28 @@
251 }; 251 };
252 252
253 pci0: pci@e0008500 { 253 pci0: pci@e0008500 {
254 interrupt-map-mask = <0xf800 0 0 7>; 254 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
255 interrupt-map = < 255 interrupt-map = <
256 /* IDSEL 0x0E -mini PCI */ 256 /* IDSEL 0x0E -mini PCI */
257 0x7000 0 0 1 &ipic 18 8 257 0x7000 0x0 0x0 0x1 &ipic 18 0x8
258 0x7000 0 0 2 &ipic 18 8 258 0x7000 0x0 0x0 0x2 &ipic 18 0x8
259 0x7000 0 0 3 &ipic 18 8 259 0x7000 0x0 0x0 0x3 &ipic 18 0x8
260 0x7000 0 0 4 &ipic 18 8 260 0x7000 0x0 0x0 0x4 &ipic 18 0x8
261 261
262 /* IDSEL 0x0F -mini PCI */ 262 /* IDSEL 0x0F -mini PCI */
263 0x7800 0 0 1 &ipic 17 8 263 0x7800 0x0 0x0 0x1 &ipic 17 0x8
264 0x7800 0 0 2 &ipic 17 8 264 0x7800 0x0 0x0 0x2 &ipic 17 0x8
265 0x7800 0 0 3 &ipic 17 8 265 0x7800 0x0 0x0 0x3 &ipic 17 0x8
266 0x7800 0 0 4 &ipic 17 8 266 0x7800 0x0 0x0 0x4 &ipic 17 0x8
267 267
268 /* IDSEL 0x10 - PCI slot */ 268 /* IDSEL 0x10 - PCI slot */
269 0x8000 0 0 1 &ipic 48 8 269 0x8000 0x0 0x0 0x1 &ipic 48 0x8
270 0x8000 0 0 2 &ipic 17 8 270 0x8000 0x0 0x0 0x2 &ipic 17 0x8
271 0x8000 0 0 3 &ipic 48 8 271 0x8000 0x0 0x0 0x3 &ipic 48 0x8
272 0x8000 0 0 4 &ipic 17 8>; 272 0x8000 0x0 0x0 0x4 &ipic 17 0x8>;
273 interrupt-parent = < &ipic >; 273 interrupt-parent = <&ipic>;
274 interrupts = <66 8>; 274 interrupts = <66 0x8>;
275 bus-range = <0 0>; 275 bus-range = <0x0 0x0>;
276 ranges = <0x02000000 0 0x90000000 0x90000000 0 0x10000000 276 ranges = <0x02000000 0 0x90000000 0x90000000 0 0x10000000
277 0x42000000 0 0x80000000 0x80000000 0 0x10000000 277 0x42000000 0 0x80000000 0x80000000 0 0x10000000
278 0x01000000 0 0x00000000 0xe0300000 0 0x00100000>; 278 0x01000000 0 0x00000000 0xe0300000 0 0x00100000>;