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authorKumar Gala <galak@kernel.crashing.org>2008-04-17 10:40:48 -0400
committerKumar Gala <galak@kernel.crashing.org>2008-04-17 10:40:48 -0400
commit998c610363b26f3793ad8121eeb3a749b1034824 (patch)
treef90d357678f79860fe583fced9b88c8c89806a2a /arch/powerpc/boot/dts/mpc7448hpc2.dts
parent280bb34bc0f7c664b59077b609ce93507a54c848 (diff)
[POWERPC] fsl: Convert dts to v1 syntax
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/boot/dts/mpc7448hpc2.dts')
-rw-r--r--arch/powerpc/boot/dts/mpc7448hpc2.dts97
1 files changed, 49 insertions, 48 deletions
diff --git a/arch/powerpc/boot/dts/mpc7448hpc2.dts b/arch/powerpc/boot/dts/mpc7448hpc2.dts
index 8fb542387436..4936349b87cd 100644
--- a/arch/powerpc/boot/dts/mpc7448hpc2.dts
+++ b/arch/powerpc/boot/dts/mpc7448hpc2.dts
@@ -1,7 +1,7 @@
1/* 1/*
2 * MPC7448HPC2 (Taiga) board Device Tree Source 2 * MPC7448HPC2 (Taiga) board Device Tree Source
3 * 3 *
4 * Copyright 2006 Freescale Semiconductor Inc. 4 * Copyright 2006, 2008 Freescale Semiconductor Inc.
5 * 2006 Roy Zang <Roy Zang at freescale.com>. 5 * 2006 Roy Zang <Roy Zang at freescale.com>.
6 * 6 *
7 * This program is free software; you can redistribute it and/or modify it 7 * This program is free software; you can redistribute it and/or modify it
@@ -10,6 +10,7 @@
10 * option) any later version. 10 * option) any later version.
11 */ 11 */
12 12
13/dts-v1/;
13 14
14/ { 15/ {
15 model = "mpc7448hpc2"; 16 model = "mpc7448hpc2";
@@ -23,11 +24,11 @@
23 24
24 PowerPC,7448@0 { 25 PowerPC,7448@0 {
25 device_type = "cpu"; 26 device_type = "cpu";
26 reg = <0>; 27 reg = <0x0>;
27 d-cache-line-size = <20>; // 32 bytes 28 d-cache-line-size = <32>; // 32 bytes
28 i-cache-line-size = <20>; // 32 bytes 29 i-cache-line-size = <32>; // 32 bytes
29 d-cache-size = <8000>; // L1, 32K bytes 30 d-cache-size = <0x8000>; // L1, 32K bytes
30 i-cache-size = <8000>; // L1, 32K bytes 31 i-cache-size = <0x8000>; // L1, 32K bytes
31 timebase-frequency = <0>; // 33 MHz, from uboot 32 timebase-frequency = <0>; // 33 MHz, from uboot
32 clock-frequency = <0>; // From U-Boot 33 clock-frequency = <0>; // From U-Boot
33 bus-frequency = <0>; // From U-Boot 34 bus-frequency = <0>; // From U-Boot
@@ -36,7 +37,7 @@
36 37
37 memory { 38 memory {
38 device_type = "memory"; 39 device_type = "memory";
39 reg = <00000000 20000000 // DDR2 512M at 0 40 reg = <0x0 0x20000000 // DDR2 512M at 0
40 >; 41 >;
41 }; 42 };
42 43
@@ -44,14 +45,14 @@
44 #address-cells = <1>; 45 #address-cells = <1>;
45 #size-cells = <1>; 46 #size-cells = <1>;
46 device_type = "tsi-bridge"; 47 device_type = "tsi-bridge";
47 ranges = <00000000 c0000000 00010000>; 48 ranges = <0x0 0xc0000000 0x10000>;
48 reg = <c0000000 00010000>; 49 reg = <0xc0000000 0x10000>;
49 bus-frequency = <0>; 50 bus-frequency = <0>;
50 51
51 i2c@7000 { 52 i2c@7000 {
52 interrupt-parent = <&mpic>; 53 interrupt-parent = <&mpic>;
53 interrupts = <E 0>; 54 interrupts = <14 0>;
54 reg = <7000 400>; 55 reg = <0x7000 0x400>;
55 device_type = "i2c"; 56 device_type = "i2c";
56 compatible = "tsi108-i2c"; 57 compatible = "tsi108-i2c";
57 }; 58 };
@@ -59,20 +60,20 @@
59 MDIO: mdio@6000 { 60 MDIO: mdio@6000 {
60 device_type = "mdio"; 61 device_type = "mdio";
61 compatible = "tsi108-mdio"; 62 compatible = "tsi108-mdio";
62 reg = <6000 50>; 63 reg = <0x6000 0x50>;
63 #address-cells = <1>; 64 #address-cells = <1>;
64 #size-cells = <0>; 65 #size-cells = <0>;
65 66
66 phy8: ethernet-phy@8 { 67 phy8: ethernet-phy@8 {
67 interrupt-parent = <&mpic>; 68 interrupt-parent = <&mpic>;
68 interrupts = <2 1>; 69 interrupts = <2 1>;
69 reg = <8>; 70 reg = <0x8>;
70 }; 71 };
71 72
72 phy9: ethernet-phy@9 { 73 phy9: ethernet-phy@9 {
73 interrupt-parent = <&mpic>; 74 interrupt-parent = <&mpic>;
74 interrupts = <2 1>; 75 interrupts = <2 1>;
75 reg = <9>; 76 reg = <0x9>;
76 }; 77 };
77 78
78 }; 79 };
@@ -82,9 +83,9 @@
82 #size-cells = <0>; 83 #size-cells = <0>;
83 device_type = "network"; 84 device_type = "network";
84 compatible = "tsi108-ethernet"; 85 compatible = "tsi108-ethernet";
85 reg = <6000 200>; 86 reg = <0x6000 0x200>;
86 address = [ 00 06 D2 00 00 01 ]; 87 address = [ 00 06 D2 00 00 01 ];
87 interrupts = <10 2>; 88 interrupts = <16 2>;
88 interrupt-parent = <&mpic>; 89 interrupt-parent = <&mpic>;
89 mdio-handle = <&MDIO>; 90 mdio-handle = <&MDIO>;
90 phy-handle = <&phy8>; 91 phy-handle = <&phy8>;
@@ -96,9 +97,9 @@
96 #size-cells = <0>; 97 #size-cells = <0>;
97 device_type = "network"; 98 device_type = "network";
98 compatible = "tsi108-ethernet"; 99 compatible = "tsi108-ethernet";
99 reg = <6400 200>; 100 reg = <0x6400 0x200>;
100 address = [ 00 06 D2 00 00 02 ]; 101 address = [ 00 06 D2 00 00 02 ];
101 interrupts = <11 2>; 102 interrupts = <17 2>;
102 interrupt-parent = <&mpic>; 103 interrupt-parent = <&mpic>;
103 mdio-handle = <&MDIO>; 104 mdio-handle = <&MDIO>;
104 phy-handle = <&phy9>; 105 phy-handle = <&phy9>;
@@ -107,18 +108,18 @@
107 serial@7808 { 108 serial@7808 {
108 device_type = "serial"; 109 device_type = "serial";
109 compatible = "ns16550"; 110 compatible = "ns16550";
110 reg = <7808 200>; 111 reg = <0x7808 0x200>;
111 clock-frequency = <3f6b5a00>; 112 clock-frequency = <1064000000>;
112 interrupts = <c 0>; 113 interrupts = <12 0>;
113 interrupt-parent = <&mpic>; 114 interrupt-parent = <&mpic>;
114 }; 115 };
115 116
116 serial@7c08 { 117 serial@7c08 {
117 device_type = "serial"; 118 device_type = "serial";
118 compatible = "ns16550"; 119 compatible = "ns16550";
119 reg = <7c08 200>; 120 reg = <0x7c08 0x200>;
120 clock-frequency = <3f6b5a00>; 121 clock-frequency = <1064000000>;
121 interrupts = <d 0>; 122 interrupts = <13 0>;
122 interrupt-parent = <&mpic>; 123 interrupt-parent = <&mpic>;
123 }; 124 };
124 125
@@ -127,7 +128,7 @@
127 interrupt-controller; 128 interrupt-controller;
128 #address-cells = <0>; 129 #address-cells = <0>;
129 #interrupt-cells = <2>; 130 #interrupt-cells = <2>;
130 reg = <7400 400>; 131 reg = <0x7400 0x400>;
131 compatible = "chrp,open-pic"; 132 compatible = "chrp,open-pic";
132 device_type = "open-pic"; 133 device_type = "open-pic";
133 big-endian; 134 big-endian;
@@ -138,39 +139,39 @@
138 #interrupt-cells = <1>; 139 #interrupt-cells = <1>;
139 #size-cells = <2>; 140 #size-cells = <2>;
140 #address-cells = <3>; 141 #address-cells = <3>;
141 reg = <1000 1000>; 142 reg = <0x1000 0x1000>;
142 bus-range = <0 0>; 143 bus-range = <0 0>;
143 ranges = <02000000 0 e0000000 e0000000 0 1A000000 144 ranges = <0x2000000 0x0 0xe0000000 0xe0000000 0x0 0x1a000000
144 01000000 0 00000000 fa000000 0 00010000>; 145 0x1000000 0x0 0x0 0xfa000000 0x0 0x10000>;
145 clock-frequency = <7f28154>; 146 clock-frequency = <133333332>;
146 interrupt-parent = <&mpic>; 147 interrupt-parent = <&mpic>;
147 interrupts = <17 2>; 148 interrupts = <23 2>;
148 interrupt-map-mask = <f800 0 0 7>; 149 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
149 interrupt-map = < 150 interrupt-map = <
150 151
151 /* IDSEL 0x11 */ 152 /* IDSEL 0x11 */
152 0800 0 0 1 &RT0 24 0 153 0x800 0x0 0x0 0x1 &RT0 0x24 0x0
153 0800 0 0 2 &RT0 25 0 154 0x800 0x0 0x0 0x2 &RT0 0x25 0x0
154 0800 0 0 3 &RT0 26 0 155 0x800 0x0 0x0 0x3 &RT0 0x26 0x0
155 0800 0 0 4 &RT0 27 0 156 0x800 0x0 0x0 0x4 &RT0 0x27 0x0
156 157
157 /* IDSEL 0x12 */ 158 /* IDSEL 0x12 */
158 1000 0 0 1 &RT0 25 0 159 0x1000 0x0 0x0 0x1 &RT0 0x25 0x0
159 1000 0 0 2 &RT0 26 0 160 0x1000 0x0 0x0 0x2 &RT0 0x26 0x0
160 1000 0 0 3 &RT0 27 0 161 0x1000 0x0 0x0 0x3 &RT0 0x27 0x0
161 1000 0 0 4 &RT0 24 0 162 0x1000 0x0 0x0 0x4 &RT0 0x24 0x0
162 163
163 /* IDSEL 0x13 */ 164 /* IDSEL 0x13 */
164 1800 0 0 1 &RT0 26 0 165 0x1800 0x0 0x0 0x1 &RT0 0x26 0x0
165 1800 0 0 2 &RT0 27 0 166 0x1800 0x0 0x0 0x2 &RT0 0x27 0x0
166 1800 0 0 3 &RT0 24 0 167 0x1800 0x0 0x0 0x3 &RT0 0x24 0x0
167 1800 0 0 4 &RT0 25 0 168 0x1800 0x0 0x0 0x4 &RT0 0x25 0x0
168 169
169 /* IDSEL 0x14 */ 170 /* IDSEL 0x14 */
170 2000 0 0 1 &RT0 27 0 171 0x2000 0x0 0x0 0x1 &RT0 0x27 0x0
171 2000 0 0 2 &RT0 24 0 172 0x2000 0x0 0x0 0x2 &RT0 0x24 0x0
172 2000 0 0 3 &RT0 25 0 173 0x2000 0x0 0x0 0x3 &RT0 0x25 0x0
173 2000 0 0 4 &RT0 26 0 174 0x2000 0x0 0x0 0x4 &RT0 0x26 0x0
174 >; 175 >;
175 176
176 RT0: router@1180 { 177 RT0: router@1180 {
@@ -180,7 +181,7 @@
180 #address-cells = <0>; 181 #address-cells = <0>;
181 #interrupt-cells = <2>; 182 #interrupt-cells = <2>;
182 big-endian; 183 big-endian;
183 interrupts = <17 2>; 184 interrupts = <23 2>;
184 interrupt-parent = <&mpic>; 185 interrupt-parent = <&mpic>;
185 }; 186 };
186 }; 187 };
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-12 14:06:47 -0500