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authorGrant Likely <grant.likely@secretlab.ca>2008-04-29 09:19:07 -0400
committerGrant Likely <grant.likely@secretlab.ca>2008-04-29 09:19:07 -0400
commita2884f37b6fe0074df70ebeb3a6c54201267663c (patch)
tree5a4eec613f670d05a380d9190ae521aa480e4652 /arch/powerpc/boot/dts/lite5200b.dts
parent8f3ba2dc811228213bcbdc2c8b389a8d6fa66c09 (diff)
[POWERPC] mpc5200: Switch mpc5200 dts files to dts-v1 format
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
Diffstat (limited to 'arch/powerpc/boot/dts/lite5200b.dts')
-rw-r--r--arch/powerpc/boot/dts/lite5200b.dts146
1 files changed, 71 insertions, 75 deletions
diff --git a/arch/powerpc/boot/dts/lite5200b.dts b/arch/powerpc/boot/dts/lite5200b.dts
index 2e9bc397ae9a..7bd5b9c399b8 100644
--- a/arch/powerpc/boot/dts/lite5200b.dts
+++ b/arch/powerpc/boot/dts/lite5200b.dts
@@ -10,11 +10,7 @@
10 * option) any later version. 10 * option) any later version.
11 */ 11 */
12 12
13/* 13/dts-v1/;
14 * WARNING: Do not depend on this tree layout remaining static just yet.
15 * The MPC5200 device tree conventions are still in flux
16 * Keep an eye on the linuxppc-dev mailing list for more details
17 */
18 14
19/ { 15/ {
20 model = "fsl,lite5200b"; 16 model = "fsl,lite5200b";
@@ -29,10 +25,10 @@
29 PowerPC,5200@0 { 25 PowerPC,5200@0 {
30 device_type = "cpu"; 26 device_type = "cpu";
31 reg = <0>; 27 reg = <0>;
32 d-cache-line-size = <20>; 28 d-cache-line-size = <32>;
33 i-cache-line-size = <20>; 29 i-cache-line-size = <32>;
34 d-cache-size = <4000>; // L1, 16K 30 d-cache-size = <0x4000>; // L1, 16K
35 i-cache-size = <4000>; // L1, 16K 31 i-cache-size = <0x4000>; // L1, 16K
36 timebase-frequency = <0>; // from bootloader 32 timebase-frequency = <0>; // from bootloader
37 bus-frequency = <0>; // from bootloader 33 bus-frequency = <0>; // from bootloader
38 clock-frequency = <0>; // from bootloader 34 clock-frequency = <0>; // from bootloader
@@ -41,21 +37,21 @@
41 37
42 memory { 38 memory {
43 device_type = "memory"; 39 device_type = "memory";
44 reg = <00000000 10000000>; // 256MB 40 reg = <0x00000000 0x10000000>; // 256MB
45 }; 41 };
46 42
47 soc5200@f0000000 { 43 soc5200@f0000000 {
48 #address-cells = <1>; 44 #address-cells = <1>;
49 #size-cells = <1>; 45 #size-cells = <1>;
50 compatible = "fsl,mpc5200b-immr"; 46 compatible = "fsl,mpc5200b-immr";
51 ranges = <0 f0000000 0000c000>; 47 ranges = <0 0xf0000000 0x0000c000>;
52 reg = <f0000000 00000100>; 48 reg = <0xf0000000 0x00000100>;
53 bus-frequency = <0>; // from bootloader 49 bus-frequency = <0>; // from bootloader
54 system-frequency = <0>; // from bootloader 50 system-frequency = <0>; // from bootloader
55 51
56 cdm@200 { 52 cdm@200 {
57 compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm"; 53 compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm";
58 reg = <200 38>; 54 reg = <0x200 0x38>;
59 }; 55 };
60 56
61 mpc5200_pic: interrupt-controller@500 { 57 mpc5200_pic: interrupt-controller@500 {
@@ -64,13 +60,13 @@
64 #interrupt-cells = <3>; 60 #interrupt-cells = <3>;
65 device_type = "interrupt-controller"; 61 device_type = "interrupt-controller";
66 compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic"; 62 compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic";
67 reg = <500 80>; 63 reg = <0x500 0x80>;
68 }; 64 };
69 65
70 timer@600 { // General Purpose Timer 66 timer@600 { // General Purpose Timer
71 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 67 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
72 cell-index = <0>; 68 cell-index = <0>;
73 reg = <600 10>; 69 reg = <0x600 0x10>;
74 interrupts = <1 9 0>; 70 interrupts = <1 9 0>;
75 interrupt-parent = <&mpc5200_pic>; 71 interrupt-parent = <&mpc5200_pic>;
76 fsl,has-wdt; 72 fsl,has-wdt;
@@ -79,63 +75,63 @@
79 timer@610 { // General Purpose Timer 75 timer@610 { // General Purpose Timer
80 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 76 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
81 cell-index = <1>; 77 cell-index = <1>;
82 reg = <610 10>; 78 reg = <0x610 0x10>;
83 interrupts = <1 a 0>; 79 interrupts = <1 10 0>;
84 interrupt-parent = <&mpc5200_pic>; 80 interrupt-parent = <&mpc5200_pic>;
85 }; 81 };
86 82
87 timer@620 { // General Purpose Timer 83 timer@620 { // General Purpose Timer
88 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 84 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
89 cell-index = <2>; 85 cell-index = <2>;
90 reg = <620 10>; 86 reg = <0x620 0x10>;
91 interrupts = <1 b 0>; 87 interrupts = <1 11 0>;
92 interrupt-parent = <&mpc5200_pic>; 88 interrupt-parent = <&mpc5200_pic>;
93 }; 89 };
94 90
95 timer@630 { // General Purpose Timer 91 timer@630 { // General Purpose Timer
96 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 92 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
97 cell-index = <3>; 93 cell-index = <3>;
98 reg = <630 10>; 94 reg = <0x630 0x10>;
99 interrupts = <1 c 0>; 95 interrupts = <1 12 0>;
100 interrupt-parent = <&mpc5200_pic>; 96 interrupt-parent = <&mpc5200_pic>;
101 }; 97 };
102 98
103 timer@640 { // General Purpose Timer 99 timer@640 { // General Purpose Timer
104 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 100 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
105 cell-index = <4>; 101 cell-index = <4>;
106 reg = <640 10>; 102 reg = <0x640 0x10>;
107 interrupts = <1 d 0>; 103 interrupts = <1 13 0>;
108 interrupt-parent = <&mpc5200_pic>; 104 interrupt-parent = <&mpc5200_pic>;
109 }; 105 };
110 106
111 timer@650 { // General Purpose Timer 107 timer@650 { // General Purpose Timer
112 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 108 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
113 cell-index = <5>; 109 cell-index = <5>;
114 reg = <650 10>; 110 reg = <0x650 0x10>;
115 interrupts = <1 e 0>; 111 interrupts = <1 14 0>;
116 interrupt-parent = <&mpc5200_pic>; 112 interrupt-parent = <&mpc5200_pic>;
117 }; 113 };
118 114
119 timer@660 { // General Purpose Timer 115 timer@660 { // General Purpose Timer
120 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 116 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
121 cell-index = <6>; 117 cell-index = <6>;
122 reg = <660 10>; 118 reg = <0x660 0x10>;
123 interrupts = <1 f 0>; 119 interrupts = <1 15 0>;
124 interrupt-parent = <&mpc5200_pic>; 120 interrupt-parent = <&mpc5200_pic>;
125 }; 121 };
126 122
127 timer@670 { // General Purpose Timer 123 timer@670 { // General Purpose Timer
128 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 124 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
129 cell-index = <7>; 125 cell-index = <7>;
130 reg = <670 10>; 126 reg = <0x670 0x10>;
131 interrupts = <1 10 0>; 127 interrupts = <1 16 0>;
132 interrupt-parent = <&mpc5200_pic>; 128 interrupt-parent = <&mpc5200_pic>;
133 }; 129 };
134 130
135 rtc@800 { // Real time clock 131 rtc@800 { // Real time clock
136 compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc"; 132 compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc";
137 device_type = "rtc"; 133 device_type = "rtc";
138 reg = <800 100>; 134 reg = <0x800 0x100>;
139 interrupts = <1 5 0 1 6 0>; 135 interrupts = <1 5 0 1 6 0>;
140 interrupt-parent = <&mpc5200_pic>; 136 interrupt-parent = <&mpc5200_pic>;
141 }; 137 };
@@ -143,43 +139,43 @@
143 can@900 { 139 can@900 {
144 compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan"; 140 compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
145 cell-index = <0>; 141 cell-index = <0>;
146 interrupts = <2 11 0>; 142 interrupts = <2 17 0>;
147 interrupt-parent = <&mpc5200_pic>; 143 interrupt-parent = <&mpc5200_pic>;
148 reg = <900 80>; 144 reg = <0x900 0x80>;
149 }; 145 };
150 146
151 can@980 { 147 can@980 {
152 compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan"; 148 compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
153 cell-index = <1>; 149 cell-index = <1>;
154 interrupts = <2 12 0>; 150 interrupts = <2 18 0>;
155 interrupt-parent = <&mpc5200_pic>; 151 interrupt-parent = <&mpc5200_pic>;
156 reg = <980 80>; 152 reg = <0x980 0x80>;
157 }; 153 };
158 154
159 gpio@b00 { 155 gpio@b00 {
160 compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio"; 156 compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio";
161 reg = <b00 40>; 157 reg = <0xb00 0x40>;
162 interrupts = <1 7 0>; 158 interrupts = <1 7 0>;
163 interrupt-parent = <&mpc5200_pic>; 159 interrupt-parent = <&mpc5200_pic>;
164 }; 160 };
165 161
166 gpio@c00 { 162 gpio@c00 {
167 compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup"; 163 compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup";
168 reg = <c00 40>; 164 reg = <0xc00 0x40>;
169 interrupts = <1 8 0 0 3 0>; 165 interrupts = <1 8 0 0 3 0>;
170 interrupt-parent = <&mpc5200_pic>; 166 interrupt-parent = <&mpc5200_pic>;
171 }; 167 };
172 168
173 spi@f00 { 169 spi@f00 {
174 compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi"; 170 compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
175 reg = <f00 20>; 171 reg = <0xf00 0x20>;
176 interrupts = <2 d 0 2 e 0>; 172 interrupts = <2 13 0 2 14 0>;
177 interrupt-parent = <&mpc5200_pic>; 173 interrupt-parent = <&mpc5200_pic>;
178 }; 174 };
179 175
180 usb@1000 { 176 usb@1000 {
181 compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be"; 177 compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be";
182 reg = <1000 ff>; 178 reg = <0x1000 0xff>;
183 interrupts = <2 6 0>; 179 interrupts = <2 6 0>;
184 interrupt-parent = <&mpc5200_pic>; 180 interrupt-parent = <&mpc5200_pic>;
185 }; 181 };
@@ -187,17 +183,17 @@
187 dma-controller@1200 { 183 dma-controller@1200 {
188 device_type = "dma-controller"; 184 device_type = "dma-controller";
189 compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm"; 185 compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm";
190 reg = <1200 80>; 186 reg = <0x1200 0x80>;
191 interrupts = <3 0 0 3 1 0 3 2 0 3 3 0 187 interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
192 3 4 0 3 5 0 3 6 0 3 7 0 188 3 4 0 3 5 0 3 6 0 3 7 0
193 3 8 0 3 9 0 3 a 0 3 b 0 189 3 8 0 3 9 0 3 10 0 3 11 0
194 3 c 0 3 d 0 3 e 0 3 f 0>; 190 3 12 0 3 13 0 3 14 0 3 15 0>;
195 interrupt-parent = <&mpc5200_pic>; 191 interrupt-parent = <&mpc5200_pic>;
196 }; 192 };
197 193
198 xlb@1f00 { 194 xlb@1f00 {
199 compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb"; 195 compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb";
200 reg = <1f00 100>; 196 reg = <0x1f00 0x100>;
201 }; 197 };
202 198
203 serial@2000 { // PSC1 199 serial@2000 { // PSC1
@@ -205,7 +201,7 @@
205 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; 201 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
206 port-number = <0>; // Logical port assignment 202 port-number = <0>; // Logical port assignment
207 cell-index = <0>; 203 cell-index = <0>;
208 reg = <2000 100>; 204 reg = <0x2000 0x100>;
209 interrupts = <2 1 0>; 205 interrupts = <2 1 0>;
210 interrupt-parent = <&mpc5200_pic>; 206 interrupt-parent = <&mpc5200_pic>;
211 }; 207 };
@@ -214,7 +210,7 @@
214 //ac97@2200 { // PSC2 210 //ac97@2200 { // PSC2
215 // compatible = "fsl,mpc5200b-psc-ac97","fsl,mpc5200-psc-ac97"; 211 // compatible = "fsl,mpc5200b-psc-ac97","fsl,mpc5200-psc-ac97";
216 // cell-index = <1>; 212 // cell-index = <1>;
217 // reg = <2200 100>; 213 // reg = <0x2200 0x100>;
218 // interrupts = <2 2 0>; 214 // interrupts = <2 2 0>;
219 // interrupt-parent = <&mpc5200_pic>; 215 // interrupt-parent = <&mpc5200_pic>;
220 //}; 216 //};
@@ -223,7 +219,7 @@
223 //i2s@2400 { // PSC3 219 //i2s@2400 { // PSC3
224 // compatible = "fsl,mpc5200b-psc-i2s"; //not 5200 compatible 220 // compatible = "fsl,mpc5200b-psc-i2s"; //not 5200 compatible
225 // cell-index = <2>; 221 // cell-index = <2>;
226 // reg = <2400 100>; 222 // reg = <0x2400 0x100>;
227 // interrupts = <2 3 0>; 223 // interrupts = <2 3 0>;
228 // interrupt-parent = <&mpc5200_pic>; 224 // interrupt-parent = <&mpc5200_pic>;
229 //}; 225 //};
@@ -233,8 +229,8 @@
233 // device_type = "serial"; 229 // device_type = "serial";
234 // compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; 230 // compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
235 // cell-index = <3>; 231 // cell-index = <3>;
236 // reg = <2600 100>; 232 // reg = <0x2600 0x100>;
237 // interrupts = <2 b 0>; 233 // interrupts = <2 11 0>;
238 // interrupt-parent = <&mpc5200_pic>; 234 // interrupt-parent = <&mpc5200_pic>;
239 //}; 235 //};
240 236
@@ -243,8 +239,8 @@
243 // device_type = "serial"; 239 // device_type = "serial";
244 // compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; 240 // compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
245 // cell-index = <4>; 241 // cell-index = <4>;
246 // reg = <2800 100>; 242 // reg = <0x2800 0x100>;
247 // interrupts = <2 c 0>; 243 // interrupts = <2 12 0>;
248 // interrupt-parent = <&mpc5200_pic>; 244 // interrupt-parent = <&mpc5200_pic>;
249 //}; 245 //};
250 246
@@ -252,7 +248,7 @@
252 //spi@2c00 { // PSC6 248 //spi@2c00 { // PSC6
253 // compatible = "fsl,mpc5200b-psc-spi","fsl,mpc5200-psc-spi"; 249 // compatible = "fsl,mpc5200b-psc-spi","fsl,mpc5200-psc-spi";
254 // cell-index = <5>; 250 // cell-index = <5>;
255 // reg = <2c00 100>; 251 // reg = <0x2c00 0x100>;
256 // interrupts = <2 4 0>; 252 // interrupts = <2 4 0>;
257 // interrupt-parent = <&mpc5200_pic>; 253 // interrupt-parent = <&mpc5200_pic>;
258 //}; 254 //};
@@ -260,7 +256,7 @@
260 ethernet@3000 { 256 ethernet@3000 {
261 device_type = "network"; 257 device_type = "network";
262 compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec"; 258 compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
263 reg = <3000 400>; 259 reg = <0x3000 0x400>;
264 local-mac-address = [ 00 00 00 00 00 00 ]; 260 local-mac-address = [ 00 00 00 00 00 00 ];
265 interrupts = <2 5 0>; 261 interrupts = <2 5 0>;
266 interrupt-parent = <&mpc5200_pic>; 262 interrupt-parent = <&mpc5200_pic>;
@@ -271,11 +267,11 @@
271 #address-cells = <1>; 267 #address-cells = <1>;
272 #size-cells = <0>; 268 #size-cells = <0>;
273 compatible = "fsl,mpc5200b-mdio", "fsl,mpc5200-mdio"; 269 compatible = "fsl,mpc5200b-mdio", "fsl,mpc5200-mdio";
274 reg = <3000 400>; // fec range, since we need to setup fec interrupts 270 reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
275 interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co. 271 interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
276 interrupt-parent = <&mpc5200_pic>; 272 interrupt-parent = <&mpc5200_pic>;
277 273
278 phy0:ethernet-phy@0 { 274 phy0: ethernet-phy@0 {
279 device_type = "ethernet-phy"; 275 device_type = "ethernet-phy";
280 reg = <0>; 276 reg = <0>;
281 }; 277 };
@@ -284,7 +280,7 @@
284 ata@3a00 { 280 ata@3a00 {
285 device_type = "ata"; 281 device_type = "ata";
286 compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata"; 282 compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata";
287 reg = <3a00 100>; 283 reg = <0x3a00 0x100>;
288 interrupts = <2 7 0>; 284 interrupts = <2 7 0>;
289 interrupt-parent = <&mpc5200_pic>; 285 interrupt-parent = <&mpc5200_pic>;
290 }; 286 };
@@ -294,8 +290,8 @@
294 #size-cells = <0>; 290 #size-cells = <0>;
295 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c"; 291 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
296 cell-index = <0>; 292 cell-index = <0>;
297 reg = <3d00 40>; 293 reg = <0x3d00 0x40>;
298 interrupts = <2 f 0>; 294 interrupts = <2 15 0>;
299 interrupt-parent = <&mpc5200_pic>; 295 interrupt-parent = <&mpc5200_pic>;
300 fsl5200-clocking; 296 fsl5200-clocking;
301 }; 297 };
@@ -305,14 +301,14 @@
305 #size-cells = <0>; 301 #size-cells = <0>;
306 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c"; 302 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
307 cell-index = <1>; 303 cell-index = <1>;
308 reg = <3d40 40>; 304 reg = <0x3d40 0x40>;
309 interrupts = <2 10 0>; 305 interrupts = <2 16 0>;
310 interrupt-parent = <&mpc5200_pic>; 306 interrupt-parent = <&mpc5200_pic>;
311 fsl5200-clocking; 307 fsl5200-clocking;
312 }; 308 };
313 sram@8000 { 309 sram@8000 {
314 compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram","sram"; 310 compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram","sram";
315 reg = <8000 4000>; 311 reg = <0x8000 0x4000>;
316 }; 312 };
317 }; 313 };
318 314
@@ -322,23 +318,23 @@
322 #address-cells = <3>; 318 #address-cells = <3>;
323 device_type = "pci"; 319 device_type = "pci";
324 compatible = "fsl,mpc5200b-pci","fsl,mpc5200-pci"; 320 compatible = "fsl,mpc5200b-pci","fsl,mpc5200-pci";
325 reg = <f0000d00 100>; 321 reg = <0xf0000d00 0x100>;
326 interrupt-map-mask = <f800 0 0 7>; 322 interrupt-map-mask = <0xf800 0 0 7>;
327 interrupt-map = <c000 0 0 1 &mpc5200_pic 0 0 3 // 1st slot 323 interrupt-map = <0xc000 0 0 1 &mpc5200_pic 0 0 3 // 1st slot
328 c000 0 0 2 &mpc5200_pic 1 1 3 324 0xc000 0 0 2 &mpc5200_pic 1 1 3
329 c000 0 0 3 &mpc5200_pic 1 2 3 325 0xc000 0 0 3 &mpc5200_pic 1 2 3
330 c000 0 0 4 &mpc5200_pic 1 3 3 326 0xc000 0 0 4 &mpc5200_pic 1 3 3
331 327
332 c800 0 0 1 &mpc5200_pic 1 1 3 // 2nd slot 328 0xc800 0 0 1 &mpc5200_pic 1 1 3 // 2nd slot
333 c800 0 0 2 &mpc5200_pic 1 2 3 329 0xc800 0 0 2 &mpc5200_pic 1 2 3
334 c800 0 0 3 &mpc5200_pic 1 3 3 330 0xc800 0 0 3 &mpc5200_pic 1 3 3
335 c800 0 0 4 &mpc5200_pic 0 0 3>; 331 0xc800 0 0 4 &mpc5200_pic 0 0 3>;
336 clock-frequency = <0>; // From boot loader 332 clock-frequency = <0>; // From boot loader
337 interrupts = <2 8 0 2 9 0 2 a 0>; 333 interrupts = <2 8 0 2 9 0 2 10 0>;
338 interrupt-parent = <&mpc5200_pic>; 334 interrupt-parent = <&mpc5200_pic>;
339 bus-range = <0 0>; 335 bus-range = <0 0>;
340 ranges = <42000000 0 80000000 80000000 0 20000000 336 ranges = <0x42000000 0 0x80000000 0x80000000 0 0x20000000
341 02000000 0 a0000000 a0000000 0 10000000 337 0x02000000 0 0xa0000000 0xa0000000 0 0x10000000
342 01000000 0 00000000 b0000000 0 01000000>; 338 0x01000000 0 0x00000000 0xb0000000 0 0x01000000>;
343 }; 339 };
344}; 340};
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-26 17:39:57 -0500