diff options
author | Grant Likely <grant.likely@secretlab.ca> | 2009-02-03 14:30:26 -0500 |
---|---|---|
committer | Grant Likely <grant.likely@secretlab.ca> | 2009-02-03 14:30:26 -0500 |
commit | b8842451079a3034363320b932205d9cea791e9d (patch) | |
tree | 0b8b0e2f2b2a244501dd9956803635136ba60ab0 /arch/powerpc/boot/dts/lite5200b.dts | |
parent | 3b5ebf8e1ac88babf60772d54bc81b180b5f53b0 (diff) |
powerpc/5200: Trim cruft from device trees
Trim out obsolete/extraneous properties and tighten up some usage
conventions. Changes include:
- removal of device_type properties
- removal of cell-index properties
- Addition of gpio-controller and #gpio-cells properties to gpio
nodes
- Move common interrupt-parent property out of device nodes and
into top level parent node.
This patch also include what looks to be just trivial editorial
whitespace/format changes, but there is real method in this
madness. Editorial changes were made to keep the all the
mpc5200 board device trees as similar as possible so that diffs
between them only show the real differences between the boards.
The pcm030 device tree was most affected by this because many
of the comments had been changed from // to /* */ style and
some cell values where changed from decimal to hex format when
it was cloned from one of the other 5200 device trees.
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
Reviewed-by: Wolfram Sang <w.sang@pengutronix.de>
Diffstat (limited to 'arch/powerpc/boot/dts/lite5200b.dts')
-rw-r--r-- | arch/powerpc/boot/dts/lite5200b.dts | 63 |
1 files changed, 10 insertions, 53 deletions
diff --git a/arch/powerpc/boot/dts/lite5200b.dts b/arch/powerpc/boot/dts/lite5200b.dts index 63e3bb48e843..c63e3566479e 100644 --- a/arch/powerpc/boot/dts/lite5200b.dts +++ b/arch/powerpc/boot/dts/lite5200b.dts | |||
@@ -17,6 +17,7 @@ | |||
17 | compatible = "fsl,lite5200b"; | 17 | compatible = "fsl,lite5200b"; |
18 | #address-cells = <1>; | 18 | #address-cells = <1>; |
19 | #size-cells = <1>; | 19 | #size-cells = <1>; |
20 | interrupt-parent = <&mpc5200_pic>; | ||
20 | 21 | ||
21 | cpus { | 22 | cpus { |
22 | #address-cells = <1>; | 23 | #address-cells = <1>; |
@@ -58,136 +59,112 @@ | |||
58 | // 5200 interrupts are encoded into two levels; | 59 | // 5200 interrupts are encoded into two levels; |
59 | interrupt-controller; | 60 | interrupt-controller; |
60 | #interrupt-cells = <3>; | 61 | #interrupt-cells = <3>; |
61 | device_type = "interrupt-controller"; | ||
62 | compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic"; | 62 | compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic"; |
63 | reg = <0x500 0x80>; | 63 | reg = <0x500 0x80>; |
64 | }; | 64 | }; |
65 | 65 | ||
66 | timer@600 { // General Purpose Timer | 66 | timer@600 { // General Purpose Timer |
67 | compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; | 67 | compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; |
68 | cell-index = <0>; | ||
69 | reg = <0x600 0x10>; | 68 | reg = <0x600 0x10>; |
70 | interrupts = <1 9 0>; | 69 | interrupts = <1 9 0>; |
71 | interrupt-parent = <&mpc5200_pic>; | ||
72 | fsl,has-wdt; | 70 | fsl,has-wdt; |
73 | }; | 71 | }; |
74 | 72 | ||
75 | timer@610 { // General Purpose Timer | 73 | timer@610 { // General Purpose Timer |
76 | compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; | 74 | compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; |
77 | cell-index = <1>; | ||
78 | reg = <0x610 0x10>; | 75 | reg = <0x610 0x10>; |
79 | interrupts = <1 10 0>; | 76 | interrupts = <1 10 0>; |
80 | interrupt-parent = <&mpc5200_pic>; | ||
81 | }; | 77 | }; |
82 | 78 | ||
83 | timer@620 { // General Purpose Timer | 79 | timer@620 { // General Purpose Timer |
84 | compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; | 80 | compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; |
85 | cell-index = <2>; | ||
86 | reg = <0x620 0x10>; | 81 | reg = <0x620 0x10>; |
87 | interrupts = <1 11 0>; | 82 | interrupts = <1 11 0>; |
88 | interrupt-parent = <&mpc5200_pic>; | ||
89 | }; | 83 | }; |
90 | 84 | ||
91 | timer@630 { // General Purpose Timer | 85 | timer@630 { // General Purpose Timer |
92 | compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; | 86 | compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; |
93 | cell-index = <3>; | ||
94 | reg = <0x630 0x10>; | 87 | reg = <0x630 0x10>; |
95 | interrupts = <1 12 0>; | 88 | interrupts = <1 12 0>; |
96 | interrupt-parent = <&mpc5200_pic>; | ||
97 | }; | 89 | }; |
98 | 90 | ||
99 | timer@640 { // General Purpose Timer | 91 | timer@640 { // General Purpose Timer |
100 | compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; | 92 | compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; |
101 | cell-index = <4>; | ||
102 | reg = <0x640 0x10>; | 93 | reg = <0x640 0x10>; |
103 | interrupts = <1 13 0>; | 94 | interrupts = <1 13 0>; |
104 | interrupt-parent = <&mpc5200_pic>; | ||
105 | }; | 95 | }; |
106 | 96 | ||
107 | timer@650 { // General Purpose Timer | 97 | timer@650 { // General Purpose Timer |
108 | compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; | 98 | compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; |
109 | cell-index = <5>; | ||
110 | reg = <0x650 0x10>; | 99 | reg = <0x650 0x10>; |
111 | interrupts = <1 14 0>; | 100 | interrupts = <1 14 0>; |
112 | interrupt-parent = <&mpc5200_pic>; | ||
113 | }; | 101 | }; |
114 | 102 | ||
115 | timer@660 { // General Purpose Timer | 103 | timer@660 { // General Purpose Timer |
116 | compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; | 104 | compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; |
117 | cell-index = <6>; | ||
118 | reg = <0x660 0x10>; | 105 | reg = <0x660 0x10>; |
119 | interrupts = <1 15 0>; | 106 | interrupts = <1 15 0>; |
120 | interrupt-parent = <&mpc5200_pic>; | ||
121 | }; | 107 | }; |
122 | 108 | ||
123 | timer@670 { // General Purpose Timer | 109 | timer@670 { // General Purpose Timer |
124 | compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; | 110 | compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; |
125 | cell-index = <7>; | ||
126 | reg = <0x670 0x10>; | 111 | reg = <0x670 0x10>; |
127 | interrupts = <1 16 0>; | 112 | interrupts = <1 16 0>; |
128 | interrupt-parent = <&mpc5200_pic>; | ||
129 | }; | 113 | }; |
130 | 114 | ||
131 | rtc@800 { // Real time clock | 115 | rtc@800 { // Real time clock |
132 | compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc"; | 116 | compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc"; |
133 | reg = <0x800 0x100>; | 117 | reg = <0x800 0x100>; |
134 | interrupts = <1 5 0 1 6 0>; | 118 | interrupts = <1 5 0 1 6 0>; |
135 | interrupt-parent = <&mpc5200_pic>; | ||
136 | }; | 119 | }; |
137 | 120 | ||
138 | can@900 { | 121 | can@900 { |
139 | compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan"; | 122 | compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan"; |
140 | cell-index = <0>; | ||
141 | interrupts = <2 17 0>; | 123 | interrupts = <2 17 0>; |
142 | interrupt-parent = <&mpc5200_pic>; | ||
143 | reg = <0x900 0x80>; | 124 | reg = <0x900 0x80>; |
144 | }; | 125 | }; |
145 | 126 | ||
146 | can@980 { | 127 | can@980 { |
147 | compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan"; | 128 | compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan"; |
148 | cell-index = <1>; | ||
149 | interrupts = <2 18 0>; | 129 | interrupts = <2 18 0>; |
150 | interrupt-parent = <&mpc5200_pic>; | ||
151 | reg = <0x980 0x80>; | 130 | reg = <0x980 0x80>; |
152 | }; | 131 | }; |
153 | 132 | ||
154 | gpio@b00 { | 133 | gpio_simple: gpio@b00 { |
155 | compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio"; | 134 | compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio"; |
156 | reg = <0xb00 0x40>; | 135 | reg = <0xb00 0x40>; |
157 | interrupts = <1 7 0>; | 136 | interrupts = <1 7 0>; |
158 | interrupt-parent = <&mpc5200_pic>; | 137 | gpio-controller; |
138 | #gpio-cells = <2>; | ||
159 | }; | 139 | }; |
160 | 140 | ||
161 | gpio@c00 { | 141 | gpio_wkup: gpio@c00 { |
162 | compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup"; | 142 | compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup"; |
163 | reg = <0xc00 0x40>; | 143 | reg = <0xc00 0x40>; |
164 | interrupts = <1 8 0 0 3 0>; | 144 | interrupts = <1 8 0 0 3 0>; |
165 | interrupt-parent = <&mpc5200_pic>; | 145 | gpio-controller; |
146 | #gpio-cells = <2>; | ||
166 | }; | 147 | }; |
167 | 148 | ||
168 | spi@f00 { | 149 | spi@f00 { |
169 | compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi"; | 150 | compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi"; |
170 | reg = <0xf00 0x20>; | 151 | reg = <0xf00 0x20>; |
171 | interrupts = <2 13 0 2 14 0>; | 152 | interrupts = <2 13 0 2 14 0>; |
172 | interrupt-parent = <&mpc5200_pic>; | ||
173 | }; | 153 | }; |
174 | 154 | ||
175 | usb@1000 { | 155 | usb@1000 { |
176 | compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be"; | 156 | compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be"; |
177 | reg = <0x1000 0xff>; | 157 | reg = <0x1000 0xff>; |
178 | interrupts = <2 6 0>; | 158 | interrupts = <2 6 0>; |
179 | interrupt-parent = <&mpc5200_pic>; | ||
180 | }; | 159 | }; |
181 | 160 | ||
182 | dma-controller@1200 { | 161 | dma-controller@1200 { |
183 | device_type = "dma-controller"; | ||
184 | compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm"; | 162 | compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm"; |
185 | reg = <0x1200 0x80>; | 163 | reg = <0x1200 0x80>; |
186 | interrupts = <3 0 0 3 1 0 3 2 0 3 3 0 | 164 | interrupts = <3 0 0 3 1 0 3 2 0 3 3 0 |
187 | 3 4 0 3 5 0 3 6 0 3 7 0 | 165 | 3 4 0 3 5 0 3 6 0 3 7 0 |
188 | 3 8 0 3 9 0 3 10 0 3 11 0 | 166 | 3 8 0 3 9 0 3 10 0 3 11 0 |
189 | 3 12 0 3 13 0 3 14 0 3 15 0>; | 167 | 3 12 0 3 13 0 3 14 0 3 15 0>; |
190 | interrupt-parent = <&mpc5200_pic>; | ||
191 | }; | 168 | }; |
192 | 169 | ||
193 | xlb@1f00 { | 170 | xlb@1f00 { |
@@ -196,13 +173,10 @@ | |||
196 | }; | 173 | }; |
197 | 174 | ||
198 | serial@2000 { // PSC1 | 175 | serial@2000 { // PSC1 |
199 | device_type = "serial"; | ||
200 | compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; | 176 | compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; |
201 | port-number = <0>; // Logical port assignment | ||
202 | cell-index = <0>; | 177 | cell-index = <0>; |
203 | reg = <0x2000 0x100>; | 178 | reg = <0x2000 0x100>; |
204 | interrupts = <2 1 0>; | 179 | interrupts = <2 1 0>; |
205 | interrupt-parent = <&mpc5200_pic>; | ||
206 | }; | 180 | }; |
207 | 181 | ||
208 | // PSC2 in ac97 mode example | 182 | // PSC2 in ac97 mode example |
@@ -211,7 +185,6 @@ | |||
211 | // cell-index = <1>; | 185 | // cell-index = <1>; |
212 | // reg = <0x2200 0x100>; | 186 | // reg = <0x2200 0x100>; |
213 | // interrupts = <2 2 0>; | 187 | // interrupts = <2 2 0>; |
214 | // interrupt-parent = <&mpc5200_pic>; | ||
215 | //}; | 188 | //}; |
216 | 189 | ||
217 | // PSC3 in CODEC mode example | 190 | // PSC3 in CODEC mode example |
@@ -220,27 +193,22 @@ | |||
220 | // cell-index = <2>; | 193 | // cell-index = <2>; |
221 | // reg = <0x2400 0x100>; | 194 | // reg = <0x2400 0x100>; |
222 | // interrupts = <2 3 0>; | 195 | // interrupts = <2 3 0>; |
223 | // interrupt-parent = <&mpc5200_pic>; | ||
224 | //}; | 196 | //}; |
225 | 197 | ||
226 | // PSC4 in uart mode example | 198 | // PSC4 in uart mode example |
227 | //serial@2600 { // PSC4 | 199 | //serial@2600 { // PSC4 |
228 | // device_type = "serial"; | ||
229 | // compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; | 200 | // compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; |
230 | // cell-index = <3>; | 201 | // cell-index = <3>; |
231 | // reg = <0x2600 0x100>; | 202 | // reg = <0x2600 0x100>; |
232 | // interrupts = <2 11 0>; | 203 | // interrupts = <2 11 0>; |
233 | // interrupt-parent = <&mpc5200_pic>; | ||
234 | //}; | 204 | //}; |
235 | 205 | ||
236 | // PSC5 in uart mode example | 206 | // PSC5 in uart mode example |
237 | //serial@2800 { // PSC5 | 207 | //serial@2800 { // PSC5 |
238 | // device_type = "serial"; | ||
239 | // compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; | 208 | // compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; |
240 | // cell-index = <4>; | 209 | // cell-index = <4>; |
241 | // reg = <0x2800 0x100>; | 210 | // reg = <0x2800 0x100>; |
242 | // interrupts = <2 12 0>; | 211 | // interrupts = <2 12 0>; |
243 | // interrupt-parent = <&mpc5200_pic>; | ||
244 | //}; | 212 | //}; |
245 | 213 | ||
246 | // PSC6 in spi mode example | 214 | // PSC6 in spi mode example |
@@ -249,49 +217,40 @@ | |||
249 | // cell-index = <5>; | 217 | // cell-index = <5>; |
250 | // reg = <0x2c00 0x100>; | 218 | // reg = <0x2c00 0x100>; |
251 | // interrupts = <2 4 0>; | 219 | // interrupts = <2 4 0>; |
252 | // interrupt-parent = <&mpc5200_pic>; | ||
253 | //}; | 220 | //}; |
254 | 221 | ||
255 | ethernet@3000 { | 222 | ethernet@3000 { |
256 | device_type = "network"; | ||
257 | compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec"; | 223 | compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec"; |
258 | reg = <0x3000 0x400>; | 224 | reg = <0x3000 0x400>; |
259 | local-mac-address = [ 00 00 00 00 00 00 ]; | 225 | local-mac-address = [ 00 00 00 00 00 00 ]; |
260 | interrupts = <2 5 0>; | 226 | interrupts = <2 5 0>; |
261 | interrupt-parent = <&mpc5200_pic>; | ||
262 | phy-handle = <&phy0>; | 227 | phy-handle = <&phy0>; |
263 | }; | 228 | }; |
264 | 229 | ||
265 | mdio@3000 { | 230 | mdio@3000 { |
266 | #address-cells = <1>; | 231 | #address-cells = <1>; |
267 | #size-cells = <0>; | 232 | #size-cells = <0>; |
268 | compatible = "fsl,mpc5200b-mdio", "fsl,mpc5200-mdio"; | 233 | compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio"; |
269 | reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts | 234 | reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts |
270 | interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co. | 235 | interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co. |
271 | interrupt-parent = <&mpc5200_pic>; | ||
272 | 236 | ||
273 | phy0: ethernet-phy@0 { | 237 | phy0: ethernet-phy@0 { |
274 | device_type = "ethernet-phy"; | ||
275 | reg = <0>; | 238 | reg = <0>; |
276 | }; | 239 | }; |
277 | }; | 240 | }; |
278 | 241 | ||
279 | ata@3a00 { | 242 | ata@3a00 { |
280 | device_type = "ata"; | ||
281 | compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata"; | 243 | compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata"; |
282 | reg = <0x3a00 0x100>; | 244 | reg = <0x3a00 0x100>; |
283 | interrupts = <2 7 0>; | 245 | interrupts = <2 7 0>; |
284 | interrupt-parent = <&mpc5200_pic>; | ||
285 | }; | 246 | }; |
286 | 247 | ||
287 | i2c@3d00 { | 248 | i2c@3d00 { |
288 | #address-cells = <1>; | 249 | #address-cells = <1>; |
289 | #size-cells = <0>; | 250 | #size-cells = <0>; |
290 | compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c"; | 251 | compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c"; |
291 | cell-index = <0>; | ||
292 | reg = <0x3d00 0x40>; | 252 | reg = <0x3d00 0x40>; |
293 | interrupts = <2 15 0>; | 253 | interrupts = <2 15 0>; |
294 | interrupt-parent = <&mpc5200_pic>; | ||
295 | fsl5200-clocking; | 254 | fsl5200-clocking; |
296 | }; | 255 | }; |
297 | 256 | ||
@@ -299,14 +258,13 @@ | |||
299 | #address-cells = <1>; | 258 | #address-cells = <1>; |
300 | #size-cells = <0>; | 259 | #size-cells = <0>; |
301 | compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c"; | 260 | compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c"; |
302 | cell-index = <1>; | ||
303 | reg = <0x3d40 0x40>; | 261 | reg = <0x3d40 0x40>; |
304 | interrupts = <2 16 0>; | 262 | interrupts = <2 16 0>; |
305 | interrupt-parent = <&mpc5200_pic>; | ||
306 | fsl5200-clocking; | 263 | fsl5200-clocking; |
307 | }; | 264 | }; |
265 | |||
308 | sram@8000 { | 266 | sram@8000 { |
309 | compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram","sram"; | 267 | compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram"; |
310 | reg = <0x8000 0x4000>; | 268 | reg = <0x8000 0x4000>; |
311 | }; | 269 | }; |
312 | }; | 270 | }; |
@@ -330,7 +288,6 @@ | |||
330 | 0xc800 0 0 4 &mpc5200_pic 0 0 3>; | 288 | 0xc800 0 0 4 &mpc5200_pic 0 0 3>; |
331 | clock-frequency = <0>; // From boot loader | 289 | clock-frequency = <0>; // From boot loader |
332 | interrupts = <2 8 0 2 9 0 2 10 0>; | 290 | interrupts = <2 8 0 2 9 0 2 10 0>; |
333 | interrupt-parent = <&mpc5200_pic>; | ||
334 | bus-range = <0 0>; | 291 | bus-range = <0 0>; |
335 | ranges = <0x42000000 0 0x80000000 0x80000000 0 0x20000000 | 292 | ranges = <0x42000000 0 0x80000000 0x80000000 0 0x20000000 |
336 | 0x02000000 0 0xa0000000 0xa0000000 0 0x10000000 | 293 | 0x02000000 0 0xa0000000 0xa0000000 0 0x10000000 |