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authorGrant Likely <grant.likely@secretlab.ca>2008-04-29 09:19:07 -0400
committerGrant Likely <grant.likely@secretlab.ca>2008-04-29 09:19:07 -0400
commita2884f37b6fe0074df70ebeb3a6c54201267663c (patch)
tree5a4eec613f670d05a380d9190ae521aa480e4652 /arch/powerpc/boot/dts/lite5200.dts
parent8f3ba2dc811228213bcbdc2c8b389a8d6fa66c09 (diff)
[POWERPC] mpc5200: Switch mpc5200 dts files to dts-v1 format
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
Diffstat (limited to 'arch/powerpc/boot/dts/lite5200.dts')
-rw-r--r--arch/powerpc/boot/dts/lite5200.dts132
1 files changed, 67 insertions, 65 deletions
diff --git a/arch/powerpc/boot/dts/lite5200.dts b/arch/powerpc/boot/dts/lite5200.dts
index 09b4e16154d6..2cf9a8768f44 100644
--- a/arch/powerpc/boot/dts/lite5200.dts
+++ b/arch/powerpc/boot/dts/lite5200.dts
@@ -10,6 +10,8 @@
10 * option) any later version. 10 * option) any later version.
11 */ 11 */
12 12
13/dts-v1/;
14
13/ { 15/ {
14 model = "fsl,lite5200"; 16 model = "fsl,lite5200";
15 compatible = "fsl,lite5200"; 17 compatible = "fsl,lite5200";
@@ -23,10 +25,10 @@
23 PowerPC,5200@0 { 25 PowerPC,5200@0 {
24 device_type = "cpu"; 26 device_type = "cpu";
25 reg = <0>; 27 reg = <0>;
26 d-cache-line-size = <20>; 28 d-cache-line-size = <32>;
27 i-cache-line-size = <20>; 29 i-cache-line-size = <32>;
28 d-cache-size = <4000>; // L1, 16K 30 d-cache-size = <0x4000>; // L1, 16K
29 i-cache-size = <4000>; // L1, 16K 31 i-cache-size = <0x4000>; // L1, 16K
30 timebase-frequency = <0>; // from bootloader 32 timebase-frequency = <0>; // from bootloader
31 bus-frequency = <0>; // from bootloader 33 bus-frequency = <0>; // from bootloader
32 clock-frequency = <0>; // from bootloader 34 clock-frequency = <0>; // from bootloader
@@ -35,21 +37,21 @@
35 37
36 memory { 38 memory {
37 device_type = "memory"; 39 device_type = "memory";
38 reg = <00000000 04000000>; // 64MB 40 reg = <0x00000000 0x04000000>; // 64MB
39 }; 41 };
40 42
41 soc5200@f0000000 { 43 soc5200@f0000000 {
42 #address-cells = <1>; 44 #address-cells = <1>;
43 #size-cells = <1>; 45 #size-cells = <1>;
44 compatible = "fsl,mpc5200-immr"; 46 compatible = "fsl,mpc5200-immr";
45 ranges = <0 f0000000 0000c000>; 47 ranges = <0 0xf0000000 0x0000c000>;
46 reg = <f0000000 00000100>; 48 reg = <0xf0000000 0x00000100>;
47 bus-frequency = <0>; // from bootloader 49 bus-frequency = <0>; // from bootloader
48 system-frequency = <0>; // from bootloader 50 system-frequency = <0>; // from bootloader
49 51
50 cdm@200 { 52 cdm@200 {
51 compatible = "fsl,mpc5200-cdm"; 53 compatible = "fsl,mpc5200-cdm";
52 reg = <200 38>; 54 reg = <0x200 0x38>;
53 }; 55 };
54 56
55 mpc5200_pic: interrupt-controller@500 { 57 mpc5200_pic: interrupt-controller@500 {
@@ -58,13 +60,13 @@
58 #interrupt-cells = <3>; 60 #interrupt-cells = <3>;
59 device_type = "interrupt-controller"; 61 device_type = "interrupt-controller";
60 compatible = "fsl,mpc5200-pic"; 62 compatible = "fsl,mpc5200-pic";
61 reg = <500 80>; 63 reg = <0x500 0x80>;
62 }; 64 };
63 65
64 timer@600 { // General Purpose Timer 66 timer@600 { // General Purpose Timer
65 compatible = "fsl,mpc5200-gpt"; 67 compatible = "fsl,mpc5200-gpt";
66 cell-index = <0>; 68 cell-index = <0>;
67 reg = <600 10>; 69 reg = <0x600 0x10>;
68 interrupts = <1 9 0>; 70 interrupts = <1 9 0>;
69 interrupt-parent = <&mpc5200_pic>; 71 interrupt-parent = <&mpc5200_pic>;
70 fsl,has-wdt; 72 fsl,has-wdt;
@@ -73,63 +75,63 @@
73 timer@610 { // General Purpose Timer 75 timer@610 { // General Purpose Timer
74 compatible = "fsl,mpc5200-gpt"; 76 compatible = "fsl,mpc5200-gpt";
75 cell-index = <1>; 77 cell-index = <1>;
76 reg = <610 10>; 78 reg = <0x610 0x10>;
77 interrupts = <1 a 0>; 79 interrupts = <1 10 0>;
78 interrupt-parent = <&mpc5200_pic>; 80 interrupt-parent = <&mpc5200_pic>;
79 }; 81 };
80 82
81 timer@620 { // General Purpose Timer 83 timer@620 { // General Purpose Timer
82 compatible = "fsl,mpc5200-gpt"; 84 compatible = "fsl,mpc5200-gpt";
83 cell-index = <2>; 85 cell-index = <2>;
84 reg = <620 10>; 86 reg = <0x620 0x10>;
85 interrupts = <1 b 0>; 87 interrupts = <1 11 0>;
86 interrupt-parent = <&mpc5200_pic>; 88 interrupt-parent = <&mpc5200_pic>;
87 }; 89 };
88 90
89 timer@630 { // General Purpose Timer 91 timer@630 { // General Purpose Timer
90 compatible = "fsl,mpc5200-gpt"; 92 compatible = "fsl,mpc5200-gpt";
91 cell-index = <3>; 93 cell-index = <3>;
92 reg = <630 10>; 94 reg = <0x630 0x10>;
93 interrupts = <1 c 0>; 95 interrupts = <1 12 0>;
94 interrupt-parent = <&mpc5200_pic>; 96 interrupt-parent = <&mpc5200_pic>;
95 }; 97 };
96 98
97 timer@640 { // General Purpose Timer 99 timer@640 { // General Purpose Timer
98 compatible = "fsl,mpc5200-gpt"; 100 compatible = "fsl,mpc5200-gpt";
99 cell-index = <4>; 101 cell-index = <4>;
100 reg = <640 10>; 102 reg = <0x640 0x10>;
101 interrupts = <1 d 0>; 103 interrupts = <1 13 0>;
102 interrupt-parent = <&mpc5200_pic>; 104 interrupt-parent = <&mpc5200_pic>;
103 }; 105 };
104 106
105 timer@650 { // General Purpose Timer 107 timer@650 { // General Purpose Timer
106 compatible = "fsl,mpc5200-gpt"; 108 compatible = "fsl,mpc5200-gpt";
107 cell-index = <5>; 109 cell-index = <5>;
108 reg = <650 10>; 110 reg = <0x650 0x10>;
109 interrupts = <1 e 0>; 111 interrupts = <1 14 0>;
110 interrupt-parent = <&mpc5200_pic>; 112 interrupt-parent = <&mpc5200_pic>;
111 }; 113 };
112 114
113 timer@660 { // General Purpose Timer 115 timer@660 { // General Purpose Timer
114 compatible = "fsl,mpc5200-gpt"; 116 compatible = "fsl,mpc5200-gpt";
115 cell-index = <6>; 117 cell-index = <6>;
116 reg = <660 10>; 118 reg = <0x660 0x10>;
117 interrupts = <1 f 0>; 119 interrupts = <1 15 0>;
118 interrupt-parent = <&mpc5200_pic>; 120 interrupt-parent = <&mpc5200_pic>;
119 }; 121 };
120 122
121 timer@670 { // General Purpose Timer 123 timer@670 { // General Purpose Timer
122 compatible = "fsl,mpc5200-gpt"; 124 compatible = "fsl,mpc5200-gpt";
123 cell-index = <7>; 125 cell-index = <7>;
124 reg = <670 10>; 126 reg = <0x670 0x10>;
125 interrupts = <1 10 0>; 127 interrupts = <1 16 0>;
126 interrupt-parent = <&mpc5200_pic>; 128 interrupt-parent = <&mpc5200_pic>;
127 }; 129 };
128 130
129 rtc@800 { // Real time clock 131 rtc@800 { // Real time clock
130 compatible = "fsl,mpc5200-rtc"; 132 compatible = "fsl,mpc5200-rtc";
131 device_type = "rtc"; 133 device_type = "rtc";
132 reg = <800 100>; 134 reg = <0x800 0x100>;
133 interrupts = <1 5 0 1 6 0>; 135 interrupts = <1 5 0 1 6 0>;
134 interrupt-parent = <&mpc5200_pic>; 136 interrupt-parent = <&mpc5200_pic>;
135 }; 137 };
@@ -137,43 +139,43 @@
137 can@900 { 139 can@900 {
138 compatible = "fsl,mpc5200-mscan"; 140 compatible = "fsl,mpc5200-mscan";
139 cell-index = <0>; 141 cell-index = <0>;
140 interrupts = <2 11 0>; 142 interrupts = <2 17 0>;
141 interrupt-parent = <&mpc5200_pic>; 143 interrupt-parent = <&mpc5200_pic>;
142 reg = <900 80>; 144 reg = <0x900 0x80>;
143 }; 145 };
144 146
145 can@980 { 147 can@980 {
146 compatible = "fsl,mpc5200-mscan"; 148 compatible = "fsl,mpc5200-mscan";
147 cell-index = <1>; 149 cell-index = <1>;
148 interrupts = <2 12 0>; 150 interrupts = <2 18 0>;
149 interrupt-parent = <&mpc5200_pic>; 151 interrupt-parent = <&mpc5200_pic>;
150 reg = <980 80>; 152 reg = <0x980 0x80>;
151 }; 153 };
152 154
153 gpio@b00 { 155 gpio@b00 {
154 compatible = "fsl,mpc5200-gpio"; 156 compatible = "fsl,mpc5200-gpio";
155 reg = <b00 40>; 157 reg = <0xb00 0x40>;
156 interrupts = <1 7 0>; 158 interrupts = <1 7 0>;
157 interrupt-parent = <&mpc5200_pic>; 159 interrupt-parent = <&mpc5200_pic>;
158 }; 160 };
159 161
160 gpio@c00 { 162 gpio@c00 {
161 compatible = "fsl,mpc5200-gpio-wkup"; 163 compatible = "fsl,mpc5200-gpio-wkup";
162 reg = <c00 40>; 164 reg = <0xc00 0x40>;
163 interrupts = <1 8 0 0 3 0>; 165 interrupts = <1 8 0 0 3 0>;
164 interrupt-parent = <&mpc5200_pic>; 166 interrupt-parent = <&mpc5200_pic>;
165 }; 167 };
166 168
167 spi@f00 { 169 spi@f00 {
168 compatible = "fsl,mpc5200-spi"; 170 compatible = "fsl,mpc5200-spi";
169 reg = <f00 20>; 171 reg = <0xf00 0x20>;
170 interrupts = <2 d 0 2 e 0>; 172 interrupts = <2 13 0 2 14 0>;
171 interrupt-parent = <&mpc5200_pic>; 173 interrupt-parent = <&mpc5200_pic>;
172 }; 174 };
173 175
174 usb@1000 { 176 usb@1000 {
175 compatible = "fsl,mpc5200-ohci","ohci-be"; 177 compatible = "fsl,mpc5200-ohci","ohci-be";
176 reg = <1000 ff>; 178 reg = <0x1000 0xff>;
177 interrupts = <2 6 0>; 179 interrupts = <2 6 0>;
178 interrupt-parent = <&mpc5200_pic>; 180 interrupt-parent = <&mpc5200_pic>;
179 }; 181 };
@@ -181,17 +183,17 @@
181 dma-controller@1200 { 183 dma-controller@1200 {
182 device_type = "dma-controller"; 184 device_type = "dma-controller";
183 compatible = "fsl,mpc5200-bestcomm"; 185 compatible = "fsl,mpc5200-bestcomm";
184 reg = <1200 80>; 186 reg = <0x1200 0x80>;
185 interrupts = <3 0 0 3 1 0 3 2 0 3 3 0 187 interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
186 3 4 0 3 5 0 3 6 0 3 7 0 188 3 4 0 3 5 0 3 6 0 3 7 0
187 3 8 0 3 9 0 3 a 0 3 b 0 189 3 8 0 3 9 0 3 10 0 3 11 0
188 3 c 0 3 d 0 3 e 0 3 f 0>; 190 3 12 0 3 13 0 3 14 0 3 15 0>;
189 interrupt-parent = <&mpc5200_pic>; 191 interrupt-parent = <&mpc5200_pic>;
190 }; 192 };
191 193
192 xlb@1f00 { 194 xlb@1f00 {
193 compatible = "fsl,mpc5200-xlb"; 195 compatible = "fsl,mpc5200-xlb";
194 reg = <1f00 100>; 196 reg = <0x1f00 0x100>;
195 }; 197 };
196 198
197 serial@2000 { // PSC1 199 serial@2000 { // PSC1
@@ -199,7 +201,7 @@
199 compatible = "fsl,mpc5200-psc-uart"; 201 compatible = "fsl,mpc5200-psc-uart";
200 port-number = <0>; // Logical port assignment 202 port-number = <0>; // Logical port assignment
201 cell-index = <0>; 203 cell-index = <0>;
202 reg = <2000 100>; 204 reg = <0x2000 0x100>;
203 interrupts = <2 1 0>; 205 interrupts = <2 1 0>;
204 interrupt-parent = <&mpc5200_pic>; 206 interrupt-parent = <&mpc5200_pic>;
205 }; 207 };
@@ -208,7 +210,7 @@
208 //ac97@2200 { // PSC2 210 //ac97@2200 { // PSC2
209 // compatible = "fsl,mpc5200-psc-ac97"; 211 // compatible = "fsl,mpc5200-psc-ac97";
210 // cell-index = <1>; 212 // cell-index = <1>;
211 // reg = <2200 100>; 213 // reg = <0x2200 0x100>;
212 // interrupts = <2 2 0>; 214 // interrupts = <2 2 0>;
213 // interrupt-parent = <&mpc5200_pic>; 215 // interrupt-parent = <&mpc5200_pic>;
214 //}; 216 //};
@@ -217,7 +219,7 @@
217 //i2s@2400 { // PSC3 219 //i2s@2400 { // PSC3
218 // compatible = "fsl,mpc5200-psc-i2s"; 220 // compatible = "fsl,mpc5200-psc-i2s";
219 // cell-index = <2>; 221 // cell-index = <2>;
220 // reg = <2400 100>; 222 // reg = <0x2400 0x100>;
221 // interrupts = <2 3 0>; 223 // interrupts = <2 3 0>;
222 // interrupt-parent = <&mpc5200_pic>; 224 // interrupt-parent = <&mpc5200_pic>;
223 //}; 225 //};
@@ -227,8 +229,8 @@
227 // device_type = "serial"; 229 // device_type = "serial";
228 // compatible = "fsl,mpc5200-psc-uart"; 230 // compatible = "fsl,mpc5200-psc-uart";
229 // cell-index = <3>; 231 // cell-index = <3>;
230 // reg = <2600 100>; 232 // reg = <0x2600 0x100>;
231 // interrupts = <2 b 0>; 233 // interrupts = <2 11 0>;
232 // interrupt-parent = <&mpc5200_pic>; 234 // interrupt-parent = <&mpc5200_pic>;
233 //}; 235 //};
234 236
@@ -237,8 +239,8 @@
237 // device_type = "serial"; 239 // device_type = "serial";
238 // compatible = "fsl,mpc5200-psc-uart"; 240 // compatible = "fsl,mpc5200-psc-uart";
239 // cell-index = <4>; 241 // cell-index = <4>;
240 // reg = <2800 100>; 242 // reg = <0x2800 0x100>;
241 // interrupts = <2 c 0>; 243 // interrupts = <2 12 0>;
242 // interrupt-parent = <&mpc5200_pic>; 244 // interrupt-parent = <&mpc5200_pic>;
243 //}; 245 //};
244 246
@@ -246,7 +248,7 @@
246 //spi@2c00 { // PSC6 248 //spi@2c00 { // PSC6
247 // compatible = "fsl,mpc5200-psc-spi"; 249 // compatible = "fsl,mpc5200-psc-spi";
248 // cell-index = <5>; 250 // cell-index = <5>;
249 // reg = <2c00 100>; 251 // reg = <0x2c00 0x100>;
250 // interrupts = <2 4 0>; 252 // interrupts = <2 4 0>;
251 // interrupt-parent = <&mpc5200_pic>; 253 // interrupt-parent = <&mpc5200_pic>;
252 //}; 254 //};
@@ -254,7 +256,7 @@
254 ethernet@3000 { 256 ethernet@3000 {
255 device_type = "network"; 257 device_type = "network";
256 compatible = "fsl,mpc5200-fec"; 258 compatible = "fsl,mpc5200-fec";
257 reg = <3000 800>; 259 reg = <0x3000 0x400>;
258 local-mac-address = [ 00 00 00 00 00 00 ]; 260 local-mac-address = [ 00 00 00 00 00 00 ];
259 interrupts = <2 5 0>; 261 interrupts = <2 5 0>;
260 interrupt-parent = <&mpc5200_pic>; 262 interrupt-parent = <&mpc5200_pic>;
@@ -265,11 +267,11 @@
265 #address-cells = <1>; 267 #address-cells = <1>;
266 #size-cells = <0>; 268 #size-cells = <0>;
267 compatible = "fsl,mpc5200-mdio"; 269 compatible = "fsl,mpc5200-mdio";
268 reg = <3000 400>; // fec range, since we need to setup fec interrupts 270 reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
269 interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co. 271 interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
270 interrupt-parent = <&mpc5200_pic>; 272 interrupt-parent = <&mpc5200_pic>;
271 273
272 phy0:ethernet-phy@1 { 274 phy0: ethernet-phy@1 {
273 device_type = "ethernet-phy"; 275 device_type = "ethernet-phy";
274 reg = <1>; 276 reg = <1>;
275 }; 277 };
@@ -278,7 +280,7 @@
278 ata@3a00 { 280 ata@3a00 {
279 device_type = "ata"; 281 device_type = "ata";
280 compatible = "fsl,mpc5200-ata"; 282 compatible = "fsl,mpc5200-ata";
281 reg = <3a00 100>; 283 reg = <0x3a00 0x100>;
282 interrupts = <2 7 0>; 284 interrupts = <2 7 0>;
283 interrupt-parent = <&mpc5200_pic>; 285 interrupt-parent = <&mpc5200_pic>;
284 }; 286 };
@@ -288,8 +290,8 @@
288 #size-cells = <0>; 290 #size-cells = <0>;
289 compatible = "fsl,mpc5200-i2c","fsl-i2c"; 291 compatible = "fsl,mpc5200-i2c","fsl-i2c";
290 cell-index = <0>; 292 cell-index = <0>;
291 reg = <3d00 40>; 293 reg = <0x3d00 0x40>;
292 interrupts = <2 f 0>; 294 interrupts = <2 15 0>;
293 interrupt-parent = <&mpc5200_pic>; 295 interrupt-parent = <&mpc5200_pic>;
294 fsl5200-clocking; 296 fsl5200-clocking;
295 }; 297 };
@@ -299,14 +301,14 @@
299 #size-cells = <0>; 301 #size-cells = <0>;
300 compatible = "fsl,mpc5200-i2c","fsl-i2c"; 302 compatible = "fsl,mpc5200-i2c","fsl-i2c";
301 cell-index = <1>; 303 cell-index = <1>;
302 reg = <3d40 40>; 304 reg = <0x3d40 0x40>;
303 interrupts = <2 10 0>; 305 interrupts = <2 16 0>;
304 interrupt-parent = <&mpc5200_pic>; 306 interrupt-parent = <&mpc5200_pic>;
305 fsl5200-clocking; 307 fsl5200-clocking;
306 }; 308 };
307 sram@8000 { 309 sram@8000 {
308 compatible = "fsl,mpc5200-sram","sram"; 310 compatible = "fsl,mpc5200-sram","sram";
309 reg = <8000 4000>; 311 reg = <0x8000 0x4000>;
310 }; 312 };
311 }; 313 };
312 314
@@ -316,18 +318,18 @@
316 #address-cells = <3>; 318 #address-cells = <3>;
317 device_type = "pci"; 319 device_type = "pci";
318 compatible = "fsl,mpc5200-pci"; 320 compatible = "fsl,mpc5200-pci";
319 reg = <f0000d00 100>; 321 reg = <0xf0000d00 0x100>;
320 interrupt-map-mask = <f800 0 0 7>; 322 interrupt-map-mask = <0xf800 0 0 7>;
321 interrupt-map = <c000 0 0 1 &mpc5200_pic 0 0 3 323 interrupt-map = <0xc000 0 0 1 &mpc5200_pic 0 0 3
322 c000 0 0 2 &mpc5200_pic 0 0 3 324 0xc000 0 0 2 &mpc5200_pic 0 0 3
323 c000 0 0 3 &mpc5200_pic 0 0 3 325 0xc000 0 0 3 &mpc5200_pic 0 0 3
324 c000 0 0 4 &mpc5200_pic 0 0 3>; 326 0xc000 0 0 4 &mpc5200_pic 0 0 3>;
325 clock-frequency = <0>; // From boot loader 327 clock-frequency = <0>; // From boot loader
326 interrupts = <2 8 0 2 9 0 2 a 0>; 328 interrupts = <2 8 0 2 9 0 2 10 0>;
327 interrupt-parent = <&mpc5200_pic>; 329 interrupt-parent = <&mpc5200_pic>;
328 bus-range = <0 0>; 330 bus-range = <0 0>;
329 ranges = <42000000 0 80000000 80000000 0 20000000 331 ranges = <0x42000000 0 0x80000000 0x80000000 0 0x20000000
330 02000000 0 a0000000 a0000000 0 10000000 332 0x02000000 0 0xa0000000 0xa0000000 0 0x10000000
331 01000000 0 00000000 b0000000 0 01000000>; 333 0x01000000 0 0x00000000 0xb0000000 0 0x01000000>;
332 }; 334 };
333}; 335};
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-29 18:23:47 -0400