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authorKumar Gala <galak@kernel.crashing.org>2008-04-17 10:40:48 -0400
committerKumar Gala <galak@kernel.crashing.org>2008-04-17 10:40:48 -0400
commit998c610363b26f3793ad8121eeb3a749b1034824 (patch)
treef90d357678f79860fe583fced9b88c8c89806a2a /arch/powerpc/boot/dts/kuroboxHD.dts
parent280bb34bc0f7c664b59077b609ce93507a54c848 (diff)
[POWERPC] fsl: Convert dts to v1 syntax
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/boot/dts/kuroboxHD.dts')
-rw-r--r--arch/powerpc/boot/dts/kuroboxHD.dts83
1 files changed, 43 insertions, 40 deletions
diff --git a/arch/powerpc/boot/dts/kuroboxHD.dts b/arch/powerpc/boot/dts/kuroboxHD.dts
index 446958854519..2e5a1a1812b6 100644
--- a/arch/powerpc/boot/dts/kuroboxHD.dts
+++ b/arch/powerpc/boot/dts/kuroboxHD.dts
@@ -7,6 +7,7 @@
7 * Based on sandpoint.dts 7 * Based on sandpoint.dts
8 * 8 *
9 * 2006 (c) G. Liakhovetski <g.liakhovetski@gmx.de> 9 * 2006 (c) G. Liakhovetski <g.liakhovetski@gmx.de>
10 * Copyright 2008 Freescale Semiconductor, Inc.
10 * 11 *
11 * This file is licensed under 12 * This file is licensed under
12 * the terms of the GNU General Public License version 2. This program 13 * the terms of the GNU General Public License version 2. This program
@@ -17,6 +18,8 @@ XXXX add flash parts, rtc, ??
17 18
18 */ 19 */
19 20
21/dts-v1/;
22
20/ { 23/ {
21 model = "KuroboxHD"; 24 model = "KuroboxHD";
22 compatible = "linkstation"; 25 compatible = "linkstation";
@@ -35,19 +38,19 @@ XXXX add flash parts, rtc, ??
35 38
36 PowerPC,603e { /* Really 8241 */ 39 PowerPC,603e { /* Really 8241 */
37 device_type = "cpu"; 40 device_type = "cpu";
38 reg = <0>; 41 reg = <0x0>;
39 clock-frequency = <bebc200>; /* Fixed by bootloader */ 42 clock-frequency = <200000000>; /* Fixed by bootloader */
40 timebase-frequency = <1743000>; /* Fixed by bootloader */ 43 timebase-frequency = <24391680>; /* Fixed by bootloader */
41 bus-frequency = <0>; /* Fixed by bootloader */ 44 bus-frequency = <0>; /* Fixed by bootloader */
42 /* Following required by dtc but not used */ 45 /* Following required by dtc but not used */
43 i-cache-size = <4000>; 46 i-cache-size = <0x4000>;
44 d-cache-size = <4000>; 47 d-cache-size = <0x4000>;
45 }; 48 };
46 }; 49 };
47 50
48 memory { 51 memory {
49 device_type = "memory"; 52 device_type = "memory";
50 reg = <00000000 04000000>; 53 reg = <0x0 0x4000000>;
51 }; 54 };
52 55
53 soc10x { /* AFAICT need to make soc for 8245's uarts to be defined */ 56 soc10x { /* AFAICT need to make soc for 8245's uarts to be defined */
@@ -56,26 +59,26 @@ XXXX add flash parts, rtc, ??
56 device_type = "soc"; 59 device_type = "soc";
57 compatible = "mpc10x"; 60 compatible = "mpc10x";
58 store-gathering = <0>; /* 0 == off, !0 == on */ 61 store-gathering = <0>; /* 0 == off, !0 == on */
59 reg = <80000000 00100000>; 62 reg = <0x80000000 0x100000>;
60 ranges = <80000000 80000000 70000000 /* pci mem space */ 63 ranges = <0x80000000 0x80000000 0x70000000 /* pci mem space */
61 fc000000 fc000000 00100000 /* EUMB */ 64 0xfc000000 0xfc000000 0x100000 /* EUMB */
62 fe000000 fe000000 00c00000 /* pci i/o space */ 65 0xfe000000 0xfe000000 0xc00000 /* pci i/o space */
63 fec00000 fec00000 00300000 /* pci cfg regs */ 66 0xfec00000 0xfec00000 0x300000 /* pci cfg regs */
64 fef00000 fef00000 00100000>; /* pci iack */ 67 0xfef00000 0xfef00000 0x100000>; /* pci iack */
65 68
66 i2c@80003000 { 69 i2c@80003000 {
67 #address-cells = <1>; 70 #address-cells = <1>;
68 #size-cells = <0>; 71 #size-cells = <0>;
69 cell-index = <0>; 72 cell-index = <0>;
70 compatible = "fsl-i2c"; 73 compatible = "fsl-i2c";
71 reg = <80003000 1000>; 74 reg = <0x80003000 0x1000>;
72 interrupts = <5 2>; 75 interrupts = <5 2>;
73 interrupt-parent = <&mpic>; 76 interrupt-parent = <&mpic>;
74 77
75 rtc@32 { 78 rtc@32 {
76 device_type = "rtc"; 79 device_type = "rtc";
77 compatible = "ricoh,rs5c372a"; 80 compatible = "ricoh,rs5c372a";
78 reg = <32>; 81 reg = <0x32>;
79 }; 82 };
80 }; 83 };
81 84
@@ -83,9 +86,9 @@ XXXX add flash parts, rtc, ??
83 cell-index = <0>; 86 cell-index = <0>;
84 device_type = "serial"; 87 device_type = "serial";
85 compatible = "ns16550"; 88 compatible = "ns16550";
86 reg = <80004500 8>; 89 reg = <0x80004500 0x8>;
87 clock-frequency = <5d08d88>; 90 clock-frequency = <97553800>;
88 current-speed = <2580>; 91 current-speed = <9600>;
89 interrupts = <9 0>; 92 interrupts = <9 0>;
90 interrupt-parent = <&mpic>; 93 interrupt-parent = <&mpic>;
91 }; 94 };
@@ -94,10 +97,10 @@ XXXX add flash parts, rtc, ??
94 cell-index = <1>; 97 cell-index = <1>;
95 device_type = "serial"; 98 device_type = "serial";
96 compatible = "ns16550"; 99 compatible = "ns16550";
97 reg = <80004600 8>; 100 reg = <0x80004600 0x8>;
98 clock-frequency = <5d08d88>; 101 clock-frequency = <97553800>;
99 current-speed = <e100>; 102 current-speed = <57600>;
100 interrupts = <a 0>; 103 interrupts = <10 0>;
101 interrupt-parent = <&mpic>; 104 interrupt-parent = <&mpic>;
102 }; 105 };
103 106
@@ -107,7 +110,7 @@ XXXX add flash parts, rtc, ??
107 device_type = "open-pic"; 110 device_type = "open-pic";
108 compatible = "chrp,open-pic"; 111 compatible = "chrp,open-pic";
109 interrupt-controller; 112 interrupt-controller;
110 reg = <80040000 40000>; 113 reg = <0x80040000 0x40000>;
111 }; 114 };
112 115
113 pci0: pci@fec00000 { 116 pci0: pci@fec00000 {
@@ -116,29 +119,29 @@ XXXX add flash parts, rtc, ??
116 #interrupt-cells = <1>; 119 #interrupt-cells = <1>;
117 device_type = "pci"; 120 device_type = "pci";
118 compatible = "mpc10x-pci"; 121 compatible = "mpc10x-pci";
119 reg = <fec00000 400000>; 122 reg = <0xfec00000 0x400000>;
120 ranges = <01000000 0 0 fe000000 0 00c00000 123 ranges = <0x1000000 0x0 0x0 0xfe000000 0x0 0xc00000
121 02000000 0 80000000 80000000 0 70000000>; 124 0x2000000 0x0 0x80000000 0x80000000 0x0 0x70000000>;
122 bus-range = <0 ff>; 125 bus-range = <0 255>;
123 clock-frequency = <7f28155>; 126 clock-frequency = <133333333>;
124 interrupt-parent = <&mpic>; 127 interrupt-parent = <&mpic>;
125 interrupt-map-mask = <f800 0 0 7>; 128 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
126 interrupt-map = < 129 interrupt-map = <
127 /* IDSEL 11 - IRQ0 ETH */ 130 /* IDSEL 11 - IRQ0 ETH */
128 5800 0 0 1 &mpic 0 1 131 0x5800 0x0 0x0 0x1 &mpic 0x0 0x1
129 5800 0 0 2 &mpic 1 1 132 0x5800 0x0 0x0 0x2 &mpic 0x1 0x1
130 5800 0 0 3 &mpic 2 1 133 0x5800 0x0 0x0 0x3 &mpic 0x2 0x1
131 5800 0 0 4 &mpic 3 1 134 0x5800 0x0 0x0 0x4 &mpic 0x3 0x1
132 /* IDSEL 12 - IRQ1 IDE0 */ 135 /* IDSEL 12 - IRQ1 IDE0 */
133 6000 0 0 1 &mpic 1 1 136 0x6000 0x0 0x0 0x1 &mpic 0x1 0x1
134 6000 0 0 2 &mpic 2 1 137 0x6000 0x0 0x0 0x2 &mpic 0x2 0x1
135 6000 0 0 3 &mpic 3 1 138 0x6000 0x0 0x0 0x3 &mpic 0x3 0x1
136 6000 0 0 4 &mpic 0 1 139 0x6000 0x0 0x0 0x4 &mpic 0x0 0x1
137 /* IDSEL 14 - IRQ3 USB2.0 */ 140 /* IDSEL 14 - IRQ3 USB2.0 */
138 7000 0 0 1 &mpic 3 1 141 0x7000 0x0 0x0 0x1 &mpic 0x3 0x1
139 7000 0 0 2 &mpic 3 1 142 0x7000 0x0 0x0 0x2 &mpic 0x3 0x1
140 7000 0 0 3 &mpic 3 1 143 0x7000 0x0 0x0 0x3 &mpic 0x3 0x1
141 7000 0 0 4 &mpic 3 1 144 0x7000 0x0 0x0 0x4 &mpic 0x3 0x1
142 >; 145 >;
143 }; 146 };
144 }; 147 };
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-18 04:54:29 -0500