diff options
author | Kumar Gala <galak@kernel.crashing.org> | 2009-03-31 09:46:25 -0400 |
---|---|---|
committer | Kumar Gala <galak@kernel.crashing.org> | 2009-03-31 09:46:25 -0400 |
commit | fe671772ab1bf5624f2c4dbe2295e6ebeb8055fc (patch) | |
tree | 281b703232b95c2009468f5c4975e97a2f7384c5 /arch/powerpc/boot/dts/ksi8560.dts | |
parent | 9310933c832719b095f82dab30c6bf4e75e937ee (diff) |
powerpc/85xx: Use fsl,mpc85.. as prefix for memory ctrl & l2-cache nodes
Older devices tree's used "fsl,85.." instead of the preferred
"fsl,mpc85.." for the memory controller & l2 cache controller nodes.
The EDAC code is the only use of these and has been updated for some
time to support both "fsl,85.." and "fsl,mpc85.."
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/boot/dts/ksi8560.dts')
-rw-r--r-- | arch/powerpc/boot/dts/ksi8560.dts | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/powerpc/boot/dts/ksi8560.dts b/arch/powerpc/boot/dts/ksi8560.dts index 308fe7c29dea..c9cfd374bffb 100644 --- a/arch/powerpc/boot/dts/ksi8560.dts +++ b/arch/powerpc/boot/dts/ksi8560.dts | |||
@@ -57,14 +57,14 @@ | |||
57 | bus-frequency = <0>; /* Fixed by bootwrapper */ | 57 | bus-frequency = <0>; /* Fixed by bootwrapper */ |
58 | 58 | ||
59 | memory-controller@2000 { | 59 | memory-controller@2000 { |
60 | compatible = "fsl,8540-memory-controller"; | 60 | compatible = "fsl,mpc8540-memory-controller"; |
61 | reg = <0x2000 0x1000>; | 61 | reg = <0x2000 0x1000>; |
62 | interrupt-parent = <&mpic>; | 62 | interrupt-parent = <&mpic>; |
63 | interrupts = <0x12 0x2>; | 63 | interrupts = <0x12 0x2>; |
64 | }; | 64 | }; |
65 | 65 | ||
66 | L2: l2-cache-controller@20000 { | 66 | L2: l2-cache-controller@20000 { |
67 | compatible = "fsl,8540-l2-cache-controller"; | 67 | compatible = "fsl,mpc8540-l2-cache-controller"; |
68 | reg = <0x20000 0x1000>; | 68 | reg = <0x20000 0x1000>; |
69 | cache-line-size = <0x20>; /* 32 bytes */ | 69 | cache-line-size = <0x20>; /* 32 bytes */ |
70 | cache-size = <0x40000>; /* L2, 256K */ | 70 | cache-size = <0x40000>; /* L2, 256K */ |