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authorBenjamin Herrenschmidt <benh@kernel.crashing.org>2007-12-20 23:39:34 -0500
committerJosh Boyer <jwboyer@linux.vnet.ibm.com>2007-12-23 14:14:57 -0500
commit3de9c9cd22c69c6aa2e17d4dcf55dcf1260b5718 (patch)
tree1bb1665e7eda052017cd4b0c53a699883aa30691 /arch/powerpc/boot/dts/katmai.dts
parent190de005384204ba4dc339c3d05f8d40f6b16643 (diff)
[POWERPC] 4xx: Base support for 440SPe "Katmai" eval board
This adds base support for the Katmai board, including PCI-X and PCI-Express (but no RTC, nvram, etc... yet). Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Acked-by: Stefan Roese <sr@denx.de> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
Diffstat (limited to 'arch/powerpc/boot/dts/katmai.dts')
-rw-r--r--arch/powerpc/boot/dts/katmai.dts392
1 files changed, 392 insertions, 0 deletions
diff --git a/arch/powerpc/boot/dts/katmai.dts b/arch/powerpc/boot/dts/katmai.dts
new file mode 100644
index 000000000000..cc2810e05516
--- /dev/null
+++ b/arch/powerpc/boot/dts/katmai.dts
@@ -0,0 +1,392 @@
1/*
2 * Device Tree Source for AMCC Katmai eval board
3 *
4 * Copyright (c) 2006, 2007 IBM Corp.
5 * Benjamin Herrenschmidt <benh@kernel.crashing.org>
6 *
7 * Copyright (c) 2006, 2007 IBM Corp.
8 * Josh Boyer <jwboyer@linux.vnet.ibm.com>
9 *
10 * This file is licensed under the terms of the GNU General Public
11 * License version 2. This program is licensed "as is" without
12 * any warranty of any kind, whether express or implied.
13 */
14
15/ {
16 #address-cells = <2>;
17 #size-cells = <1>;
18 model = "amcc,katmai";
19 compatible = "amcc,katmai";
20 dcr-parent = <&/cpus/PowerPC,440SPe@0>;
21
22 cpus {
23 #address-cells = <1>;
24 #size-cells = <0>;
25
26 PowerPC,440SPe@0 {
27 device_type = "cpu";
28 reg = <0>;
29 clock-frequency = <0>; /* Filled in by zImage */
30 timebase-frequency = <0>; /* Filled in by zImage */
31 i-cache-line-size = <20>;
32 d-cache-line-size = <20>;
33 i-cache-size = <20000>;
34 d-cache-size = <20000>;
35 dcr-controller;
36 dcr-access-method = "native";
37 };
38 };
39
40 memory {
41 device_type = "memory";
42 reg = <0 0 0>; /* Filled in by zImage */
43 };
44
45 UIC0: interrupt-controller0 {
46 compatible = "ibm,uic-440spe","ibm,uic";
47 interrupt-controller;
48 cell-index = <0>;
49 dcr-reg = <0c0 009>;
50 #address-cells = <0>;
51 #size-cells = <0>;
52 #interrupt-cells = <2>;
53 };
54
55 UIC1: interrupt-controller1 {
56 compatible = "ibm,uic-440spe","ibm,uic";
57 interrupt-controller;
58 cell-index = <1>;
59 dcr-reg = <0d0 009>;
60 #address-cells = <0>;
61 #size-cells = <0>;
62 #interrupt-cells = <2>;
63 interrupts = <1e 4 1f 4>; /* cascade */
64 interrupt-parent = <&UIC0>;
65 };
66
67 UIC2: interrupt-controller2 {
68 compatible = "ibm,uic-440spe","ibm,uic";
69 interrupt-controller;
70 cell-index = <2>;
71 dcr-reg = <0e0 009>;
72 #address-cells = <0>;
73 #size-cells = <0>;
74 #interrupt-cells = <2>;
75 interrupts = <a 4 b 4>; /* cascade */
76 interrupt-parent = <&UIC0>;
77 };
78
79 UIC3: interrupt-controller3 {
80 compatible = "ibm,uic-440spe","ibm,uic";
81 interrupt-controller;
82 cell-index = <3>;
83 dcr-reg = <0f0 009>;
84 #address-cells = <0>;
85 #size-cells = <0>;
86 #interrupt-cells = <2>;
87 interrupts = <10 4 11 4>; /* cascade */
88 interrupt-parent = <&UIC0>;
89 };
90
91 SDR0: sdr {
92 compatible = "ibm,sdr-440spe";
93 dcr-reg = <00e 002>;
94 };
95
96 CPR0: cpr {
97 compatible = "ibm,cpr-440spe";
98 dcr-reg = <00c 002>;
99 };
100
101 plb {
102 compatible = "ibm,plb-440spe", "ibm,plb-440gp", "ibm,plb4";
103 #address-cells = <2>;
104 #size-cells = <1>;
105 ranges;
106 clock-frequency = <0>; /* Filled in by zImage */
107
108 SDRAM0: sdram {
109 compatible = "ibm,sdram-440spe", "ibm,sdram-405gp";
110 dcr-reg = <010 2>;
111 };
112
113 MAL0: mcmal {
114 compatible = "ibm,mcmal-440spe", "ibm,mcmal2";
115 dcr-reg = <180 62>;
116 num-tx-chans = <2>;
117 num-rx-chans = <1>;
118 interrupt-parent = <&MAL0>;
119 interrupts = <0 1 2 3 4>;
120 #interrupt-cells = <1>;
121 #address-cells = <0>;
122 #size-cells = <0>;
123 interrupt-map = </*TXEOB*/ 0 &UIC1 6 4
124 /*RXEOB*/ 1 &UIC1 7 4
125 /*SERR*/ 2 &UIC1 1 4
126 /*TXDE*/ 3 &UIC1 2 4
127 /*RXDE*/ 4 &UIC1 3 4>;
128 };
129
130 POB0: opb {
131 compatible = "ibm,opb-440spe", "ibm,opb-440gp", "ibm,opb";
132 #address-cells = <1>;
133 #size-cells = <1>;
134 ranges = <00000000 4 e0000000 20000000>;
135 clock-frequency = <0>; /* Filled in by zImage */
136
137 EBC0: ebc {
138 compatible = "ibm,ebc-440spe", "ibm,ebc-440gp", "ibm,ebc";
139 dcr-reg = <012 2>;
140 #address-cells = <2>;
141 #size-cells = <1>;
142 clock-frequency = <0>; /* Filled in by zImage */
143 interrupts = <5 1>;
144 interrupt-parent = <&UIC1>;
145 };
146
147 UART0: serial@10000200 {
148 device_type = "serial";
149 compatible = "ns16550";
150 reg = <10000200 8>;
151 virtual-reg = <a0000200>;
152 clock-frequency = <0>; /* Filled in by zImage */
153 current-speed = <1c200>;
154 interrupt-parent = <&UIC0>;
155 interrupts = <0 4>;
156 };
157
158 UART1: serial@10000300 {
159 device_type = "serial";
160 compatible = "ns16550";
161 reg = <10000300 8>;
162 virtual-reg = <a0000300>;
163 clock-frequency = <0>;
164 current-speed = <0>;
165 interrupt-parent = <&UIC0>;
166 interrupts = <1 4>;
167 };
168
169
170 UART2: serial@10000600 {
171 device_type = "serial";
172 compatible = "ns16550";
173 reg = <10000600 8>;
174 virtual-reg = <a0000600>;
175 clock-frequency = <0>;
176 current-speed = <0>;
177 interrupt-parent = <&UIC1>;
178 interrupts = <5 4>;
179 };
180
181 IIC0: i2c@10000400 {
182 device_type = "i2c";
183 compatible = "ibm,iic-440spe", "ibm,iic-440gp", "ibm,iic";
184 reg = <10000400 14>;
185 interrupt-parent = <&UIC0>;
186 interrupts = <2 4>;
187 };
188
189 IIC1: i2c@10000500 {
190 device_type = "i2c";
191 compatible = "ibm,iic-440spe", "ibm,iic-440gp", "ibm,iic";
192 reg = <10000500 14>;
193 interrupt-parent = <&UIC0>;
194 interrupts = <3 4>;
195 };
196
197 EMAC0: ethernet@10000800 {
198 linux,network-index = <0>;
199 device_type = "network";
200 compatible = "ibm,emac-440spe", "ibm,emac4";
201 interrupt-parent = <&UIC1>;
202 interrupts = <1c 4 1d 4>;
203 reg = <10000800 70>;
204 local-mac-address = [000000000000];
205 mal-device = <&MAL0>;
206 mal-tx-channel = <0>;
207 mal-rx-channel = <0>;
208 cell-index = <0>;
209 max-frame-size = <5dc>;
210 rx-fifo-size = <1000>;
211 tx-fifo-size = <800>;
212 phy-mode = "gmii";
213 phy-map = <00000000>;
214 has-inverted-stacr-oc;
215 has-new-stacr-staopc;
216 };
217 };
218
219 PCIX0: pci@c0ec00000 {
220 device_type = "pci";
221 #interrupt-cells = <1>;
222 #size-cells = <2>;
223 #address-cells = <3>;
224 compatible = "ibm,plb-pcix-440spe", "ibm,plb-pcix";
225 primary;
226 large-inbound-windows;
227 enable-msi-hole;
228 reg = <c 0ec00000 8 /* Config space access */
229 0 0 0 /* no IACK cycles */
230 c 0ed00000 4 /* Special cycles */
231 c 0ec80000 100 /* Internal registers */
232 c 0ec80100 fc>; /* Internal messaging registers */
233
234 /* Outbound ranges, one memory and one IO,
235 * later cannot be changed
236 */
237 ranges = <02000000 0 80000000 0000000d 80000000 0 80000000
238 01000000 0 00000000 0000000c 08000000 0 00010000>;
239
240 /* Inbound 2GB range starting at 0 */
241 dma-ranges = <42000000 0 0 0 0 0 80000000>;
242
243 /* This drives busses 0 to 0xf */
244 bus-range = <0 f>;
245
246 /*
247 * On Katmai, the following PCI-X interrupts signals
248 * have to be enabled via jumpers (only INTA is
249 * enabled per default):
250 *
251 * INTB: J3: 1-2
252 * INTC: J2: 1-2
253 * INTD: J1: 1-2
254 */
255 interrupt-map-mask = <f800 0 0 7>;
256 interrupt-map = <
257 /* IDSEL 1 */
258 0800 0 0 1 &UIC1 14 8
259 0800 0 0 2 &UIC1 13 8
260 0800 0 0 3 &UIC1 12 8
261 0800 0 0 4 &UIC1 11 8
262 >;
263 };
264
265 PCIE0: pciex@d00000000 {
266 device_type = "pci";
267 #interrupt-cells = <1>;
268 #size-cells = <2>;
269 #address-cells = <3>;
270 compatible = "ibm,plb-pciex-440speB", "ibm,plb-pciex";
271 primary;
272 port = <0>; /* port number */
273 reg = <d 00000000 20000000 /* Config space access */
274 c 10000000 00001000>; /* Registers */
275 dcr-reg = <100 020>;
276 sdr-base = <300>;
277
278 /* Outbound ranges, one memory and one IO,
279 * later cannot be changed
280 */
281 ranges = <02000000 0 80000000 0000000e 00000000 0 80000000
282 01000000 0 00000000 0000000f 80000000 0 00010000>;
283
284 /* Inbound 2GB range starting at 0 */
285 dma-ranges = <42000000 0 0 0 0 0 80000000>;
286
287 /* This drives busses 10 to 0x1f */
288 bus-range = <10 1f>;
289
290 /* Legacy interrupts (note the weird polarity, the bridge seems
291 * to invert PCIe legacy interrupts).
292 * We are de-swizzling here because the numbers are actually for
293 * port of the root complex virtual P2P bridge. But I want
294 * to avoid putting a node for it in the tree, so the numbers
295 * below are basically de-swizzled numbers.
296 * The real slot is on idsel 0, so the swizzling is 1:1
297 */
298 interrupt-map-mask = <0000 0 0 7>;
299 interrupt-map = <
300 0000 0 0 1 &UIC3 0 4 /* swizzled int A */
301 0000 0 0 2 &UIC3 1 4 /* swizzled int B */
302 0000 0 0 3 &UIC3 2 4 /* swizzled int C */
303 0000 0 0 4 &UIC3 3 4 /* swizzled int D */>;
304 };
305
306 PCIE1: pciex@d20000000 {
307 device_type = "pci";
308 #interrupt-cells = <1>;
309 #size-cells = <2>;
310 #address-cells = <3>;
311 compatible = "ibm,plb-pciex-440speB", "ibm,plb-pciex";
312 primary;
313 port = <1>; /* port number */
314 reg = <d 20000000 20000000 /* Config space access */
315 c 10001000 00001000>; /* Registers */
316 dcr-reg = <120 020>;
317 sdr-base = <340>;
318
319 /* Outbound ranges, one memory and one IO,
320 * later cannot be changed
321 */
322 ranges = <02000000 0 80000000 0000000e 80000000 0 80000000
323 01000000 0 00000000 0000000f 80010000 0 00010000>;
324
325 /* Inbound 2GB range starting at 0 */
326 dma-ranges = <42000000 0 0 0 0 0 80000000>;
327
328 /* This drives busses 10 to 0x1f */
329 bus-range = <20 2f>;
330
331 /* Legacy interrupts (note the weird polarity, the bridge seems
332 * to invert PCIe legacy interrupts).
333 * We are de-swizzling here because the numbers are actually for
334 * port of the root complex virtual P2P bridge. But I want
335 * to avoid putting a node for it in the tree, so the numbers
336 * below are basically de-swizzled numbers.
337 * The real slot is on idsel 0, so the swizzling is 1:1
338 */
339 interrupt-map-mask = <0000 0 0 7>;
340 interrupt-map = <
341 0000 0 0 1 &UIC3 4 4 /* swizzled int A */
342 0000 0 0 2 &UIC3 5 4 /* swizzled int B */
343 0000 0 0 3 &UIC3 6 4 /* swizzled int C */
344 0000 0 0 4 &UIC3 7 4 /* swizzled int D */>;
345 };
346
347 PCIE2: pciex@d40000000 {
348 device_type = "pci";
349 #interrupt-cells = <1>;
350 #size-cells = <2>;
351 #address-cells = <3>;
352 compatible = "ibm,plb-pciex-440speB", "ibm,plb-pciex";
353 primary;
354 port = <2>; /* port number */
355 reg = <d 40000000 20000000 /* Config space access */
356 c 10002000 00001000>; /* Registers */
357 dcr-reg = <140 020>;
358 sdr-base = <370>;
359
360 /* Outbound ranges, one memory and one IO,
361 * later cannot be changed
362 */
363 ranges = <02000000 0 80000000 0000000f 00000000 0 80000000
364 01000000 0 00000000 0000000f 80020000 0 00010000>;
365
366 /* Inbound 2GB range starting at 0 */
367 dma-ranges = <42000000 0 0 0 0 0 80000000>;
368
369 /* This drives busses 10 to 0x1f */
370 bus-range = <30 3f>;
371
372 /* Legacy interrupts (note the weird polarity, the bridge seems
373 * to invert PCIe legacy interrupts).
374 * We are de-swizzling here because the numbers are actually for
375 * port of the root complex virtual P2P bridge. But I want
376 * to avoid putting a node for it in the tree, so the numbers
377 * below are basically de-swizzled numbers.
378 * The real slot is on idsel 0, so the swizzling is 1:1
379 */
380 interrupt-map-mask = <0000 0 0 7>;
381 interrupt-map = <
382 0000 0 0 1 &UIC3 8 4 /* swizzled int A */
383 0000 0 0 2 &UIC3 9 4 /* swizzled int B */
384 0000 0 0 3 &UIC3 a 4 /* swizzled int C */
385 0000 0 0 4 &UIC3 b 4 /* swizzled int D */>;
386 };
387 };
388
389 chosen {
390 linux,stdout-path = "/plb/opb/serial@10000200";
391 };
392};
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