aboutsummaryrefslogtreecommitdiffstats
path: root/arch/powerpc/boot/dts/fsl/t2081si-post.dtsi
diff options
context:
space:
mode:
authorShengzhou Liu <Shengzhou.Liu@freescale.com>2014-06-11 06:10:04 -0400
committerScott Wood <scottwood@freescale.com>2014-07-02 18:32:41 -0400
commit1d8de8fceda93735f8d05e56f9a8cd0eb3d44007 (patch)
treea0d18b9d7df0bb2c9fdbb81dcccb2812dc26e1ed /arch/powerpc/boot/dts/fsl/t2081si-post.dtsi
parent087dfae3fe3fe6f8b18285890eb9255ec8478d52 (diff)
powerpc/fsl-booke: Add support for T2080/T2081 SoC
The T2080 QorIQ multicore processor combines four dual-threaded e6500 Power Architecture processor cores with high-performance datapath acceleration logic and network and peripheral bus interfaces required for networking, telecom/datacom, wireless infrastructure, and mil/aerospace applications. The T2080 SoC includes the following function and features: - Four dual-threaded 64-bit Power architecture e6500 cores, up to 1.8GHz - 2MB L2 cache and 512KB CoreNet platform cache (CPC) - Hierarchical interconnect fabric - One 32-/64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving - Data Path Acceleration Architecture (DPAA) incorporating acceleration - 16 SerDes lanes up to 10.3125 GHz - 8 Ethernet interfaces (multiple 1G/2.5G/10G MACs) - High-speed peripheral interfaces - Four PCI Express controllers (two PCIe 2.0 and two PCIe 3.0) - Two Serial RapidIO 2.0 controllers/ports running at up to 5 GHz - Additional peripheral interfaces - Two serial ATA (SATA 2.0) controllers - Two high-speed USB 2.0 controllers with integrated PHY - Enhanced secure digital host controller (SD/SDXC/eMMC) - Enhanced serial peripheral interface (eSPI) - Four I2C controllers - Four 2-pin UARTs or two 4-pin UARTs - Integrated Flash Controller supporting NAND and NOR flash - Three eight-channel DMA engines - Support for hardware virtualization and partitioning enforcement - QorIQ Platform's Trust Architecture 2.0 T2081 is a reduced personality of T2080 with following difference: Feature T2080 T2081 1G Ethernet numbers: 8 6 10G Ethernet numbers: 4 2 SerDes lanes: 16 8 Serial RapidIO,RMan: 2 no SATA Controller: 2 no Aurora: yes no SoC Package: 896-pins 780-pins Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> [scottwood@freescale.com: added fsl,qoriq-pci-v3.0 for U-Boot compat] Signed-off-by: Scott Wood <scottwood@freescale.com>
Diffstat (limited to 'arch/powerpc/boot/dts/fsl/t2081si-post.dtsi')
-rw-r--r--arch/powerpc/boot/dts/fsl/t2081si-post.dtsi435
1 files changed, 435 insertions, 0 deletions
diff --git a/arch/powerpc/boot/dts/fsl/t2081si-post.dtsi b/arch/powerpc/boot/dts/fsl/t2081si-post.dtsi
new file mode 100644
index 000000000000..97479f0ce630
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/t2081si-post.dtsi
@@ -0,0 +1,435 @@
1/*
2 * T2081 Silicon/SoC Device Tree Source (post include)
3 *
4 * Copyright 2013 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35&ifc {
36 #address-cells = <2>;
37 #size-cells = <1>;
38 compatible = "fsl,ifc", "simple-bus";
39 interrupts = <25 2 0 0>;
40};
41
42/* controller at 0x240000 */
43&pci0 {
44 compatible = "fsl,t2080-pcie", "fsl,qoriq-pcie-v3.0", "fsl,qoriq-pcie";
45 device_type = "pci";
46 #size-cells = <2>;
47 #address-cells = <3>;
48 bus-range = <0x0 0xff>;
49 interrupts = <20 2 0 0>;
50 fsl,iommu-parent = <&pamu0>;
51 pcie@0 {
52 reg = <0 0 0 0 0>;
53 #interrupt-cells = <1>;
54 #size-cells = <2>;
55 #address-cells = <3>;
56 device_type = "pci";
57 interrupts = <20 2 0 0>;
58 interrupt-map-mask = <0xf800 0 0 7>;
59 interrupt-map = <
60 /* IDSEL 0x0 */
61 0000 0 0 1 &mpic 40 1 0 0
62 0000 0 0 2 &mpic 1 1 0 0
63 0000 0 0 3 &mpic 2 1 0 0
64 0000 0 0 4 &mpic 3 1 0 0
65 >;
66 };
67};
68
69/* controller at 0x250000 */
70&pci1 {
71 compatible = "fsl,t2080-pcie", "fsl,qoriq-pcie-v3.0", "fsl,qoriq-pcie";
72 device_type = "pci";
73 #size-cells = <2>;
74 #address-cells = <3>;
75 bus-range = <0 0xff>;
76 interrupts = <21 2 0 0>;
77 fsl,iommu-parent = <&pamu0>;
78 pcie@0 {
79 reg = <0 0 0 0 0>;
80 #interrupt-cells = <1>;
81 #size-cells = <2>;
82 #address-cells = <3>;
83 device_type = "pci";
84 interrupts = <21 2 0 0>;
85 interrupt-map-mask = <0xf800 0 0 7>;
86 interrupt-map = <
87 /* IDSEL 0x0 */
88 0000 0 0 1 &mpic 41 1 0 0
89 0000 0 0 2 &mpic 5 1 0 0
90 0000 0 0 3 &mpic 6 1 0 0
91 0000 0 0 4 &mpic 7 1 0 0
92 >;
93 };
94};
95
96/* controller at 0x260000 */
97&pci2 {
98 compatible = "fsl,t2080-pcie", "fsl,qoriq-pcie-v3.0", "fsl,qoriq-pcie";
99 device_type = "pci";
100 #size-cells = <2>;
101 #address-cells = <3>;
102 bus-range = <0x0 0xff>;
103 interrupts = <22 2 0 0>;
104 fsl,iommu-parent = <&pamu0>;
105 pcie@0 {
106 reg = <0 0 0 0 0>;
107 #interrupt-cells = <1>;
108 #size-cells = <2>;
109 #address-cells = <3>;
110 device_type = "pci";
111 interrupts = <22 2 0 0>;
112 interrupt-map-mask = <0xf800 0 0 7>;
113 interrupt-map = <
114 /* IDSEL 0x0 */
115 0000 0 0 1 &mpic 42 1 0 0
116 0000 0 0 2 &mpic 9 1 0 0
117 0000 0 0 3 &mpic 10 1 0 0
118 0000 0 0 4 &mpic 11 1 0 0
119 >;
120 };
121};
122
123/* controller at 0x270000 */
124&pci3 {
125 compatible = "fsl,t2080-pcie", "fsl,qoriq-pcie-v3.0", "fsl,qoriq-pcie";
126 device_type = "pci";
127 #size-cells = <2>;
128 #address-cells = <3>;
129 bus-range = <0x0 0xff>;
130 interrupts = <23 2 0 0>;
131 fsl,iommu-parent = <&pamu0>;
132 pcie@0 {
133 reg = <0 0 0 0 0>;
134 #interrupt-cells = <1>;
135 #size-cells = <2>;
136 #address-cells = <3>;
137 device_type = "pci";
138 interrupts = <23 2 0 0>;
139 interrupt-map-mask = <0xf800 0 0 7>;
140 interrupt-map = <
141 /* IDSEL 0x0 */
142 0000 0 0 1 &mpic 43 1 0 0
143 0000 0 0 2 &mpic 0 1 0 0
144 0000 0 0 3 &mpic 4 1 0 0
145 0000 0 0 4 &mpic 8 1 0 0
146 >;
147 };
148};
149
150&dcsr {
151 #address-cells = <1>;
152 #size-cells = <1>;
153 compatible = "fsl,dcsr", "simple-bus";
154
155 dcsr-epu@0 {
156 compatible = "fsl,t2080-dcsr-epu", "fsl,dcsr-epu";
157 interrupts = <52 2 0 0
158 84 2 0 0
159 85 2 0 0
160 94 2 0 0
161 95 2 0 0>;
162 reg = <0x0 0x1000>;
163 };
164 dcsr-npc {
165 compatible = "fsl,t2080-dcsr-cnpc", "fsl,dcsr-cnpc";
166 reg = <0x1000 0x1000 0x1002000 0x10000>;
167 };
168 dcsr-nxc@2000 {
169 compatible = "fsl,dcsr-nxc";
170 reg = <0x2000 0x1000>;
171 };
172 dcsr-corenet {
173 compatible = "fsl,dcsr-corenet";
174 reg = <0x8000 0x1000 0x1A000 0x1000>;
175 };
176 dcsr-ocn@11000 {
177 compatible = "fsl,t2080-dcsr-ocn", "fsl,dcsr-ocn";
178 reg = <0x11000 0x1000>;
179 };
180 dcsr-ddr@12000 {
181 compatible = "fsl,dcsr-ddr";
182 dev-handle = <&ddr1>;
183 reg = <0x12000 0x1000>;
184 };
185 dcsr-nal@18000 {
186 compatible = "fsl,t2080-dcsr-nal", "fsl,dcsr-nal";
187 reg = <0x18000 0x1000>;
188 };
189 dcsr-rcpm@22000 {
190 compatible = "fsl,t2080-dcsr-rcpm", "fsl,dcsr-rcpm";
191 reg = <0x22000 0x1000>;
192 };
193 dcsr-snpc@30000 {
194 compatible = "fsl,t2080-dcsr-snpc", "fsl,dcsr-snpc";
195 reg = <0x30000 0x1000 0x1022000 0x10000>;
196 };
197 dcsr-snpc@31000 {
198 compatible = "fsl,t2080-dcsr-snpc", "fsl,dcsr-snpc";
199 reg = <0x31000 0x1000 0x1042000 0x10000>;
200 };
201 dcsr-snpc@32000 {
202 compatible = "fsl,t2080-dcsr-snpc", "fsl,dcsr-snpc";
203 reg = <0x32000 0x1000 0x1062000 0x10000>;
204 };
205 dcsr-cpu-sb-proxy@100000 {
206 compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
207 cpu-handle = <&cpu0>;
208 reg = <0x100000 0x1000 0x101000 0x1000>;
209 };
210 dcsr-cpu-sb-proxy@108000 {
211 compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
212 cpu-handle = <&cpu1>;
213 reg = <0x108000 0x1000 0x109000 0x1000>;
214 };
215 dcsr-cpu-sb-proxy@110000 {
216 compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
217 cpu-handle = <&cpu2>;
218 reg = <0x110000 0x1000 0x111000 0x1000>;
219 };
220 dcsr-cpu-sb-proxy@118000 {
221 compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
222 cpu-handle = <&cpu3>;
223 reg = <0x118000 0x1000 0x119000 0x1000>;
224 };
225};
226
227&soc {
228 #address-cells = <1>;
229 #size-cells = <1>;
230 device_type = "soc";
231 compatible = "simple-bus";
232
233 soc-sram-error {
234 compatible = "fsl,soc-sram-error";
235 interrupts = <16 2 1 29>;
236 };
237
238 corenet-law@0 {
239 compatible = "fsl,corenet-law";
240 reg = <0x0 0x1000>;
241 fsl,num-laws = <32>;
242 };
243
244 ddr1: memory-controller@8000 {
245 compatible = "fsl,qoriq-memory-controller-v4.7",
246 "fsl,qoriq-memory-controller";
247 reg = <0x8000 0x1000>;
248 interrupts = <16 2 1 23>;
249 };
250
251 cpc: l3-cache-controller@10000 {
252 compatible = "fsl,t2080-l3-cache-controller", "cache";
253 reg = <0x10000 0x1000
254 0x11000 0x1000
255 0x12000 0x1000>;
256 interrupts = <16 2 1 27
257 16 2 1 26
258 16 2 1 25>;
259 };
260
261 corenet-cf@18000 {
262 compatible = "fsl,corenet2-cf", "fsl,corenet-cf";
263 reg = <0x18000 0x1000>;
264 interrupts = <16 2 1 31>;
265 fsl,ccf-num-csdids = <32>;
266 fsl,ccf-num-snoopids = <32>;
267 };
268
269 iommu@20000 {
270 compatible = "fsl,pamu-v1.0", "fsl,pamu";
271 reg = <0x20000 0x3000>;
272 fsl,portid-mapping = <0x8000>;
273 ranges = <0 0x20000 0x3000>;
274 #address-cells = <1>;
275 #size-cells = <1>;
276 interrupts = <
277 24 2 0 0
278 16 2 1 30>;
279
280 pamu0: pamu@0 {
281 reg = <0 0x1000>;
282 fsl,primary-cache-geometry = <32 1>;
283 fsl,secondary-cache-geometry = <128 2>;
284 };
285
286 pamu1: pamu@1000 {
287 reg = <0x1000 0x1000>;
288 fsl,primary-cache-geometry = <32 1>;
289 fsl,secondary-cache-geometry = <128 2>;
290 };
291
292 pamu2: pamu@2000 {
293 reg = <0x2000 0x1000>;
294 fsl,primary-cache-geometry = <32 1>;
295 fsl,secondary-cache-geometry = <128 2>;
296 };
297 };
298
299/include/ "qoriq-mpic4.3.dtsi"
300
301 guts: global-utilities@e0000 {
302 compatible = "fsl,t2080-device-config", "fsl,qoriq-device-config-2.0";
303 reg = <0xe0000 0xe00>;
304 fsl,has-rstcr;
305 fsl,liodn-bits = <12>;
306 };
307
308 clockgen: global-utilities@e1000 {
309 compatible = "fsl,t2080-clockgen", "fsl,qoriq-clockgen-2.0";
310 ranges = <0x0 0xe1000 0x1000>;
311 reg = <0xe1000 0x1000>;
312 #address-cells = <1>;
313 #size-cells = <1>;
314
315 sysclk: sysclk {
316 #clock-cells = <0>;
317 compatible = "fsl,qoriq-sysclk-2.0";
318 clock-output-names = "sysclk", "fixed-clock";
319 };
320
321 pll0: pll0@800 {
322 #clock-cells = <1>;
323 reg = <0x800 4>;
324 compatible = "fsl,qoriq-core-pll-2.0";
325 clocks = <&sysclk>;
326 clock-output-names = "pll0", "pll0-div2", "pll0-div4";
327 };
328
329 pll1: pll1@820 {
330 #clock-cells = <1>;
331 reg = <0x820 4>;
332 compatible = "fsl,qoriq-core-pll-2.0";
333 clocks = <&sysclk>;
334 clock-output-names = "pll1", "pll1-div2", "pll1-div4";
335 };
336
337 mux0: mux0@0 {
338 #clock-cells = <0>;
339 reg = <0x0 4>;
340 compatible = "fsl,qoriq-core-mux-2.0";
341 clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>,
342 <&pll1 0>, <&pll1 1>, <&pll1 2>;
343 clock-names = "pll0", "pll0-div2", "pll1-div4",
344 "pll1", "pll1-div2", "pll1-div4";
345 clock-output-names = "cmux0";
346 };
347
348 mux1: mux1@20 {
349 #clock-cells = <0>;
350 reg = <0x20 4>;
351 compatible = "fsl,qoriq-core-mux-2.0";
352 clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>,
353 <&pll1 0>, <&pll1 1>, <&pll1 2>;
354 clock-names = "pll0", "pll0-div2", "pll1-div4",
355 "pll1", "pll1-div2", "pll1-div4";
356 clock-output-names = "cmux1";
357 };
358 };
359
360 rcpm: global-utilities@e2000 {
361 compatible = "fsl,t2080-rcpm", "fsl,qoriq-rcpm-2.0";
362 reg = <0xe2000 0x1000>;
363 };
364
365 sfp: sfp@e8000 {
366 compatible = "fsl,t2080-sfp";
367 reg = <0xe8000 0x1000>;
368 };
369
370 serdes: serdes@ea000 {
371 compatible = "fsl,t2080-serdes";
372 reg = <0xea000 0x4000>;
373 };
374
375/include/ "elo3-dma-0.dtsi"
376 dma@100300 {
377 fsl,iommu-parent = <&pamu0>;
378 fsl,liodn-reg = <&guts 0x580>; /* DMA1LIODNR */
379 };
380/include/ "elo3-dma-1.dtsi"
381 dma@101300 {
382 fsl,iommu-parent = <&pamu0>;
383 fsl,liodn-reg = <&guts 0x584>; /* DMA2LIODNR */
384 };
385/include/ "elo3-dma-2.dtsi"
386 dma@102300 {
387 fsl,iommu-parent = <&pamu0>;
388 fsl,liodn-reg = <&guts 0x588>; /* DMA3LIODNR */
389 };
390
391/include/ "qoriq-espi-0.dtsi"
392 spi@110000 {
393 fsl,espi-num-chipselects = <4>;
394 };
395
396/include/ "qoriq-esdhc-0.dtsi"
397 sdhc@114000 {
398 compatible = "fsl,t2080-esdhc", "fsl,esdhc";
399 fsl,iommu-parent = <&pamu1>;
400 fsl,liodn-reg = <&guts 0x530>; /* SDMMCLIODNR */
401 sdhci,auto-cmd12;
402 };
403/include/ "qoriq-i2c-0.dtsi"
404/include/ "qoriq-i2c-1.dtsi"
405/include/ "qoriq-duart-0.dtsi"
406/include/ "qoriq-duart-1.dtsi"
407/include/ "qoriq-gpio-0.dtsi"
408/include/ "qoriq-gpio-1.dtsi"
409/include/ "qoriq-gpio-2.dtsi"
410/include/ "qoriq-gpio-3.dtsi"
411/include/ "qoriq-usb2-mph-0.dtsi"
412 usb0: usb@210000 {
413 compatible = "fsl-usb2-mph-v2.4", "fsl-usb2-mph";
414 fsl,iommu-parent = <&pamu1>;
415 fsl,liodn-reg = <&guts 0x520>; /* USB1LIODNR */
416 phy_type = "utmi";
417 port0;
418 };
419/include/ "qoriq-usb2-dr-0.dtsi"
420 usb1: usb@211000 {
421 compatible = "fsl-usb2-dr-v2.4", "fsl-usb2-dr";
422 fsl,iommu-parent = <&pamu1>;
423 fsl,liodn-reg = <&guts 0x524>; /* USB1LIODNR */
424 dr_mode = "host";
425 phy_type = "utmi";
426 };
427/include/ "qoriq-sec5.2-0.dtsi"
428
429 L2_1: l2-cache-controller@c20000 {
430 /* Cluster 0 L2 cache */
431 compatible = "fsl,t2080-l2-cache-controller";
432 reg = <0xc20000 0x40000>;
433 next-level-cache = <&cpc>;
434 };
435};
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-17 13:17:29 -0500