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authorDavid Gibson <david@gibson.dropbear.id.au>2008-05-15 02:46:39 -0400
committerJosh Boyer <jwboyer@linux.vnet.ibm.com>2008-05-29 08:06:56 -0400
commit71f349799b34c8b6ce3df42126b4de6cfa16456d (patch)
tree995a9385920e7be80ea9a872442caf1d475c935a /arch/powerpc/boot/dts/canyonlands.dts
parentb786af117b360843349cf66165c4efa0217ca2a7 (diff)
[POWERPC] Convert remaining dts-v0 files to v1
At the moment we have a mixture of left-over version 0 and new-format version 1 files in arch/powerpc/boot/dts. This is potentially confusing to people new to the dts format attempting to figure it out. So, this patch converts all the as-yet unconverted dts v0 files and converts them to v1. They're mechanically-converted, and not hand tweaked so in some cases they're not 100% in keeping with usual v1 style, but the convertor program does have some heuristics so the discrepancies aren't too bad. I have checked that this patch produces no changes to the resulting dtb binaries. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Acked-by: Josh Boyer <jwboyer@linux.vnet.ibm.com> Acked-by: Geoff Levand <geoffrey.levand@am.sony.com> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
Diffstat (limited to 'arch/powerpc/boot/dts/canyonlands.dts')
-rw-r--r--arch/powerpc/boot/dts/canyonlands.dts222
1 files changed, 112 insertions, 110 deletions
diff --git a/arch/powerpc/boot/dts/canyonlands.dts b/arch/powerpc/boot/dts/canyonlands.dts
index 39634124929b..f9fe03252150 100644
--- a/arch/powerpc/boot/dts/canyonlands.dts
+++ b/arch/powerpc/boot/dts/canyonlands.dts
@@ -8,12 +8,14 @@
8 * any warranty of any kind, whether express or implied. 8 * any warranty of any kind, whether express or implied.
9 */ 9 */
10 10
11/dts-v1/;
12
11/ { 13/ {
12 #address-cells = <2>; 14 #address-cells = <2>;
13 #size-cells = <1>; 15 #size-cells = <1>;
14 model = "amcc,canyonlands"; 16 model = "amcc,canyonlands";
15 compatible = "amcc,canyonlands"; 17 compatible = "amcc,canyonlands";
16 dcr-parent = <&/cpus/cpu@0>; 18 dcr-parent = <&{/cpus/cpu@0}>;
17 19
18 aliases { 20 aliases {
19 ethernet0 = &EMAC0; 21 ethernet0 = &EMAC0;
@@ -29,13 +31,13 @@
29 cpu@0 { 31 cpu@0 {
30 device_type = "cpu"; 32 device_type = "cpu";
31 model = "PowerPC,460EX"; 33 model = "PowerPC,460EX";
32 reg = <0>; 34 reg = <0x00000000>;
33 clock-frequency = <0>; /* Filled in by U-Boot */ 35 clock-frequency = <0>; /* Filled in by U-Boot */
34 timebase-frequency = <0>; /* Filled in by U-Boot */ 36 timebase-frequency = <0>; /* Filled in by U-Boot */
35 i-cache-line-size = <20>; 37 i-cache-line-size = <32>;
36 d-cache-line-size = <20>; 38 d-cache-line-size = <32>;
37 i-cache-size = <8000>; 39 i-cache-size = <32768>;
38 d-cache-size = <8000>; 40 d-cache-size = <32768>;
39 dcr-controller; 41 dcr-controller;
40 dcr-access-method = "native"; 42 dcr-access-method = "native";
41 }; 43 };
@@ -43,14 +45,14 @@
43 45
44 memory { 46 memory {
45 device_type = "memory"; 47 device_type = "memory";
46 reg = <0 0 0>; /* Filled in by U-Boot */ 48 reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */
47 }; 49 };
48 50
49 UIC0: interrupt-controller0 { 51 UIC0: interrupt-controller0 {
50 compatible = "ibm,uic-460ex","ibm,uic"; 52 compatible = "ibm,uic-460ex","ibm,uic";
51 interrupt-controller; 53 interrupt-controller;
52 cell-index = <0>; 54 cell-index = <0>;
53 dcr-reg = <0c0 009>; 55 dcr-reg = <0x0c0 0x009>;
54 #address-cells = <0>; 56 #address-cells = <0>;
55 #size-cells = <0>; 57 #size-cells = <0>;
56 #interrupt-cells = <2>; 58 #interrupt-cells = <2>;
@@ -60,11 +62,11 @@
60 compatible = "ibm,uic-460ex","ibm,uic"; 62 compatible = "ibm,uic-460ex","ibm,uic";
61 interrupt-controller; 63 interrupt-controller;
62 cell-index = <1>; 64 cell-index = <1>;
63 dcr-reg = <0d0 009>; 65 dcr-reg = <0x0d0 0x009>;
64 #address-cells = <0>; 66 #address-cells = <0>;
65 #size-cells = <0>; 67 #size-cells = <0>;
66 #interrupt-cells = <2>; 68 #interrupt-cells = <2>;
67 interrupts = <1e 4 1f 4>; /* cascade */ 69 interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
68 interrupt-parent = <&UIC0>; 70 interrupt-parent = <&UIC0>;
69 }; 71 };
70 72
@@ -72,11 +74,11 @@
72 compatible = "ibm,uic-460ex","ibm,uic"; 74 compatible = "ibm,uic-460ex","ibm,uic";
73 interrupt-controller; 75 interrupt-controller;
74 cell-index = <2>; 76 cell-index = <2>;
75 dcr-reg = <0e0 009>; 77 dcr-reg = <0x0e0 0x009>;
76 #address-cells = <0>; 78 #address-cells = <0>;
77 #size-cells = <0>; 79 #size-cells = <0>;
78 #interrupt-cells = <2>; 80 #interrupt-cells = <2>;
79 interrupts = <a 4 b 4>; /* cascade */ 81 interrupts = <0xa 0x4 0xb 0x4>; /* cascade */
80 interrupt-parent = <&UIC0>; 82 interrupt-parent = <&UIC0>;
81 }; 83 };
82 84
@@ -84,22 +86,22 @@
84 compatible = "ibm,uic-460ex","ibm,uic"; 86 compatible = "ibm,uic-460ex","ibm,uic";
85 interrupt-controller; 87 interrupt-controller;
86 cell-index = <3>; 88 cell-index = <3>;
87 dcr-reg = <0f0 009>; 89 dcr-reg = <0x0f0 0x009>;
88 #address-cells = <0>; 90 #address-cells = <0>;
89 #size-cells = <0>; 91 #size-cells = <0>;
90 #interrupt-cells = <2>; 92 #interrupt-cells = <2>;
91 interrupts = <10 4 11 4>; /* cascade */ 93 interrupts = <0x10 0x4 0x11 0x4>; /* cascade */
92 interrupt-parent = <&UIC0>; 94 interrupt-parent = <&UIC0>;
93 }; 95 };
94 96
95 SDR0: sdr { 97 SDR0: sdr {
96 compatible = "ibm,sdr-460ex"; 98 compatible = "ibm,sdr-460ex";
97 dcr-reg = <00e 002>; 99 dcr-reg = <0x00e 0x002>;
98 }; 100 };
99 101
100 CPR0: cpr { 102 CPR0: cpr {
101 compatible = "ibm,cpr-460ex"; 103 compatible = "ibm,cpr-460ex";
102 dcr-reg = <00c 002>; 104 dcr-reg = <0x00c 0x002>;
103 }; 105 };
104 106
105 plb { 107 plb {
@@ -111,74 +113,74 @@
111 113
112 SDRAM0: sdram { 114 SDRAM0: sdram {
113 compatible = "ibm,sdram-460ex", "ibm,sdram-405gp"; 115 compatible = "ibm,sdram-460ex", "ibm,sdram-405gp";
114 dcr-reg = <010 2>; 116 dcr-reg = <0x010 0x002>;
115 }; 117 };
116 118
117 MAL0: mcmal { 119 MAL0: mcmal {
118 compatible = "ibm,mcmal-460ex", "ibm,mcmal2"; 120 compatible = "ibm,mcmal-460ex", "ibm,mcmal2";
119 dcr-reg = <180 62>; 121 dcr-reg = <0x180 0x062>;
120 num-tx-chans = <2>; 122 num-tx-chans = <2>;
121 num-rx-chans = <10>; 123 num-rx-chans = <16>;
122 #address-cells = <0>; 124 #address-cells = <0>;
123 #size-cells = <0>; 125 #size-cells = <0>;
124 interrupt-parent = <&UIC2>; 126 interrupt-parent = <&UIC2>;
125 interrupts = < /*TXEOB*/ 6 4 127 interrupts = < /*TXEOB*/ 0x6 0x4
126 /*RXEOB*/ 7 4 128 /*RXEOB*/ 0x7 0x4
127 /*SERR*/ 3 4 129 /*SERR*/ 0x3 0x4
128 /*TXDE*/ 4 4 130 /*TXDE*/ 0x4 0x4
129 /*RXDE*/ 5 4>; 131 /*RXDE*/ 0x5 0x4>;
130 }; 132 };
131 133
132 POB0: opb { 134 POB0: opb {
133 compatible = "ibm,opb-460ex", "ibm,opb"; 135 compatible = "ibm,opb-460ex", "ibm,opb";
134 #address-cells = <1>; 136 #address-cells = <1>;
135 #size-cells = <1>; 137 #size-cells = <1>;
136 ranges = <b0000000 4 b0000000 50000000>; 138 ranges = <0xb0000000 0x00000004 0xb0000000 0x50000000>;
137 clock-frequency = <0>; /* Filled in by U-Boot */ 139 clock-frequency = <0>; /* Filled in by U-Boot */
138 140
139 EBC0: ebc { 141 EBC0: ebc {
140 compatible = "ibm,ebc-460ex", "ibm,ebc"; 142 compatible = "ibm,ebc-460ex", "ibm,ebc";
141 dcr-reg = <012 2>; 143 dcr-reg = <0x012 0x002>;
142 #address-cells = <2>; 144 #address-cells = <2>;
143 #size-cells = <1>; 145 #size-cells = <1>;
144 clock-frequency = <0>; /* Filled in by U-Boot */ 146 clock-frequency = <0>; /* Filled in by U-Boot */
145 /* ranges property is supplied by U-Boot */ 147 /* ranges property is supplied by U-Boot */
146 interrupts = <6 4>; 148 interrupts = <0x6 0x4>;
147 interrupt-parent = <&UIC1>; 149 interrupt-parent = <&UIC1>;
148 150
149 nor_flash@0,0 { 151 nor_flash@0,0 {
150 compatible = "amd,s29gl512n", "cfi-flash"; 152 compatible = "amd,s29gl512n", "cfi-flash";
151 bank-width = <2>; 153 bank-width = <2>;
152 reg = <0 000000 4000000>; 154 reg = <0x00000000 0x00000000 0x04000000>;
153 #address-cells = <1>; 155 #address-cells = <1>;
154 #size-cells = <1>; 156 #size-cells = <1>;
155 partition@0 { 157 partition@0 {
156 label = "kernel"; 158 label = "kernel";
157 reg = <0 1e0000>; 159 reg = <0x00000000 0x001e0000>;
158 }; 160 };
159 partition@1e0000 { 161 partition@1e0000 {
160 label = "dtb"; 162 label = "dtb";
161 reg = <1e0000 20000>; 163 reg = <0x001e0000 0x00020000>;
162 }; 164 };
163 partition@200000 { 165 partition@200000 {
164 label = "ramdisk"; 166 label = "ramdisk";
165 reg = <200000 1400000>; 167 reg = <0x00200000 0x01400000>;
166 }; 168 };
167 partition@1600000 { 169 partition@1600000 {
168 label = "jffs2"; 170 label = "jffs2";
169 reg = <1600000 400000>; 171 reg = <0x01600000 0x00400000>;
170 }; 172 };
171 partition@1a00000 { 173 partition@1a00000 {
172 label = "user"; 174 label = "user";
173 reg = <1a00000 2560000>; 175 reg = <0x01a00000 0x02560000>;
174 }; 176 };
175 partition@3f60000 { 177 partition@3f60000 {
176 label = "env"; 178 label = "env";
177 reg = <3f60000 40000>; 179 reg = <0x03f60000 0x00040000>;
178 }; 180 };
179 partition@3fa0000 { 181 partition@3fa0000 {
180 label = "u-boot"; 182 label = "u-boot";
181 reg = <3fa0000 60000>; 183 reg = <0x03fa0000 0x00060000>;
182 }; 184 };
183 }; 185 };
184 }; 186 };
@@ -186,103 +188,103 @@
186 UART0: serial@ef600300 { 188 UART0: serial@ef600300 {
187 device_type = "serial"; 189 device_type = "serial";
188 compatible = "ns16550"; 190 compatible = "ns16550";
189 reg = <ef600300 8>; 191 reg = <0xef600300 0x00000008>;
190 virtual-reg = <ef600300>; 192 virtual-reg = <0xef600300>;
191 clock-frequency = <0>; /* Filled in by U-Boot */ 193 clock-frequency = <0>; /* Filled in by U-Boot */
192 current-speed = <0>; /* Filled in by U-Boot */ 194 current-speed = <0>; /* Filled in by U-Boot */
193 interrupt-parent = <&UIC1>; 195 interrupt-parent = <&UIC1>;
194 interrupts = <1 4>; 196 interrupts = <0x1 0x4>;
195 }; 197 };
196 198
197 UART1: serial@ef600400 { 199 UART1: serial@ef600400 {
198 device_type = "serial"; 200 device_type = "serial";
199 compatible = "ns16550"; 201 compatible = "ns16550";
200 reg = <ef600400 8>; 202 reg = <0xef600400 0x00000008>;
201 virtual-reg = <ef600400>; 203 virtual-reg = <0xef600400>;
202 clock-frequency = <0>; /* Filled in by U-Boot */ 204 clock-frequency = <0>; /* Filled in by U-Boot */
203 current-speed = <0>; /* Filled in by U-Boot */ 205 current-speed = <0>; /* Filled in by U-Boot */
204 interrupt-parent = <&UIC0>; 206 interrupt-parent = <&UIC0>;
205 interrupts = <1 4>; 207 interrupts = <0x1 0x4>;
206 }; 208 };
207 209
208 UART2: serial@ef600500 { 210 UART2: serial@ef600500 {
209 device_type = "serial"; 211 device_type = "serial";
210 compatible = "ns16550"; 212 compatible = "ns16550";
211 reg = <ef600500 8>; 213 reg = <0xef600500 0x00000008>;
212 virtual-reg = <ef600500>; 214 virtual-reg = <0xef600500>;
213 clock-frequency = <0>; /* Filled in by U-Boot */ 215 clock-frequency = <0>; /* Filled in by U-Boot */
214 current-speed = <0>; /* Filled in by U-Boot */ 216 current-speed = <0>; /* Filled in by U-Boot */
215 interrupt-parent = <&UIC1>; 217 interrupt-parent = <&UIC1>;
216 interrupts = <1d 4>; 218 interrupts = <0x1d 0x4>;
217 }; 219 };
218 220
219 UART3: serial@ef600600 { 221 UART3: serial@ef600600 {
220 device_type = "serial"; 222 device_type = "serial";
221 compatible = "ns16550"; 223 compatible = "ns16550";
222 reg = <ef600600 8>; 224 reg = <0xef600600 0x00000008>;
223 virtual-reg = <ef600600>; 225 virtual-reg = <0xef600600>;
224 clock-frequency = <0>; /* Filled in by U-Boot */ 226 clock-frequency = <0>; /* Filled in by U-Boot */
225 current-speed = <0>; /* Filled in by U-Boot */ 227 current-speed = <0>; /* Filled in by U-Boot */
226 interrupt-parent = <&UIC1>; 228 interrupt-parent = <&UIC1>;
227 interrupts = <1e 4>; 229 interrupts = <0x1e 0x4>;
228 }; 230 };
229 231
230 IIC0: i2c@ef600700 { 232 IIC0: i2c@ef600700 {
231 compatible = "ibm,iic-460ex", "ibm,iic"; 233 compatible = "ibm,iic-460ex", "ibm,iic";
232 reg = <ef600700 14>; 234 reg = <0xef600700 0x00000014>;
233 interrupt-parent = <&UIC0>; 235 interrupt-parent = <&UIC0>;
234 interrupts = <2 4>; 236 interrupts = <0x2 0x4>;
235 }; 237 };
236 238
237 IIC1: i2c@ef600800 { 239 IIC1: i2c@ef600800 {
238 compatible = "ibm,iic-460ex", "ibm,iic"; 240 compatible = "ibm,iic-460ex", "ibm,iic";
239 reg = <ef600800 14>; 241 reg = <0xef600800 0x00000014>;
240 interrupt-parent = <&UIC0>; 242 interrupt-parent = <&UIC0>;
241 interrupts = <3 4>; 243 interrupts = <0x3 0x4>;
242 }; 244 };
243 245
244 ZMII0: emac-zmii@ef600d00 { 246 ZMII0: emac-zmii@ef600d00 {
245 compatible = "ibm,zmii-460ex", "ibm,zmii"; 247 compatible = "ibm,zmii-460ex", "ibm,zmii";
246 reg = <ef600d00 c>; 248 reg = <0xef600d00 0x0000000c>;
247 }; 249 };
248 250
249 RGMII0: emac-rgmii@ef601500 { 251 RGMII0: emac-rgmii@ef601500 {
250 compatible = "ibm,rgmii-460ex", "ibm,rgmii"; 252 compatible = "ibm,rgmii-460ex", "ibm,rgmii";
251 reg = <ef601500 8>; 253 reg = <0xef601500 0x00000008>;
252 has-mdio; 254 has-mdio;
253 }; 255 };
254 256
255 TAH0: emac-tah@ef601350 { 257 TAH0: emac-tah@ef601350 {
256 compatible = "ibm,tah-460ex", "ibm,tah"; 258 compatible = "ibm,tah-460ex", "ibm,tah";
257 reg = <ef601350 30>; 259 reg = <0xef601350 0x00000030>;
258 }; 260 };
259 261
260 TAH1: emac-tah@ef601450 { 262 TAH1: emac-tah@ef601450 {
261 compatible = "ibm,tah-460ex", "ibm,tah"; 263 compatible = "ibm,tah-460ex", "ibm,tah";
262 reg = <ef601450 30>; 264 reg = <0xef601450 0x00000030>;
263 }; 265 };
264 266
265 EMAC0: ethernet@ef600e00 { 267 EMAC0: ethernet@ef600e00 {
266 device_type = "network"; 268 device_type = "network";
267 compatible = "ibm,emac-460ex", "ibm,emac4"; 269 compatible = "ibm,emac-460ex", "ibm,emac4";
268 interrupt-parent = <&EMAC0>; 270 interrupt-parent = <&EMAC0>;
269 interrupts = <0 1>; 271 interrupts = <0x0 0x1>;
270 #interrupt-cells = <1>; 272 #interrupt-cells = <1>;
271 #address-cells = <0>; 273 #address-cells = <0>;
272 #size-cells = <0>; 274 #size-cells = <0>;
273 interrupt-map = </*Status*/ 0 &UIC2 10 4 275 interrupt-map = </*Status*/ 0x0 &UIC2 0x10 0x4
274 /*Wake*/ 1 &UIC2 14 4>; 276 /*Wake*/ 0x1 &UIC2 0x14 0x4>;
275 reg = <ef600e00 70>; 277 reg = <0xef600e00 0x00000070>;
276 local-mac-address = [000000000000]; /* Filled in by U-Boot */ 278 local-mac-address = [000000000000]; /* Filled in by U-Boot */
277 mal-device = <&MAL0>; 279 mal-device = <&MAL0>;
278 mal-tx-channel = <0>; 280 mal-tx-channel = <0>;
279 mal-rx-channel = <0>; 281 mal-rx-channel = <0>;
280 cell-index = <0>; 282 cell-index = <0>;
281 max-frame-size = <2328>; 283 max-frame-size = <9000>;
282 rx-fifo-size = <1000>; 284 rx-fifo-size = <4096>;
283 tx-fifo-size = <800>; 285 tx-fifo-size = <2048>;
284 phy-mode = "rgmii"; 286 phy-mode = "rgmii";
285 phy-map = <00000000>; 287 phy-map = <0x00000000>;
286 rgmii-device = <&RGMII0>; 288 rgmii-device = <&RGMII0>;
287 rgmii-channel = <0>; 289 rgmii-channel = <0>;
288 tah-device = <&TAH0>; 290 tah-device = <&TAH0>;
@@ -295,23 +297,23 @@
295 device_type = "network"; 297 device_type = "network";
296 compatible = "ibm,emac-460ex", "ibm,emac4"; 298 compatible = "ibm,emac-460ex", "ibm,emac4";
297 interrupt-parent = <&EMAC1>; 299 interrupt-parent = <&EMAC1>;
298 interrupts = <0 1>; 300 interrupts = <0x0 0x1>;
299 #interrupt-cells = <1>; 301 #interrupt-cells = <1>;
300 #address-cells = <0>; 302 #address-cells = <0>;
301 #size-cells = <0>; 303 #size-cells = <0>;
302 interrupt-map = </*Status*/ 0 &UIC2 11 4 304 interrupt-map = </*Status*/ 0x0 &UIC2 0x11 0x4
303 /*Wake*/ 1 &UIC2 15 4>; 305 /*Wake*/ 0x1 &UIC2 0x15 0x4>;
304 reg = <ef600f00 70>; 306 reg = <0xef600f00 0x00000070>;
305 local-mac-address = [000000000000]; /* Filled in by U-Boot */ 307 local-mac-address = [000000000000]; /* Filled in by U-Boot */
306 mal-device = <&MAL0>; 308 mal-device = <&MAL0>;
307 mal-tx-channel = <1>; 309 mal-tx-channel = <1>;
308 mal-rx-channel = <8>; 310 mal-rx-channel = <8>;
309 cell-index = <1>; 311 cell-index = <1>;
310 max-frame-size = <2328>; 312 max-frame-size = <9000>;
311 rx-fifo-size = <1000>; 313 rx-fifo-size = <4096>;
312 tx-fifo-size = <800>; 314 tx-fifo-size = <2048>;
313 phy-mode = "rgmii"; 315 phy-mode = "rgmii";
314 phy-map = <00000000>; 316 phy-map = <0x00000000>;
315 rgmii-device = <&RGMII0>; 317 rgmii-device = <&RGMII0>;
316 rgmii-channel = <1>; 318 rgmii-channel = <1>;
317 tah-device = <&TAH1>; 319 tah-device = <&TAH1>;
@@ -331,27 +333,27 @@
331 primary; 333 primary;
332 large-inbound-windows; 334 large-inbound-windows;
333 enable-msi-hole; 335 enable-msi-hole;
334 reg = <c 0ec00000 8 /* Config space access */ 336 reg = <0x0000000c 0x0ec00000 0x00000008 /* Config space access */
335 0 0 0 /* no IACK cycles */ 337 0x00000000 0x00000000 0x00000000 /* no IACK cycles */
336 c 0ed00000 4 /* Special cycles */ 338 0x0000000c 0x0ed00000 0x00000004 /* Special cycles */
337 c 0ec80000 100 /* Internal registers */ 339 0x0000000c 0x0ec80000 0x00000100 /* Internal registers */
338 c 0ec80100 fc>; /* Internal messaging registers */ 340 0x0000000c 0x0ec80100 0x000000fc>; /* Internal messaging registers */
339 341
340 /* Outbound ranges, one memory and one IO, 342 /* Outbound ranges, one memory and one IO,
341 * later cannot be changed 343 * later cannot be changed
342 */ 344 */
343 ranges = <02000000 0 80000000 0000000d 80000000 0 80000000 345 ranges = <0x02000000 0x00000000 0x80000000 0x0000000d 0x80000000 0x00000000 0x80000000
344 01000000 0 00000000 0000000c 08000000 0 00010000>; 346 0x01000000 0x00000000 0x00000000 0x0000000c 0x08000000 0x00000000 0x00010000>;
345 347
346 /* Inbound 2GB range starting at 0 */ 348 /* Inbound 2GB range starting at 0 */
347 dma-ranges = <42000000 0 0 0 0 0 80000000>; 349 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
348 350
349 /* This drives busses 0 to 0x3f */ 351 /* This drives busses 0 to 0x3f */
350 bus-range = <0 3f>; 352 bus-range = <0x0 0x3f>;
351 353
352 /* All PCI interrupts are routed to ext IRQ 2 -> UIC1-0 */ 354 /* All PCI interrupts are routed to ext IRQ 2 -> UIC1-0 */
353 interrupt-map-mask = <0000 0 0 0>; 355 interrupt-map-mask = <0x0 0x0 0x0 0x0>;
354 interrupt-map = < 0000 0 0 0 &UIC1 0 8 >; 356 interrupt-map = < 0x0 0x0 0x0 0x0 &UIC1 0x0 0x8 >;
355 }; 357 };
356 358
357 PCIE0: pciex@d00000000 { 359 PCIE0: pciex@d00000000 {
@@ -361,23 +363,23 @@
361 #address-cells = <3>; 363 #address-cells = <3>;
362 compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex"; 364 compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex";
363 primary; 365 primary;
364 port = <0>; /* port number */ 366 port = <0x0>; /* port number */
365 reg = <d 00000000 20000000 /* Config space access */ 367 reg = <0x0000000d 0x00000000 0x20000000 /* Config space access */
366 c 08010000 00001000>; /* Registers */ 368 0x0000000c 0x08010000 0x00001000>; /* Registers */
367 dcr-reg = <100 020>; 369 dcr-reg = <0x100 0x020>;
368 sdr-base = <300>; 370 sdr-base = <0x300>;
369 371
370 /* Outbound ranges, one memory and one IO, 372 /* Outbound ranges, one memory and one IO,
371 * later cannot be changed 373 * later cannot be changed
372 */ 374 */
373 ranges = <02000000 0 80000000 0000000e 00000000 0 80000000 375 ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x00000000 0x00000000 0x80000000
374 01000000 0 00000000 0000000f 80000000 0 00010000>; 376 0x01000000 0x00000000 0x00000000 0x0000000f 0x80000000 0x00000000 0x00010000>;
375 377
376 /* Inbound 2GB range starting at 0 */ 378 /* Inbound 2GB range starting at 0 */
377 dma-ranges = <42000000 0 0 0 0 0 80000000>; 379 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
378 380
379 /* This drives busses 40 to 0x7f */ 381 /* This drives busses 40 to 0x7f */
380 bus-range = <40 7f>; 382 bus-range = <0x40 0x7f>;
381 383
382 /* Legacy interrupts (note the weird polarity, the bridge seems 384 /* Legacy interrupts (note the weird polarity, the bridge seems
383 * to invert PCIe legacy interrupts). 385 * to invert PCIe legacy interrupts).
@@ -387,12 +389,12 @@
387 * below are basically de-swizzled numbers. 389 * below are basically de-swizzled numbers.
388 * The real slot is on idsel 0, so the swizzling is 1:1 390 * The real slot is on idsel 0, so the swizzling is 1:1
389 */ 391 */
390 interrupt-map-mask = <0000 0 0 7>; 392 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
391 interrupt-map = < 393 interrupt-map = <
392 0000 0 0 1 &UIC3 c 4 /* swizzled int A */ 394 0x0 0x0 0x0 0x1 &UIC3 0xc 0x4 /* swizzled int A */
393 0000 0 0 2 &UIC3 d 4 /* swizzled int B */ 395 0x0 0x0 0x0 0x2 &UIC3 0xd 0x4 /* swizzled int B */
394 0000 0 0 3 &UIC3 e 4 /* swizzled int C */ 396 0x0 0x0 0x0 0x3 &UIC3 0xe 0x4 /* swizzled int C */
395 0000 0 0 4 &UIC3 f 4 /* swizzled int D */>; 397 0x0 0x0 0x0 0x4 &UIC3 0xf 0x4 /* swizzled int D */>;
396 }; 398 };
397 399
398 PCIE1: pciex@d20000000 { 400 PCIE1: pciex@d20000000 {
@@ -402,23 +404,23 @@
402 #address-cells = <3>; 404 #address-cells = <3>;
403 compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex"; 405 compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex";
404 primary; 406 primary;
405 port = <1>; /* port number */ 407 port = <0x1>; /* port number */
406 reg = <d 20000000 20000000 /* Config space access */ 408 reg = <0x0000000d 0x20000000 0x20000000 /* Config space access */
407 c 08011000 00001000>; /* Registers */ 409 0x0000000c 0x08011000 0x00001000>; /* Registers */
408 dcr-reg = <120 020>; 410 dcr-reg = <0x120 0x020>;
409 sdr-base = <340>; 411 sdr-base = <0x340>;
410 412
411 /* Outbound ranges, one memory and one IO, 413 /* Outbound ranges, one memory and one IO,
412 * later cannot be changed 414 * later cannot be changed
413 */ 415 */
414 ranges = <02000000 0 80000000 0000000e 80000000 0 80000000 416 ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x80000000 0x00000000 0x80000000
415 01000000 0 00000000 0000000f 80010000 0 00010000>; 417 0x01000000 0x00000000 0x00000000 0x0000000f 0x80010000 0x00000000 0x00010000>;
416 418
417 /* Inbound 2GB range starting at 0 */ 419 /* Inbound 2GB range starting at 0 */
418 dma-ranges = <42000000 0 0 0 0 0 80000000>; 420 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
419 421
420 /* This drives busses 80 to 0xbf */ 422 /* This drives busses 80 to 0xbf */
421 bus-range = <80 bf>; 423 bus-range = <0x80 0xbf>;
422 424
423 /* Legacy interrupts (note the weird polarity, the bridge seems 425 /* Legacy interrupts (note the weird polarity, the bridge seems
424 * to invert PCIe legacy interrupts). 426 * to invert PCIe legacy interrupts).
@@ -428,12 +430,12 @@
428 * below are basically de-swizzled numbers. 430 * below are basically de-swizzled numbers.
429 * The real slot is on idsel 0, so the swizzling is 1:1 431 * The real slot is on idsel 0, so the swizzling is 1:1
430 */ 432 */
431 interrupt-map-mask = <0000 0 0 7>; 433 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
432 interrupt-map = < 434 interrupt-map = <
433 0000 0 0 1 &UIC3 10 4 /* swizzled int A */ 435 0x0 0x0 0x0 0x1 &UIC3 0x10 0x4 /* swizzled int A */
434 0000 0 0 2 &UIC3 11 4 /* swizzled int B */ 436 0x0 0x0 0x0 0x2 &UIC3 0x11 0x4 /* swizzled int B */
435 0000 0 0 3 &UIC3 12 4 /* swizzled int C */ 437 0x0 0x0 0x0 0x3 &UIC3 0x12 0x4 /* swizzled int C */
436 0000 0 0 4 &UIC3 13 4 /* swizzled int D */>; 438 0x0 0x0 0x0 0x4 &UIC3 0x13 0x4 /* swizzled int D */>;
437 }; 439 };
438 }; 440 };
439}; 441};
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-26 06:05:27 -0500