diff options
author | Josh Boyer <jwboyer@linux.vnet.ibm.com> | 2007-08-20 08:30:32 -0400 |
---|---|---|
committer | Josh Boyer <jwboyer@linux.vnet.ibm.com> | 2007-08-20 08:30:32 -0400 |
commit | 2ba4573cdaf98b0f3acb8795a66f412c1c41284a (patch) | |
tree | 34e161751ed0192c5b1af1f2001d4b035b985f34 /arch/powerpc/boot/dcr.h | |
parent | 8c1449bdb4c7e9c4492ba18ded70fd8669eeffae (diff) |
[POWERPC] Bamboo zImage wrapper
Add a bootwrapper for the AMCC 440EP Bamboo Eval board. This also adds a
common fixup_clock function for all 440EP(x) chips.
Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
Acked-by: David Gibson <david@gibson.dropbear.id.au>
Diffstat (limited to 'arch/powerpc/boot/dcr.h')
-rw-r--r-- | arch/powerpc/boot/dcr.h | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/arch/powerpc/boot/dcr.h b/arch/powerpc/boot/dcr.h index c95d1a9222c9..e158311c501b 100644 --- a/arch/powerpc/boot/dcr.h +++ b/arch/powerpc/boot/dcr.h | |||
@@ -124,4 +124,14 @@ static const unsigned long sdram_bxcr[] = { SDRAM0_B0CR, SDRAM0_B1CR, SDRAM0_B2C | |||
124 | #define DCRN_MAL0_CFG 0x180 | 124 | #define DCRN_MAL0_CFG 0x180 |
125 | #define MAL_RESET 0x80000000 | 125 | #define MAL_RESET 0x80000000 |
126 | 126 | ||
127 | /* 440EP Clock/Power-on Reset regs */ | ||
128 | #define DCRN_CPR0_ADDR 0xc | ||
129 | #define DCRN_CPR0_DATA 0xd | ||
130 | #define CPR0_PLLD0 0x60 | ||
131 | #define CPR0_OPBD0 0xc0 | ||
132 | #define CPR0_PERD0 0xe0 | ||
133 | #define CPR0_PRIMBD0 0xa0 | ||
134 | #define CPR0_SCPID 0x120 | ||
135 | #define CPR0_PLLC0 0x40 | ||
136 | |||
127 | #endif /* _PPC_BOOT_DCR_H_ */ | 137 | #endif /* _PPC_BOOT_DCR_H_ */ |