[POWERPC] PowerPC 440EPx: Sequoia bootwrapper

Bootwrapper code for AMCC PPC440EPx Sequoia.

Signed-off-by: Valentine Barshak <vbarshak@ru.mvista.com>
Acked-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>

1 files changed, 108 insertions, 0 deletions

diff --git a/arch/powerpc/boot/4xx.c b/arch/powerpc/boot/4xx.c
index 642d8780bb31..ebf9e217612d 100644
--- a/arch/powerpc/boot/4xx.c
+++ b/arch/powerpc/boot/4xx.c
@@ -39,6 +39,114 @@ void ibm4xx_fixup_memsize(void)
         dt_fixup_memory(0, memsize);
 }
 
+/* 4xx DDR1/2 Denali memory controller support */
+/* DDR0 registers */
+#define DDR0_02                 2
+#define DDR0_08                 8
+#define DDR0_10                 10
+#define DDR0_14                 14
+#define DDR0_42                 42
+#define DDR0_43                 43
+
+/* DDR0_02 */
+#define DDR_START               0x1
+#define DDR_START_SHIFT         0
+#define DDR_MAX_CS_REG          0x3
+#define DDR_MAX_CS_REG_SHIFT    24
+#define DDR_MAX_COL_REG         0xf
+#define DDR_MAX_COL_REG_SHIFT   16
+#define DDR_MAX_ROW_REG         0xf
+#define DDR_MAX_ROW_REG_SHIFT   8
+/* DDR0_08 */
+#define DDR_DDR2_MODE           0x1
+#define DDR_DDR2_MODE_SHIFT     0
+/* DDR0_10 */
+#define DDR_CS_MAP              0x3
+#define DDR_CS_MAP_SHIFT        8
+/* DDR0_14 */
+#define DDR_REDUC               0x1
+#define DDR_REDUC_SHIFT         16
+/* DDR0_42 */
+#define DDR_APIN                0x7
+#define DDR_APIN_SHIFT          24
+/* DDR0_43 */
+#define DDR_COL_SZ              0x7
+#define DDR_COL_SZ_SHIFT        8
+#define DDR_BANK8               0x1
+#define DDR_BANK8_SHIFT         0
+
+#define DDR_GET_VAL(val, mask, shift)   (((val) >> (shift)) & (mask))
+
+static inline u32 mfdcr_sdram0(u32 reg)
+{
+        mtdcr(DCRN_SDRAM0_CFGADDR, reg);
+        return mfdcr(DCRN_SDRAM0_CFGDATA);
+}
+
+void ibm4xx_denali_fixup_memsize(void)
+{
+        u32 val, max_cs, max_col, max_row;
+        u32 cs, col, row, bank, dpath;
+        unsigned long memsize;
+
+        val = mfdcr_sdram0(DDR0_02);
+        if (!DDR_GET_VAL(val, DDR_START, DDR_START_SHIFT))
+                fatal("DDR controller is not initialized\n");
+
+        /* get maximum cs col and row values */
+        max_cs  = DDR_GET_VAL(val, DDR_MAX_CS_REG, DDR_MAX_CS_REG_SHIFT);
+        max_col = DDR_GET_VAL(val, DDR_MAX_COL_REG, DDR_MAX_COL_REG_SHIFT);
+        max_row = DDR_GET_VAL(val, DDR_MAX_ROW_REG, DDR_MAX_ROW_REG_SHIFT);
+
+        /* get CS value */
+        val = mfdcr_sdram0(DDR0_10);
+
+        val = DDR_GET_VAL(val, DDR_CS_MAP, DDR_CS_MAP_SHIFT);
+        cs = 0;
+        while (val) {
+                if (val && 0x1)
+                        cs++;
+                val = val >> 1;
+        }
+
+        if (!cs)
+                fatal("No memory installed\n");
+        if (cs > max_cs)
+                fatal("DDR wrong CS configuration\n");
+
+        /* get data path bytes */
+        val = mfdcr_sdram0(DDR0_14);
+
+        if (DDR_GET_VAL(val, DDR_REDUC, DDR_REDUC_SHIFT))
+                dpath = 8; /* 64 bits */
+        else
+                dpath = 4; /* 32 bits */
+
+        /* get adress pins (rows) */
+        val = mfdcr_sdram0(DDR0_42);
+
+        row = DDR_GET_VAL(val, DDR_APIN, DDR_APIN_SHIFT);
+        if (row > max_row)
+                fatal("DDR wrong APIN configuration\n");
+        row = max_row - row;
+
+        /* get collomn size and banks */
+        val = mfdcr_sdram0(DDR0_43);
+
+        col = DDR_GET_VAL(val, DDR_COL_SZ, DDR_COL_SZ_SHIFT);
+        if (col > max_col)
+                fatal("DDR wrong COL configuration\n");
+        col = max_col - col;
+
+        if (DDR_GET_VAL(val, DDR_BANK8, DDR_BANK8_SHIFT))
+                bank = 8; /* 8 banks */
+        else
+                bank = 4; /* 4 banks */
+
+        memsize = cs * (1 << (col+row)) * bank * dpath;
+        dt_fixup_memory(0, memsize);
+}
+
 #define SPRN_DBCR0_40X 0x3F2
 #define SPRN_DBCR0_44X 0x134
 #define DBCR0_RST_SYSTEM 0x30000000