diff options
author | Kyle McMartin <kyle@parisc-linux.org> | 2006-08-13 22:17:19 -0400 |
---|---|---|
committer | Matthew Wilcox <willy@parisc-linux.org> | 2006-10-04 08:45:37 -0400 |
commit | 3d73cf5e18c47d416db4d0734245d3fb087603d9 (patch) | |
tree | 4a80d0f24493a2be47828fa17ecc358b473ba38b /arch/parisc | |
parent | f86e45131f9d41b1617fbaac7aa1ef23e8d0ab48 (diff) |
[PARISC] Abstract shift register left in .S
Abstract existing shift register left macros as shift register
right are. This lends itself to a nice clean up of some #ifdef
blocks in entry.S
Signed-off-by: Kyle McMartin <kyle@parisc-linux.org>
Diffstat (limited to 'arch/parisc')
-rw-r--r-- | arch/parisc/kernel/entry.S | 19 |
1 files changed, 4 insertions, 15 deletions
diff --git a/arch/parisc/kernel/entry.S b/arch/parisc/kernel/entry.S index 192357a3b9fe..d55b45d54f4d 100644 --- a/arch/parisc/kernel/entry.S +++ b/arch/parisc/kernel/entry.S | |||
@@ -30,6 +30,7 @@ | |||
30 | 30 | ||
31 | 31 | ||
32 | #include <asm/psw.h> | 32 | #include <asm/psw.h> |
33 | #include <asm/cache.h> /* for L1_CACHE_SHIFT */ | ||
33 | #include <asm/assembly.h> /* for LDREG/STREG defines */ | 34 | #include <asm/assembly.h> /* for LDREG/STREG defines */ |
34 | #include <asm/pgtable.h> | 35 | #include <asm/pgtable.h> |
35 | #include <asm/signal.h> | 36 | #include <asm/signal.h> |
@@ -478,11 +479,7 @@ | |||
478 | bb,>=,n \pmd,_PxD_PRESENT_BIT,\fault | 479 | bb,>=,n \pmd,_PxD_PRESENT_BIT,\fault |
479 | DEP %r0,31,PxD_FLAG_SHIFT,\pmd /* clear flags */ | 480 | DEP %r0,31,PxD_FLAG_SHIFT,\pmd /* clear flags */ |
480 | copy \pmd,%r9 | 481 | copy \pmd,%r9 |
481 | #ifdef CONFIG_64BIT | 482 | SHLREG %r9,PxD_VALUE_SHIFT,\pmd |
482 | shld %r9,PxD_VALUE_SHIFT,\pmd | ||
483 | #else | ||
484 | shlw %r9,PxD_VALUE_SHIFT,\pmd | ||
485 | #endif | ||
486 | EXTR \va,31-PAGE_SHIFT,ASM_BITS_PER_PTE,\index | 483 | EXTR \va,31-PAGE_SHIFT,ASM_BITS_PER_PTE,\index |
487 | DEP %r0,31,PAGE_SHIFT,\pmd /* clear offset */ | 484 | DEP %r0,31,PAGE_SHIFT,\pmd /* clear offset */ |
488 | shladd \index,BITS_PER_PTE_ENTRY,\pmd,\pmd | 485 | shladd \index,BITS_PER_PTE_ENTRY,\pmd,\pmd |
@@ -970,11 +967,7 @@ intr_return: | |||
970 | /* shift left ____cacheline_aligned (aka L1_CACHE_BYTES) amount | 967 | /* shift left ____cacheline_aligned (aka L1_CACHE_BYTES) amount |
971 | ** irq_stat[] is defined using ____cacheline_aligned. | 968 | ** irq_stat[] is defined using ____cacheline_aligned. |
972 | */ | 969 | */ |
973 | #ifdef CONFIG_64BIT | 970 | SHLREG %r1,L1_CACHE_SHIFT,%r20 |
974 | shld %r1, 6, %r20 | ||
975 | #else | ||
976 | shlw %r1, 5, %r20 | ||
977 | #endif | ||
978 | add %r19,%r20,%r19 /* now have &irq_stat[smp_processor_id()] */ | 971 | add %r19,%r20,%r19 /* now have &irq_stat[smp_processor_id()] */ |
979 | #endif /* CONFIG_SMP */ | 972 | #endif /* CONFIG_SMP */ |
980 | 973 | ||
@@ -2115,11 +2108,7 @@ syscall_check_bh: | |||
2115 | ldw TI_CPU-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r26 /* cpu # */ | 2108 | ldw TI_CPU-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r26 /* cpu # */ |
2116 | 2109 | ||
2117 | /* shift left ____cacheline_aligned (aka L1_CACHE_BYTES) bits */ | 2110 | /* shift left ____cacheline_aligned (aka L1_CACHE_BYTES) bits */ |
2118 | #ifdef CONFIG_64BIT | 2111 | SHLREG %r26,L1_CACHE_SHIFT,%r20 |
2119 | shld %r26, 6, %r20 | ||
2120 | #else | ||
2121 | shlw %r26, 5, %r20 | ||
2122 | #endif | ||
2123 | add %r19,%r20,%r19 /* now have &irq_stat[smp_processor_id()] */ | 2112 | add %r19,%r20,%r19 /* now have &irq_stat[smp_processor_id()] */ |
2124 | #endif /* CONFIG_SMP */ | 2113 | #endif /* CONFIG_SMP */ |
2125 | 2114 | ||