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authorRandolph Chung <tausq@debian.org>2006-12-12 08:51:54 -0500
committerKyle McMartin <kyle@athena.road.mcmartin.ca>2007-02-17 00:41:30 -0500
commitd6ce8626dbc7d277d29b62e31c24ce777c60546b (patch)
tree1078d6aa204de1bc5d64a9595c7c1599fcd6eb52 /arch/parisc
parent592ac93a607109e0643da6c23ae07ac749e973b1 (diff)
[PARISC] Clean up the cache and tlb headers
No changes in functionality. Signed-off-by: Randolph Chung <tausq@debian.org> Signed-off-by: Kyle McMartin <kyle@parisc-linux.org>
Diffstat (limited to 'arch/parisc')
-rw-r--r--arch/parisc/kernel/cache.c186
-rw-r--r--arch/parisc/kernel/traps.c5
2 files changed, 179 insertions, 12 deletions
diff --git a/arch/parisc/kernel/cache.c b/arch/parisc/kernel/cache.c
index 0be51e92a2fc..75582c5a3211 100644
--- a/arch/parisc/kernel/cache.c
+++ b/arch/parisc/kernel/cache.c
@@ -68,16 +68,6 @@ flush_cache_all_local(void)
68} 68}
69EXPORT_SYMBOL(flush_cache_all_local); 69EXPORT_SYMBOL(flush_cache_all_local);
70 70
71/* flushes EVERYTHING (tlb & cache) */
72
73void
74flush_all_caches(void)
75{
76 flush_cache_all();
77 flush_tlb_all();
78}
79EXPORT_SYMBOL(flush_all_caches);
80
81void 71void
82update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t pte) 72update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t pte)
83{ 73{
@@ -270,6 +260,83 @@ void disable_sr_hashing(void)
270 panic("SpaceID hashing is still on!\n"); 260 panic("SpaceID hashing is still on!\n");
271} 261}
272 262
263/* Simple function to work out if we have an existing address translation
264 * for a user space vma. */
265static inline int translation_exists(struct vm_area_struct *vma,
266 unsigned long addr, unsigned long pfn)
267{
268 pgd_t *pgd = pgd_offset(vma->vm_mm, addr);
269 pmd_t *pmd;
270 pte_t pte;
271
272 if(pgd_none(*pgd))
273 return 0;
274
275 pmd = pmd_offset(pgd, addr);
276 if(pmd_none(*pmd) || pmd_bad(*pmd))
277 return 0;
278
279 /* We cannot take the pte lock here: flush_cache_page is usually
280 * called with pte lock already held. Whereas flush_dcache_page
281 * takes flush_dcache_mmap_lock, which is lower in the hierarchy:
282 * the vma itself is secure, but the pte might come or go racily.
283 */
284 pte = *pte_offset_map(pmd, addr);
285 /* But pte_unmap() does nothing on this architecture */
286
287 /* Filter out coincidental file entries and swap entries */
288 if (!(pte_val(pte) & (_PAGE_FLUSH|_PAGE_PRESENT)))
289 return 0;
290
291 return pte_pfn(pte) == pfn;
292}
293
294/* Private function to flush a page from the cache of a non-current
295 * process. cr25 contains the Page Directory of the current user
296 * process; we're going to hijack both it and the user space %sr3 to
297 * temporarily make the non-current process current. We have to do
298 * this because cache flushing may cause a non-access tlb miss which
299 * the handlers have to fill in from the pgd of the non-current
300 * process. */
301static inline void
302flush_user_cache_page_non_current(struct vm_area_struct *vma,
303 unsigned long vmaddr)
304{
305 /* save the current process space and pgd */
306 unsigned long space = mfsp(3), pgd = mfctl(25);
307
308 /* we don't mind taking interrups since they may not
309 * do anything with user space, but we can't
310 * be preempted here */
311 preempt_disable();
312
313 /* make us current */
314 mtctl(__pa(vma->vm_mm->pgd), 25);
315 mtsp(vma->vm_mm->context, 3);
316
317 flush_user_dcache_page(vmaddr);
318 if(vma->vm_flags & VM_EXEC)
319 flush_user_icache_page(vmaddr);
320
321 /* put the old current process back */
322 mtsp(space, 3);
323 mtctl(pgd, 25);
324 preempt_enable();
325}
326
327
328static inline void
329__flush_cache_page(struct vm_area_struct *vma, unsigned long vmaddr)
330{
331 if (likely(vma->vm_mm->context == mfsp(3))) {
332 flush_user_dcache_page(vmaddr);
333 if (vma->vm_flags & VM_EXEC)
334 flush_user_icache_page(vmaddr);
335 } else {
336 flush_user_cache_page_non_current(vma, vmaddr);
337 }
338}
339
273void flush_dcache_page(struct page *page) 340void flush_dcache_page(struct page *page)
274{ 341{
275 struct address_space *mapping = page_mapping(page); 342 struct address_space *mapping = page_mapping(page);
@@ -342,7 +409,7 @@ void clear_user_page_asm(void *page, unsigned long vaddr)
342#define FLUSH_THRESHOLD 0x80000 /* 0.5MB */ 409#define FLUSH_THRESHOLD 0x80000 /* 0.5MB */
343int parisc_cache_flush_threshold __read_mostly = FLUSH_THRESHOLD; 410int parisc_cache_flush_threshold __read_mostly = FLUSH_THRESHOLD;
344 411
345void parisc_setup_cache_timing(void) 412void __init parisc_setup_cache_timing(void)
346{ 413{
347 unsigned long rangetime, alltime; 414 unsigned long rangetime, alltime;
348 unsigned long size; 415 unsigned long size;
@@ -366,6 +433,9 @@ void parisc_setup_cache_timing(void)
366 if (!parisc_cache_flush_threshold) 433 if (!parisc_cache_flush_threshold)
367 parisc_cache_flush_threshold = FLUSH_THRESHOLD; 434 parisc_cache_flush_threshold = FLUSH_THRESHOLD;
368 435
436 if (parisc_cache_flush_threshold > cache_info.dc_size)
437 parisc_cache_flush_threshold = cache_info.dc_size;
438
369 printk(KERN_INFO "Setting cache flush threshold to %x (%d CPUs online)\n", parisc_cache_flush_threshold, num_online_cpus()); 439 printk(KERN_INFO "Setting cache flush threshold to %x (%d CPUs online)\n", parisc_cache_flush_threshold, num_online_cpus());
370} 440}
371 441
@@ -410,3 +480,97 @@ void kunmap_parisc(void *addr)
410} 480}
411EXPORT_SYMBOL(kunmap_parisc); 481EXPORT_SYMBOL(kunmap_parisc);
412#endif 482#endif
483
484void __flush_tlb_range(unsigned long sid, unsigned long start,
485 unsigned long end)
486{
487 unsigned long npages;
488
489 npages = ((end - (start & PAGE_MASK)) + (PAGE_SIZE - 1)) >> PAGE_SHIFT;
490 if (npages >= 512) /* 2MB of space: arbitrary, should be tuned */
491 flush_tlb_all();
492 else {
493 mtsp(sid, 1);
494 purge_tlb_start();
495 if (split_tlb) {
496 while (npages--) {
497 pdtlb(start);
498 pitlb(start);
499 start += PAGE_SIZE;
500 }
501 } else {
502 while (npages--) {
503 pdtlb(start);
504 start += PAGE_SIZE;
505 }
506 }
507 purge_tlb_end();
508 }
509}
510
511static void cacheflush_h_tmp_function(void *dummy)
512{
513 flush_cache_all_local();
514}
515
516void flush_cache_all(void)
517{
518 on_each_cpu(cacheflush_h_tmp_function, NULL, 1, 1);
519}
520
521void flush_cache_mm(struct mm_struct *mm)
522{
523#ifdef CONFIG_SMP
524 flush_cache_all();
525#else
526 flush_cache_all_local();
527#endif
528}
529
530void
531flush_user_dcache_range(unsigned long start, unsigned long end)
532{
533 if ((end - start) < parisc_cache_flush_threshold)
534 flush_user_dcache_range_asm(start,end);
535 else
536 flush_data_cache();
537}
538
539void
540flush_user_icache_range(unsigned long start, unsigned long end)
541{
542 if ((end - start) < parisc_cache_flush_threshold)
543 flush_user_icache_range_asm(start,end);
544 else
545 flush_instruction_cache();
546}
547
548
549void flush_cache_range(struct vm_area_struct *vma,
550 unsigned long start, unsigned long end)
551{
552 int sr3;
553
554 if (!vma->vm_mm->context) {
555 BUG();
556 return;
557 }
558
559 sr3 = mfsp(3);
560 if (vma->vm_mm->context == sr3) {
561 flush_user_dcache_range(start,end);
562 flush_user_icache_range(start,end);
563 } else {
564 flush_cache_all();
565 }
566}
567
568void
569flush_cache_page(struct vm_area_struct *vma, unsigned long vmaddr, unsigned long pfn)
570{
571 BUG_ON(!vma->vm_mm->context);
572
573 if (likely(translation_exists(vma, vmaddr, pfn)))
574 __flush_cache_page(vma, vmaddr);
575
576}
diff --git a/arch/parisc/kernel/traps.c b/arch/parisc/kernel/traps.c
index 65cd6ca32fed..fa0811295acc 100644
--- a/arch/parisc/kernel/traps.c
+++ b/arch/parisc/kernel/traps.c
@@ -39,6 +39,8 @@
39#include <asm/pdc.h> 39#include <asm/pdc.h>
40#include <asm/pdc_chassis.h> 40#include <asm/pdc_chassis.h>
41#include <asm/unwind.h> 41#include <asm/unwind.h>
42#include <asm/tlbflush.h>
43#include <asm/cacheflush.h>
42 44
43#include "../math-emu/math-emu.h" /* for handle_fpe() */ 45#include "../math-emu/math-emu.h" /* for handle_fpe() */
44 46
@@ -554,7 +556,8 @@ void handle_interruption(int code, struct pt_regs *regs)
554 /* Low-priority machine check */ 556 /* Low-priority machine check */
555 pdc_chassis_send_status(PDC_CHASSIS_DIRECT_LPMC); 557 pdc_chassis_send_status(PDC_CHASSIS_DIRECT_LPMC);
556 558
557 flush_all_caches(); 559 flush_cache_all();
560 flush_tlb_all();
558 cpu_lpmc(5, regs); 561 cpu_lpmc(5, regs);
559 return; 562 return;
560 563