[PARISC] Ensure all ldcw uses are ldcw,co on pa2.0

ldcw,co should always be used on pa2.0, otherwise the strict cache
width alignment requirement is not relaxed.

Signed-off-by: Kyle McMartin <kyle@parisc-linux.org>

2 files changed, 4 insertions, 4 deletions

diff --git a/arch/parisc/kernel/entry.S b/arch/parisc/kernel/entry.S
index d9e53cf0372b..630730c32a5a 100644
--- a/arch/parisc/kernel/entry.S
+++ b/arch/parisc/kernel/entry.S
@@ -1638,7 +1638,7 @@ dbit_trap_20w:
         load32          PA(pa_dbit_lock),t0
 
 dbit_spin_20w:
-        ldcw            0(t0),t1
+        LDCW            0(t0),t1
         cmpib,=         0,t1,dbit_spin_20w
         nop
 
@@ -1674,7 +1674,7 @@ dbit_trap_11:
         load32          PA(pa_dbit_lock),t0
 
 dbit_spin_11:
-        ldcw            0(t0),t1
+        LDCW            0(t0),t1
         cmpib,=         0,t1,dbit_spin_11
         nop
 
@@ -1714,7 +1714,7 @@ dbit_trap_20:
         load32          PA(pa_dbit_lock),t0
 
 dbit_spin_20:
-        ldcw            0(t0),t1
+        LDCW            0(t0),t1
         cmpib,=         0,t1,dbit_spin_20
         nop
 
diff --git a/arch/parisc/kernel/syscall.S b/arch/parisc/kernel/syscall.S
index 479d9a017cd1..a028c990cbff 100644
--- a/arch/parisc/kernel/syscall.S
+++ b/arch/parisc/kernel/syscall.S
@@ -541,7 +541,7 @@ cas_nocontend:
 # endif
 /* ENABLE_LWS_DEBUG */
 
-        ldcw    0(%sr2,%r20), %r28                      /* Try to acquire the lock */
+        LDCW    0(%sr2,%r20), %r28                      /* Try to acquire the lock */
         cmpb,<>,n       %r0, %r28, cas_action           /* Did we get it? */
 cas_wouldblock:
         ldo     2(%r0), %r28                            /* 2nd case */