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authorSimon Arlott <simon@fire.lp0.eu>2007-05-11 15:42:34 -0400
committerKyle McMartin <kyle@athena.road.mcmartin.ca>2007-05-22 22:52:16 -0400
commit7022672e4046fac4699aa5f8ff2a5213b7ec4ff9 (patch)
tree2df6e94faf275ebab1ff61a211323f5b758ae909 /arch/parisc/kernel/perf.c
parentb5e8b733a18a1192666005f95f44e02440b057d4 (diff)
[PARISC] spelling fixes: arch/parisc/
Spelling fixes in arch/parisc/. Signed-off-by: Simon Arlott <simon@fire.lp0.eu> Acked-by: Grant Grundler <grundler@parisc-linux.org> Signed-off-by: Kyle McMartin <kyle@parisc-linux.org>
Diffstat (limited to 'arch/parisc/kernel/perf.c')
-rw-r--r--arch/parisc/kernel/perf.c12
1 files changed, 6 insertions, 6 deletions
diff --git a/arch/parisc/kernel/perf.c b/arch/parisc/kernel/perf.c
index 08717380e025..89d6d5ad44b5 100644
--- a/arch/parisc/kernel/perf.c
+++ b/arch/parisc/kernel/perf.c
@@ -171,7 +171,7 @@ static const uint64_t perf_bitmasks[] = {
171 171
172/* 172/*
173 * Write control bitmasks for Pa-8700 processor given 173 * Write control bitmasks for Pa-8700 processor given
174 * somethings have changed slightly. 174 * some things have changed slightly.
175 */ 175 */
176static const uint64_t perf_bitmasks_piranha[] = { 176static const uint64_t perf_bitmasks_piranha[] = {
177 0x0000000000000000ul, /* first dbl word must be zero */ 177 0x0000000000000000ul, /* first dbl word must be zero */
@@ -576,27 +576,27 @@ static int perf_stop_counters(uint32_t *raddr)
576 if (!perf_rdr_read_ubuf(16, userbuf)) 576 if (!perf_rdr_read_ubuf(16, userbuf))
577 return -13; 577 return -13;
578 578
579 /* Counter0 is bits 1398 thru 1429 */ 579 /* Counter0 is bits 1398 to 1429 */
580 tmp64 = (userbuf[21] << 22) & 0x00000000ffc00000; 580 tmp64 = (userbuf[21] << 22) & 0x00000000ffc00000;
581 tmp64 |= (userbuf[22] >> 42) & 0x00000000003fffff; 581 tmp64 |= (userbuf[22] >> 42) & 0x00000000003fffff;
582 /* OR sticky0 (bit 1430) to counter0 bit 32 */ 582 /* OR sticky0 (bit 1430) to counter0 bit 32 */
583 tmp64 |= (userbuf[22] >> 10) & 0x0000000080000000; 583 tmp64 |= (userbuf[22] >> 10) & 0x0000000080000000;
584 raddr[0] = (uint32_t)tmp64; 584 raddr[0] = (uint32_t)tmp64;
585 585
586 /* Counter1 is bits 1431 thru 1462 */ 586 /* Counter1 is bits 1431 to 1462 */
587 tmp64 = (userbuf[22] >> 9) & 0x00000000ffffffff; 587 tmp64 = (userbuf[22] >> 9) & 0x00000000ffffffff;
588 /* OR sticky1 (bit 1463) to counter1 bit 32 */ 588 /* OR sticky1 (bit 1463) to counter1 bit 32 */
589 tmp64 |= (userbuf[22] << 23) & 0x0000000080000000; 589 tmp64 |= (userbuf[22] << 23) & 0x0000000080000000;
590 raddr[1] = (uint32_t)tmp64; 590 raddr[1] = (uint32_t)tmp64;
591 591
592 /* Counter2 is bits 1464 thru 1495 */ 592 /* Counter2 is bits 1464 to 1495 */
593 tmp64 = (userbuf[22] << 24) & 0x00000000ff000000; 593 tmp64 = (userbuf[22] << 24) & 0x00000000ff000000;
594 tmp64 |= (userbuf[23] >> 40) & 0x0000000000ffffff; 594 tmp64 |= (userbuf[23] >> 40) & 0x0000000000ffffff;
595 /* OR sticky2 (bit 1496) to counter2 bit 32 */ 595 /* OR sticky2 (bit 1496) to counter2 bit 32 */
596 tmp64 |= (userbuf[23] >> 8) & 0x0000000080000000; 596 tmp64 |= (userbuf[23] >> 8) & 0x0000000080000000;
597 raddr[2] = (uint32_t)tmp64; 597 raddr[2] = (uint32_t)tmp64;
598 598
599 /* Counter3 is bits 1497 thru 1528 */ 599 /* Counter3 is bits 1497 to 1528 */
600 tmp64 = (userbuf[23] >> 7) & 0x00000000ffffffff; 600 tmp64 = (userbuf[23] >> 7) & 0x00000000ffffffff;
601 /* OR sticky3 (bit 1529) to counter3 bit 32 */ 601 /* OR sticky3 (bit 1529) to counter3 bit 32 */
602 tmp64 |= (userbuf[23] << 25) & 0x0000000080000000; 602 tmp64 |= (userbuf[23] << 25) & 0x0000000080000000;
@@ -618,7 +618,7 @@ static int perf_stop_counters(uint32_t *raddr)
618 userbuf[23] = 0; 618 userbuf[23] = 0;
619 619
620 /* 620 /*
621 * Write back the zero'ed bytes + the image given 621 * Write back the zeroed bytes + the image given
622 * the read was destructive. 622 * the read was destructive.
623 */ 623 */
624 perf_rdr_write(16, userbuf); 624 perf_rdr_write(16, userbuf);