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authorHelge Deller <deller@parisc-linux.org>2006-04-20 16:40:23 -0400
committerKyle McMartin <kyle@hera.kernel.org>2006-04-21 18:20:34 -0400
commit2fd83038160531245099c3c5b3511fa4b80765eb (patch)
tree6145a9e78723c76ceac722eb60267c0116983c12 /arch/parisc/kernel/pacache.S
parentd668da80d613def981c573354e1853e38bd0698d (diff)
[PARISC] Further work for multiple page sizes
More work towards supporing multiple page sizes on 64-bit. Convert some assumptions that 64bit uses 3 level page tables into testing PT_NLEVELS. Also some BUG() to BUG_ON() conversions and some cleanups to assembler. Signed-off-by: Helge Deller <deller@parisc-linux.org> Signed-off-by: Kyle McMartin <kyle@parisc-linux.org>
Diffstat (limited to 'arch/parisc/kernel/pacache.S')
-rw-r--r--arch/parisc/kernel/pacache.S25
1 files changed, 12 insertions, 13 deletions
diff --git a/arch/parisc/kernel/pacache.S b/arch/parisc/kernel/pacache.S
index 7a4f07e8d3c3..f600556414d1 100644
--- a/arch/parisc/kernel/pacache.S
+++ b/arch/parisc/kernel/pacache.S
@@ -65,7 +65,7 @@ flush_tlb_all_local:
65 */ 65 */
66 66
67 /* pcxt_ssm_bug - relied upon translation! PA 2.0 Arch. F-4 and F-5 */ 67 /* pcxt_ssm_bug - relied upon translation! PA 2.0 Arch. F-4 and F-5 */
68 rsm PSW_SM_I, %r19 /* save I-bit state */ 68 rsm PSW_SM_I, %r19 /* save I-bit state */
69 load32 PA(1f), %r1 69 load32 PA(1f), %r1
70 nop 70 nop
71 nop 71 nop
@@ -84,8 +84,7 @@ flush_tlb_all_local:
84 rfi 84 rfi
85 nop 85 nop
86 86
871: ldil L%PA(cache_info), %r1 871: load32 PA(cache_info), %r1
88 ldo R%PA(cache_info)(%r1), %r1
89 88
90 /* Flush Instruction Tlb */ 89 /* Flush Instruction Tlb */
91 90
@@ -212,8 +211,7 @@ flush_instruction_cache_local:
212 .entry 211 .entry
213 212
214 mtsp %r0, %sr1 213 mtsp %r0, %sr1
215 ldil L%cache_info, %r1 214 load32 cache_info, %r1
216 ldo R%cache_info(%r1), %r1
217 215
218 /* Flush Instruction Cache */ 216 /* Flush Instruction Cache */
219 217
@@ -254,8 +252,7 @@ flush_data_cache_local:
254 .entry 252 .entry
255 253
256 mtsp %r0, %sr1 254 mtsp %r0, %sr1
257 ldil L%cache_info, %r1 255 load32 cache_info, %r1
258 ldo R%cache_info(%r1), %r1
259 256
260 /* Flush Data Cache */ 257 /* Flush Data Cache */
261 258
@@ -303,7 +300,8 @@ copy_user_page_asm:
303 */ 300 */
304 301
305 ldd 0(%r25), %r19 302 ldd 0(%r25), %r19
306 ldi 32, %r1 /* PAGE_SIZE/128 == 32 */ 303 ldi ASM_PAGE_SIZE_DIV128, %r1
304
307 ldw 64(%r25), %r0 /* prefetch 1 cacheline ahead */ 305 ldw 64(%r25), %r0 /* prefetch 1 cacheline ahead */
308 ldw 128(%r25), %r0 /* prefetch 2 */ 306 ldw 128(%r25), %r0 /* prefetch 2 */
309 307
@@ -368,7 +366,7 @@ copy_user_page_asm:
368 * use ldd/std on a 32 bit kernel. 366 * use ldd/std on a 32 bit kernel.
369 */ 367 */
370 ldw 0(%r25), %r19 368 ldw 0(%r25), %r19
371 ldi 64, %r1 /* PAGE_SIZE/64 == 64 */ 369 ldi ASM_PAGE_SIZE_DIV64, %r1
372 370
3731: 3711:
374 ldw 4(%r25), %r20 372 ldw 4(%r25), %r20
@@ -461,6 +459,7 @@ copy_user_page_asm:
461 sub %r25, %r1, %r23 /* move physical addr into non shadowed reg */ 459 sub %r25, %r1, %r23 /* move physical addr into non shadowed reg */
462 460
463 ldil L%(TMPALIAS_MAP_START), %r28 461 ldil L%(TMPALIAS_MAP_START), %r28
462 /* FIXME for different page sizes != 4k */
464#ifdef CONFIG_64BIT 463#ifdef CONFIG_64BIT
465 extrd,u %r26,56,32, %r26 /* convert phys addr to tlb insert format */ 464 extrd,u %r26,56,32, %r26 /* convert phys addr to tlb insert format */
466 extrd,u %r23,56,32, %r23 /* convert phys addr to tlb insert format */ 465 extrd,u %r23,56,32, %r23 /* convert phys addr to tlb insert format */
@@ -551,6 +550,7 @@ __clear_user_page_asm:
551#ifdef CONFIG_64BIT 550#ifdef CONFIG_64BIT
552#if (TMPALIAS_MAP_START >= 0x80000000) 551#if (TMPALIAS_MAP_START >= 0x80000000)
553 depdi 0, 31,32, %r28 /* clear any sign extension */ 552 depdi 0, 31,32, %r28 /* clear any sign extension */
553 /* FIXME: page size dependend */
554#endif 554#endif
555 extrd,u %r26, 56,32, %r26 /* convert phys addr to tlb insert format */ 555 extrd,u %r26, 56,32, %r26 /* convert phys addr to tlb insert format */
556 depd %r25, 63,22, %r28 /* Form aliased virtual address 'to' */ 556 depd %r25, 63,22, %r28 /* Form aliased virtual address 'to' */
@@ -566,10 +566,10 @@ __clear_user_page_asm:
566 pdtlb 0(%r28) 566 pdtlb 0(%r28)
567 567
568#ifdef CONFIG_64BIT 568#ifdef CONFIG_64BIT
569 ldi 32, %r1 /* PAGE_SIZE/128 == 32 */ 569 ldi ASM_PAGE_SIZE_DIV128, %r1
570 570
571 /* PREFETCH (Write) has not (yet) been proven to help here */ 571 /* PREFETCH (Write) has not (yet) been proven to help here */
572/* #define PREFETCHW_OP ldd 256(%0), %r0 */ 572 /* #define PREFETCHW_OP ldd 256(%0), %r0 */
573 573
5741: std %r0, 0(%r28) 5741: std %r0, 0(%r28)
575 std %r0, 8(%r28) 575 std %r0, 8(%r28)
@@ -591,8 +591,7 @@ __clear_user_page_asm:
591 ldo 128(%r28), %r28 591 ldo 128(%r28), %r28
592 592
593#else /* ! CONFIG_64BIT */ 593#else /* ! CONFIG_64BIT */
594 594 ldi ASM_PAGE_SIZE_DIV64, %r1
595 ldi 64, %r1 /* PAGE_SIZE/64 == 64 */
596 595
5971: 5961:
598 stw %r0, 0(%r28) 597 stw %r0, 0(%r28)