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authorKyle McMartin <kyle@mcmartin.ca>2008-05-15 10:53:57 -0400
committerKyle McMartin <kyle@mcmartin.ca>2008-05-15 11:03:43 -0400
commit872f6debcae63309eb39bfc2cc9462fb83450ee0 (patch)
tree7a1bb365c00e791b8e3d8e848b6f0e97e9b3ab69 /arch/parisc/kernel/entry.S
parentf54d8a1b3fef79bb1aa2f0840dd356ce7bb180f9 (diff)
parisc: use conditional macro for 64-bit wide ops
This work enables us to remove -traditional from $AFLAGS on parisc. Signed-off-by: Kyle McMartin <kyle@mcmartin.ca>
Diffstat (limited to 'arch/parisc/kernel/entry.S')
-rw-r--r--arch/parisc/kernel/entry.S46
1 files changed, 19 insertions, 27 deletions
diff --git a/arch/parisc/kernel/entry.S b/arch/parisc/kernel/entry.S
index 1a3935e61ab7..5d0837458c19 100644
--- a/arch/parisc/kernel/entry.S
+++ b/arch/parisc/kernel/entry.S
@@ -41,16 +41,8 @@
41#include <linux/init.h> 41#include <linux/init.h>
42 42
43#ifdef CONFIG_64BIT 43#ifdef CONFIG_64BIT
44#define CMPIB cmpib,*
45#define CMPB cmpb,*
46#define COND(x) *x
47
48 .level 2.0w 44 .level 2.0w
49#else 45#else
50#define CMPIB cmpib,
51#define CMPB cmpb,
52#define COND(x) x
53
54 .level 2.0 46 .level 2.0
55#endif 47#endif
56 48
@@ -958,9 +950,9 @@ intr_check_sig:
958 * Only do signals if we are returning to user space 950 * Only do signals if we are returning to user space
959 */ 951 */
960 LDREG PT_IASQ0(%r16), %r20 952 LDREG PT_IASQ0(%r16), %r20
961 CMPIB=,n 0,%r20,intr_restore /* backward */ 953 cmpib,COND(=),n 0,%r20,intr_restore /* backward */
962 LDREG PT_IASQ1(%r16), %r20 954 LDREG PT_IASQ1(%r16), %r20
963 CMPIB=,n 0,%r20,intr_restore /* backward */ 955 cmpib,COND(=),n 0,%r20,intr_restore /* backward */
964 956
965 copy %r0, %r25 /* long in_syscall = 0 */ 957 copy %r0, %r25 /* long in_syscall = 0 */
966#ifdef CONFIG_64BIT 958#ifdef CONFIG_64BIT
@@ -1014,10 +1006,10 @@ intr_do_resched:
1014 * we jump back to intr_restore. 1006 * we jump back to intr_restore.
1015 */ 1007 */
1016 LDREG PT_IASQ0(%r16), %r20 1008 LDREG PT_IASQ0(%r16), %r20
1017 CMPIB= 0, %r20, intr_do_preempt 1009 cmpib,COND(=) 0, %r20, intr_do_preempt
1018 nop 1010 nop
1019 LDREG PT_IASQ1(%r16), %r20 1011 LDREG PT_IASQ1(%r16), %r20
1020 CMPIB= 0, %r20, intr_do_preempt 1012 cmpib,COND(=) 0, %r20, intr_do_preempt
1021 nop 1013 nop
1022 1014
1023#ifdef CONFIG_64BIT 1015#ifdef CONFIG_64BIT
@@ -1046,7 +1038,7 @@ intr_do_preempt:
1046 /* current_thread_info()->preempt_count */ 1038 /* current_thread_info()->preempt_count */
1047 mfctl %cr30, %r1 1039 mfctl %cr30, %r1
1048 LDREG TI_PRE_COUNT(%r1), %r19 1040 LDREG TI_PRE_COUNT(%r1), %r19
1049 CMPIB<> 0, %r19, intr_restore /* if preempt_count > 0 */ 1041 cmpib,COND(<>) 0, %r19, intr_restore /* if preempt_count > 0 */
1050 nop /* prev insn branched backwards */ 1042 nop /* prev insn branched backwards */
1051 1043
1052 /* check if we interrupted a critical path */ 1044 /* check if we interrupted a critical path */
@@ -1065,7 +1057,7 @@ intr_do_preempt:
1065 */ 1057 */
1066 1058
1067intr_extint: 1059intr_extint:
1068 CMPIB=,n 0,%r16,1f 1060 cmpib,COND(=),n 0,%r16,1f
1069 1061
1070 get_stack_use_cr30 1062 get_stack_use_cr30
1071 b,n 2f 1063 b,n 2f
@@ -1100,7 +1092,7 @@ ENDPROC(syscall_exit_rfi)
1100 1092
1101ENTRY(intr_save) /* for os_hpmc */ 1093ENTRY(intr_save) /* for os_hpmc */
1102 mfsp %sr7,%r16 1094 mfsp %sr7,%r16
1103 CMPIB=,n 0,%r16,1f 1095 cmpib,COND(=),n 0,%r16,1f
1104 get_stack_use_cr30 1096 get_stack_use_cr30
1105 b 2f 1097 b 2f
1106 copy %r8,%r26 1098 copy %r8,%r26
@@ -1122,7 +1114,7 @@ ENTRY(intr_save) /* for os_hpmc */
1122 * adjust isr/ior below. 1114 * adjust isr/ior below.
1123 */ 1115 */
1124 1116
1125 CMPIB=,n 6,%r26,skip_save_ior 1117 cmpib,COND(=),n 6,%r26,skip_save_ior
1126 1118
1127 1119
1128 mfctl %cr20, %r16 /* isr */ 1120 mfctl %cr20, %r16 /* isr */
@@ -1451,11 +1443,11 @@ nadtlb_emulate:
1451 bb,>=,n %r9,26,nadtlb_nullify /* m bit not set, just nullify */ 1443 bb,>=,n %r9,26,nadtlb_nullify /* m bit not set, just nullify */
1452 BL get_register,%r25 1444 BL get_register,%r25
1453 extrw,u %r9,15,5,%r8 /* Get index register # */ 1445 extrw,u %r9,15,5,%r8 /* Get index register # */
1454 CMPIB=,n -1,%r1,nadtlb_fault /* have to use slow path */ 1446 cmpib,COND(=),n -1,%r1,nadtlb_fault /* have to use slow path */
1455 copy %r1,%r24 1447 copy %r1,%r24
1456 BL get_register,%r25 1448 BL get_register,%r25
1457 extrw,u %r9,10,5,%r8 /* Get base register # */ 1449 extrw,u %r9,10,5,%r8 /* Get base register # */
1458 CMPIB=,n -1,%r1,nadtlb_fault /* have to use slow path */ 1450 cmpib,COND(=),n -1,%r1,nadtlb_fault /* have to use slow path */
1459 BL set_register,%r25 1451 BL set_register,%r25
1460 add,l %r1,%r24,%r1 /* doesn't affect c/b bits */ 1452 add,l %r1,%r24,%r1 /* doesn't affect c/b bits */
1461 1453
@@ -1487,7 +1479,7 @@ nadtlb_probe_check:
1487 cmpb,<>,n %r16,%r17,nadtlb_fault /* Must be probe,[rw]*/ 1479 cmpb,<>,n %r16,%r17,nadtlb_fault /* Must be probe,[rw]*/
1488 BL get_register,%r25 /* Find the target register */ 1480 BL get_register,%r25 /* Find the target register */
1489 extrw,u %r9,31,5,%r8 /* Get target register */ 1481 extrw,u %r9,31,5,%r8 /* Get target register */
1490 CMPIB=,n -1,%r1,nadtlb_fault /* have to use slow path */ 1482 cmpib,COND(=),n -1,%r1,nadtlb_fault /* have to use slow path */
1491 BL set_register,%r25 1483 BL set_register,%r25
1492 copy %r0,%r1 /* Write zero to target register */ 1484 copy %r0,%r1 /* Write zero to target register */
1493 b nadtlb_nullify /* Nullify return insn */ 1485 b nadtlb_nullify /* Nullify return insn */
@@ -1571,12 +1563,12 @@ dbit_trap_20w:
1571 L3_ptep ptp,pte,t0,va,dbit_fault 1563 L3_ptep ptp,pte,t0,va,dbit_fault
1572 1564
1573#ifdef CONFIG_SMP 1565#ifdef CONFIG_SMP
1574 CMPIB=,n 0,spc,dbit_nolock_20w 1566 cmpib,COND(=),n 0,spc,dbit_nolock_20w
1575 load32 PA(pa_dbit_lock),t0 1567 load32 PA(pa_dbit_lock),t0
1576 1568
1577dbit_spin_20w: 1569dbit_spin_20w:
1578 LDCW 0(t0),t1 1570 LDCW 0(t0),t1
1579 cmpib,= 0,t1,dbit_spin_20w 1571 cmpib,COND(=) 0,t1,dbit_spin_20w
1580 nop 1572 nop
1581 1573
1582dbit_nolock_20w: 1574dbit_nolock_20w:
@@ -1587,7 +1579,7 @@ dbit_nolock_20w:
1587 1579
1588 idtlbt pte,prot 1580 idtlbt pte,prot
1589#ifdef CONFIG_SMP 1581#ifdef CONFIG_SMP
1590 CMPIB=,n 0,spc,dbit_nounlock_20w 1582 cmpib,COND(=),n 0,spc,dbit_nounlock_20w
1591 ldi 1,t1 1583 ldi 1,t1
1592 stw t1,0(t0) 1584 stw t1,0(t0)
1593 1585
@@ -1607,7 +1599,7 @@ dbit_trap_11:
1607 L2_ptep ptp,pte,t0,va,dbit_fault 1599 L2_ptep ptp,pte,t0,va,dbit_fault
1608 1600
1609#ifdef CONFIG_SMP 1601#ifdef CONFIG_SMP
1610 CMPIB=,n 0,spc,dbit_nolock_11 1602 cmpib,COND(=),n 0,spc,dbit_nolock_11
1611 load32 PA(pa_dbit_lock),t0 1603 load32 PA(pa_dbit_lock),t0
1612 1604
1613dbit_spin_11: 1605dbit_spin_11:
@@ -1629,7 +1621,7 @@ dbit_nolock_11:
1629 1621
1630 mtsp t1, %sr1 /* Restore sr1 */ 1622 mtsp t1, %sr1 /* Restore sr1 */
1631#ifdef CONFIG_SMP 1623#ifdef CONFIG_SMP
1632 CMPIB=,n 0,spc,dbit_nounlock_11 1624 cmpib,COND(=),n 0,spc,dbit_nounlock_11
1633 ldi 1,t1 1625 ldi 1,t1
1634 stw t1,0(t0) 1626 stw t1,0(t0)
1635 1627
@@ -1647,7 +1639,7 @@ dbit_trap_20:
1647 L2_ptep ptp,pte,t0,va,dbit_fault 1639 L2_ptep ptp,pte,t0,va,dbit_fault
1648 1640
1649#ifdef CONFIG_SMP 1641#ifdef CONFIG_SMP
1650 CMPIB=,n 0,spc,dbit_nolock_20 1642 cmpib,COND(=),n 0,spc,dbit_nolock_20
1651 load32 PA(pa_dbit_lock),t0 1643 load32 PA(pa_dbit_lock),t0
1652 1644
1653dbit_spin_20: 1645dbit_spin_20:
@@ -1666,7 +1658,7 @@ dbit_nolock_20:
1666 idtlbt pte,prot 1658 idtlbt pte,prot
1667 1659
1668#ifdef CONFIG_SMP 1660#ifdef CONFIG_SMP
1669 CMPIB=,n 0,spc,dbit_nounlock_20 1661 cmpib,COND(=),n 0,spc,dbit_nounlock_20
1670 ldi 1,t1 1662 ldi 1,t1
1671 stw t1,0(t0) 1663 stw t1,0(t0)
1672 1664
@@ -1995,7 +1987,7 @@ ENTRY(syscall_exit)
1995 1987
1996 /* We can't use "CMPIB<> PER_HPUX" since "im5" field is sign extended */ 1988 /* We can't use "CMPIB<> PER_HPUX" since "im5" field is sign extended */
1997 ldo -PER_HPUX(%r19), %r19 1989 ldo -PER_HPUX(%r19), %r19
1998 CMPIB<>,n 0,%r19,1f 1990 cmpib,COND(<>),n 0,%r19,1f
1999 1991
2000 /* Save other hpux returns if personality is PER_HPUX */ 1992 /* Save other hpux returns if personality is PER_HPUX */
2001 STREG %r22,TASK_PT_GR22(%r1) 1993 STREG %r22,TASK_PT_GR22(%r1)