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authorJames Bottomley <James.Bottomley@HansenPartnership.com>2010-12-22 11:22:11 -0500
committerJames Bottomley <James.Bottomley@suse.de>2011-01-15 09:44:40 -0500
commitf311847c2fcebd81912e2f0caf8a461dec28db41 (patch)
tree802ef2aa01bd0d662e60412366a40c827fd3e875 /arch/parisc/include/asm
parent38567333a6dabd0f2b4150e9fb6dd8e3ba2985e5 (diff)
parisc: flush pages through tmpalias space
The kernel has an 8M tmpailas space (originally designed for copying and clearing pages but now only used for clearing). The idea is to place zeros into the cache above a physical page rather than into the physical page and flush the cache, because often the zeros end up being replaced quickly anyway. We can also use the tmpalias space for flushing a page. The difference here is that we have to do tmpalias processing in the non access data and instruction traps. The principle is the same: as long as we know the physical address and have a virtual address congruent to the real one, the flush will be effective. In order to use the tmpalias space, the icache miss path has to be enhanced to check for the alias region to make the fic instruction effective. Signed-off-by: James Bottomley <James.Bottomley@suse.de>
Diffstat (limited to 'arch/parisc/include/asm')
-rw-r--r--arch/parisc/include/asm/cacheflush.h7
1 files changed, 4 insertions, 3 deletions
diff --git a/arch/parisc/include/asm/cacheflush.h b/arch/parisc/include/asm/cacheflush.h
index f388a85bba11..dc9286a4dcc7 100644
--- a/arch/parisc/include/asm/cacheflush.h
+++ b/arch/parisc/include/asm/cacheflush.h
@@ -26,8 +26,6 @@ void flush_user_dcache_range_asm(unsigned long, unsigned long);
26void flush_kernel_dcache_range_asm(unsigned long, unsigned long); 26void flush_kernel_dcache_range_asm(unsigned long, unsigned long);
27void flush_kernel_dcache_page_asm(void *); 27void flush_kernel_dcache_page_asm(void *);
28void flush_kernel_icache_page(void *); 28void flush_kernel_icache_page(void *);
29void flush_user_dcache_page(unsigned long);
30void flush_user_icache_page(unsigned long);
31void flush_user_dcache_range(unsigned long, unsigned long); 29void flush_user_dcache_range(unsigned long, unsigned long);
32void flush_user_icache_range(unsigned long, unsigned long); 30void flush_user_icache_range(unsigned long, unsigned long);
33 31
@@ -90,12 +88,15 @@ void flush_cache_page(struct vm_area_struct *vma, unsigned long vmaddr, unsigned
90void flush_cache_range(struct vm_area_struct *vma, 88void flush_cache_range(struct vm_area_struct *vma,
91 unsigned long start, unsigned long end); 89 unsigned long start, unsigned long end);
92 90
91/* defined in pacache.S exported in cache.c used by flush_anon_page */
92void flush_dcache_page_asm(unsigned long phys_addr, unsigned long vaddr);
93
93#define ARCH_HAS_FLUSH_ANON_PAGE 94#define ARCH_HAS_FLUSH_ANON_PAGE
94static inline void 95static inline void
95flush_anon_page(struct vm_area_struct *vma, struct page *page, unsigned long vmaddr) 96flush_anon_page(struct vm_area_struct *vma, struct page *page, unsigned long vmaddr)
96{ 97{
97 if (PageAnon(page)) 98 if (PageAnon(page))
98 flush_user_dcache_page(vmaddr); 99 flush_dcache_page_asm(page_to_phys(page), vmaddr);
99} 100}
100 101
101#define ARCH_HAS_FLUSH_KERNEL_DCACHE_PAGE 102#define ARCH_HAS_FLUSH_KERNEL_DCACHE_PAGE