MN10300: And Panasonic AM34 subarch and implement SMP

Implement the Panasonic MN10300 AM34 CPU subarch and implement SMP support for
MN10300.  Also implement support for the MN2WS0060 processor and the ASB2364
evaluation board which are AM34 based.

Signed-off-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com>
Signed-off-by: Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com>
Signed-off-by: David Howells <dhowells@redhat.com>

5 files changed, 409 insertions, 0 deletions

diff --git a/arch/mn10300/unit-asb2364/include/unit/clock.h b/arch/mn10300/unit-asb2364/include/unit/clock.h
new file mode 100644
index 000000000000..d34ac9a7508b
--- /dev/null
+++ b/arch/mn10300/unit-asb2364/include/unit/clock.h
@@ -0,0 +1,29 @@
+/* clock.h: unit-specific clocks
+ *
+ * Copyright (C) 2002 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ *
+ * Modified by Matsushita Electric Industrial Co., Ltd.
+ * Modifications:
+ *      23-Feb-2007 MEI Add define for watchdog timer.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#ifndef _ASM_UNIT_CLOCK_H
+#define _ASM_UNIT_CLOCK_H
+
+#ifndef __ASSEMBLY__
+
+#define MN10300_IOCLK           100000000UL             /* for DDR800 */
+/*#define MN10300_IOCLK         83333333UL */           /* for DDR667 */
+#define MN10300_IOBCLK          MN10300_IOCLK           /* IOBCLK is equal to IOCLK */
+
+#endif /* !__ASSEMBLY__ */
+
+#define MN10300_WDCLK           27000000UL
+
+#endif /* _ASM_UNIT_CLOCK_H */
diff --git a/arch/mn10300/unit-asb2364/include/unit/fpga-regs.h b/arch/mn10300/unit-asb2364/include/unit/fpga-regs.h
new file mode 100644
index 000000000000..a039a50c91db
--- /dev/null
+++ b/arch/mn10300/unit-asb2364/include/unit/fpga-regs.h
@@ -0,0 +1,50 @@
+/* ASB2364 FPGA registers
+ */
+
+#ifndef _ASM_UNIT_FPGA_REGS_H
+#define _ASM_UNIT_FPGA_REGS_H
+
+#include <asm/cpu-regs.h>
+
+#ifdef __KERNEL__
+
+#define ASB2364_FPGA_REG_RESET_LAN      __SYSREG(0xa9001300, u16)
+#define ASB2364_FPGA_REG_RESET_UART     __SYSREG(0xa9001304, u16)
+#define ASB2364_FPGA_REG_RESET_I2C      __SYSREG(0xa9001308, u16)
+#define ASB2364_FPGA_REG_RESET_USB      __SYSREG(0xa900130c, u16)
+#define ASB2364_FPGA_REG_RESET_AV       __SYSREG(0xa9001310, u16)
+
+#define ASB2364_FPGA_REG_IRQ_LAN        __SYSREG(0xa9001510, u16)
+#define ASB2364_FPGA_REG_IRQ_UART       __SYSREG(0xa9001514, u16)
+#define ASB2364_FPGA_REG_IRQ_I2C        __SYSREG(0xa9001518, u16)
+#define ASB2364_FPGA_REG_IRQ_USB        __SYSREG(0xa900151c, u16)
+#define ASB2364_FPGA_REG_IRQ_FPGA       __SYSREG(0xa9001524, u16)
+
+#define ASB2364_FPGA_REG_MASK_LAN       __SYSREG(0xa9001590, u16)
+#define ASB2364_FPGA_REG_MASK_UART      __SYSREG(0xa9001594, u16)
+#define ASB2364_FPGA_REG_MASK_I2C       __SYSREG(0xa9001598, u16)
+#define ASB2364_FPGA_REG_MASK_USB       __SYSREG(0xa900159c, u16)
+#define ASB2364_FPGA_REG_MASK_FPGA      __SYSREG(0xa90015a4, u16)
+
+#define ASB2364_FPGA_REG_CPLD5_SET1     __SYSREG(0xa9002500, u16)
+#define ASB2364_FPGA_REG_CPLD5_SET2     __SYSREG(0xa9002504, u16)
+#define ASB2364_FPGA_REG_CPLD6_SET1     __SYSREG(0xa9002600, u16)
+#define ASB2364_FPGA_REG_CPLD6_SET2     __SYSREG(0xa9002604, u16)
+#define ASB2364_FPGA_REG_CPLD7_SET1     __SYSREG(0xa9002700, u16)
+#define ASB2364_FPGA_REG_CPLD7_SET2     __SYSREG(0xa9002704, u16)
+#define ASB2364_FPGA_REG_CPLD8_SET1     __SYSREG(0xa9002800, u16)
+#define ASB2364_FPGA_REG_CPLD8_SET2     __SYSREG(0xa9002804, u16)
+#define ASB2364_FPGA_REG_CPLD9_SET1     __SYSREG(0xa9002900, u16)
+#define ASB2364_FPGA_REG_CPLD9_SET2     __SYSREG(0xa9002904, u16)
+#define ASB2364_FPGA_REG_CPLD10_SET1    __SYSREG(0xa9002a00, u16)
+#define ASB2364_FPGA_REG_CPLD10_SET2    __SYSREG(0xa9002a04, u16)
+
+#define SyncExBus()                                     \
+        do {                                            \
+                unsigned short w;                       \
+                w = *(volatile short *)0xa9000000;      \
+        } while (0)
+
+#endif /* __KERNEL__ */
+
+#endif /* _ASM_UNIT_FPGA_REGS_H */
diff --git a/arch/mn10300/unit-asb2364/include/unit/leds.h b/arch/mn10300/unit-asb2364/include/unit/leds.h
new file mode 100644
index 000000000000..03a3933ad323
--- /dev/null
+++ b/arch/mn10300/unit-asb2364/include/unit/leds.h
@@ -0,0 +1,54 @@
+/* Unit-specific leds
+ *
+ * Copyright (C) 2005 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#ifndef _ASM_UNIT_LEDS_H
+#define _ASM_UNIT_LEDS_H
+
+#include <asm/pio-regs.h>
+#include <asm/cpu-regs.h>
+#include <asm/exceptions.h>
+
+#define MN10300_USE_7SEGLEDS    0
+
+#define ASB2364_7SEGLEDS        __SYSREG(0xA9001630, u32)
+
+/*
+ * use the 7-segment LEDs to indicate states
+ */
+
+#if MN10300_USE_7SEGLEDS
+/* flip the 7-segment LEDs between "Gdb-" and "----" */
+#define mn10300_set_gdbleds(ONOFF)                                      \
+        do {                                                            \
+                ASB2364_7SEGLEDS = (ONOFF) ? 0x8543077f : 0x7f7f7f7f;   \
+        } while (0)
+#else
+#define mn10300_set_gdbleds(ONOFF) do {} while (0)
+#endif
+
+#if MN10300_USE_7SEGLEDS
+/* indicate double-fault by displaying "db-f" on the LEDs */
+#define mn10300_set_dbfleds                     \
+        mov     0x43077f1d,d0           ;       \
+        mov     d0,(ASB2364_7SEGLEDS)
+#else
+#define mn10300_set_dbfleds
+#endif
+
+#ifndef __ASSEMBLY__
+extern void peripheral_leds_display_exception(enum exception_code);
+extern void peripheral_leds_led_chase(void);
+extern void peripheral_leds7x4_display_dec(unsigned int, unsigned int);
+extern void peripheral_leds7x4_display_hex(unsigned int, unsigned int);
+extern void debug_to_serial(const char *, int);
+#endif /* __ASSEMBLY__ */
+
+#endif /* _ASM_UNIT_LEDS_H */
diff --git a/arch/mn10300/unit-asb2364/include/unit/serial.h b/arch/mn10300/unit-asb2364/include/unit/serial.h
new file mode 100644
index 000000000000..7f048bbfdfd7
--- /dev/null
+++ b/arch/mn10300/unit-asb2364/include/unit/serial.h
@@ -0,0 +1,151 @@
+/* Unit-specific 8250 serial ports
+ *
+ * Copyright (C) 2005 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#ifndef _ASM_UNIT_SERIAL_H
+#define _ASM_UNIT_SERIAL_H
+
+#include <asm/cpu-regs.h>
+#include <proc/irq.h>
+#include <unit/fpga-regs.h>
+#include <linux/serial_reg.h>
+
+#define SERIAL_PORT0_BASE_ADDRESS       0xA8200000
+
+#define SERIAL_IRQ      XIRQ1   /* single serial (TL16C550C)    (Lo) */
+
+/*
+ * The ASB2364 has an 12.288 MHz clock
+ * for your UART.
+ *
+ * It'd be nice if someone built a serial card with a 24.576 MHz
+ * clock, since the 16550A is capable of handling a top speed of 1.5
+ * megabits/second; but this requires the faster clock.
+ */
+#define BASE_BAUD (12288000 / 16)
+
+/*
+ * dispose of the /dev/ttyS0 and /dev/ttyS1 serial ports
+ */
+#ifndef CONFIG_GDBSTUB_ON_TTYSx
+
+#define SERIAL_PORT_DFNS                                                \
+        {                                                               \
+                .baud_base      = BASE_BAUD,                            \
+                .irq            = SERIAL_IRQ,                           \
+                .flags          = STD_COM_FLAGS,                        \
+                .iomem_base     = (u8 *) SERIAL_PORT0_BASE_ADDRESS,     \
+                .iomem_reg_shift = 1,                                   \
+                .io_type        = SERIAL_IO_MEM,                        \
+        },
+
+#ifndef __ASSEMBLY__
+
+static inline void __debug_to_serial(const char *p, int n)
+{
+}
+
+#endif /* !__ASSEMBLY__ */
+
+#else /* CONFIG_GDBSTUB_ON_TTYSx */
+
+#define SERIAL_PORT_DFNS /* stolen by gdb-stub */
+
+#if defined(CONFIG_GDBSTUB_ON_TTYS0)
+#define GDBPORT_SERIAL_RX       __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_RX  * 4, u8)
+#define GDBPORT_SERIAL_TX       __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_TX  * 4, u8)
+#define GDBPORT_SERIAL_DLL      __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_DLL * 4, u8)
+#define GDBPORT_SERIAL_DLM      __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_DLM * 4, u8)
+#define GDBPORT_SERIAL_IER      __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_IER * 4, u8)
+#define GDBPORT_SERIAL_IIR      __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_IIR * 4, u8)
+#define GDBPORT_SERIAL_FCR      __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_FCR * 4, u8)
+#define GDBPORT_SERIAL_LCR      __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_LCR * 4, u8)
+#define GDBPORT_SERIAL_MCR      __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_MCR * 4, u8)
+#define GDBPORT_SERIAL_LSR      __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_LSR * 4, u8)
+#define GDBPORT_SERIAL_MSR      __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_MSR * 4, u8)
+#define GDBPORT_SERIAL_SCR      __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_SCR * 4, u8)
+#define GDBPORT_SERIAL_IRQ      SERIAL_IRQ
+
+#elif defined(CONFIG_GDBSTUB_ON_TTYS1)
+#error The ASB2364 does not have a /dev/ttyS1
+#endif
+
+#ifndef __ASSEMBLY__
+
+static inline void __debug_to_serial(const char *p, int n)
+{
+        char ch;
+
+#define LSR_WAIT_FOR(STATE)     \
+        do {} while (!(GDBPORT_SERIAL_LSR & UART_LSR_##STATE))
+#define FLOWCTL_QUERY(LINE)     \
+        ({ GDBPORT_SERIAL_MSR & UART_MSR_##LINE; })
+#define FLOWCTL_WAIT_FOR(LINE)  \
+        do {} while (!(GDBPORT_SERIAL_MSR & UART_MSR_##LINE))
+#define FLOWCTL_CLEAR(LINE)     \
+        do { GDBPORT_SERIAL_MCR &= ~UART_MCR_##LINE; } while (0)
+#define FLOWCTL_SET(LINE)       \
+        do { GDBPORT_SERIAL_MCR |= UART_MCR_##LINE; } while (0)
+
+        FLOWCTL_SET(DTR);
+
+        for (; n > 0; n--) {
+                LSR_WAIT_FOR(THRE);
+                FLOWCTL_WAIT_FOR(CTS);
+
+                ch = *p++;
+                if (ch == 0x0a) {
+                        GDBPORT_SERIAL_TX = 0x0d;
+                        LSR_WAIT_FOR(THRE);
+                        FLOWCTL_WAIT_FOR(CTS);
+                }
+                GDBPORT_SERIAL_TX = ch;
+        }
+
+        FLOWCTL_CLEAR(DTR);
+}
+
+#endif /* !__ASSEMBLY__ */
+
+#endif /* CONFIG_GDBSTUB_ON_TTYSx */
+
+#define SERIAL_INITIALIZE                                       \
+do {                                                            \
+        /* release reset */                                     \
+        ASB2364_FPGA_REG_RESET_UART = 0x0001;                   \
+        SyncExBus();                                            \
+} while (0)
+
+#define SERIAL_CHECK_INTERRUPT                                  \
+do {                                                            \
+        if ((ASB2364_FPGA_REG_IRQ_UART & 0x0001) == 0x0001) {   \
+                return IRQ_NONE;                                \
+        }                                                       \
+} while (0)
+
+#define SERIAL_CLEAR_INTERRUPT                                  \
+do {                                                            \
+        ASB2364_FPGA_REG_IRQ_UART = 0x0001;                     \
+        SyncExBus();                                            \
+} while (0)
+
+#define SERIAL_SET_INT_MASK                                     \
+do {                                                            \
+        ASB2364_FPGA_REG_MASK_UART = 0x0001;                    \
+        SyncExBus();                                            \
+} while (0)
+
+#define SERIAL_CLEAR_INT_MASK                                   \
+do {                                                            \
+        ASB2364_FPGA_REG_MASK_UART = 0x0000;                    \
+        SyncExBus();                                            \
+} while (0)
+
+#endif /* _ASM_UNIT_SERIAL_H */
diff --git a/arch/mn10300/unit-asb2364/include/unit/timex.h b/arch/mn10300/unit-asb2364/include/unit/timex.h
new file mode 100644
index 000000000000..b5223f705ef8
--- /dev/null
+++ b/arch/mn10300/unit-asb2364/include/unit/timex.h
@@ -0,0 +1,125 @@
+/* timex.h: MN2WS0038 architecture timer specifications
+ *
+ * Copyright (C) 2002 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+#ifndef _ASM_UNIT_TIMEX_H
+#define _ASM_UNIT_TIMEX_H
+
+#ifndef __ASSEMBLY__
+#include <linux/irq.h>
+#endif /* __ASSEMBLY__ */
+
+#include <asm/timer-regs.h>
+#include <unit/clock.h>
+#include <asm/param.h>
+
+/*
+ * jiffies counter specifications
+ */
+
+#define TMJCBR_MAX              0xffffff        /* 24bit */
+#define TMJCBC                  TMTBC
+
+#define TMJCMD                  TMTMD
+#define TMJCBR                  TMTBR
+#define TMJCIRQ                 TMTIRQ
+#define TMJCICR                 TMTICR
+
+#ifndef __ASSEMBLY__
+
+#define MN10300_SRC_IOBCLK      MN10300_IOBCLK
+
+#ifndef HZ
+# error HZ undeclared.
+#endif /* !HZ */
+
+#define MN10300_JCCLK           (MN10300_SRC_IOBCLK)
+#define MN10300_TSCCLK          (MN10300_SRC_IOBCLK)
+
+#define MN10300_JC_PER_HZ       ((MN10300_JCCLK + HZ / 2) / HZ)
+#define MN10300_TSC_PER_HZ      ((MN10300_TSCCLK + HZ / 2) / HZ)
+
+/* Check bit width of MTM interval value that sets base register */
+#if (MN10300_JC_PER_HZ - 1) > TMJCBR_MAX
+# error MTM tick timer interval value is overflow.
+#endif
+
+
+static inline void startup_jiffies_counter(void)
+{
+        u32 sync;
+
+        TMJCBR = MN10300_JC_PER_HZ - 1;
+        sync = TMJCBR;
+
+        TMJCMD = TMTMD_TMTLDE;
+        TMJCMD = TMTMD_TMTCNE;
+        sync = TMJCMD;
+
+        TMJCICR |= GxICR_ENABLE | GxICR_DETECT | GxICR_REQUEST;
+        sync = TMJCICR;
+}
+
+static inline void shutdown_jiffies_counter(void)
+{
+}
+
+#endif /* !__ASSEMBLY__ */
+
+
+/*
+ * timestamp counter specifications
+ */
+
+#define TMTSCBR_MAX     0xffffffff
+#define TMTSCMD         TMSMD
+#define TMTSCBR         TMSBR
+#define TMTSCBC         TMSBC
+#define TMTSCICR        TMSICR
+
+#ifndef __ASSEMBLY__
+
+static inline void startup_timestamp_counter(void)
+{
+        u32 sync;
+
+        /* set up TMS(Timestamp) 32bit timer register to count real time
+         * - count down from 4Gig-1 to 0 and wrap at IOBCLK rate
+         */
+
+        TMTSCBR = TMTSCBR_MAX;
+        sync = TMTSCBR;
+
+        TMTSCICR = 0;
+        sync = TMTSCICR;
+
+        TMTSCMD = TMTMD_TMTLDE;
+        TMTSCMD = TMTMD_TMTCNE;
+        sync = TMTSCMD;
+}
+
+static inline void shutdown_timestamp_counter(void)
+{
+        TMTSCMD = 0;
+}
+
+/*
+ * we use a cascaded pair of 16-bit down-counting timers to count I/O
+ * clock cycles for the purposes of time keeping
+ */
+typedef unsigned long cycles_t;
+
+static inline cycles_t read_timestamp_counter(void)
+{
+        return (cycles_t)TMTSCBC;
+}
+
+#endif /* !__ASSEMBLY__ */
+
+#endif /* _ASM_UNIT_TIMEX_H */