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authorLinus Torvalds <torvalds@linux-foundation.org>2010-10-27 21:53:26 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2010-10-27 21:53:26 -0400
commitbdab225015fbbb45ccd8913f5d7c01b2bf67d8b2 (patch)
tree5ef62301face958977a084bf2b6c5300296a25f2 /arch/mn10300/proc-mn103e010/proc-init.c
parent7c5814c7199851c5fe9395d08fc1ab3c8c1531ea (diff)
parent7c7fcf762e405eb040ee10d22d656a791f616122 (diff)
Merge git://git.kernel.org/pub/scm/linux/kernel/git/dhowells/linux-2.6-mn10300
* git://git.kernel.org/pub/scm/linux/kernel/git/dhowells/linux-2.6-mn10300: (44 commits) MN10300: Save frame pointer in thread_info struct rather than global var MN10300: Change "Matsushita" to "Panasonic". MN10300: Create a defconfig for the ASB2364 board MN10300: Update the ASB2303 defconfig MN10300: ASB2364: Add support for SMSC911X and SMC911X MN10300: ASB2364: Handle the IRQ multiplexer in the FPGA MN10300: Generic time support MN10300: Specify an ELF HWCAP flag for MN10300 Atomic Operations Unit support MN10300: Map userspace atomic op regs as a vmalloc page MN10300: And Panasonic AM34 subarch and implement SMP MN10300: Delete idle_timestamp from irq_cpustat_t MN10300: Make various interrupt priority settings configurable MN10300: Optimise do_csum() MN10300: Implement atomic ops using atomic ops unit MN10300: Make the FPU operate in non-lazy mode under SMP MN10300: SMP TLB flushing MN10300: Use the [ID]PTEL2 registers rather than [ID]PTEL for TLB control MN10300: Make the use of PIDR to mark TLB entries controllable MN10300: Rename __flush_tlb*() to local_flush_tlb*() MN10300: AM34 erratum requires MMUCTR read and write on exception entry ...
Diffstat (limited to 'arch/mn10300/proc-mn103e010/proc-init.c')
-rw-r--r--arch/mn10300/proc-mn103e010/proc-init.c37
1 files changed, 37 insertions, 0 deletions
diff --git a/arch/mn10300/proc-mn103e010/proc-init.c b/arch/mn10300/proc-mn103e010/proc-init.c
index 9a482efafa82..27b97980dca4 100644
--- a/arch/mn10300/proc-mn103e010/proc-init.c
+++ b/arch/mn10300/proc-mn103e010/proc-init.c
@@ -9,7 +9,9 @@
9 * 2 of the Licence, or (at your option) any later version. 9 * 2 of the Licence, or (at your option) any later version.
10 */ 10 */
11#include <linux/kernel.h> 11#include <linux/kernel.h>
12#include <asm/fpu.h>
12#include <asm/rtc.h> 13#include <asm/rtc.h>
14#include <asm/busctl-regs.h>
13 15
14/* 16/*
15 * initialise the on-silicon processor peripherals 17 * initialise the on-silicon processor peripherals
@@ -28,6 +30,7 @@ asmlinkage void __init processor_init(void)
28 __set_intr_stub(EXCEP_DAERROR, dtlb_aerror); 30 __set_intr_stub(EXCEP_DAERROR, dtlb_aerror);
29 __set_intr_stub(EXCEP_BUSERROR, raw_bus_error); 31 __set_intr_stub(EXCEP_BUSERROR, raw_bus_error);
30 __set_intr_stub(EXCEP_DOUBLE_FAULT, double_fault); 32 __set_intr_stub(EXCEP_DOUBLE_FAULT, double_fault);
33 __set_intr_stub(EXCEP_FPU_DISABLED, fpu_disabled);
31 __set_intr_stub(EXCEP_SYSCALL0, system_call); 34 __set_intr_stub(EXCEP_SYSCALL0, system_call);
32 35
33 __set_intr_stub(EXCEP_NMI, nmi_handler); 36 __set_intr_stub(EXCEP_NMI, nmi_handler);
@@ -73,3 +76,37 @@ asmlinkage void __init processor_init(void)
73 76
74 calibrate_clock(); 77 calibrate_clock();
75} 78}
79
80/*
81 * determine the memory size and base from the memory controller regs
82 */
83void __init get_mem_info(unsigned long *mem_base, unsigned long *mem_size)
84{
85 unsigned long base, size;
86
87 *mem_base = 0;
88 *mem_size = 0;
89
90 base = SDBASE(0);
91 if (base & SDBASE_CE) {
92 size = (base & SDBASE_CBAM) << SDBASE_CBAM_SHIFT;
93 size = ~size + 1;
94 base &= SDBASE_CBA;
95
96 printk(KERN_INFO "SDRAM[0]: %luMb @%08lx\n", size >> 20, base);
97 *mem_size += size;
98 *mem_base = base;
99 }
100
101 base = SDBASE(1);
102 if (base & SDBASE_CE) {
103 size = (base & SDBASE_CBAM) << SDBASE_CBAM_SHIFT;
104 size = ~size + 1;
105 base &= SDBASE_CBA;
106
107 printk(KERN_INFO "SDRAM[1]: %luMb @%08lx\n", size >> 20, base);
108 *mem_size += size;
109 if (*mem_base == 0)
110 *mem_base = base;
111 }
112}