diff options
author | Akira Takeuchi <takeuchi.akr@jp.panasonic.com> | 2010-10-27 12:28:49 -0400 |
---|---|---|
committer | David Howells <dhowells@redhat.com> | 2010-10-27 12:28:49 -0400 |
commit | a9bc60ebfd5766ce5f6095d0fed3d9978990122f (patch) | |
tree | d6044bbb56bbb06fb6f13fab9f079a20938d0960 /arch/mn10300/mm | |
parent | 492e675116003b99dfcf0fa70084027e86bc0161 (diff) |
MN10300: Make the use of PIDR to mark TLB entries controllable
Make controllable the use of the PIDR register to mark TLB entries as belonging
to particular processes.
Signed-off-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com>
Signed-off-by: Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com>
Signed-off-by: David Howells <dhowells@redhat.com>
Diffstat (limited to 'arch/mn10300/mm')
-rw-r--r-- | arch/mn10300/mm/mmu-context.c | 41 |
1 files changed, 11 insertions, 30 deletions
diff --git a/arch/mn10300/mm/mmu-context.c b/arch/mn10300/mm/mmu-context.c index 3d83966e30e1..a4f7d3dcc6e6 100644 --- a/arch/mn10300/mm/mmu-context.c +++ b/arch/mn10300/mm/mmu-context.c | |||
@@ -13,40 +13,15 @@ | |||
13 | #include <asm/mmu_context.h> | 13 | #include <asm/mmu_context.h> |
14 | #include <asm/tlbflush.h> | 14 | #include <asm/tlbflush.h> |
15 | 15 | ||
16 | #ifdef CONFIG_MN10300_TLB_USE_PIDR | ||
16 | /* | 17 | /* |
17 | * list of the MMU contexts last allocated on each CPU | 18 | * list of the MMU contexts last allocated on each CPU |
18 | */ | 19 | */ |
19 | unsigned long mmu_context_cache[NR_CPUS] = { | 20 | unsigned long mmu_context_cache[NR_CPUS] = { |
20 | [0 ... NR_CPUS - 1] = MMU_CONTEXT_FIRST_VERSION * 2 - 1, | 21 | [0 ... NR_CPUS - 1] = |
22 | MMU_CONTEXT_FIRST_VERSION * 2 - (1 - MMU_CONTEXT_TLBPID_LOCK_NR), | ||
21 | }; | 23 | }; |
22 | 24 | #endif /* CONFIG_MN10300_TLB_USE_PIDR */ | |
23 | /* | ||
24 | * flush the specified TLB entry | ||
25 | */ | ||
26 | void local_flush_tlb_page(struct mm_struct *mm, unsigned long addr) | ||
27 | { | ||
28 | unsigned long pteu, cnx, flags; | ||
29 | |||
30 | addr &= PAGE_MASK; | ||
31 | |||
32 | /* make sure the context doesn't migrate and defend against | ||
33 | * interference from vmalloc'd regions */ | ||
34 | local_irq_save(flags); | ||
35 | |||
36 | cnx = mm_context(mm); | ||
37 | |||
38 | if (cnx != MMU_NO_CONTEXT) { | ||
39 | pteu = addr | (cnx & 0x000000ffUL); | ||
40 | IPTEU = pteu; | ||
41 | DPTEU = pteu; | ||
42 | if (IPTEL & xPTEL_V) | ||
43 | IPTEL = 0; | ||
44 | if (DPTEL & xPTEL_V) | ||
45 | DPTEL = 0; | ||
46 | } | ||
47 | |||
48 | local_irq_restore(flags); | ||
49 | } | ||
50 | 25 | ||
51 | /* | 26 | /* |
52 | * preemptively set a TLB entry | 27 | * preemptively set a TLB entry |
@@ -63,10 +38,16 @@ void update_mmu_cache(struct vm_area_struct *vma, unsigned long addr, pte_t *pte | |||
63 | * interference from vmalloc'd regions */ | 38 | * interference from vmalloc'd regions */ |
64 | local_irq_save(flags); | 39 | local_irq_save(flags); |
65 | 40 | ||
41 | cnx = ~MMU_NO_CONTEXT; | ||
42 | #ifdef CONFIG_MN10300_TLB_USE_PIDR | ||
66 | cnx = mm_context(vma->vm_mm); | 43 | cnx = mm_context(vma->vm_mm); |
44 | #endif | ||
67 | 45 | ||
68 | if (cnx != MMU_NO_CONTEXT) { | 46 | if (cnx != MMU_NO_CONTEXT) { |
69 | pteu = addr | (cnx & 0x000000ffUL); | 47 | pteu = addr; |
48 | #ifdef CONFIG_MN10300_TLB_USE_PIDR | ||
49 | pteu |= cnx & MMU_CONTEXT_TLBPID_MASK; | ||
50 | #endif | ||
70 | if (!(pte_val(pte) & _PAGE_NX)) { | 51 | if (!(pte_val(pte) & _PAGE_NX)) { |
71 | IPTEU = pteu; | 52 | IPTEU = pteu; |
72 | if (IPTEL & xPTEL_V) | 53 | if (IPTEL & xPTEL_V) |