diff options
author | Linus Torvalds <torvalds@linux-foundation.org> | 2010-10-27 21:53:26 -0400 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2010-10-27 21:53:26 -0400 |
commit | bdab225015fbbb45ccd8913f5d7c01b2bf67d8b2 (patch) | |
tree | 5ef62301face958977a084bf2b6c5300296a25f2 /arch/mn10300/mm/cache-smp-inv.c | |
parent | 7c5814c7199851c5fe9395d08fc1ab3c8c1531ea (diff) | |
parent | 7c7fcf762e405eb040ee10d22d656a791f616122 (diff) |
Merge git://git.kernel.org/pub/scm/linux/kernel/git/dhowells/linux-2.6-mn10300
* git://git.kernel.org/pub/scm/linux/kernel/git/dhowells/linux-2.6-mn10300: (44 commits)
MN10300: Save frame pointer in thread_info struct rather than global var
MN10300: Change "Matsushita" to "Panasonic".
MN10300: Create a defconfig for the ASB2364 board
MN10300: Update the ASB2303 defconfig
MN10300: ASB2364: Add support for SMSC911X and SMC911X
MN10300: ASB2364: Handle the IRQ multiplexer in the FPGA
MN10300: Generic time support
MN10300: Specify an ELF HWCAP flag for MN10300 Atomic Operations Unit support
MN10300: Map userspace atomic op regs as a vmalloc page
MN10300: And Panasonic AM34 subarch and implement SMP
MN10300: Delete idle_timestamp from irq_cpustat_t
MN10300: Make various interrupt priority settings configurable
MN10300: Optimise do_csum()
MN10300: Implement atomic ops using atomic ops unit
MN10300: Make the FPU operate in non-lazy mode under SMP
MN10300: SMP TLB flushing
MN10300: Use the [ID]PTEL2 registers rather than [ID]PTEL for TLB control
MN10300: Make the use of PIDR to mark TLB entries controllable
MN10300: Rename __flush_tlb*() to local_flush_tlb*()
MN10300: AM34 erratum requires MMUCTR read and write on exception entry
...
Diffstat (limited to 'arch/mn10300/mm/cache-smp-inv.c')
-rw-r--r-- | arch/mn10300/mm/cache-smp-inv.c | 153 |
1 files changed, 153 insertions, 0 deletions
diff --git a/arch/mn10300/mm/cache-smp-inv.c b/arch/mn10300/mm/cache-smp-inv.c new file mode 100644 index 000000000000..ff1787358c8e --- /dev/null +++ b/arch/mn10300/mm/cache-smp-inv.c | |||
@@ -0,0 +1,153 @@ | |||
1 | /* Functions for global i/dcache invalidation when caching in SMP | ||
2 | * | ||
3 | * Copyright (C) 2010 Red Hat, Inc. All Rights Reserved. | ||
4 | * Written by David Howells (dhowells@redhat.com) | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or | ||
7 | * modify it under the terms of the GNU General Public Licence | ||
8 | * as published by the Free Software Foundation; either version | ||
9 | * 2 of the Licence, or (at your option) any later version. | ||
10 | */ | ||
11 | #include <linux/mm.h> | ||
12 | #include <asm/cacheflush.h> | ||
13 | #include "cache-smp.h" | ||
14 | |||
15 | /** | ||
16 | * mn10300_icache_inv - Globally invalidate instruction cache | ||
17 | * | ||
18 | * Invalidate the instruction cache on all CPUs. | ||
19 | */ | ||
20 | void mn10300_icache_inv(void) | ||
21 | { | ||
22 | unsigned long flags; | ||
23 | |||
24 | flags = smp_lock_cache(); | ||
25 | mn10300_local_icache_inv(); | ||
26 | smp_cache_call(SMP_ICACHE_INV, 0, 0); | ||
27 | smp_unlock_cache(flags); | ||
28 | } | ||
29 | |||
30 | /** | ||
31 | * mn10300_icache_inv_page - Globally invalidate a page of instruction cache | ||
32 | * @start: The address of the page of memory to be invalidated. | ||
33 | * | ||
34 | * Invalidate a range of addresses in the instruction cache on all CPUs | ||
35 | * covering the page that includes the given address. | ||
36 | */ | ||
37 | void mn10300_icache_inv_page(unsigned long start) | ||
38 | { | ||
39 | unsigned long flags; | ||
40 | |||
41 | start &= ~(PAGE_SIZE-1); | ||
42 | |||
43 | flags = smp_lock_cache(); | ||
44 | mn10300_local_icache_inv_page(start); | ||
45 | smp_cache_call(SMP_ICACHE_INV_RANGE, start, start + PAGE_SIZE); | ||
46 | smp_unlock_cache(flags); | ||
47 | } | ||
48 | |||
49 | /** | ||
50 | * mn10300_icache_inv_range - Globally invalidate range of instruction cache | ||
51 | * @start: The start address of the region to be invalidated. | ||
52 | * @end: The end address of the region to be invalidated. | ||
53 | * | ||
54 | * Invalidate a range of addresses in the instruction cache on all CPUs, | ||
55 | * between start and end-1 inclusive. | ||
56 | */ | ||
57 | void mn10300_icache_inv_range(unsigned long start, unsigned long end) | ||
58 | { | ||
59 | unsigned long flags; | ||
60 | |||
61 | flags = smp_lock_cache(); | ||
62 | mn10300_local_icache_inv_range(start, end); | ||
63 | smp_cache_call(SMP_ICACHE_INV_RANGE, start, end); | ||
64 | smp_unlock_cache(flags); | ||
65 | } | ||
66 | |||
67 | /** | ||
68 | * mn10300_icache_inv_range2 - Globally invalidate range of instruction cache | ||
69 | * @start: The start address of the region to be invalidated. | ||
70 | * @size: The size of the region to be invalidated. | ||
71 | * | ||
72 | * Invalidate a range of addresses in the instruction cache on all CPUs, | ||
73 | * between start and start+size-1 inclusive. | ||
74 | */ | ||
75 | void mn10300_icache_inv_range2(unsigned long start, unsigned long size) | ||
76 | { | ||
77 | unsigned long flags; | ||
78 | |||
79 | flags = smp_lock_cache(); | ||
80 | mn10300_local_icache_inv_range2(start, size); | ||
81 | smp_cache_call(SMP_ICACHE_INV_RANGE, start, start + size); | ||
82 | smp_unlock_cache(flags); | ||
83 | } | ||
84 | |||
85 | /** | ||
86 | * mn10300_dcache_inv - Globally invalidate data cache | ||
87 | * | ||
88 | * Invalidate the data cache on all CPUs. | ||
89 | */ | ||
90 | void mn10300_dcache_inv(void) | ||
91 | { | ||
92 | unsigned long flags; | ||
93 | |||
94 | flags = smp_lock_cache(); | ||
95 | mn10300_local_dcache_inv(); | ||
96 | smp_cache_call(SMP_DCACHE_INV, 0, 0); | ||
97 | smp_unlock_cache(flags); | ||
98 | } | ||
99 | |||
100 | /** | ||
101 | * mn10300_dcache_inv_page - Globally invalidate a page of data cache | ||
102 | * @start: The address of the page of memory to be invalidated. | ||
103 | * | ||
104 | * Invalidate a range of addresses in the data cache on all CPUs covering the | ||
105 | * page that includes the given address. | ||
106 | */ | ||
107 | void mn10300_dcache_inv_page(unsigned long start) | ||
108 | { | ||
109 | unsigned long flags; | ||
110 | |||
111 | start &= ~(PAGE_SIZE-1); | ||
112 | |||
113 | flags = smp_lock_cache(); | ||
114 | mn10300_local_dcache_inv_page(start); | ||
115 | smp_cache_call(SMP_DCACHE_INV_RANGE, start, start + PAGE_SIZE); | ||
116 | smp_unlock_cache(flags); | ||
117 | } | ||
118 | |||
119 | /** | ||
120 | * mn10300_dcache_inv_range - Globally invalidate range of data cache | ||
121 | * @start: The start address of the region to be invalidated. | ||
122 | * @end: The end address of the region to be invalidated. | ||
123 | * | ||
124 | * Invalidate a range of addresses in the data cache on all CPUs, between start | ||
125 | * and end-1 inclusive. | ||
126 | */ | ||
127 | void mn10300_dcache_inv_range(unsigned long start, unsigned long end) | ||
128 | { | ||
129 | unsigned long flags; | ||
130 | |||
131 | flags = smp_lock_cache(); | ||
132 | mn10300_local_dcache_inv_range(start, end); | ||
133 | smp_cache_call(SMP_DCACHE_INV_RANGE, start, end); | ||
134 | smp_unlock_cache(flags); | ||
135 | } | ||
136 | |||
137 | /** | ||
138 | * mn10300_dcache_inv_range2 - Globally invalidate range of data cache | ||
139 | * @start: The start address of the region to be invalidated. | ||
140 | * @size: The size of the region to be invalidated. | ||
141 | * | ||
142 | * Invalidate a range of addresses in the data cache on all CPUs, between start | ||
143 | * and start+size-1 inclusive. | ||
144 | */ | ||
145 | void mn10300_dcache_inv_range2(unsigned long start, unsigned long size) | ||
146 | { | ||
147 | unsigned long flags; | ||
148 | |||
149 | flags = smp_lock_cache(); | ||
150 | mn10300_local_dcache_inv_range2(start, size); | ||
151 | smp_cache_call(SMP_DCACHE_INV_RANGE, start, start + size); | ||
152 | smp_unlock_cache(flags); | ||
153 | } | ||