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authorLinus Torvalds <torvalds@linux-foundation.org>2010-10-27 21:53:26 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2010-10-27 21:53:26 -0400
commitbdab225015fbbb45ccd8913f5d7c01b2bf67d8b2 (patch)
tree5ef62301face958977a084bf2b6c5300296a25f2 /arch/mn10300/lib
parent7c5814c7199851c5fe9395d08fc1ab3c8c1531ea (diff)
parent7c7fcf762e405eb040ee10d22d656a791f616122 (diff)
Merge git://git.kernel.org/pub/scm/linux/kernel/git/dhowells/linux-2.6-mn10300
* git://git.kernel.org/pub/scm/linux/kernel/git/dhowells/linux-2.6-mn10300: (44 commits) MN10300: Save frame pointer in thread_info struct rather than global var MN10300: Change "Matsushita" to "Panasonic". MN10300: Create a defconfig for the ASB2364 board MN10300: Update the ASB2303 defconfig MN10300: ASB2364: Add support for SMSC911X and SMC911X MN10300: ASB2364: Handle the IRQ multiplexer in the FPGA MN10300: Generic time support MN10300: Specify an ELF HWCAP flag for MN10300 Atomic Operations Unit support MN10300: Map userspace atomic op regs as a vmalloc page MN10300: And Panasonic AM34 subarch and implement SMP MN10300: Delete idle_timestamp from irq_cpustat_t MN10300: Make various interrupt priority settings configurable MN10300: Optimise do_csum() MN10300: Implement atomic ops using atomic ops unit MN10300: Make the FPU operate in non-lazy mode under SMP MN10300: SMP TLB flushing MN10300: Use the [ID]PTEL2 registers rather than [ID]PTEL for TLB control MN10300: Make the use of PIDR to mark TLB entries controllable MN10300: Rename __flush_tlb*() to local_flush_tlb*() MN10300: AM34 erratum requires MMUCTR read and write on exception entry ...
Diffstat (limited to 'arch/mn10300/lib')
-rw-r--r--arch/mn10300/lib/bitops.c4
-rw-r--r--arch/mn10300/lib/delay.c8
-rw-r--r--arch/mn10300/lib/do_csum.S49
3 files changed, 28 insertions, 33 deletions
diff --git a/arch/mn10300/lib/bitops.c b/arch/mn10300/lib/bitops.c
index 440a7dcbf87b..a66c6cdaf442 100644
--- a/arch/mn10300/lib/bitops.c
+++ b/arch/mn10300/lib/bitops.c
@@ -15,7 +15,7 @@
15/* 15/*
16 * try flipping a bit using BSET and BCLR 16 * try flipping a bit using BSET and BCLR
17 */ 17 */
18void change_bit(int nr, volatile void *addr) 18void change_bit(unsigned long nr, volatile void *addr)
19{ 19{
20 if (test_bit(nr, addr)) 20 if (test_bit(nr, addr))
21 goto try_clear_bit; 21 goto try_clear_bit;
@@ -34,7 +34,7 @@ try_clear_bit:
34/* 34/*
35 * try flipping a bit using BSET and BCLR and returning the old value 35 * try flipping a bit using BSET and BCLR and returning the old value
36 */ 36 */
37int test_and_change_bit(int nr, volatile void *addr) 37int test_and_change_bit(unsigned long nr, volatile void *addr)
38{ 38{
39 if (test_bit(nr, addr)) 39 if (test_bit(nr, addr))
40 goto try_clear_bit; 40 goto try_clear_bit;
diff --git a/arch/mn10300/lib/delay.c b/arch/mn10300/lib/delay.c
index fdf6f710f94e..8e7ceb8ba33d 100644
--- a/arch/mn10300/lib/delay.c
+++ b/arch/mn10300/lib/delay.c
@@ -38,14 +38,14 @@ EXPORT_SYMBOL(__delay);
38 */ 38 */
39void __udelay(unsigned long usecs) 39void __udelay(unsigned long usecs)
40{ 40{
41 signed long ioclk, stop; 41 unsigned long start, stop, cnt;
42 42
43 /* usecs * CLK / 1E6 */ 43 /* usecs * CLK / 1E6 */
44 stop = __muldiv64u(usecs, MN10300_TSCCLK, 1000000); 44 stop = __muldiv64u(usecs, MN10300_TSCCLK, 1000000);
45 stop = TMTSCBC - stop; 45 start = TMTSCBC;
46 46
47 do { 47 do {
48 ioclk = TMTSCBC; 48 cnt = start - TMTSCBC;
49 } while (stop < ioclk); 49 } while (cnt < stop);
50} 50}
51EXPORT_SYMBOL(__udelay); 51EXPORT_SYMBOL(__udelay);
diff --git a/arch/mn10300/lib/do_csum.S b/arch/mn10300/lib/do_csum.S
index e138994e1667..1d27bba0cd8f 100644
--- a/arch/mn10300/lib/do_csum.S
+++ b/arch/mn10300/lib/do_csum.S
@@ -10,26 +10,25 @@
10 */ 10 */
11#include <asm/cache.h> 11#include <asm/cache.h>
12 12
13 .section .text 13 .section .text
14 .balign L1_CACHE_BYTES 14 .balign L1_CACHE_BYTES
15 15
16############################################################################### 16###############################################################################
17# 17#
18# unsigned int do_csum(const unsigned char *buff, size_t len) 18# unsigned int do_csum(const unsigned char *buff, int len)
19# 19#
20############################################################################### 20###############################################################################
21 .globl do_csum 21 .globl do_csum
22 .type do_csum,@function 22 .type do_csum,@function
23do_csum: 23do_csum:
24 movm [d2,d3],(sp) 24 movm [d2,d3],(sp)
25 mov d0,(12,sp)
26 mov d1,(16,sp)
27 mov d1,d2 # count 25 mov d1,d2 # count
28 mov d0,a0 # buff 26 mov d0,a0 # buff
27 mov a0,a1
29 clr d1 # accumulator 28 clr d1 # accumulator
30 29
31 cmp +0,d2 30 cmp +0,d2
32 beq do_csum_done # return if zero-length buffer 31 ble do_csum_done # check for zero length or negative
33 32
34 # 4-byte align the buffer pointer 33 # 4-byte align the buffer pointer
35 btst +3,a0 34 btst +3,a0
@@ -41,17 +40,15 @@ do_csum:
41 inc a0 40 inc a0
42 asl +8,d0 41 asl +8,d0
43 add d0,d1 42 add d0,d1
44 addc +0,d1
45 add -1,d2 43 add -1,d2
46do_csum_addr_not_odd:
47 44
45do_csum_addr_not_odd:
48 cmp +2,d2 46 cmp +2,d2
49 bcs do_csum_fewer_than_4 47 bcs do_csum_fewer_than_4
50 btst +2,a0 48 btst +2,a0
51 beq do_csum_now_4b_aligned 49 beq do_csum_now_4b_aligned
52 movhu (a0+),d0 50 movhu (a0+),d0
53 add d0,d1 51 add d0,d1
54 addc +0,d1
55 add -2,d2 52 add -2,d2
56 cmp +4,d2 53 cmp +4,d2
57 bcs do_csum_fewer_than_4 54 bcs do_csum_fewer_than_4
@@ -66,20 +63,20 @@ do_csum_now_4b_aligned:
66 63
67do_csum_loop: 64do_csum_loop:
68 mov (a0+),d0 65 mov (a0+),d0
69 add d0,d1
70 mov (a0+),e0 66 mov (a0+),e0
71 addc e0,d1
72 mov (a0+),e1 67 mov (a0+),e1
73 addc e1,d1
74 mov (a0+),e3 68 mov (a0+),e3
69 add d0,d1
70 addc e0,d1
71 addc e1,d1
75 addc e3,d1 72 addc e3,d1
76 mov (a0+),d0 73 mov (a0+),d0
77 addc d0,d1
78 mov (a0+),e0 74 mov (a0+),e0
79 addc e0,d1
80 mov (a0+),e1 75 mov (a0+),e1
81 addc e1,d1
82 mov (a0+),e3 76 mov (a0+),e3
77 addc d0,d1
78 addc e0,d1
79 addc e1,d1
83 addc e3,d1 80 addc e3,d1
84 addc +0,d1 81 addc +0,d1
85 82
@@ -94,12 +91,12 @@ do_csum_remainder:
94 cmp +16,d2 91 cmp +16,d2
95 bcs do_csum_fewer_than_16 92 bcs do_csum_fewer_than_16
96 mov (a0+),d0 93 mov (a0+),d0
97 add d0,d1
98 mov (a0+),e0 94 mov (a0+),e0
99 addc e0,d1
100 mov (a0+),e1 95 mov (a0+),e1
101 addc e1,d1
102 mov (a0+),e3 96 mov (a0+),e3
97 add d0,d1
98 addc e0,d1
99 addc e1,d1
103 addc e3,d1 100 addc e3,d1
104 addc +0,d1 101 addc +0,d1
105 add -16,d2 102 add -16,d2
@@ -131,9 +128,9 @@ do_csum_fewer_than_4:
131 xor_cmp d0,d0,+2,d2 128 xor_cmp d0,d0,+2,d2
132 bcs do_csum_fewer_than_2 129 bcs do_csum_fewer_than_2
133 movhu (a0+),d0 130 movhu (a0+),d0
134do_csum_fewer_than_2:
135 and +1,d2 131 and +1,d2
136 beq do_csum_add_last_bit 132 beq do_csum_add_last_bit
133do_csum_fewer_than_2:
137 movbu (a0),d3 134 movbu (a0),d3
138 add d3,d0 135 add d3,d0
139do_csum_add_last_bit: 136do_csum_add_last_bit:
@@ -142,21 +139,19 @@ do_csum_add_last_bit:
142 139
143do_csum_done: 140do_csum_done:
144 # compress the checksum down to 16 bits 141 # compress the checksum down to 16 bits
145 mov +0xffff0000,d2 142 mov +0xffff0000,d0
146 and d1,d2 143 and d1,d0
147 asl +16,d1 144 asl +16,d1
148 add d2,d1,d0 145 add d1,d0
149 addc +0xffff,d0 146 addc +0xffff,d0
150 lsr +16,d0 147 lsr +16,d0
151 148
152 # flip the halves of the word result if the buffer was oddly aligned 149 # flip the halves of the word result if the buffer was oddly aligned
153 mov (12,sp),d1 150 and +1,a1
154 and +1,d1
155 beq do_csum_not_oddly_aligned 151 beq do_csum_not_oddly_aligned
156 swaph d0,d0 # exchange bits 15:8 with 7:0 152 swaph d0,d0 # exchange bits 15:8 with 7:0
157 153
158do_csum_not_oddly_aligned: 154do_csum_not_oddly_aligned:
159 ret [d2,d3],8 155 ret [d2,d3],8
160 156
161do_csum_end: 157 .size do_csum, .-do_csum
162 .size do_csum, do_csum_end-do_csum