diff options
author | Akira Takeuchi <takeuchi.akr@jp.panasonic.com> | 2010-10-27 12:28:49 -0400 |
---|---|---|
committer | David Howells <dhowells@redhat.com> | 2010-10-27 12:28:49 -0400 |
commit | a9bc60ebfd5766ce5f6095d0fed3d9978990122f (patch) | |
tree | d6044bbb56bbb06fb6f13fab9f079a20938d0960 /arch/mn10300/include/asm/tlbflush.h | |
parent | 492e675116003b99dfcf0fa70084027e86bc0161 (diff) |
MN10300: Make the use of PIDR to mark TLB entries controllable
Make controllable the use of the PIDR register to mark TLB entries as belonging
to particular processes.
Signed-off-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com>
Signed-off-by: Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com>
Signed-off-by: David Howells <dhowells@redhat.com>
Diffstat (limited to 'arch/mn10300/include/asm/tlbflush.h')
-rw-r--r-- | arch/mn10300/include/asm/tlbflush.h | 43 |
1 files changed, 40 insertions, 3 deletions
diff --git a/arch/mn10300/include/asm/tlbflush.h b/arch/mn10300/include/asm/tlbflush.h index 5d54bf57e6c3..c3c194d4031e 100644 --- a/arch/mn10300/include/asm/tlbflush.h +++ b/arch/mn10300/include/asm/tlbflush.h | |||
@@ -13,6 +13,12 @@ | |||
13 | 13 | ||
14 | #include <asm/processor.h> | 14 | #include <asm/processor.h> |
15 | 15 | ||
16 | struct tlb_state { | ||
17 | struct mm_struct *active_mm; | ||
18 | int state; | ||
19 | }; | ||
20 | DECLARE_PER_CPU_SHARED_ALIGNED(struct tlb_state, cpu_tlbstate); | ||
21 | |||
16 | /** | 22 | /** |
17 | * local_flush_tlb - Flush the current MM's entries from the local CPU's TLBs | 23 | * local_flush_tlb - Flush the current MM's entries from the local CPU's TLBs |
18 | */ | 24 | */ |
@@ -31,20 +37,51 @@ static inline void local_flush_tlb(void) | |||
31 | /** | 37 | /** |
32 | * local_flush_tlb_all - Flush all entries from the local CPU's TLBs | 38 | * local_flush_tlb_all - Flush all entries from the local CPU's TLBs |
33 | */ | 39 | */ |
34 | #define local_flush_tlb_all() local_flush_tlb() | 40 | static inline void local_flush_tlb_all(void) |
41 | { | ||
42 | local_flush_tlb(); | ||
43 | } | ||
35 | 44 | ||
36 | /** | 45 | /** |
37 | * local_flush_tlb_one - Flush one entry from the local CPU's TLBs | 46 | * local_flush_tlb_one - Flush one entry from the local CPU's TLBs |
38 | */ | 47 | */ |
39 | #define local_flush_tlb_one(addr) local_flush_tlb() | 48 | static inline void local_flush_tlb_one(unsigned long addr) |
49 | { | ||
50 | local_flush_tlb(); | ||
51 | } | ||
40 | 52 | ||
41 | /** | 53 | /** |
42 | * local_flush_tlb_page - Flush a page's entry from the local CPU's TLBs | 54 | * local_flush_tlb_page - Flush a page's entry from the local CPU's TLBs |
43 | * @mm: The MM to flush for | 55 | * @mm: The MM to flush for |
44 | * @addr: The address of the target page in RAM (not its page struct) | 56 | * @addr: The address of the target page in RAM (not its page struct) |
45 | */ | 57 | */ |
46 | extern void local_flush_tlb_page(struct mm_struct *mm, unsigned long addr); | 58 | static inline |
59 | void local_flush_tlb_page(struct mm_struct *mm, unsigned long addr) | ||
60 | { | ||
61 | unsigned long pteu, flags, cnx; | ||
62 | |||
63 | addr &= PAGE_MASK; | ||
47 | 64 | ||
65 | local_irq_save(flags); | ||
66 | |||
67 | cnx = 1; | ||
68 | #ifdef CONFIG_MN10300_TLB_USE_PIDR | ||
69 | cnx = mm->context.tlbpid[smp_processor_id()]; | ||
70 | #endif | ||
71 | if (cnx) { | ||
72 | pteu = addr; | ||
73 | #ifdef CONFIG_MN10300_TLB_USE_PIDR | ||
74 | pteu |= cnx & xPTEU_PID; | ||
75 | #endif | ||
76 | IPTEU = pteu; | ||
77 | DPTEU = pteu; | ||
78 | if (IPTEL & xPTEL_V) | ||
79 | IPTEL = 0; | ||
80 | if (DPTEL & xPTEL_V) | ||
81 | DPTEL = 0; | ||
82 | } | ||
83 | local_irq_restore(flags); | ||
84 | } | ||
48 | 85 | ||
49 | /* | 86 | /* |
50 | * TLB flushing: | 87 | * TLB flushing: |