diff options
author | Linus Torvalds <torvalds@g5.osdl.org> | 2006-06-29 16:44:45 -0400 |
---|---|---|
committer | Linus Torvalds <torvalds@g5.osdl.org> | 2006-06-29 16:44:45 -0400 |
commit | 8d231c11fd0b694c447e59e687754b6999eea0a2 (patch) | |
tree | b0b3c17efff7018bbf948e489f642c8079f33cc0 /arch/mips | |
parent | 1f1332f727c3229eb2166a83fec5d3de6a73dce2 (diff) | |
parent | 8db089c6b5594c961fb6bc6d613b9926e0d3d98f (diff) |
Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus
* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus: (33 commits)
[MIPS] Add missing backslashes to macro definitions.
[MIPS] Death list of board support to be removed after 2.6.18.
[MIPS] Remove BSD and Sys V compat data types.
[MIPS] ioc3.h: Uses u8, so include <linux/types.h>.
[MIPS] 74K: Assume it will also have an AR bit in config7
[MIPS] Treat CPUs with AR bit as physically indexed.
[MIPS] Oprofile: Support VSMP on 34K.
[MIPS] MIPS32/MIPS64 S-cache fix and cleanup
[MIPS] excite: PCI makefile needs to use += if it wants a chance to work.
[MIPS] excite: plat_setup -> plat_mem_setup.
[MIPS] au1xxx: export dbdma functions
[MIPS] au1xxx: dbdma, no sleeping under spin_lock
[MIPS] au1xxx: fix PSC_SMBTXRX_RSR.
[MIPS] Early printk for IP27.
[MIPS] Fix handling of 0 length I & D caches.
[MIPS] Typo fixes.
[MIPS] MIPS32/MIPS64 secondary cache management
[MIPS] Fix FIXADDR_TOP for TX39/TX49.
[MIPS] Remove first timer interrupt setup in wrppmc_timer_setup()
[MIPS] Fix configuration of R2 CPU features and multithreading.
...
Diffstat (limited to 'arch/mips')
45 files changed, 476 insertions, 423 deletions
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 08c2ece4ae40..747a9c1228f2 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig | |||
@@ -308,6 +308,7 @@ config MIPS_ATLAS | |||
308 | select SYS_SUPPORTS_64BIT_KERNEL | 308 | select SYS_SUPPORTS_64BIT_KERNEL |
309 | select SYS_SUPPORTS_BIG_ENDIAN | 309 | select SYS_SUPPORTS_BIG_ENDIAN |
310 | select SYS_SUPPORTS_LITTLE_ENDIAN | 310 | select SYS_SUPPORTS_LITTLE_ENDIAN |
311 | select SYS_SUPPORTS_MULTITHREADING if EXPERIMENTAL | ||
311 | help | 312 | help |
312 | This enables support for the MIPS Technologies Atlas evaluation | 313 | This enables support for the MIPS Technologies Atlas evaluation |
313 | board. | 314 | board. |
@@ -324,6 +325,7 @@ config MIPS_MALTA | |||
324 | select I8259 | 325 | select I8259 |
325 | select MIPS_BOARDS_GEN | 326 | select MIPS_BOARDS_GEN |
326 | select MIPS_BONITO64 | 327 | select MIPS_BONITO64 |
328 | select MIPS_CPU_SCACHE | ||
327 | select MIPS_GT64120 | 329 | select MIPS_GT64120 |
328 | select MIPS_MSC | 330 | select MIPS_MSC |
329 | select SWAP_IO_SPACE | 331 | select SWAP_IO_SPACE |
@@ -336,6 +338,7 @@ config MIPS_MALTA | |||
336 | select SYS_SUPPORTS_64BIT_KERNEL | 338 | select SYS_SUPPORTS_64BIT_KERNEL |
337 | select SYS_SUPPORTS_BIG_ENDIAN | 339 | select SYS_SUPPORTS_BIG_ENDIAN |
338 | select SYS_SUPPORTS_LITTLE_ENDIAN | 340 | select SYS_SUPPORTS_LITTLE_ENDIAN |
341 | select SYS_SUPPORTS_MULTITHREADING | ||
339 | help | 342 | help |
340 | This enables support for the MIPS Technologies Malta evaluation | 343 | This enables support for the MIPS Technologies Malta evaluation |
341 | board. | 344 | board. |
@@ -358,7 +361,7 @@ config MIPS_SEAD | |||
358 | board. | 361 | board. |
359 | 362 | ||
360 | config WR_PPMC | 363 | config WR_PPMC |
361 | bool "Support for Wind River PPMC board" | 364 | bool "Wind River PPMC board" |
362 | select IRQ_CPU | 365 | select IRQ_CPU |
363 | select BOOT_ELF32 | 366 | select BOOT_ELF32 |
364 | select DMA_NONCOHERENT | 367 | select DMA_NONCOHERENT |
@@ -536,6 +539,7 @@ config PMC_YOSEMITE | |||
536 | select SYS_SUPPORTS_64BIT_KERNEL | 539 | select SYS_SUPPORTS_64BIT_KERNEL |
537 | select SYS_SUPPORTS_BIG_ENDIAN | 540 | select SYS_SUPPORTS_BIG_ENDIAN |
538 | select SYS_SUPPORTS_HIGHMEM | 541 | select SYS_SUPPORTS_HIGHMEM |
542 | select SYS_SUPPORTS_SMP | ||
539 | help | 543 | help |
540 | Yosemite is an evaluation board for the RM9000x2 processor | 544 | Yosemite is an evaluation board for the RM9000x2 processor |
541 | manufactured by PMC-Sierra. | 545 | manufactured by PMC-Sierra. |
@@ -590,6 +594,7 @@ config SGI_IP22 | |||
590 | select SYS_SUPPORTS_32BIT_KERNEL | 594 | select SYS_SUPPORTS_32BIT_KERNEL |
591 | select SYS_SUPPORTS_64BIT_KERNEL | 595 | select SYS_SUPPORTS_64BIT_KERNEL |
592 | select SYS_SUPPORTS_BIG_ENDIAN | 596 | select SYS_SUPPORTS_BIG_ENDIAN |
597 | select SYS_SUPPORTS_SMP | ||
593 | help | 598 | help |
594 | This are the SGI Indy, Challenge S and Indigo2, as well as certain | 599 | This are the SGI Indy, Challenge S and Indigo2, as well as certain |
595 | OEM variants like the Tandem CMN B006S. To compile a Linux kernel | 600 | OEM variants like the Tandem CMN B006S. To compile a Linux kernel |
@@ -601,6 +606,7 @@ config SGI_IP27 | |||
601 | select ARC64 | 606 | select ARC64 |
602 | select BOOT_ELF64 | 607 | select BOOT_ELF64 |
603 | select DMA_IP27 | 608 | select DMA_IP27 |
609 | select EARLY_PRINTK | ||
604 | select HW_HAS_PCI | 610 | select HW_HAS_PCI |
605 | select PCI_DOMAINS | 611 | select PCI_DOMAINS |
606 | select SYS_HAS_CPU_R10000 | 612 | select SYS_HAS_CPU_R10000 |
@@ -1249,7 +1255,7 @@ config CPU_R6000 | |||
1249 | select CPU_SUPPORTS_32BIT_KERNEL | 1255 | select CPU_SUPPORTS_32BIT_KERNEL |
1250 | help | 1256 | help |
1251 | MIPS Technologies R6000 and R6000A series processors. Note these | 1257 | MIPS Technologies R6000 and R6000A series processors. Note these |
1252 | processors are extremly rare and the support for them is incomplete. | 1258 | processors are extremely rare and the support for them is incomplete. |
1253 | 1259 | ||
1254 | config CPU_NEVADA | 1260 | config CPU_NEVADA |
1255 | bool "RM52xx" | 1261 | bool "RM52xx" |
@@ -1370,7 +1376,7 @@ config SYS_HAS_CPU_SB1 | |||
1370 | endmenu | 1376 | endmenu |
1371 | 1377 | ||
1372 | # | 1378 | # |
1373 | # These two indicate any levelof the MIPS32 and MIPS64 architecture | 1379 | # These two indicate any level of the MIPS32 and MIPS64 architecture |
1374 | # | 1380 | # |
1375 | config CPU_MIPS32 | 1381 | config CPU_MIPS32 |
1376 | bool | 1382 | bool |
@@ -1381,7 +1387,7 @@ config CPU_MIPS64 | |||
1381 | default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 | 1387 | default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 |
1382 | 1388 | ||
1383 | # | 1389 | # |
1384 | # These two indicate the revision of the architecture, either 32 bot 64 bit. | 1390 | # These two indicate the revision of the architecture, either Release 1 or Release 2 |
1385 | # | 1391 | # |
1386 | config CPU_MIPSR1 | 1392 | config CPU_MIPSR1 |
1387 | bool | 1393 | bool |
@@ -1474,6 +1480,13 @@ config IP22_CPU_SCACHE | |||
1474 | bool | 1480 | bool |
1475 | select BOARD_SCACHE | 1481 | select BOARD_SCACHE |
1476 | 1482 | ||
1483 | # | ||
1484 | # Support for a MIPS32 / MIPS64 style S-caches | ||
1485 | # | ||
1486 | config MIPS_CPU_SCACHE | ||
1487 | bool | ||
1488 | select BOARD_SCACHE | ||
1489 | |||
1477 | config R5000_CPU_SCACHE | 1490 | config R5000_CPU_SCACHE |
1478 | bool | 1491 | bool |
1479 | select BOARD_SCACHE | 1492 | select BOARD_SCACHE |
@@ -1493,32 +1506,57 @@ config SIBYTE_DMA_PAGEOPS | |||
1493 | config CPU_HAS_PREFETCH | 1506 | config CPU_HAS_PREFETCH |
1494 | bool | 1507 | bool |
1495 | 1508 | ||
1496 | config MIPS_MT | ||
1497 | bool "Enable MIPS MT" | ||
1498 | |||
1499 | choice | 1509 | choice |
1500 | prompt "MIPS MT options" | 1510 | prompt "MIPS MT options" |
1501 | depends on MIPS_MT | 1511 | |
1512 | config MIPS_MT_DISABLED | ||
1513 | bool "Disable multithreading support." | ||
1514 | help | ||
1515 | Use this option if your workload can't take advantage of | ||
1516 | MIPS hardware multithreading support. On systems that don't have | ||
1517 | the option of an MT-enabled processor this option will be the only | ||
1518 | option in this menu. | ||
1502 | 1519 | ||
1503 | config MIPS_MT_SMTC | 1520 | config MIPS_MT_SMTC |
1504 | bool "SMTC: Use all TCs on all VPEs for SMP" | 1521 | bool "SMTC: Use all TCs on all VPEs for SMP" |
1522 | depends on CPU_MIPS32_R2 | ||
1523 | #depends on CPU_MIPS64_R2 # once there is hardware ... | ||
1524 | depends on SYS_SUPPORTS_MULTITHREADING | ||
1505 | select CPU_MIPSR2_IRQ_VI | 1525 | select CPU_MIPSR2_IRQ_VI |
1506 | select CPU_MIPSR2_SRS | 1526 | select CPU_MIPSR2_SRS |
1527 | select MIPS_MT | ||
1507 | select SMP | 1528 | select SMP |
1529 | help | ||
1530 | This is a kernel model which is known a SMTC or lately has been | ||
1531 | marketesed into SMVP. | ||
1508 | 1532 | ||
1509 | config MIPS_MT_SMP | 1533 | config MIPS_MT_SMP |
1510 | bool "Use 1 TC on each available VPE for SMP" | 1534 | bool "Use 1 TC on each available VPE for SMP" |
1535 | depends on SYS_SUPPORTS_MULTITHREADING | ||
1536 | select CPU_MIPSR2_IRQ_VI | ||
1537 | select CPU_MIPSR2_SRS | ||
1538 | select MIPS_MT | ||
1511 | select SMP | 1539 | select SMP |
1540 | help | ||
1541 | This is a kernel model which is also known a VSMP or lately | ||
1542 | has been marketesed into SMVP. | ||
1512 | 1543 | ||
1513 | config MIPS_VPE_LOADER | 1544 | config MIPS_VPE_LOADER |
1514 | bool "VPE loader support." | 1545 | bool "VPE loader support." |
1515 | depends on MIPS_MT | 1546 | depends on SYS_SUPPORTS_MULTITHREADING |
1547 | select MIPS_MT | ||
1516 | help | 1548 | help |
1517 | Includes a loader for loading an elf relocatable object | 1549 | Includes a loader for loading an elf relocatable object |
1518 | onto another VPE and running it. | 1550 | onto another VPE and running it. |
1519 | 1551 | ||
1520 | endchoice | 1552 | endchoice |
1521 | 1553 | ||
1554 | config MIPS_MT | ||
1555 | bool | ||
1556 | |||
1557 | config SYS_SUPPORTS_MULTITHREADING | ||
1558 | bool | ||
1559 | |||
1522 | config MIPS_MT_FPAFF | 1560 | config MIPS_MT_FPAFF |
1523 | bool "Dynamic FPU affinity for FP-intensive threads" | 1561 | bool "Dynamic FPU affinity for FP-intensive threads" |
1524 | depends on MIPS_MT | 1562 | depends on MIPS_MT |
@@ -1575,32 +1613,23 @@ config CPU_HAS_LLSC | |||
1575 | config CPU_HAS_WB | 1613 | config CPU_HAS_WB |
1576 | bool | 1614 | bool |
1577 | 1615 | ||
1616 | # | ||
1617 | # Vectored interrupt mode is an R2 feature | ||
1618 | # | ||
1578 | config CPU_MIPSR2_IRQ_VI | 1619 | config CPU_MIPSR2_IRQ_VI |
1579 | bool "Vectored interrupt mode" | 1620 | bool |
1580 | depends on CPU_MIPSR2 | ||
1581 | help | ||
1582 | Vectored interrupt mode allowing faster dispatching of interrupts. | ||
1583 | The board support code needs to be written to take advantage of this | ||
1584 | mode. Compatibility code is included to allow the kernel to run on | ||
1585 | a CPU that does not support vectored interrupts. It's safe to | ||
1586 | say Y here. | ||
1587 | 1621 | ||
1622 | # | ||
1623 | # Extended interrupt mode is an R2 feature | ||
1624 | # | ||
1588 | config CPU_MIPSR2_IRQ_EI | 1625 | config CPU_MIPSR2_IRQ_EI |
1589 | bool "External interrupt controller mode" | 1626 | bool |
1590 | depends on CPU_MIPSR2 | ||
1591 | help | ||
1592 | Extended interrupt mode takes advantage of an external interrupt | ||
1593 | controller to allow fast dispatching from many possible interrupt | ||
1594 | sources. Say N unless you know that external interrupt support is | ||
1595 | required. | ||
1596 | 1627 | ||
1628 | # | ||
1629 | # Shadow registers are an R2 feature | ||
1630 | # | ||
1597 | config CPU_MIPSR2_SRS | 1631 | config CPU_MIPSR2_SRS |
1598 | bool "Make shadow set registers available for interrupt handlers" | 1632 | bool |
1599 | depends on CPU_MIPSR2_IRQ_VI || CPU_MIPSR2_IRQ_EI | ||
1600 | help | ||
1601 | Allow the kernel to use shadow register sets for fast interrupts. | ||
1602 | Interrupt handlers must be specially written to use shadow sets. | ||
1603 | Say N unless you know that shadow register set upport is needed. | ||
1604 | 1633 | ||
1605 | config CPU_HAS_SYNC | 1634 | config CPU_HAS_SYNC |
1606 | bool | 1635 | bool |
@@ -1681,8 +1710,8 @@ source "mm/Kconfig" | |||
1681 | 1710 | ||
1682 | config SMP | 1711 | config SMP |
1683 | bool "Multi-Processing support" | 1712 | bool "Multi-Processing support" |
1684 | depends on CPU_RM9000 || ((SIBYTE_BCM1x80 || SIBYTE_BCM1x55 || SIBYTE_SB1250 || QEMU) && !SIBYTE_STANDALONE) || SGI_IP27 || MIPS_MT_SMP || MIPS_MT_SMTC | 1713 | depends on SYS_SUPPORTS_SMP |
1685 | ---help--- | 1714 | help |
1686 | This enables support for systems with more than one CPU. If you have | 1715 | This enables support for systems with more than one CPU. If you have |
1687 | a system with only one CPU, like most personal computers, say N. If | 1716 | a system with only one CPU, like most personal computers, say N. If |
1688 | you have a system with more than one CPU, say Y. | 1717 | you have a system with more than one CPU, say Y. |
@@ -1701,6 +1730,9 @@ config SMP | |||
1701 | 1730 | ||
1702 | If you don't know what to do here, say N. | 1731 | If you don't know what to do here, say N. |
1703 | 1732 | ||
1733 | config SYS_SUPPORTS_SMP | ||
1734 | bool | ||
1735 | |||
1704 | config NR_CPUS | 1736 | config NR_CPUS |
1705 | int "Maximum number of CPUs (2-64)" | 1737 | int "Maximum number of CPUs (2-64)" |
1706 | range 2 64 | 1738 | range 2 64 |
diff --git a/arch/mips/Makefile b/arch/mips/Makefile index d5930148495a..ebbb9adc0e2f 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile | |||
@@ -374,6 +374,7 @@ core-$(CONFIG_PMC_YOSEMITE) += arch/mips/pmc-sierra/yosemite/ | |||
374 | cflags-$(CONFIG_PMC_YOSEMITE) += -Iinclude/asm-mips/mach-yosemite | 374 | cflags-$(CONFIG_PMC_YOSEMITE) += -Iinclude/asm-mips/mach-yosemite |
375 | load-$(CONFIG_PMC_YOSEMITE) += 0xffffffff80100000 | 375 | load-$(CONFIG_PMC_YOSEMITE) += 0xffffffff80100000 |
376 | 376 | ||
377 | # | ||
377 | # Qemu simulating MIPS32 4Kc | 378 | # Qemu simulating MIPS32 4Kc |
378 | # | 379 | # |
379 | core-$(CONFIG_QEMU) += arch/mips/qemu/ | 380 | core-$(CONFIG_QEMU) += arch/mips/qemu/ |
diff --git a/arch/mips/au1000/common/dbdma.c b/arch/mips/au1000/common/dbdma.c index 6ee090bd86c9..a547e47dd5fd 100644 --- a/arch/mips/au1000/common/dbdma.c +++ b/arch/mips/au1000/common/dbdma.c | |||
@@ -290,7 +290,7 @@ au1xxx_dbdma_chan_alloc(u32 srcid, u32 destid, | |||
290 | /* If kmalloc fails, it is caught below same | 290 | /* If kmalloc fails, it is caught below same |
291 | * as a channel not available. | 291 | * as a channel not available. |
292 | */ | 292 | */ |
293 | ctp = kmalloc(sizeof(chan_tab_t), GFP_KERNEL); | 293 | ctp = kmalloc(sizeof(chan_tab_t), GFP_ATOMIC); |
294 | chan_tab_ptr[i] = ctp; | 294 | chan_tab_ptr[i] = ctp; |
295 | break; | 295 | break; |
296 | } | 296 | } |
@@ -730,6 +730,8 @@ au1xxx_dbdma_get_dest(u32 chanid, void **buf, int *nbytes) | |||
730 | return rv; | 730 | return rv; |
731 | } | 731 | } |
732 | 732 | ||
733 | EXPORT_SYMBOL_GPL(au1xxx_dbdma_get_dest); | ||
734 | |||
733 | void | 735 | void |
734 | au1xxx_dbdma_stop(u32 chanid) | 736 | au1xxx_dbdma_stop(u32 chanid) |
735 | { | 737 | { |
@@ -821,6 +823,8 @@ au1xxx_get_dma_residue(u32 chanid) | |||
821 | return rv; | 823 | return rv; |
822 | } | 824 | } |
823 | 825 | ||
826 | EXPORT_SYMBOL_GPL(au1xxx_get_dma_residue); | ||
827 | |||
824 | void | 828 | void |
825 | au1xxx_dbdma_chan_free(u32 chanid) | 829 | au1xxx_dbdma_chan_free(u32 chanid) |
826 | { | 830 | { |
diff --git a/arch/mips/au1000/common/irq.c b/arch/mips/au1000/common/irq.c index da74ac21954b..12d6edee895e 100644 --- a/arch/mips/au1000/common/irq.c +++ b/arch/mips/au1000/common/irq.c | |||
@@ -585,13 +585,13 @@ void intc1_req1_irqdispatch(struct pt_regs *regs) | |||
585 | * au_sleep function in power.c.....maybe I should just pm_register() | 585 | * au_sleep function in power.c.....maybe I should just pm_register() |
586 | * them instead? | 586 | * them instead? |
587 | */ | 587 | */ |
588 | static uint sleep_intctl_config0[2]; | 588 | static unsigned int sleep_intctl_config0[2]; |
589 | static uint sleep_intctl_config1[2]; | 589 | static unsigned int sleep_intctl_config1[2]; |
590 | static uint sleep_intctl_config2[2]; | 590 | static unsigned int sleep_intctl_config2[2]; |
591 | static uint sleep_intctl_src[2]; | 591 | static unsigned int sleep_intctl_src[2]; |
592 | static uint sleep_intctl_assign[2]; | 592 | static unsigned int sleep_intctl_assign[2]; |
593 | static uint sleep_intctl_wake[2]; | 593 | static unsigned int sleep_intctl_wake[2]; |
594 | static uint sleep_intctl_mask[2]; | 594 | static unsigned int sleep_intctl_mask[2]; |
595 | 595 | ||
596 | void | 596 | void |
597 | save_au1xxx_intctl(void) | 597 | save_au1xxx_intctl(void) |
diff --git a/arch/mips/au1000/common/power.c b/arch/mips/au1000/common/power.c index f4926315fb68..b035513fe30a 100644 --- a/arch/mips/au1000/common/power.c +++ b/arch/mips/au1000/common/power.c | |||
@@ -80,17 +80,17 @@ static DEFINE_SPINLOCK(pm_lock); | |||
80 | * We only have to save/restore registers that aren't otherwise | 80 | * We only have to save/restore registers that aren't otherwise |
81 | * done as part of a driver pm_* function. | 81 | * done as part of a driver pm_* function. |
82 | */ | 82 | */ |
83 | static uint sleep_aux_pll_cntrl; | 83 | static unsigned int sleep_aux_pll_cntrl; |
84 | static uint sleep_cpu_pll_cntrl; | 84 | static unsigned int sleep_cpu_pll_cntrl; |
85 | static uint sleep_pin_function; | 85 | static unsigned int sleep_pin_function; |
86 | static uint sleep_uart0_inten; | 86 | static unsigned int sleep_uart0_inten; |
87 | static uint sleep_uart0_fifoctl; | 87 | static unsigned int sleep_uart0_fifoctl; |
88 | static uint sleep_uart0_linectl; | 88 | static unsigned int sleep_uart0_linectl; |
89 | static uint sleep_uart0_clkdiv; | 89 | static unsigned int sleep_uart0_clkdiv; |
90 | static uint sleep_uart0_enable; | 90 | static unsigned int sleep_uart0_enable; |
91 | static uint sleep_usbhost_enable; | 91 | static unsigned int sleep_usbhost_enable; |
92 | static uint sleep_usbdev_enable; | 92 | static unsigned int sleep_usbdev_enable; |
93 | static uint sleep_static_memctlr[4][3]; | 93 | static unsigned int sleep_static_memctlr[4][3]; |
94 | 94 | ||
95 | /* Define this to cause the value you write to /proc/sys/pm/sleep to | 95 | /* Define this to cause the value you write to /proc/sys/pm/sleep to |
96 | * set the TOY timer for the amount of time you want to sleep. | 96 | * set the TOY timer for the amount of time you want to sleep. |
diff --git a/arch/mips/au1000/csb250/init.c b/arch/mips/au1000/csb250/init.c index a4898b1bc66a..83f1b31a0b8e 100644 --- a/arch/mips/au1000/csb250/init.c +++ b/arch/mips/au1000/csb250/init.c | |||
@@ -65,9 +65,9 @@ int __init prom_init(int argc, char **argv, char **envp, int *prom_vec) | |||
65 | 65 | ||
66 | /* We use a0 and a1 to pass initrd start and size. | 66 | /* We use a0 and a1 to pass initrd start and size. |
67 | */ | 67 | */ |
68 | if (((uint) argc > 0) && ((uint)argv > 0)) { | 68 | if (((unsigned int) argc > 0) && ((uint)argv > 0)) { |
69 | my_initrd_start = (uint)argc; | 69 | my_initrd_start = (unsigned int)argc; |
70 | my_initrd_size = (uint)argv; | 70 | my_initrd_size = (unsigned int)argv; |
71 | } | 71 | } |
72 | 72 | ||
73 | /* First argv is ignored. | 73 | /* First argv is ignored. |
diff --git a/arch/mips/basler/excite/excite_setup.c b/arch/mips/basler/excite/excite_setup.c index 005b025605e6..3d7670edd5cd 100644 --- a/arch/mips/basler/excite/excite_setup.c +++ b/arch/mips/basler/excite/excite_setup.c | |||
@@ -254,7 +254,7 @@ static int __init excite_platform_init(void) | |||
254 | return 0; | 254 | return 0; |
255 | } | 255 | } |
256 | 256 | ||
257 | void __init plat_setup(void) | 257 | void __init plat_mem_setup(void) |
258 | { | 258 | { |
259 | volatile u32 * const boot_ocd_base = (u32 *) 0xbf7fc000; | 259 | volatile u32 * const boot_ocd_base = (u32 *) 0xbf7fc000; |
260 | 260 | ||
diff --git a/arch/mips/ddb5xxx/common/prom.c b/arch/mips/ddb5xxx/common/prom.c index 00c62c1c28a3..20c845c84d4b 100644 --- a/arch/mips/ddb5xxx/common/prom.c +++ b/arch/mips/ddb5xxx/common/prom.c | |||
@@ -21,8 +21,6 @@ | |||
21 | const char *get_system_type(void) | 21 | const char *get_system_type(void) |
22 | { | 22 | { |
23 | switch (mips_machtype) { | 23 | switch (mips_machtype) { |
24 | case MACH_NEC_DDB5074: return "NEC DDB Vrc-5074"; | ||
25 | case MACH_NEC_DDB5476: return "NEC DDB Vrc-5476"; | ||
26 | case MACH_NEC_DDB5477: return "NEC DDB Vrc-5477"; | 24 | case MACH_NEC_DDB5477: return "NEC DDB Vrc-5477"; |
27 | case MACH_NEC_ROCKHOPPER: return "NEC Rockhopper"; | 25 | case MACH_NEC_ROCKHOPPER: return "NEC Rockhopper"; |
28 | case MACH_NEC_ROCKHOPPERII: return "NEC RockhopperII"; | 26 | case MACH_NEC_ROCKHOPPERII: return "NEC RockhopperII"; |
diff --git a/arch/mips/gt64120/common/Makefile b/arch/mips/gt64120/common/Makefile index eba5051015a5..1ef676e22ab4 100644 --- a/arch/mips/gt64120/common/Makefile +++ b/arch/mips/gt64120/common/Makefile | |||
@@ -3,4 +3,3 @@ | |||
3 | # | 3 | # |
4 | 4 | ||
5 | obj-y += time.o | 5 | obj-y += time.o |
6 | obj-$(CONFIG_PCI) += pci.o | ||
diff --git a/arch/mips/gt64120/common/pci.c b/arch/mips/gt64120/common/pci.c deleted file mode 100644 index e9e5419a0d53..000000000000 --- a/arch/mips/gt64120/common/pci.c +++ /dev/null | |||
@@ -1,147 +0,0 @@ | |||
1 | /* | ||
2 | * BRIEF MODULE DESCRIPTION | ||
3 | * Galileo Evaluation Boards PCI support. | ||
4 | * | ||
5 | * The general-purpose functions to read/write and configure the GT64120A's | ||
6 | * PCI registers (function names start with pci0 or pci1) are either direct | ||
7 | * copies of functions written by Galileo Technology, or are modifications | ||
8 | * of their functions to work with Linux 2.4 vs Linux 2.2. These functions | ||
9 | * are Copyright - Galileo Technology. | ||
10 | * | ||
11 | * Other functions are derived from other MIPS PCI implementations, or were | ||
12 | * written by RidgeRun, Inc, Copyright (C) 2000 RidgeRun, Inc. | ||
13 | * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com | ||
14 | * | ||
15 | * This program is free software; you can redistribute it and/or modify it | ||
16 | * under the terms of the GNU General Public License as published by the | ||
17 | * Free Software Foundation; either version 2 of the License, or (at your | ||
18 | * option) any later version. | ||
19 | * | ||
20 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED | ||
21 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | ||
22 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN | ||
23 | * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, | ||
24 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT | ||
25 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF | ||
26 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON | ||
27 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | ||
28 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | ||
29 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | ||
30 | * | ||
31 | * You should have received a copy of the GNU General Public License along | ||
32 | * with this program; if not, write to the Free Software Foundation, Inc., | ||
33 | * 675 Mass Ave, Cambridge, MA 02139, USA. | ||
34 | */ | ||
35 | #include <linux/init.h> | ||
36 | #include <linux/types.h> | ||
37 | #include <linux/pci.h> | ||
38 | #include <linux/kernel.h> | ||
39 | #include <asm/gt64120.h> | ||
40 | |||
41 | #define SELF 0 | ||
42 | |||
43 | /* | ||
44 | * pciXReadConfigReg - Read from a PCI configuration register | ||
45 | * - Make sure the GT is configured as a master before | ||
46 | * reading from another device on the PCI. | ||
47 | * - The function takes care of Big/Little endian conversion. | ||
48 | * INPUTS: regOffset: The register offset as it apears in the GT spec (or PCI | ||
49 | * spec) | ||
50 | * pciDevNum: The device number needs to be addressed. | ||
51 | * RETURNS: data , if the data == 0xffffffff check the master abort bit in the | ||
52 | * cause register to make sure the data is valid | ||
53 | * | ||
54 | * Configuration Address 0xCF8: | ||
55 | * | ||
56 | * 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number | ||
57 | * |congif|Reserved| Bus |Device|Function|Register|00| | ||
58 | * |Enable| |Number|Number| Number | Number | | <=field Name | ||
59 | * | ||
60 | */ | ||
61 | static unsigned int pci0ReadConfigReg(int offset, struct pci_dev *device) | ||
62 | { | ||
63 | unsigned int DataForRegCf8; | ||
64 | unsigned int data; | ||
65 | |||
66 | DataForRegCf8 = ((PCI_SLOT(device->devfn) << 11) | | ||
67 | (PCI_FUNC(device->devfn) << 8) | | ||
68 | (offset & ~0x3)) | 0x80000000; | ||
69 | GT_WRITE(GT_PCI0_CFGADDR_OFS, DataForRegCf8); | ||
70 | |||
71 | /* | ||
72 | * The casual observer might wonder why the READ is duplicated here, | ||
73 | * rather than immediately following the WRITE, and just have the swap | ||
74 | * in the "if". That's because there is a latency problem with trying | ||
75 | * to read immediately after setting up the address register. The "if" | ||
76 | * check gives enough time for the address to stabilize, so the READ | ||
77 | * can work. | ||
78 | */ | ||
79 | if (PCI_SLOT(device->devfn) == SELF) /* This board */ | ||
80 | return GT_READ(GT_PCI0_CFGDATA_OFS); | ||
81 | else /* PCI is little endian so swap the Data. */ | ||
82 | return __GT_READ(GT_PCI0_CFGDATA_OFS); | ||
83 | } | ||
84 | |||
85 | /* | ||
86 | * pciXWriteConfigReg - Write to a PCI configuration register | ||
87 | * - Make sure the GT is configured as a master before | ||
88 | * writingto another device on the PCI. | ||
89 | * - The function takes care of Big/Little endian conversion. | ||
90 | * Inputs: unsigned int regOffset: The register offset as it apears in the | ||
91 | * GT spec | ||
92 | * (or any other PCI device spec) | ||
93 | * pciDevNum: The device number needs to be addressed. | ||
94 | * | ||
95 | * Configuration Address 0xCF8: | ||
96 | * | ||
97 | * 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number | ||
98 | * |congif|Reserved| Bus |Device|Function|Register|00| | ||
99 | * |Enable| |Number|Number| Number | Number | | <=field Name | ||
100 | * | ||
101 | */ | ||
102 | static void pci0WriteConfigReg(unsigned int offset, | ||
103 | struct pci_dev *device, unsigned int data) | ||
104 | { | ||
105 | unsigned int DataForRegCf8; | ||
106 | |||
107 | DataForRegCf8 = ((PCI_SLOT(device->devfn) << 11) | | ||
108 | (PCI_FUNC(device->devfn) << 8) | | ||
109 | (offset & ~0x3)) | 0x80000000; | ||
110 | GT_WRITE(GT_PCI0_CFGADDR_OFS, DataForRegCf8); | ||
111 | |||
112 | if (PCI_SLOT(device->devfn) == SELF) /* This board */ | ||
113 | GT_WRITE(GT_PCI0_CFGDATA_OFS, data); | ||
114 | else /* configuration Transaction over the pci. */ | ||
115 | __GT_WRITE(GT_PCI0_CFGDATA_OFS, data); | ||
116 | } | ||
117 | |||
118 | extern struct pci_ops gt64120_pci_ops; | ||
119 | |||
120 | void __init pcibios_init(void) | ||
121 | { | ||
122 | u32 tmp; | ||
123 | struct pci_dev controller; | ||
124 | |||
125 | controller.devfn = SELF; | ||
126 | |||
127 | tmp = GT_READ(GT_PCI0_CMD_OFS); /* Huh??? -- Ralf */ | ||
128 | tmp = GT_READ(GT_PCI0_BARE_OFS); | ||
129 | |||
130 | /* | ||
131 | * You have to enable bus mastering to configure any other | ||
132 | * card on the bus. | ||
133 | */ | ||
134 | tmp = pci0ReadConfigReg(PCI_COMMAND, &controller); | ||
135 | tmp |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_SERR; | ||
136 | pci0WriteConfigReg(PCI_COMMAND, &controller, tmp); | ||
137 | |||
138 | /* | ||
139 | * Reset PCI I/O and PCI MEM values to ones supported by EVM. | ||
140 | */ | ||
141 | ioport_resource.start = GT_PCI_IO_BASE; | ||
142 | ioport_resource.end = GT_PCI_IO_BASE + GT_PCI_IO_SIZE - 1; | ||
143 | iomem_resource.start = GT_PCI_MEM_BASE; | ||
144 | iomem_resource.end = GT_PCI_MEM_BASE + GT_PCI_MEM_SIZE - 1; | ||
145 | |||
146 | pci_scan_bus(0, >64120_pci_ops, NULL); | ||
147 | } | ||
diff --git a/arch/mips/gt64120/momenco_ocelot/setup.c b/arch/mips/gt64120/momenco_ocelot/setup.c index 1193a22c4693..9804642ecf89 100644 --- a/arch/mips/gt64120/momenco_ocelot/setup.c +++ b/arch/mips/gt64120/momenco_ocelot/setup.c | |||
@@ -164,8 +164,8 @@ void __init plat_mem_setup(void) | |||
164 | pm_power_off = momenco_ocelot_power_off; | 164 | pm_power_off = momenco_ocelot_power_off; |
165 | 165 | ||
166 | /* | 166 | /* |
167 | * initrd_start = (ulong)ocelot_initrd_start; | 167 | * initrd_start = (unsigned long)ocelot_initrd_start; |
168 | * initrd_end = (ulong)ocelot_initrd_start + (ulong)ocelot_initrd_size; | 168 | * initrd_end = (unsigned long)ocelot_initrd_start + (ulong)ocelot_initrd_size; |
169 | * initrd_below_start_ok = 1; | 169 | * initrd_below_start_ok = 1; |
170 | */ | 170 | */ |
171 | 171 | ||
diff --git a/arch/mips/gt64120/wrppmc/Makefile b/arch/mips/gt64120/wrppmc/Makefile index 72606b9af12a..7cf52205511c 100644 --- a/arch/mips/gt64120/wrppmc/Makefile +++ b/arch/mips/gt64120/wrppmc/Makefile | |||
@@ -9,6 +9,6 @@ | |||
9 | # Makefile for the Wind River MIPS 4KC PPMC Eval Board | 9 | # Makefile for the Wind River MIPS 4KC PPMC Eval Board |
10 | # | 10 | # |
11 | 11 | ||
12 | obj-y += int-handler.o irq.o reset.o setup.o time.o pci.o | 12 | obj-y += irq.o reset.o setup.o time.o pci.o |
13 | 13 | ||
14 | EXTRA_AFLAGS := $(CFLAGS) | 14 | EXTRA_AFLAGS := $(CFLAGS) |
diff --git a/arch/mips/gt64120/wrppmc/int-handler.S b/arch/mips/gt64120/wrppmc/int-handler.S deleted file mode 100644 index edee7b394175..000000000000 --- a/arch/mips/gt64120/wrppmc/int-handler.S +++ /dev/null | |||
@@ -1,59 +0,0 @@ | |||
1 | /* | ||
2 | * This file is subject to the terms and conditions of the GNU General Public | ||
3 | * License. See the file "COPYING" in the main directory of this archive | ||
4 | * for more details. | ||
5 | * | ||
6 | * Copyright (C) 1995, 1996, 1997, 2003 by Ralf Baechle | ||
7 | * Copyright (C) Wind River System Inc. Rongkai.Zhan <rongkai.zhan@windriver.com> | ||
8 | */ | ||
9 | #include <asm/asm.h> | ||
10 | #include <asm/mipsregs.h> | ||
11 | #include <asm/addrspace.h> | ||
12 | #include <asm/regdef.h> | ||
13 | #include <asm/stackframe.h> | ||
14 | #include <asm/mach-wrppmc/mach-gt64120.h> | ||
15 | |||
16 | .align 5 | ||
17 | .set noat | ||
18 | NESTED(handle_IRQ, PT_SIZE, sp) | ||
19 | SAVE_ALL | ||
20 | CLI # Important: mark KERNEL mode ! | ||
21 | .set at | ||
22 | |||
23 | mfc0 t0, CP0_CAUSE # get pending interrupts | ||
24 | mfc0 t1, CP0_STATUS # get enabled interrupts | ||
25 | and t0, t0, t1 # get allowed interrupts | ||
26 | andi t0, t0, 0xFF00 | ||
27 | beqz t0, 1f | ||
28 | move a1, sp # Prepare 'struct pt_regs *regs' pointer | ||
29 | |||
30 | andi t1, t0, CAUSEF_IP7 # CPU Compare/Count internal timer | ||
31 | bnez t1, handle_cputimer_irq | ||
32 | andi t1, t0, CAUSEF_IP6 # UART 16550 port | ||
33 | bnez t1, handle_uart_irq | ||
34 | andi t1, t0, CAUSEF_IP3 # PCI INT_A | ||
35 | bnez t1, handle_pci_intA_irq | ||
36 | |||
37 | /* wrong alarm or masked ... */ | ||
38 | 1: j spurious_interrupt | ||
39 | nop | ||
40 | END(handle_IRQ) | ||
41 | |||
42 | .align 5 | ||
43 | handle_cputimer_irq: | ||
44 | li a0, WRPPMC_MIPS_TIMER_IRQ | ||
45 | jal do_IRQ | ||
46 | j ret_from_irq | ||
47 | |||
48 | .align 5 | ||
49 | handle_uart_irq: | ||
50 | li a0, WRPPMC_UART16550_IRQ | ||
51 | jal do_IRQ | ||
52 | j ret_from_irq | ||
53 | |||
54 | .align 5 | ||
55 | handle_pci_intA_irq: | ||
56 | li a0, WRPPMC_PCI_INTA_IRQ | ||
57 | jal do_IRQ | ||
58 | j ret_from_irq | ||
59 | |||
diff --git a/arch/mips/gt64120/wrppmc/irq.c b/arch/mips/gt64120/wrppmc/irq.c index 8605687e24ed..8d75a43ce877 100644 --- a/arch/mips/gt64120/wrppmc/irq.c +++ b/arch/mips/gt64120/wrppmc/irq.c | |||
@@ -30,7 +30,19 @@ | |||
30 | #include <asm/irq_cpu.h> | 30 | #include <asm/irq_cpu.h> |
31 | #include <asm/gt64120.h> | 31 | #include <asm/gt64120.h> |
32 | 32 | ||
33 | extern asmlinkage void handle_IRQ(void); | 33 | asmlinkage void plat_irq_dispatch(struct pt_regs *regs) |
34 | { | ||
35 | unsigned int pending = read_c0_status() & read_c0_cause(); | ||
36 | |||
37 | if (pending & STATUSF_IP7) | ||
38 | do_IRQ(WRPPMC_MIPS_TIMER_IRQ, regs); /* CPU Compare/Count internal timer */ | ||
39 | else if (pending & STATUSF_IP6) | ||
40 | do_IRQ(WRPPMC_UART16550_IRQ, regs); /* UART 16550 port */ | ||
41 | else if (pending & STATUSF_IP3) | ||
42 | do_IRQ(WRPPMC_PCI_INTA_IRQ, regs); /* PCI INT_A */ | ||
43 | else | ||
44 | spurious_interrupt(regs); | ||
45 | } | ||
34 | 46 | ||
35 | /** | 47 | /** |
36 | * Initialize GT64120 Interrupt Controller | 48 | * Initialize GT64120 Interrupt Controller |
@@ -50,12 +62,6 @@ void gt64120_init_pic(void) | |||
50 | 62 | ||
51 | void __init arch_init_irq(void) | 63 | void __init arch_init_irq(void) |
52 | { | 64 | { |
53 | /* enable all CPU interrupt bits. */ | ||
54 | set_c0_status(ST0_IM); /* IE bit is still 0 */ | ||
55 | |||
56 | /* Install MIPS Interrupt Trap Vector */ | ||
57 | set_except_vector(0, handle_IRQ); | ||
58 | |||
59 | /* IRQ 0 - 7 are for MIPS common irq_cpu controller */ | 65 | /* IRQ 0 - 7 are for MIPS common irq_cpu controller */ |
60 | mips_cpu_irq_init(0); | 66 | mips_cpu_irq_init(0); |
61 | 67 | ||
diff --git a/arch/mips/gt64120/wrppmc/setup.c b/arch/mips/gt64120/wrppmc/setup.c index 20c591e49dae..2db6375ef29e 100644 --- a/arch/mips/gt64120/wrppmc/setup.c +++ b/arch/mips/gt64120/wrppmc/setup.c | |||
@@ -125,7 +125,7 @@ static void wrppmc_setup_serial(void) | |||
125 | } | 125 | } |
126 | #endif | 126 | #endif |
127 | 127 | ||
128 | void __init plat_setup(void) | 128 | void __init plat_mem_setup(void) |
129 | { | 129 | { |
130 | extern void wrppmc_time_init(void); | 130 | extern void wrppmc_time_init(void); |
131 | extern void wrppmc_timer_setup(struct irqaction *); | 131 | extern void wrppmc_timer_setup(struct irqaction *); |
diff --git a/arch/mips/gt64120/wrppmc/time.c b/arch/mips/gt64120/wrppmc/time.c index 175d22adb450..6c24a82df0dd 100644 --- a/arch/mips/gt64120/wrppmc/time.c +++ b/arch/mips/gt64120/wrppmc/time.c | |||
@@ -31,10 +31,6 @@ void __init wrppmc_timer_setup(struct irqaction *irq) | |||
31 | { | 31 | { |
32 | /* Install ISR for timer interrupt */ | 32 | /* Install ISR for timer interrupt */ |
33 | setup_irq(WRPPMC_MIPS_TIMER_IRQ, irq); | 33 | setup_irq(WRPPMC_MIPS_TIMER_IRQ, irq); |
34 | |||
35 | /* to generate the first timer interrupt */ | ||
36 | write_c0_compare(mips_hpt_frequency/HZ); | ||
37 | write_c0_count(0); | ||
38 | } | 34 | } |
39 | 35 | ||
40 | /* | 36 | /* |
diff --git a/arch/mips/kernel/apm.c b/arch/mips/kernel/apm.c index 15f46b4471fd..7bdbcd811b57 100644 --- a/arch/mips/kernel/apm.c +++ b/arch/mips/kernel/apm.c | |||
@@ -260,7 +260,7 @@ static unsigned int apm_poll(struct file *fp, poll_table * wait) | |||
260 | * has acknowledge does the actual suspend happen. | 260 | * has acknowledge does the actual suspend happen. |
261 | */ | 261 | */ |
262 | static int | 262 | static int |
263 | apm_ioctl(struct inode * inode, struct file *filp, u_int cmd, u_long arg) | 263 | apm_ioctl(struct inode * inode, struct file *filp, unsigned int cmd, unsigned long arg) |
264 | { | 264 | { |
265 | struct apm_user *as = filp->private_data; | 265 | struct apm_user *as = filp->private_data; |
266 | unsigned long flags; | 266 | unsigned long flags; |
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index 8c2c359a05f4..e045aba4ebda 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c | |||
@@ -597,8 +597,6 @@ static inline void cpu_probe_mips(struct cpuinfo_mips *c) | |||
597 | break; | 597 | break; |
598 | case PRID_IMP_25KF: | 598 | case PRID_IMP_25KF: |
599 | c->cputype = CPU_25KF; | 599 | c->cputype = CPU_25KF; |
600 | /* Probe for L2 cache */ | ||
601 | c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT; | ||
602 | break; | 600 | break; |
603 | case PRID_IMP_34K: | 601 | case PRID_IMP_34K: |
604 | c->cputype = CPU_34K; | 602 | c->cputype = CPU_34K; |
diff --git a/arch/mips/kernel/entry.S b/arch/mips/kernel/entry.S index a9c6de1b9542..457565162dd5 100644 --- a/arch/mips/kernel/entry.S +++ b/arch/mips/kernel/entry.S | |||
@@ -87,7 +87,7 @@ FEXPORT(restore_all) # restore full frame | |||
87 | ori v1, v0, TCSTATUS_IXMT | 87 | ori v1, v0, TCSTATUS_IXMT |
88 | mtc0 v1, CP0_TCSTATUS | 88 | mtc0 v1, CP0_TCSTATUS |
89 | andi v0, TCSTATUS_IXMT | 89 | andi v0, TCSTATUS_IXMT |
90 | ehb | 90 | _ehb |
91 | mfc0 t0, CP0_TCCONTEXT | 91 | mfc0 t0, CP0_TCCONTEXT |
92 | DMT 9 # dmt t1 | 92 | DMT 9 # dmt t1 |
93 | jal mips_ihb | 93 | jal mips_ihb |
@@ -95,7 +95,7 @@ FEXPORT(restore_all) # restore full frame | |||
95 | andi t3, t0, 0xff00 | 95 | andi t3, t0, 0xff00 |
96 | or t2, t2, t3 | 96 | or t2, t2, t3 |
97 | mtc0 t2, CP0_STATUS | 97 | mtc0 t2, CP0_STATUS |
98 | ehb | 98 | _ehb |
99 | andi t1, t1, VPECONTROL_TE | 99 | andi t1, t1, VPECONTROL_TE |
100 | beqz t1, 1f | 100 | beqz t1, 1f |
101 | EMT | 101 | EMT |
@@ -105,7 +105,7 @@ FEXPORT(restore_all) # restore full frame | |||
105 | xori v1, v1, TCSTATUS_IXMT | 105 | xori v1, v1, TCSTATUS_IXMT |
106 | or v1, v0, v1 | 106 | or v1, v0, v1 |
107 | mtc0 v1, CP0_TCSTATUS | 107 | mtc0 v1, CP0_TCSTATUS |
108 | ehb | 108 | _ehb |
109 | xor t0, t0, t3 | 109 | xor t0, t0, t3 |
110 | mtc0 t0, CP0_TCCONTEXT | 110 | mtc0 t0, CP0_TCCONTEXT |
111 | #endif /* CONFIG_MIPS_MT_SMTC */ | 111 | #endif /* CONFIG_MIPS_MT_SMTC */ |
diff --git a/arch/mips/kernel/gdb-low.S b/arch/mips/kernel/gdb-low.S index 5fd7a8af0c62..8760131f89d9 100644 --- a/arch/mips/kernel/gdb-low.S +++ b/arch/mips/kernel/gdb-low.S | |||
@@ -291,7 +291,7 @@ | |||
291 | ori t1, t2, TCSTATUS_IXMT | 291 | ori t1, t2, TCSTATUS_IXMT |
292 | mtc0 t1, CP0_TCSTATUS | 292 | mtc0 t1, CP0_TCSTATUS |
293 | andi t2, t2, TCSTATUS_IXMT | 293 | andi t2, t2, TCSTATUS_IXMT |
294 | ehb | 294 | _ehb |
295 | DMT 9 # dmt t1 | 295 | DMT 9 # dmt t1 |
296 | jal mips_ihb | 296 | jal mips_ihb |
297 | nop | 297 | nop |
@@ -310,7 +310,7 @@ | |||
310 | xori t1, t1, TCSTATUS_IXMT | 310 | xori t1, t1, TCSTATUS_IXMT |
311 | or t1, t1, t2 | 311 | or t1, t1, t2 |
312 | mtc0 t1, CP0_TCSTATUS | 312 | mtc0 t1, CP0_TCSTATUS |
313 | ehb | 313 | _ehb |
314 | #endif /* CONFIG_MIPS_MT_SMTC */ | 314 | #endif /* CONFIG_MIPS_MT_SMTC */ |
315 | LONG_L v0, GDB_FR_STATUS(sp) | 315 | LONG_L v0, GDB_FR_STATUS(sp) |
316 | LONG_L v1, GDB_FR_EPC(sp) | 316 | LONG_L v1, GDB_FR_EPC(sp) |
diff --git a/arch/mips/kernel/genex.S b/arch/mips/kernel/genex.S index ff7af369f286..6888cde560af 100644 --- a/arch/mips/kernel/genex.S +++ b/arch/mips/kernel/genex.S | |||
@@ -214,7 +214,7 @@ NESTED(except_vec_vi_handler, 0, sp) | |||
214 | mtc0 t0, CP0_TCCONTEXT | 214 | mtc0 t0, CP0_TCCONTEXT |
215 | xor t1, t1, t0 | 215 | xor t1, t1, t0 |
216 | mtc0 t1, CP0_STATUS | 216 | mtc0 t1, CP0_STATUS |
217 | ehb | 217 | _ehb |
218 | #endif /* CONFIG_MIPS_MT_SMTC */ | 218 | #endif /* CONFIG_MIPS_MT_SMTC */ |
219 | CLI | 219 | CLI |
220 | move a0, sp | 220 | move a0, sp |
diff --git a/arch/mips/kernel/head.S b/arch/mips/kernel/head.S index bdf6f6eff721..c018098c9a56 100644 --- a/arch/mips/kernel/head.S +++ b/arch/mips/kernel/head.S | |||
@@ -96,7 +96,7 @@ | |||
96 | /* Clear TKSU, leave IXMT */ | 96 | /* Clear TKSU, leave IXMT */ |
97 | xori t0, 0x00001800 | 97 | xori t0, 0x00001800 |
98 | mtc0 t0, CP0_TCSTATUS | 98 | mtc0 t0, CP0_TCSTATUS |
99 | ehb | 99 | _ehb |
100 | /* We need to leave the global IE bit set, but clear EXL...*/ | 100 | /* We need to leave the global IE bit set, but clear EXL...*/ |
101 | mfc0 t0, CP0_STATUS | 101 | mfc0 t0, CP0_STATUS |
102 | or t0, ST0_CU0 | ST0_EXL | ST0_ERL | \set | \clr | 102 | or t0, ST0_CU0 | ST0_EXL | ST0_ERL | \set | \clr |
diff --git a/arch/mips/kernel/r4k_switch.S b/arch/mips/kernel/r4k_switch.S index db94e556fc97..e1b85e6c486a 100644 --- a/arch/mips/kernel/r4k_switch.S +++ b/arch/mips/kernel/r4k_switch.S | |||
@@ -94,7 +94,7 @@ | |||
94 | ori t1, t2, TCSTATUS_IXMT | 94 | ori t1, t2, TCSTATUS_IXMT |
95 | mtc0 t1, CP0_TCSTATUS | 95 | mtc0 t1, CP0_TCSTATUS |
96 | andi t2, t2, TCSTATUS_IXMT | 96 | andi t2, t2, TCSTATUS_IXMT |
97 | ehb | 97 | _ehb |
98 | DMT 8 # dmt t0 | 98 | DMT 8 # dmt t0 |
99 | move t1,ra | 99 | move t1,ra |
100 | jal mips_ihb | 100 | jal mips_ihb |
@@ -109,7 +109,7 @@ | |||
109 | or a2, t1 | 109 | or a2, t1 |
110 | mtc0 a2, CP0_STATUS | 110 | mtc0 a2, CP0_STATUS |
111 | #ifdef CONFIG_MIPS_MT_SMTC | 111 | #ifdef CONFIG_MIPS_MT_SMTC |
112 | ehb | 112 | _ehb |
113 | andi t0, t0, VPECONTROL_TE | 113 | andi t0, t0, VPECONTROL_TE |
114 | beqz t0, 1f | 114 | beqz t0, 1f |
115 | emt | 115 | emt |
@@ -118,7 +118,7 @@ | |||
118 | xori t1, t1, TCSTATUS_IXMT | 118 | xori t1, t1, TCSTATUS_IXMT |
119 | or t1, t1, t2 | 119 | or t1, t1, t2 |
120 | mtc0 t1, CP0_TCSTATUS | 120 | mtc0 t1, CP0_TCSTATUS |
121 | ehb | 121 | _ehb |
122 | #endif /* CONFIG_MIPS_MT_SMTC */ | 122 | #endif /* CONFIG_MIPS_MT_SMTC */ |
123 | move v0, a0 | 123 | move v0, a0 |
124 | jr ra | 124 | jr ra |
diff --git a/arch/mips/kernel/scall32-o32.S b/arch/mips/kernel/scall32-o32.S index 2d2fdf77e308..6344be46ca8c 100644 --- a/arch/mips/kernel/scall32-o32.S +++ b/arch/mips/kernel/scall32-o32.S | |||
@@ -647,6 +647,7 @@ einval: li v0, -EINVAL | |||
647 | sys sys_unshare 1 | 647 | sys sys_unshare 1 |
648 | sys sys_splice 4 | 648 | sys sys_splice 4 |
649 | sys sys_sync_file_range 7 /* 4305 */ | 649 | sys sys_sync_file_range 7 /* 4305 */ |
650 | sys sys_tee 4 | ||
650 | .endm | 651 | .endm |
651 | 652 | ||
652 | /* We pre-compute the number of _instruction_ bytes needed to | 653 | /* We pre-compute the number of _instruction_ bytes needed to |
diff --git a/arch/mips/kernel/scall64-64.S b/arch/mips/kernel/scall64-64.S index 9ba750887377..12d96c7d0bb2 100644 --- a/arch/mips/kernel/scall64-64.S +++ b/arch/mips/kernel/scall64-64.S | |||
@@ -462,3 +462,4 @@ sys_call_table: | |||
462 | PTR sys_unshare | 462 | PTR sys_unshare |
463 | PTR sys_splice | 463 | PTR sys_splice |
464 | PTR sys_sync_file_range | 464 | PTR sys_sync_file_range |
465 | PTR sys_tee /* 5265 */ | ||
diff --git a/arch/mips/kernel/scall64-n32.S b/arch/mips/kernel/scall64-n32.S index 942aca26f9c4..685698554a8a 100644 --- a/arch/mips/kernel/scall64-n32.S +++ b/arch/mips/kernel/scall64-n32.S | |||
@@ -388,3 +388,4 @@ EXPORT(sysn32_call_table) | |||
388 | PTR sys_unshare | 388 | PTR sys_unshare |
389 | PTR sys_splice | 389 | PTR sys_splice |
390 | PTR sys_sync_file_range | 390 | PTR sys_sync_file_range |
391 | PTR sys_tee | ||
diff --git a/arch/mips/kernel/scall64-o32.S b/arch/mips/kernel/scall64-o32.S index 8efb23a84131..0e632934cb76 100644 --- a/arch/mips/kernel/scall64-o32.S +++ b/arch/mips/kernel/scall64-o32.S | |||
@@ -510,4 +510,5 @@ sys_call_table: | |||
510 | PTR sys_unshare | 510 | PTR sys_unshare |
511 | PTR sys_splice | 511 | PTR sys_splice |
512 | PTR sys32_sync_file_range /* 4305 */ | 512 | PTR sys32_sync_file_range /* 4305 */ |
513 | PTR sys_tee | ||
513 | .size sys_call_table,.-sys_call_table | 514 | .size sys_call_table,.-sys_call_table |
diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c index bfcec8d9bfe4..d3e087115023 100644 --- a/arch/mips/kernel/setup.c +++ b/arch/mips/kernel/setup.c | |||
@@ -488,6 +488,9 @@ static inline void resource_init(void) | |||
488 | { | 488 | { |
489 | int i; | 489 | int i; |
490 | 490 | ||
491 | if (UNCAC_BASE != IO_BASE) | ||
492 | return; | ||
493 | |||
491 | code_resource.start = virt_to_phys(&_text); | 494 | code_resource.start = virt_to_phys(&_text); |
492 | code_resource.end = virt_to_phys(&_etext) - 1; | 495 | code_resource.end = virt_to_phys(&_etext) - 1; |
493 | data_resource.start = virt_to_phys(&_etext); | 496 | data_resource.start = virt_to_phys(&_etext); |
diff --git a/arch/mips/kernel/smtc-asm.S b/arch/mips/kernel/smtc-asm.S index c9d65196d917..72c6d98f8854 100644 --- a/arch/mips/kernel/smtc-asm.S +++ b/arch/mips/kernel/smtc-asm.S | |||
@@ -52,12 +52,12 @@ FEXPORT(__smtc_ipi_vector) | |||
52 | .set noat | 52 | .set noat |
53 | /* Disable thread scheduling to make Status update atomic */ | 53 | /* Disable thread scheduling to make Status update atomic */ |
54 | DMT 27 # dmt k1 | 54 | DMT 27 # dmt k1 |
55 | ehb | 55 | _ehb |
56 | /* Set EXL */ | 56 | /* Set EXL */ |
57 | mfc0 k0,CP0_STATUS | 57 | mfc0 k0,CP0_STATUS |
58 | ori k0,k0,ST0_EXL | 58 | ori k0,k0,ST0_EXL |
59 | mtc0 k0,CP0_STATUS | 59 | mtc0 k0,CP0_STATUS |
60 | ehb | 60 | _ehb |
61 | /* Thread scheduling now inhibited by EXL. Restore TE state. */ | 61 | /* Thread scheduling now inhibited by EXL. Restore TE state. */ |
62 | andi k1,k1,VPECONTROL_TE | 62 | andi k1,k1,VPECONTROL_TE |
63 | beqz k1,1f | 63 | beqz k1,1f |
@@ -82,7 +82,7 @@ FEXPORT(__smtc_ipi_vector) | |||
82 | li k1,ST0_CU0 | 82 | li k1,ST0_CU0 |
83 | or k1,k1,k0 | 83 | or k1,k1,k0 |
84 | mtc0 k1,CP0_STATUS | 84 | mtc0 k1,CP0_STATUS |
85 | ehb | 85 | _ehb |
86 | get_saved_sp | 86 | get_saved_sp |
87 | /* Interrupting TC will have pre-set values in slots in the new frame */ | 87 | /* Interrupting TC will have pre-set values in slots in the new frame */ |
88 | 2: subu k1,k1,PT_SIZE | 88 | 2: subu k1,k1,PT_SIZE |
@@ -90,7 +90,7 @@ FEXPORT(__smtc_ipi_vector) | |||
90 | lw k0,PT_TCSTATUS(k1) | 90 | lw k0,PT_TCSTATUS(k1) |
91 | /* Write it to TCStatus to restore CU/KSU/IXMT state */ | 91 | /* Write it to TCStatus to restore CU/KSU/IXMT state */ |
92 | mtc0 k0,$2,1 | 92 | mtc0 k0,$2,1 |
93 | ehb | 93 | _ehb |
94 | lw k0,PT_EPC(k1) | 94 | lw k0,PT_EPC(k1) |
95 | mtc0 k0,CP0_EPC | 95 | mtc0 k0,CP0_EPC |
96 | /* Save all will redundantly recompute the SP, but use it for now */ | 96 | /* Save all will redundantly recompute the SP, but use it for now */ |
@@ -116,7 +116,7 @@ LEAF(self_ipi) | |||
116 | mfc0 t0,CP0_TCSTATUS | 116 | mfc0 t0,CP0_TCSTATUS |
117 | ori t1,t0,TCSTATUS_IXMT | 117 | ori t1,t0,TCSTATUS_IXMT |
118 | mtc0 t1,CP0_TCSTATUS | 118 | mtc0 t1,CP0_TCSTATUS |
119 | ehb | 119 | _ehb |
120 | /* We know we're in kernel mode, so prepare stack frame */ | 120 | /* We know we're in kernel mode, so prepare stack frame */ |
121 | subu t1,sp,PT_SIZE | 121 | subu t1,sp,PT_SIZE |
122 | sw ra,PT_EPC(t1) | 122 | sw ra,PT_EPC(t1) |
diff --git a/arch/mips/kernel/syscall.c b/arch/mips/kernel/syscall.c index 5e8a18a8e2bd..6da8c68e89db 100644 --- a/arch/mips/kernel/syscall.c +++ b/arch/mips/kernel/syscall.c | |||
@@ -301,7 +301,7 @@ asmlinkage int _sys_sysmips(int cmd, long arg1, int arg2, int arg3) | |||
301 | * | 301 | * |
302 | * This is really horribly ugly. | 302 | * This is really horribly ugly. |
303 | */ | 303 | */ |
304 | asmlinkage int sys_ipc (uint call, int first, int second, | 304 | asmlinkage int sys_ipc (unsigned int call, int first, int second, |
305 | unsigned long third, void __user *ptr, long fifth) | 305 | unsigned long third, void __user *ptr, long fifth) |
306 | { | 306 | { |
307 | int version, ret; | 307 | int version, ret; |
@@ -359,18 +359,18 @@ asmlinkage int sys_ipc (uint call, int first, int second, | |||
359 | case SHMAT: | 359 | case SHMAT: |
360 | switch (version) { | 360 | switch (version) { |
361 | default: { | 361 | default: { |
362 | ulong raddr; | 362 | unsigned long raddr; |
363 | ret = do_shmat (first, (char __user *) ptr, second, | 363 | ret = do_shmat (first, (char __user *) ptr, second, |
364 | &raddr); | 364 | &raddr); |
365 | if (ret) | 365 | if (ret) |
366 | return ret; | 366 | return ret; |
367 | return put_user (raddr, (ulong __user *) third); | 367 | return put_user (raddr, (unsigned long __user *) third); |
368 | } | 368 | } |
369 | case 1: /* iBCS2 emulator entry point */ | 369 | case 1: /* iBCS2 emulator entry point */ |
370 | if (!segment_eq(get_fs(), get_ds())) | 370 | if (!segment_eq(get_fs(), get_ds())) |
371 | return -EINVAL; | 371 | return -EINVAL; |
372 | return do_shmat (first, (char __user *) ptr, second, | 372 | return do_shmat (first, (char __user *) ptr, second, |
373 | (ulong *) third); | 373 | (unsigned long *) third); |
374 | } | 374 | } |
375 | case SHMDT: | 375 | case SHMDT: |
376 | return sys_shmdt ((char __user *)ptr); | 376 | return sys_shmdt ((char __user *)ptr); |
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index ad16eceb24dd..67971938a2cb 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c | |||
@@ -1050,7 +1050,7 @@ void *set_except_vector(int n, void *addr) | |||
1050 | return (void *)old_handler; | 1050 | return (void *)old_handler; |
1051 | } | 1051 | } |
1052 | 1052 | ||
1053 | #ifdef CONFIG_CPU_MIPSR2 | 1053 | #ifdef CONFIG_CPU_MIPSR2_SRS |
1054 | /* | 1054 | /* |
1055 | * MIPSR2 shadow register set allocation | 1055 | * MIPSR2 shadow register set allocation |
1056 | * FIXME: SMP... | 1056 | * FIXME: SMP... |
@@ -1069,11 +1069,9 @@ static struct shadow_registers { | |||
1069 | 1069 | ||
1070 | static void mips_srs_init(void) | 1070 | static void mips_srs_init(void) |
1071 | { | 1071 | { |
1072 | #ifdef CONFIG_CPU_MIPSR2_SRS | ||
1073 | shadow_registers.sr_supported = ((read_c0_srsctl() >> 26) & 0x0f) + 1; | 1072 | shadow_registers.sr_supported = ((read_c0_srsctl() >> 26) & 0x0f) + 1; |
1074 | printk(KERN_INFO "%d MIPSR2 register sets available\n", | 1073 | printk(KERN_INFO "%d MIPSR2 register sets available\n", |
1075 | shadow_registers.sr_supported); | 1074 | shadow_registers.sr_supported); |
1076 | #endif | ||
1077 | shadow_registers.sr_allocated = 1; /* Set 0 used by kernel */ | 1075 | shadow_registers.sr_allocated = 1; /* Set 0 used by kernel */ |
1078 | } | 1076 | } |
1079 | 1077 | ||
@@ -1198,7 +1196,14 @@ void *set_vi_handler(int n, void *addr) | |||
1198 | { | 1196 | { |
1199 | return set_vi_srs_handler(n, addr, 0); | 1197 | return set_vi_srs_handler(n, addr, 0); |
1200 | } | 1198 | } |
1201 | #endif | 1199 | |
1200 | #else | ||
1201 | |||
1202 | static inline void mips_srs_init(void) | ||
1203 | { | ||
1204 | } | ||
1205 | |||
1206 | #endif /* CONFIG_CPU_MIPSR2_SRS */ | ||
1202 | 1207 | ||
1203 | /* | 1208 | /* |
1204 | * This is used by native signal handling | 1209 | * This is used by native signal handling |
@@ -1388,9 +1393,7 @@ void __init trap_init(void) | |||
1388 | else | 1393 | else |
1389 | ebase = CAC_BASE; | 1394 | ebase = CAC_BASE; |
1390 | 1395 | ||
1391 | #ifdef CONFIG_CPU_MIPSR2 | ||
1392 | mips_srs_init(); | 1396 | mips_srs_init(); |
1393 | #endif | ||
1394 | 1397 | ||
1395 | per_cpu_trap_init(); | 1398 | per_cpu_trap_init(); |
1396 | 1399 | ||
diff --git a/arch/mips/mm/Makefile b/arch/mips/mm/Makefile index 4a6220116c96..19e41fd186c4 100644 --- a/arch/mips/mm/Makefile +++ b/arch/mips/mm/Makefile | |||
@@ -30,6 +30,7 @@ obj-$(CONFIG_CPU_VR41XX) += c-r4k.o cex-gen.o pg-r4k.o tlb-r4k.o | |||
30 | obj-$(CONFIG_IP22_CPU_SCACHE) += sc-ip22.o | 30 | obj-$(CONFIG_IP22_CPU_SCACHE) += sc-ip22.o |
31 | obj-$(CONFIG_R5000_CPU_SCACHE) += sc-r5k.o | 31 | obj-$(CONFIG_R5000_CPU_SCACHE) += sc-r5k.o |
32 | obj-$(CONFIG_RM7000_CPU_SCACHE) += sc-rm7k.o | 32 | obj-$(CONFIG_RM7000_CPU_SCACHE) += sc-rm7k.o |
33 | obj-$(CONFIG_MIPS_CPU_SCACHE) += sc-mips.o | ||
33 | 34 | ||
34 | # | 35 | # |
35 | # Choose one DMA coherency model | 36 | # Choose one DMA coherency model |
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c index 4a43924cd4fc..75d887e89739 100644 --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c | |||
@@ -60,13 +60,13 @@ static unsigned long scache_size __read_mostly; | |||
60 | /* | 60 | /* |
61 | * Dummy cache handling routines for machines without boardcaches | 61 | * Dummy cache handling routines for machines without boardcaches |
62 | */ | 62 | */ |
63 | static void no_sc_noop(void) {} | 63 | static void cache_noop(void) {} |
64 | 64 | ||
65 | static struct bcache_ops no_sc_ops = { | 65 | static struct bcache_ops no_sc_ops = { |
66 | .bc_enable = (void *)no_sc_noop, | 66 | .bc_enable = (void *)cache_noop, |
67 | .bc_disable = (void *)no_sc_noop, | 67 | .bc_disable = (void *)cache_noop, |
68 | .bc_wback_inv = (void *)no_sc_noop, | 68 | .bc_wback_inv = (void *)cache_noop, |
69 | .bc_inv = (void *)no_sc_noop | 69 | .bc_inv = (void *)cache_noop |
70 | }; | 70 | }; |
71 | 71 | ||
72 | struct bcache_ops *bcops = &no_sc_ops; | 72 | struct bcache_ops *bcops = &no_sc_ops; |
@@ -94,7 +94,9 @@ static inline void r4k_blast_dcache_page_setup(void) | |||
94 | { | 94 | { |
95 | unsigned long dc_lsize = cpu_dcache_line_size(); | 95 | unsigned long dc_lsize = cpu_dcache_line_size(); |
96 | 96 | ||
97 | if (dc_lsize == 16) | 97 | if (dc_lsize == 0) |
98 | r4k_blast_dcache_page = (void *)cache_noop; | ||
99 | else if (dc_lsize == 16) | ||
98 | r4k_blast_dcache_page = blast_dcache16_page; | 100 | r4k_blast_dcache_page = blast_dcache16_page; |
99 | else if (dc_lsize == 32) | 101 | else if (dc_lsize == 32) |
100 | r4k_blast_dcache_page = r4k_blast_dcache_page_dc32; | 102 | r4k_blast_dcache_page = r4k_blast_dcache_page_dc32; |
@@ -106,7 +108,9 @@ static inline void r4k_blast_dcache_page_indexed_setup(void) | |||
106 | { | 108 | { |
107 | unsigned long dc_lsize = cpu_dcache_line_size(); | 109 | unsigned long dc_lsize = cpu_dcache_line_size(); |
108 | 110 | ||
109 | if (dc_lsize == 16) | 111 | if (dc_lsize == 0) |
112 | r4k_blast_dcache_page_indexed = (void *)cache_noop; | ||
113 | else if (dc_lsize == 16) | ||
110 | r4k_blast_dcache_page_indexed = blast_dcache16_page_indexed; | 114 | r4k_blast_dcache_page_indexed = blast_dcache16_page_indexed; |
111 | else if (dc_lsize == 32) | 115 | else if (dc_lsize == 32) |
112 | r4k_blast_dcache_page_indexed = blast_dcache32_page_indexed; | 116 | r4k_blast_dcache_page_indexed = blast_dcache32_page_indexed; |
@@ -118,7 +122,9 @@ static inline void r4k_blast_dcache_setup(void) | |||
118 | { | 122 | { |
119 | unsigned long dc_lsize = cpu_dcache_line_size(); | 123 | unsigned long dc_lsize = cpu_dcache_line_size(); |
120 | 124 | ||
121 | if (dc_lsize == 16) | 125 | if (dc_lsize == 0) |
126 | r4k_blast_dcache = (void *)cache_noop; | ||
127 | else if (dc_lsize == 16) | ||
122 | r4k_blast_dcache = blast_dcache16; | 128 | r4k_blast_dcache = blast_dcache16; |
123 | else if (dc_lsize == 32) | 129 | else if (dc_lsize == 32) |
124 | r4k_blast_dcache = blast_dcache32; | 130 | r4k_blast_dcache = blast_dcache32; |
@@ -201,7 +207,9 @@ static inline void r4k_blast_icache_page_setup(void) | |||
201 | { | 207 | { |
202 | unsigned long ic_lsize = cpu_icache_line_size(); | 208 | unsigned long ic_lsize = cpu_icache_line_size(); |
203 | 209 | ||
204 | if (ic_lsize == 16) | 210 | if (ic_lsize == 0) |
211 | r4k_blast_icache_page = (void *)cache_noop; | ||
212 | else if (ic_lsize == 16) | ||
205 | r4k_blast_icache_page = blast_icache16_page; | 213 | r4k_blast_icache_page = blast_icache16_page; |
206 | else if (ic_lsize == 32) | 214 | else if (ic_lsize == 32) |
207 | r4k_blast_icache_page = blast_icache32_page; | 215 | r4k_blast_icache_page = blast_icache32_page; |
@@ -216,7 +224,9 @@ static inline void r4k_blast_icache_page_indexed_setup(void) | |||
216 | { | 224 | { |
217 | unsigned long ic_lsize = cpu_icache_line_size(); | 225 | unsigned long ic_lsize = cpu_icache_line_size(); |
218 | 226 | ||
219 | if (ic_lsize == 16) | 227 | if (ic_lsize == 0) |
228 | r4k_blast_icache_page_indexed = (void *)cache_noop; | ||
229 | else if (ic_lsize == 16) | ||
220 | r4k_blast_icache_page_indexed = blast_icache16_page_indexed; | 230 | r4k_blast_icache_page_indexed = blast_icache16_page_indexed; |
221 | else if (ic_lsize == 32) { | 231 | else if (ic_lsize == 32) { |
222 | if (R4600_V1_INDEX_ICACHEOP_WAR && cpu_is_r4600_v1_x()) | 232 | if (R4600_V1_INDEX_ICACHEOP_WAR && cpu_is_r4600_v1_x()) |
@@ -238,7 +248,9 @@ static inline void r4k_blast_icache_setup(void) | |||
238 | { | 248 | { |
239 | unsigned long ic_lsize = cpu_icache_line_size(); | 249 | unsigned long ic_lsize = cpu_icache_line_size(); |
240 | 250 | ||
241 | if (ic_lsize == 16) | 251 | if (ic_lsize == 0) |
252 | r4k_blast_icache = (void *)cache_noop; | ||
253 | else if (ic_lsize == 16) | ||
242 | r4k_blast_icache = blast_icache16; | 254 | r4k_blast_icache = blast_icache16; |
243 | else if (ic_lsize == 32) { | 255 | else if (ic_lsize == 32) { |
244 | if (R4600_V1_INDEX_ICACHEOP_WAR && cpu_is_r4600_v1_x()) | 256 | if (R4600_V1_INDEX_ICACHEOP_WAR && cpu_is_r4600_v1_x()) |
@@ -258,7 +270,7 @@ static inline void r4k_blast_scache_page_setup(void) | |||
258 | unsigned long sc_lsize = cpu_scache_line_size(); | 270 | unsigned long sc_lsize = cpu_scache_line_size(); |
259 | 271 | ||
260 | if (scache_size == 0) | 272 | if (scache_size == 0) |
261 | r4k_blast_scache_page = (void *)no_sc_noop; | 273 | r4k_blast_scache_page = (void *)cache_noop; |
262 | else if (sc_lsize == 16) | 274 | else if (sc_lsize == 16) |
263 | r4k_blast_scache_page = blast_scache16_page; | 275 | r4k_blast_scache_page = blast_scache16_page; |
264 | else if (sc_lsize == 32) | 276 | else if (sc_lsize == 32) |
@@ -276,7 +288,7 @@ static inline void r4k_blast_scache_page_indexed_setup(void) | |||
276 | unsigned long sc_lsize = cpu_scache_line_size(); | 288 | unsigned long sc_lsize = cpu_scache_line_size(); |
277 | 289 | ||
278 | if (scache_size == 0) | 290 | if (scache_size == 0) |
279 | r4k_blast_scache_page_indexed = (void *)no_sc_noop; | 291 | r4k_blast_scache_page_indexed = (void *)cache_noop; |
280 | else if (sc_lsize == 16) | 292 | else if (sc_lsize == 16) |
281 | r4k_blast_scache_page_indexed = blast_scache16_page_indexed; | 293 | r4k_blast_scache_page_indexed = blast_scache16_page_indexed; |
282 | else if (sc_lsize == 32) | 294 | else if (sc_lsize == 32) |
@@ -294,7 +306,7 @@ static inline void r4k_blast_scache_setup(void) | |||
294 | unsigned long sc_lsize = cpu_scache_line_size(); | 306 | unsigned long sc_lsize = cpu_scache_line_size(); |
295 | 307 | ||
296 | if (scache_size == 0) | 308 | if (scache_size == 0) |
297 | r4k_blast_scache = (void *)no_sc_noop; | 309 | r4k_blast_scache = (void *)cache_noop; |
298 | else if (sc_lsize == 16) | 310 | else if (sc_lsize == 16) |
299 | r4k_blast_scache = blast_scache16; | 311 | r4k_blast_scache = blast_scache16; |
300 | else if (sc_lsize == 32) | 312 | else if (sc_lsize == 32) |
@@ -508,7 +520,7 @@ static inline void local_r4k_flush_icache_range(void *args) | |||
508 | unsigned long end = fir_args->end; | 520 | unsigned long end = fir_args->end; |
509 | 521 | ||
510 | if (!cpu_has_ic_fills_f_dc) { | 522 | if (!cpu_has_ic_fills_f_dc) { |
511 | if (end - start > dcache_size) { | 523 | if (end - start >= dcache_size) { |
512 | r4k_blast_dcache(); | 524 | r4k_blast_dcache(); |
513 | } else { | 525 | } else { |
514 | R4600_HIT_CACHEOP_WAR_IMPL; | 526 | R4600_HIT_CACHEOP_WAR_IMPL; |
@@ -683,10 +695,12 @@ static void local_r4k_flush_cache_sigtramp(void * arg) | |||
683 | unsigned long addr = (unsigned long) arg; | 695 | unsigned long addr = (unsigned long) arg; |
684 | 696 | ||
685 | R4600_HIT_CACHEOP_WAR_IMPL; | 697 | R4600_HIT_CACHEOP_WAR_IMPL; |
686 | protected_writeback_dcache_line(addr & ~(dc_lsize - 1)); | 698 | if (dc_lsize) |
699 | protected_writeback_dcache_line(addr & ~(dc_lsize - 1)); | ||
687 | if (!cpu_icache_snoops_remote_store && scache_size) | 700 | if (!cpu_icache_snoops_remote_store && scache_size) |
688 | protected_writeback_scache_line(addr & ~(sc_lsize - 1)); | 701 | protected_writeback_scache_line(addr & ~(sc_lsize - 1)); |
689 | protected_flush_icache_line(addr & ~(ic_lsize - 1)); | 702 | if (ic_lsize) |
703 | protected_flush_icache_line(addr & ~(ic_lsize - 1)); | ||
690 | if (MIPS4K_ICACHE_REFILL_WAR) { | 704 | if (MIPS4K_ICACHE_REFILL_WAR) { |
691 | __asm__ __volatile__ ( | 705 | __asm__ __volatile__ ( |
692 | ".set push\n\t" | 706 | ".set push\n\t" |
@@ -973,8 +987,10 @@ static void __init probe_pcache(void) | |||
973 | c->icache.waysize = icache_size / c->icache.ways; | 987 | c->icache.waysize = icache_size / c->icache.ways; |
974 | c->dcache.waysize = dcache_size / c->dcache.ways; | 988 | c->dcache.waysize = dcache_size / c->dcache.ways; |
975 | 989 | ||
976 | c->icache.sets = icache_size / (c->icache.linesz * c->icache.ways); | 990 | c->icache.sets = c->icache.linesz ? |
977 | c->dcache.sets = dcache_size / (c->dcache.linesz * c->dcache.ways); | 991 | icache_size / (c->icache.linesz * c->icache.ways) : 0; |
992 | c->dcache.sets = c->dcache.linesz ? | ||
993 | dcache_size / (c->dcache.linesz * c->dcache.ways) : 0; | ||
978 | 994 | ||
979 | /* | 995 | /* |
980 | * R10000 and R12000 P-caches are odd in a positive way. They're 32kB | 996 | * R10000 and R12000 P-caches are odd in a positive way. They're 32kB |
@@ -993,10 +1009,16 @@ static void __init probe_pcache(void) | |||
993 | break; | 1009 | break; |
994 | case CPU_24K: | 1010 | case CPU_24K: |
995 | case CPU_34K: | 1011 | case CPU_34K: |
996 | if (!(read_c0_config7() & (1 << 16))) | 1012 | case CPU_74K: |
1013 | if ((read_c0_config7() & (1 << 16))) { | ||
1014 | /* effectively physically indexed dcache, | ||
1015 | thus no virtual aliases. */ | ||
1016 | c->dcache.flags |= MIPS_CACHE_PINDEX; | ||
1017 | break; | ||
1018 | } | ||
997 | default: | 1019 | default: |
998 | if (c->dcache.waysize > PAGE_SIZE) | 1020 | if (c->dcache.waysize > PAGE_SIZE) |
999 | c->dcache.flags |= MIPS_CACHE_ALIASES; | 1021 | c->dcache.flags |= MIPS_CACHE_ALIASES; |
1000 | } | 1022 | } |
1001 | 1023 | ||
1002 | switch (c->cputype) { | 1024 | switch (c->cputype) { |
@@ -1092,6 +1114,7 @@ static int __init probe_scache(void) | |||
1092 | 1114 | ||
1093 | extern int r5k_sc_init(void); | 1115 | extern int r5k_sc_init(void); |
1094 | extern int rm7k_sc_init(void); | 1116 | extern int rm7k_sc_init(void); |
1117 | extern int mips_sc_init(void); | ||
1095 | 1118 | ||
1096 | static void __init setup_scache(void) | 1119 | static void __init setup_scache(void) |
1097 | { | 1120 | { |
@@ -1139,17 +1162,29 @@ static void __init setup_scache(void) | |||
1139 | return; | 1162 | return; |
1140 | 1163 | ||
1141 | default: | 1164 | default: |
1165 | if (c->isa_level == MIPS_CPU_ISA_M32R1 || | ||
1166 | c->isa_level == MIPS_CPU_ISA_M32R2 || | ||
1167 | c->isa_level == MIPS_CPU_ISA_M64R1 || | ||
1168 | c->isa_level == MIPS_CPU_ISA_M64R2) { | ||
1169 | #ifdef CONFIG_MIPS_CPU_SCACHE | ||
1170 | if (mips_sc_init ()) { | ||
1171 | scache_size = c->scache.ways * c->scache.sets * c->scache.linesz; | ||
1172 | printk("MIPS secondary cache %ldkB, %s, linesize %d bytes.\n", | ||
1173 | scache_size >> 10, | ||
1174 | way_string[c->scache.ways], c->scache.linesz); | ||
1175 | } | ||
1176 | #else | ||
1177 | if (!(c->scache.flags & MIPS_CACHE_NOT_PRESENT)) | ||
1178 | panic("Dunno how to handle MIPS32 / MIPS64 second level cache"); | ||
1179 | #endif | ||
1180 | return; | ||
1181 | } | ||
1142 | sc_present = 0; | 1182 | sc_present = 0; |
1143 | } | 1183 | } |
1144 | 1184 | ||
1145 | if (!sc_present) | 1185 | if (!sc_present) |
1146 | return; | 1186 | return; |
1147 | 1187 | ||
1148 | if ((c->isa_level == MIPS_CPU_ISA_M32R1 || | ||
1149 | c->isa_level == MIPS_CPU_ISA_M64R1) && | ||
1150 | !(c->scache.flags & MIPS_CACHE_NOT_PRESENT)) | ||
1151 | panic("Dunno how to handle MIPS32 / MIPS64 second level cache"); | ||
1152 | |||
1153 | /* compute a couple of other cache variables */ | 1188 | /* compute a couple of other cache variables */ |
1154 | c->scache.waysize = scache_size / c->scache.ways; | 1189 | c->scache.waysize = scache_size / c->scache.ways; |
1155 | 1190 | ||
@@ -1246,10 +1281,12 @@ void __init r4k_cache_init(void) | |||
1246 | * This code supports virtually indexed processors and will be | 1281 | * This code supports virtually indexed processors and will be |
1247 | * unnecessarily inefficient on physically indexed processors. | 1282 | * unnecessarily inefficient on physically indexed processors. |
1248 | */ | 1283 | */ |
1249 | shm_align_mask = max_t( unsigned long, | 1284 | if (c->dcache.linesz) |
1250 | c->dcache.sets * c->dcache.linesz - 1, | 1285 | shm_align_mask = max_t( unsigned long, |
1251 | PAGE_SIZE - 1); | 1286 | c->dcache.sets * c->dcache.linesz - 1, |
1252 | 1287 | PAGE_SIZE - 1); | |
1288 | else | ||
1289 | shm_align_mask = PAGE_SIZE-1; | ||
1253 | flush_cache_all = r4k_flush_cache_all; | 1290 | flush_cache_all = r4k_flush_cache_all; |
1254 | __flush_cache_all = r4k___flush_cache_all; | 1291 | __flush_cache_all = r4k___flush_cache_all; |
1255 | flush_cache_mm = r4k_flush_cache_mm; | 1292 | flush_cache_mm = r4k_flush_cache_mm; |
diff --git a/arch/mips/mm/sc-mips.c b/arch/mips/mm/sc-mips.c new file mode 100644 index 000000000000..42b50964c644 --- /dev/null +++ b/arch/mips/mm/sc-mips.c | |||
@@ -0,0 +1,112 @@ | |||
1 | /* | ||
2 | * Copyright (C) 2006 Chris Dearman (chris@mips.com), | ||
3 | */ | ||
4 | #include <linux/init.h> | ||
5 | #include <linux/kernel.h> | ||
6 | #include <linux/sched.h> | ||
7 | #include <linux/mm.h> | ||
8 | |||
9 | #include <asm/mipsregs.h> | ||
10 | #include <asm/bcache.h> | ||
11 | #include <asm/cacheops.h> | ||
12 | #include <asm/page.h> | ||
13 | #include <asm/pgtable.h> | ||
14 | #include <asm/system.h> | ||
15 | #include <asm/mmu_context.h> | ||
16 | #include <asm/r4kcache.h> | ||
17 | |||
18 | /* | ||
19 | * MIPS32/MIPS64 L2 cache handling | ||
20 | */ | ||
21 | |||
22 | /* | ||
23 | * Writeback and invalidate the secondary cache before DMA. | ||
24 | */ | ||
25 | static void mips_sc_wback_inv(unsigned long addr, unsigned long size) | ||
26 | { | ||
27 | blast_scache_range(addr, addr + size); | ||
28 | } | ||
29 | |||
30 | /* | ||
31 | * Invalidate the secondary cache before DMA. | ||
32 | */ | ||
33 | static void mips_sc_inv(unsigned long addr, unsigned long size) | ||
34 | { | ||
35 | blast_inv_scache_range(addr, addr + size); | ||
36 | } | ||
37 | |||
38 | static void mips_sc_enable(void) | ||
39 | { | ||
40 | /* L2 cache is permanently enabled */ | ||
41 | } | ||
42 | |||
43 | static void mips_sc_disable(void) | ||
44 | { | ||
45 | /* L2 cache is permanently enabled */ | ||
46 | } | ||
47 | |||
48 | static struct bcache_ops mips_sc_ops = { | ||
49 | .bc_enable = mips_sc_enable, | ||
50 | .bc_disable = mips_sc_disable, | ||
51 | .bc_wback_inv = mips_sc_wback_inv, | ||
52 | .bc_inv = mips_sc_inv | ||
53 | }; | ||
54 | |||
55 | static inline int __init mips_sc_probe(void) | ||
56 | { | ||
57 | struct cpuinfo_mips *c = ¤t_cpu_data; | ||
58 | unsigned int config1, config2; | ||
59 | unsigned int tmp; | ||
60 | |||
61 | /* Mark as not present until probe completed */ | ||
62 | c->scache.flags |= MIPS_CACHE_NOT_PRESENT; | ||
63 | |||
64 | /* Ignore anything but MIPSxx processors */ | ||
65 | if (c->isa_level != MIPS_CPU_ISA_M32R1 && | ||
66 | c->isa_level != MIPS_CPU_ISA_M32R2 && | ||
67 | c->isa_level != MIPS_CPU_ISA_M64R1 && | ||
68 | c->isa_level != MIPS_CPU_ISA_M64R2) | ||
69 | return 0; | ||
70 | |||
71 | /* Does this MIPS32/MIPS64 CPU have a config2 register? */ | ||
72 | config1 = read_c0_config1(); | ||
73 | if (!(config1 & MIPS_CONF_M)) | ||
74 | return 0; | ||
75 | |||
76 | config2 = read_c0_config2(); | ||
77 | tmp = (config2 >> 4) & 0x0f; | ||
78 | if (0 < tmp && tmp <= 7) | ||
79 | c->scache.linesz = 2 << tmp; | ||
80 | else | ||
81 | return 0; | ||
82 | |||
83 | tmp = (config2 >> 8) & 0x0f; | ||
84 | if (0 <= tmp && tmp <= 7) | ||
85 | c->scache.sets = 64 << tmp; | ||
86 | else | ||
87 | return 0; | ||
88 | |||
89 | tmp = (config2 >> 0) & 0x0f; | ||
90 | if (0 <= tmp && tmp <= 7) | ||
91 | c->scache.ways = tmp + 1; | ||
92 | else | ||
93 | return 0; | ||
94 | |||
95 | c->scache.waysize = c->scache.sets * c->scache.linesz; | ||
96 | c->scache.waybit = __ffs(c->scache.waysize); | ||
97 | |||
98 | c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT; | ||
99 | |||
100 | return 1; | ||
101 | } | ||
102 | |||
103 | int __init mips_sc_init(void) | ||
104 | { | ||
105 | int found = mips_sc_probe (); | ||
106 | if (found) { | ||
107 | mips_sc_enable(); | ||
108 | bcops = &mips_sc_ops; | ||
109 | } | ||
110 | return found; | ||
111 | } | ||
112 | |||
diff --git a/arch/mips/momentum/jaguar_atx/setup.c b/arch/mips/momentum/jaguar_atx/setup.c index df1485501ce6..d0419480b097 100644 --- a/arch/mips/momentum/jaguar_atx/setup.c +++ b/arch/mips/momentum/jaguar_atx/setup.c | |||
@@ -370,8 +370,8 @@ void __init plat_mem_setup(void) | |||
370 | pm_power_off = momenco_jaguar_power_off; | 370 | pm_power_off = momenco_jaguar_power_off; |
371 | 371 | ||
372 | /* | 372 | /* |
373 | * initrd_start = (ulong)jaguar_initrd_start; | 373 | * initrd_start = (unsigned long)jaguar_initrd_start; |
374 | * initrd_end = (ulong)jaguar_initrd_start + (ulong)jaguar_initrd_size; | 374 | * initrd_end = (unsigned long)jaguar_initrd_start + (ulong)jaguar_initrd_size; |
375 | * initrd_below_start_ok = 1; | 375 | * initrd_below_start_ok = 1; |
376 | */ | 376 | */ |
377 | 377 | ||
diff --git a/arch/mips/momentum/ocelot_c/setup.c b/arch/mips/momentum/ocelot_c/setup.c index 257e1d1b72dd..a0ee006d75cf 100644 --- a/arch/mips/momentum/ocelot_c/setup.c +++ b/arch/mips/momentum/ocelot_c/setup.c | |||
@@ -242,8 +242,8 @@ void __init plat_mem_setup(void) | |||
242 | pm_power_off = momenco_ocelot_power_off; | 242 | pm_power_off = momenco_ocelot_power_off; |
243 | 243 | ||
244 | /* | 244 | /* |
245 | * initrd_start = (ulong)ocelot_initrd_start; | 245 | * initrd_start = (unsigned long)ocelot_initrd_start; |
246 | * initrd_end = (ulong)ocelot_initrd_start + (ulong)ocelot_initrd_size; | 246 | * initrd_end = (unsigned long)ocelot_initrd_start + (ulong)ocelot_initrd_size; |
247 | * initrd_below_start_ok = 1; | 247 | * initrd_below_start_ok = 1; |
248 | */ | 248 | */ |
249 | 249 | ||
diff --git a/arch/mips/momentum/ocelot_g/setup.c b/arch/mips/momentum/ocelot_g/setup.c index 72143ab1e900..39da02b4e076 100644 --- a/arch/mips/momentum/ocelot_g/setup.c +++ b/arch/mips/momentum/ocelot_g/setup.c | |||
@@ -174,8 +174,8 @@ void __init plat_mem_setup(void) | |||
174 | pm_power_off = momenco_ocelot_power_off; | 174 | pm_power_off = momenco_ocelot_power_off; |
175 | 175 | ||
176 | /* | 176 | /* |
177 | * initrd_start = (ulong)ocelot_initrd_start; | 177 | * initrd_start = (unsigned long)ocelot_initrd_start; |
178 | * initrd_end = (ulong)ocelot_initrd_start + (ulong)ocelot_initrd_size; | 178 | * initrd_end = (unsigned long)ocelot_initrd_start + (ulong)ocelot_initrd_size; |
179 | * initrd_below_start_ok = 1; | 179 | * initrd_below_start_ok = 1; |
180 | */ | 180 | */ |
181 | 181 | ||
diff --git a/arch/mips/oprofile/op_model_mipsxx.c b/arch/mips/oprofile/op_model_mipsxx.c index f26a00e13204..a09c5f901233 100644 --- a/arch/mips/oprofile/op_model_mipsxx.c +++ b/arch/mips/oprofile/op_model_mipsxx.c | |||
@@ -12,16 +12,70 @@ | |||
12 | 12 | ||
13 | #include "op_impl.h" | 13 | #include "op_impl.h" |
14 | 14 | ||
15 | #define M_PERFCTL_EXL (1UL << 0) | 15 | #define M_PERFCTL_EXL (1UL << 0) |
16 | #define M_PERFCTL_KERNEL (1UL << 1) | 16 | #define M_PERFCTL_KERNEL (1UL << 1) |
17 | #define M_PERFCTL_SUPERVISOR (1UL << 2) | 17 | #define M_PERFCTL_SUPERVISOR (1UL << 2) |
18 | #define M_PERFCTL_USER (1UL << 3) | 18 | #define M_PERFCTL_USER (1UL << 3) |
19 | #define M_PERFCTL_INTERRUPT_ENABLE (1UL << 4) | 19 | #define M_PERFCTL_INTERRUPT_ENABLE (1UL << 4) |
20 | #define M_PERFCTL_EVENT(event) ((event) << 5) | 20 | #define M_PERFCTL_EVENT(event) ((event) << 5) |
21 | #define M_PERFCTL_WIDE (1UL << 30) | 21 | #define M_PERFCTL_VPEID(vpe) ((vpe) << 16) |
22 | #define M_PERFCTL_MORE (1UL << 31) | 22 | #define M_PERFCTL_MT_EN(filter) ((filter) << 20) |
23 | #define M_TC_EN_ALL M_PERFCTL_MT_EN(0) | ||
24 | #define M_TC_EN_VPE M_PERFCTL_MT_EN(1) | ||
25 | #define M_TC_EN_TC M_PERFCTL_MT_EN(2) | ||
26 | #define M_PERFCTL_TCID(tcid) ((tcid) << 22) | ||
27 | #define M_PERFCTL_WIDE (1UL << 30) | ||
28 | #define M_PERFCTL_MORE (1UL << 31) | ||
29 | |||
30 | #define M_COUNTER_OVERFLOW (1UL << 31) | ||
31 | |||
32 | #ifdef CONFIG_MIPS_MT_SMP | ||
33 | #define WHAT (M_TC_EN_VPE | M_PERFCTL_VPEID(smp_processor_id())) | ||
34 | #else | ||
35 | #define WHAT 0 | ||
36 | #endif | ||
23 | 37 | ||
24 | #define M_COUNTER_OVERFLOW (1UL << 31) | 38 | #define __define_perf_accessors(r, n, np) \ |
39 | \ | ||
40 | static inline unsigned int r_c0_ ## r ## n(void) \ | ||
41 | { \ | ||
42 | unsigned int cpu = smp_processor_id(); \ | ||
43 | \ | ||
44 | switch (cpu) { \ | ||
45 | case 0: \ | ||
46 | return read_c0_ ## r ## n(); \ | ||
47 | case 1: \ | ||
48 | return read_c0_ ## r ## np(); \ | ||
49 | default: \ | ||
50 | BUG(); \ | ||
51 | } \ | ||
52 | } \ | ||
53 | \ | ||
54 | static inline void w_c0_ ## r ## n(unsigned int value) \ | ||
55 | { \ | ||
56 | unsigned int cpu = smp_processor_id(); \ | ||
57 | \ | ||
58 | switch (cpu) { \ | ||
59 | case 0: \ | ||
60 | write_c0_ ## r ## n(value); \ | ||
61 | return; \ | ||
62 | case 1: \ | ||
63 | write_c0_ ## r ## np(value); \ | ||
64 | return; \ | ||
65 | default: \ | ||
66 | BUG(); \ | ||
67 | } \ | ||
68 | } \ | ||
69 | |||
70 | __define_perf_accessors(perfcntr, 0, 2) | ||
71 | __define_perf_accessors(perfcntr, 1, 3) | ||
72 | __define_perf_accessors(perfcntr, 2, 2) | ||
73 | __define_perf_accessors(perfcntr, 3, 2) | ||
74 | |||
75 | __define_perf_accessors(perfctrl, 0, 2) | ||
76 | __define_perf_accessors(perfctrl, 1, 3) | ||
77 | __define_perf_accessors(perfctrl, 2, 2) | ||
78 | __define_perf_accessors(perfctrl, 3, 2) | ||
25 | 79 | ||
26 | struct op_mips_model op_model_mipsxx_ops; | 80 | struct op_mips_model op_model_mipsxx_ops; |
27 | 81 | ||
@@ -66,17 +120,17 @@ static void mipsxx_cpu_setup (void *args) | |||
66 | 120 | ||
67 | switch (counters) { | 121 | switch (counters) { |
68 | case 4: | 122 | case 4: |
69 | write_c0_perfctrl3(0); | 123 | w_c0_perfctrl3(0); |
70 | write_c0_perfcntr3(reg.counter[3]); | 124 | w_c0_perfcntr3(reg.counter[3]); |
71 | case 3: | 125 | case 3: |
72 | write_c0_perfctrl2(0); | 126 | w_c0_perfctrl2(0); |
73 | write_c0_perfcntr2(reg.counter[2]); | 127 | w_c0_perfcntr2(reg.counter[2]); |
74 | case 2: | 128 | case 2: |
75 | write_c0_perfctrl1(0); | 129 | w_c0_perfctrl1(0); |
76 | write_c0_perfcntr1(reg.counter[1]); | 130 | w_c0_perfcntr1(reg.counter[1]); |
77 | case 1: | 131 | case 1: |
78 | write_c0_perfctrl0(0); | 132 | w_c0_perfctrl0(0); |
79 | write_c0_perfcntr0(reg.counter[0]); | 133 | w_c0_perfcntr0(reg.counter[0]); |
80 | } | 134 | } |
81 | } | 135 | } |
82 | 136 | ||
@@ -87,13 +141,13 @@ static void mipsxx_cpu_start(void *args) | |||
87 | 141 | ||
88 | switch (counters) { | 142 | switch (counters) { |
89 | case 4: | 143 | case 4: |
90 | write_c0_perfctrl3(reg.control[3]); | 144 | w_c0_perfctrl3(WHAT | reg.control[3]); |
91 | case 3: | 145 | case 3: |
92 | write_c0_perfctrl2(reg.control[2]); | 146 | w_c0_perfctrl2(WHAT | reg.control[2]); |
93 | case 2: | 147 | case 2: |
94 | write_c0_perfctrl1(reg.control[1]); | 148 | w_c0_perfctrl1(WHAT | reg.control[1]); |
95 | case 1: | 149 | case 1: |
96 | write_c0_perfctrl0(reg.control[0]); | 150 | w_c0_perfctrl0(WHAT | reg.control[0]); |
97 | } | 151 | } |
98 | } | 152 | } |
99 | 153 | ||
@@ -104,13 +158,13 @@ static void mipsxx_cpu_stop(void *args) | |||
104 | 158 | ||
105 | switch (counters) { | 159 | switch (counters) { |
106 | case 4: | 160 | case 4: |
107 | write_c0_perfctrl3(0); | 161 | w_c0_perfctrl3(0); |
108 | case 3: | 162 | case 3: |
109 | write_c0_perfctrl2(0); | 163 | w_c0_perfctrl2(0); |
110 | case 2: | 164 | case 2: |
111 | write_c0_perfctrl1(0); | 165 | w_c0_perfctrl1(0); |
112 | case 1: | 166 | case 1: |
113 | write_c0_perfctrl0(0); | 167 | w_c0_perfctrl0(0); |
114 | } | 168 | } |
115 | } | 169 | } |
116 | 170 | ||
@@ -124,12 +178,12 @@ static int mipsxx_perfcount_handler(struct pt_regs *regs) | |||
124 | switch (counters) { | 178 | switch (counters) { |
125 | #define HANDLE_COUNTER(n) \ | 179 | #define HANDLE_COUNTER(n) \ |
126 | case n + 1: \ | 180 | case n + 1: \ |
127 | control = read_c0_perfctrl ## n(); \ | 181 | control = r_c0_perfctrl ## n(); \ |
128 | counter = read_c0_perfcntr ## n(); \ | 182 | counter = r_c0_perfcntr ## n(); \ |
129 | if ((control & M_PERFCTL_INTERRUPT_ENABLE) && \ | 183 | if ((control & M_PERFCTL_INTERRUPT_ENABLE) && \ |
130 | (counter & M_COUNTER_OVERFLOW)) { \ | 184 | (counter & M_COUNTER_OVERFLOW)) { \ |
131 | oprofile_add_sample(regs, n); \ | 185 | oprofile_add_sample(regs, n); \ |
132 | write_c0_perfcntr ## n(reg.counter[n]); \ | 186 | w_c0_perfcntr ## n(reg.counter[n]); \ |
133 | handled = 1; \ | 187 | handled = 1; \ |
134 | } | 188 | } |
135 | HANDLE_COUNTER(3) | 189 | HANDLE_COUNTER(3) |
@@ -143,35 +197,47 @@ static int mipsxx_perfcount_handler(struct pt_regs *regs) | |||
143 | 197 | ||
144 | #define M_CONFIG1_PC (1 << 4) | 198 | #define M_CONFIG1_PC (1 << 4) |
145 | 199 | ||
146 | static inline int n_counters(void) | 200 | static inline int __n_counters(void) |
147 | { | 201 | { |
148 | if (!(read_c0_config1() & M_CONFIG1_PC)) | 202 | if (!(read_c0_config1() & M_CONFIG1_PC)) |
149 | return 0; | 203 | return 0; |
150 | if (!(read_c0_perfctrl0() & M_PERFCTL_MORE)) | 204 | if (!(r_c0_perfctrl0() & M_PERFCTL_MORE)) |
151 | return 1; | 205 | return 1; |
152 | if (!(read_c0_perfctrl1() & M_PERFCTL_MORE)) | 206 | if (!(r_c0_perfctrl1() & M_PERFCTL_MORE)) |
153 | return 2; | 207 | return 2; |
154 | if (!(read_c0_perfctrl2() & M_PERFCTL_MORE)) | 208 | if (!(r_c0_perfctrl2() & M_PERFCTL_MORE)) |
155 | return 3; | 209 | return 3; |
156 | 210 | ||
157 | return 4; | 211 | return 4; |
158 | } | 212 | } |
159 | 213 | ||
214 | static inline int n_counters(void) | ||
215 | { | ||
216 | int counters = __n_counters(); | ||
217 | |||
218 | #ifndef CONFIG_SMP | ||
219 | if (current_cpu_data.cputype == CPU_34K) | ||
220 | return counters >> 1; | ||
221 | #endif | ||
222 | |||
223 | return counters; | ||
224 | } | ||
225 | |||
160 | static inline void reset_counters(int counters) | 226 | static inline void reset_counters(int counters) |
161 | { | 227 | { |
162 | switch (counters) { | 228 | switch (counters) { |
163 | case 4: | 229 | case 4: |
164 | write_c0_perfctrl3(0); | 230 | w_c0_perfctrl3(0); |
165 | write_c0_perfcntr3(0); | 231 | w_c0_perfcntr3(0); |
166 | case 3: | 232 | case 3: |
167 | write_c0_perfctrl2(0); | 233 | w_c0_perfctrl2(0); |
168 | write_c0_perfcntr2(0); | 234 | w_c0_perfcntr2(0); |
169 | case 2: | 235 | case 2: |
170 | write_c0_perfctrl1(0); | 236 | w_c0_perfctrl1(0); |
171 | write_c0_perfcntr1(0); | 237 | w_c0_perfcntr1(0); |
172 | case 1: | 238 | case 1: |
173 | write_c0_perfctrl0(0); | 239 | w_c0_perfctrl0(0); |
174 | write_c0_perfcntr0(0); | 240 | w_c0_perfcntr0(0); |
175 | } | 241 | } |
176 | } | 242 | } |
177 | 243 | ||
@@ -201,7 +267,6 @@ static int __init mipsxx_init(void) | |||
201 | op_model_mipsxx_ops.cpu_type = "mips/25K"; | 267 | op_model_mipsxx_ops.cpu_type = "mips/25K"; |
202 | break; | 268 | break; |
203 | 269 | ||
204 | #ifndef CONFIG_SMP | ||
205 | case CPU_34K: | 270 | case CPU_34K: |
206 | op_model_mipsxx_ops.cpu_type = "mips/34K"; | 271 | op_model_mipsxx_ops.cpu_type = "mips/34K"; |
207 | break; | 272 | break; |
@@ -209,7 +274,6 @@ static int __init mipsxx_init(void) | |||
209 | case CPU_74K: | 274 | case CPU_74K: |
210 | op_model_mipsxx_ops.cpu_type = "mips/74K"; | 275 | op_model_mipsxx_ops.cpu_type = "mips/74K"; |
211 | break; | 276 | break; |
212 | #endif | ||
213 | 277 | ||
214 | case CPU_5KC: | 278 | case CPU_5KC: |
215 | op_model_mipsxx_ops.cpu_type = "mips/5K"; | 279 | op_model_mipsxx_ops.cpu_type = "mips/5K"; |
diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile index 465778c5d816..35d5927706ea 100644 --- a/arch/mips/pci/Makefile +++ b/arch/mips/pci/Makefile | |||
@@ -23,7 +23,7 @@ obj-$(CONFIG_MARKEINS) += ops-emma2rh.o pci-emma2rh.o fixup-emma2rh.o | |||
23 | # | 23 | # |
24 | # These are still pretty much in the old state, watch, go blind. | 24 | # These are still pretty much in the old state, watch, go blind. |
25 | # | 25 | # |
26 | obj-$(CONFIG_BASLER_EXCITE) = ops-titan.o pci-excite.o fixup-excite.o | 26 | obj-$(CONFIG_BASLER_EXCITE) += ops-titan.o pci-excite.o fixup-excite.o |
27 | obj-$(CONFIG_DDB5477) += fixup-ddb5477.o pci-ddb5477.o ops-ddb5477.o | 27 | obj-$(CONFIG_DDB5477) += fixup-ddb5477.o pci-ddb5477.o ops-ddb5477.o |
28 | obj-$(CONFIG_LASAT) += pci-lasat.o | 28 | obj-$(CONFIG_LASAT) += pci-lasat.o |
29 | obj-$(CONFIG_MIPS_ATLAS) += fixup-atlas.o | 29 | obj-$(CONFIG_MIPS_ATLAS) += fixup-atlas.o |
diff --git a/arch/mips/pci/ops-tx4927.c b/arch/mips/pci/ops-tx4927.c index 7688b7711329..150419c8b414 100644 --- a/arch/mips/pci/ops-tx4927.c +++ b/arch/mips/pci/ops-tx4927.c | |||
@@ -119,7 +119,7 @@ static int tx4927_pcibios_read_config(struct pci_bus *bus, unsigned int devfn, i | |||
119 | 119 | ||
120 | switch (size) { | 120 | switch (size) { |
121 | case 1: | 121 | case 1: |
122 | *val = *(volatile u8 *) ((ulong) & tx4927_pcicptr-> | 122 | *val = *(volatile u8 *) ((unsigned long) & tx4927_pcicptr-> |
123 | g2pcfgdata | | 123 | g2pcfgdata | |
124 | #ifdef __LITTLE_ENDIAN | 124 | #ifdef __LITTLE_ENDIAN |
125 | (where & 3)); | 125 | (where & 3)); |
@@ -128,7 +128,7 @@ static int tx4927_pcibios_read_config(struct pci_bus *bus, unsigned int devfn, i | |||
128 | #endif | 128 | #endif |
129 | break; | 129 | break; |
130 | case 2: | 130 | case 2: |
131 | *val = *(volatile u16 *) ((ulong) & tx4927_pcicptr-> | 131 | *val = *(volatile u16 *) ((unsigned long) & tx4927_pcicptr-> |
132 | g2pcfgdata | | 132 | g2pcfgdata | |
133 | #ifdef __LITTLE_ENDIAN | 133 | #ifdef __LITTLE_ENDIAN |
134 | (where & 3)); | 134 | (where & 3)); |
@@ -168,7 +168,7 @@ static int tx4927_pcibios_write_config(struct pci_bus *bus, unsigned int devfn, | |||
168 | 168 | ||
169 | switch (size) { | 169 | switch (size) { |
170 | case 1: | 170 | case 1: |
171 | *(volatile u8 *) ((ulong) & tx4927_pcicptr-> | 171 | *(volatile u8 *) ((unsigned long) & tx4927_pcicptr-> |
172 | g2pcfgdata | | 172 | g2pcfgdata | |
173 | #ifdef __LITTLE_ENDIAN | 173 | #ifdef __LITTLE_ENDIAN |
174 | (where & 3)) = val; | 174 | (where & 3)) = val; |
@@ -178,7 +178,7 @@ static int tx4927_pcibios_write_config(struct pci_bus *bus, unsigned int devfn, | |||
178 | break; | 178 | break; |
179 | 179 | ||
180 | case 2: | 180 | case 2: |
181 | *(volatile u16 *) ((ulong) & tx4927_pcicptr-> | 181 | *(volatile u16 *) ((unsigned long) & tx4927_pcicptr-> |
182 | g2pcfgdata | | 182 | g2pcfgdata | |
183 | #ifdef __LITTLE_ENDIAN | 183 | #ifdef __LITTLE_ENDIAN |
184 | (where & 3)) = val; | 184 | (where & 3)) = val; |
diff --git a/arch/mips/pci/ops-tx4938.c b/arch/mips/pci/ops-tx4938.c index 0ff083489efd..445007084515 100644 --- a/arch/mips/pci/ops-tx4938.c +++ b/arch/mips/pci/ops-tx4938.c | |||
@@ -106,7 +106,7 @@ static int tx4938_pcibios_read_config(struct pci_bus *bus, unsigned int devfn, | |||
106 | 106 | ||
107 | switch (size) { | 107 | switch (size) { |
108 | case 1: | 108 | case 1: |
109 | *val = *(volatile u8 *) ((ulong) & tx4938_pcicptr->g2pcfgdata | | 109 | *val = *(volatile u8 *) ((unsigned long) & tx4938_pcicptr->g2pcfgdata | |
110 | #ifdef __BIG_ENDIAN | 110 | #ifdef __BIG_ENDIAN |
111 | ((where & 3) ^ 3)); | 111 | ((where & 3) ^ 3)); |
112 | #else | 112 | #else |
@@ -114,7 +114,7 @@ static int tx4938_pcibios_read_config(struct pci_bus *bus, unsigned int devfn, | |||
114 | #endif | 114 | #endif |
115 | break; | 115 | break; |
116 | case 2: | 116 | case 2: |
117 | *val = *(volatile u16 *) ((ulong) & tx4938_pcicptr->g2pcfgdata | | 117 | *val = *(volatile u16 *) ((unsigned long) & tx4938_pcicptr->g2pcfgdata | |
118 | #ifdef __BIG_ENDIAN | 118 | #ifdef __BIG_ENDIAN |
119 | ((where & 3) ^ 2)); | 119 | ((where & 3) ^ 2)); |
120 | #else | 120 | #else |
@@ -154,7 +154,7 @@ static int tx4938_pcibios_write_config(struct pci_bus *bus, unsigned int devfn, | |||
154 | 154 | ||
155 | switch (size) { | 155 | switch (size) { |
156 | case 1: | 156 | case 1: |
157 | *(volatile u8 *) ((ulong) & tx4938_pcicptr->g2pcfgdata | | 157 | *(volatile u8 *) ((unsigned long) & tx4938_pcicptr->g2pcfgdata | |
158 | #ifdef __BIG_ENDIAN | 158 | #ifdef __BIG_ENDIAN |
159 | ((where & 3) ^ 3)) = val; | 159 | ((where & 3) ^ 3)) = val; |
160 | #else | 160 | #else |
@@ -162,7 +162,7 @@ static int tx4938_pcibios_write_config(struct pci_bus *bus, unsigned int devfn, | |||
162 | #endif | 162 | #endif |
163 | break; | 163 | break; |
164 | case 2: | 164 | case 2: |
165 | *(volatile u16 *) ((ulong) & tx4938_pcicptr->g2pcfgdata | | 165 | *(volatile u16 *) ((unsigned long) & tx4938_pcicptr->g2pcfgdata | |
166 | #ifdef __BIG_ENDIAN | 166 | #ifdef __BIG_ENDIAN |
167 | ((where & 0x3) ^ 0x2)) = val; | 167 | ((where & 0x3) ^ 0x2)) = val; |
168 | #else | 168 | #else |
diff --git a/arch/mips/sgi-ip27/Kconfig b/arch/mips/sgi-ip27/Kconfig index f14ef38646d0..5e960ae9735a 100644 --- a/arch/mips/sgi-ip27/Kconfig +++ b/arch/mips/sgi-ip27/Kconfig | |||
@@ -33,12 +33,13 @@ config MAPPED_KERNEL | |||
33 | depends on SGI_IP27 | 33 | depends on SGI_IP27 |
34 | help | 34 | help |
35 | Change the way a Linux kernel is loaded into memory on a MIPS64 | 35 | Change the way a Linux kernel is loaded into memory on a MIPS64 |
36 | machine. This is required in order to support text replication and | 36 | machine. This is required in order to support text replication on |
37 | NUMA. If you need to understand it, read the source code. | 37 | NUMA. If you need to understand it, read the source code. |
38 | 38 | ||
39 | config REPLICATE_KTEXT | 39 | config REPLICATE_KTEXT |
40 | bool "Kernel text replication support" | 40 | bool "Kernel text replication support" |
41 | depends on SGI_IP27 | 41 | depends on SGI_IP27 |
42 | select MAPPED_KERNEL | ||
42 | help | 43 | help |
43 | Say Y here to enable replicating the kernel text across multiple | 44 | Say Y here to enable replicating the kernel text across multiple |
44 | nodes in a NUMA cluster. This trades memory for speed. | 45 | nodes in a NUMA cluster. This trades memory for speed. |
diff --git a/arch/mips/sgi-ip27/Makefile b/arch/mips/sgi-ip27/Makefile index 686ba14e2882..a457263f4391 100644 --- a/arch/mips/sgi-ip27/Makefile +++ b/arch/mips/sgi-ip27/Makefile | |||
@@ -2,11 +2,12 @@ | |||
2 | # Makefile for the IP27 specific kernel interface routines under Linux. | 2 | # Makefile for the IP27 specific kernel interface routines under Linux. |
3 | # | 3 | # |
4 | 4 | ||
5 | obj-y := ip27-berr.o ip27-console.o ip27-irq.o ip27-init.o \ | 5 | obj-y := ip27-berr.o ip27-irq.o ip27-init.o ip27-klconfig.o ip27-klnuma.o \ |
6 | ip27-klconfig.o ip27-klnuma.o ip27-memory.o ip27-nmi.o ip27-reset.o \ | 6 | ip27-memory.o ip27-nmi.o ip27-reset.o ip27-timer.o ip27-hubio.o \ |
7 | ip27-timer.o ip27-hubio.o ip27-xtalk.o | 7 | ip27-xtalk.o |
8 | 8 | ||
9 | obj-$(CONFIG_KGDB) += ip27-dbgio.o | 9 | obj-$(CONFIG_EARLY_PRINTK) += ip27-console.o |
10 | obj-$(CONFIG_SMP) += ip27-smp.o | 10 | obj-$(CONFIG_KGDB) += ip27-dbgio.o |
11 | obj-$(CONFIG_SMP) += ip27-smp.o | ||
11 | 12 | ||
12 | EXTRA_AFLAGS := $(CFLAGS) | 13 | EXTRA_AFLAGS := $(CFLAGS) |
diff --git a/arch/mips/sgi-ip27/ip27-console.c b/arch/mips/sgi-ip27/ip27-console.c index 3e1ac299b804..14211e382374 100644 --- a/arch/mips/sgi-ip27/ip27-console.c +++ b/arch/mips/sgi-ip27/ip27-console.c | |||
@@ -46,33 +46,29 @@ void prom_putchar(char c) | |||
46 | uart->iu_thr = c; | 46 | uart->iu_thr = c; |
47 | } | 47 | } |
48 | 48 | ||
49 | char __init prom_getchar(void) | 49 | static void ioc3_console_write(struct console *con, const char *s, unsigned n) |
50 | { | 50 | { |
51 | return 0; | 51 | while (n-- && *s) { |
52 | if (*s == '\n') | ||
53 | prom_putchar('\r'); | ||
54 | prom_putchar(*s); | ||
55 | s++; | ||
56 | } | ||
52 | } | 57 | } |
53 | 58 | ||
54 | static void inline ioc3_console_probe(void) | 59 | static struct console ioc3_console = { |
55 | { | 60 | .name = "ioc3", |
56 | struct uart_port up; | 61 | .write = ioc3_console_write, |
57 | 62 | .flags = CON_PRINTBUFFER | CON_BOOT, | |
58 | /* | 63 | .index = -1 |
59 | * Register to interrupt zero because we share the interrupt with | 64 | }; |
60 | * the serial driver which we don't properly support yet. | ||
61 | */ | ||
62 | memset(&up, 0, sizeof(up)); | ||
63 | up.membase = (unsigned char *) console_uart(); | ||
64 | up.irq = 0; | ||
65 | up.uartclk = IOC3_CLK; | ||
66 | up.regshift = 0; | ||
67 | up.iotype = UPIO_MEM; | ||
68 | up.flags = IOC3_FLAGS; | ||
69 | up.line = 0; | ||
70 | 65 | ||
71 | if (early_serial_setup(&up)) | 66 | __init void ip27_setup_console(void) |
72 | printk(KERN_ERR "Early serial init of port 0 failed\n"); | 67 | { |
68 | register_console(&ioc3_console); | ||
73 | } | 69 | } |
74 | 70 | ||
75 | __init void ip27_setup_console(void) | 71 | void __init disable_early_printk(void) |
76 | { | 72 | { |
77 | ioc3_console_probe(); | 73 | unregister_console(&ioc3_console); |
78 | } | 74 | } |
diff --git a/arch/mips/sibyte/Kconfig b/arch/mips/sibyte/Kconfig index 816aee7fcd25..ec7a2cffacf0 100644 --- a/arch/mips/sibyte/Kconfig +++ b/arch/mips/sibyte/Kconfig | |||
@@ -3,6 +3,7 @@ config SIBYTE_SB1250 | |||
3 | select HW_HAS_PCI | 3 | select HW_HAS_PCI |
4 | select SIBYTE_HAS_LDT | 4 | select SIBYTE_HAS_LDT |
5 | select SIBYTE_SB1xxx_SOC | 5 | select SIBYTE_SB1xxx_SOC |
6 | select SYS_SUPPORTS_SMP | ||
6 | 7 | ||
7 | config SIBYTE_BCM1120 | 8 | config SIBYTE_BCM1120 |
8 | bool | 9 | bool |
@@ -30,11 +31,13 @@ config SIBYTE_BCM1x80 | |||
30 | bool | 31 | bool |
31 | select HW_HAS_PCI | 32 | select HW_HAS_PCI |
32 | select SIBYTE_SB1xxx_SOC | 33 | select SIBYTE_SB1xxx_SOC |
34 | select SYS_SUPPORTS_SMP | ||
33 | 35 | ||
34 | config SIBYTE_BCM1x55 | 36 | config SIBYTE_BCM1x55 |
35 | bool | 37 | bool |
36 | select HW_HAS_PCI | 38 | select HW_HAS_PCI |
37 | select SIBYTE_SB1xxx_SOC | 39 | select SIBYTE_SB1xxx_SOC |
40 | select SYS_SUPPORTS_SMP | ||
38 | 41 | ||
39 | config SIBYTE_SB1xxx_SOC | 42 | config SIBYTE_SB1xxx_SOC |
40 | bool | 43 | bool |