diff options
author | David Daney <ddaney@caviumnetworks.com> | 2009-06-26 12:01:43 -0400 |
---|---|---|
committer | Ralf Baechle <ralf@linux-mips.org> | 2009-12-16 20:56:57 -0500 |
commit | 362e696428590f7d0a5d0971a2d04b0372a761b8 (patch) | |
tree | 681064b9602b395d8a98cdd4c1c8ee4ee4771379 /arch/mips | |
parent | 7580c9c3938f45b0d889728d5533cb46b0322a85 (diff) |
MIPS: Reorder operations in stackframe.h for better scheduling
Reorder PT ops to avoid pipeline stalls.
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips')
-rw-r--r-- | arch/mips/include/asm/stackframe.h | 20 |
1 files changed, 12 insertions, 8 deletions
diff --git a/arch/mips/include/asm/stackframe.h b/arch/mips/include/asm/stackframe.h index db0fa7b5aeaf..dd7e220e087b 100644 --- a/arch/mips/include/asm/stackframe.h +++ b/arch/mips/include/asm/stackframe.h | |||
@@ -51,9 +51,6 @@ | |||
51 | LONG_S v1, PT_ACX(sp) | 51 | LONG_S v1, PT_ACX(sp) |
52 | #else | 52 | #else |
53 | mfhi v1 | 53 | mfhi v1 |
54 | LONG_S v1, PT_HI(sp) | ||
55 | mflo v1 | ||
56 | LONG_S v1, PT_LO(sp) | ||
57 | #endif | 54 | #endif |
58 | #ifdef CONFIG_32BIT | 55 | #ifdef CONFIG_32BIT |
59 | LONG_S $8, PT_R8(sp) | 56 | LONG_S $8, PT_R8(sp) |
@@ -62,10 +59,17 @@ | |||
62 | LONG_S $10, PT_R10(sp) | 59 | LONG_S $10, PT_R10(sp) |
63 | LONG_S $11, PT_R11(sp) | 60 | LONG_S $11, PT_R11(sp) |
64 | LONG_S $12, PT_R12(sp) | 61 | LONG_S $12, PT_R12(sp) |
62 | #ifndef CONFIG_CPU_HAS_SMARTMIPS | ||
63 | LONG_S v1, PT_HI(sp) | ||
64 | mflo v1 | ||
65 | #endif | ||
65 | LONG_S $13, PT_R13(sp) | 66 | LONG_S $13, PT_R13(sp) |
66 | LONG_S $14, PT_R14(sp) | 67 | LONG_S $14, PT_R14(sp) |
67 | LONG_S $15, PT_R15(sp) | 68 | LONG_S $15, PT_R15(sp) |
68 | LONG_S $24, PT_R24(sp) | 69 | LONG_S $24, PT_R24(sp) |
70 | #ifndef CONFIG_CPU_HAS_SMARTMIPS | ||
71 | LONG_S v1, PT_LO(sp) | ||
72 | #endif | ||
69 | .endm | 73 | .endm |
70 | 74 | ||
71 | .macro SAVE_STATIC | 75 | .macro SAVE_STATIC |
@@ -166,7 +170,6 @@ | |||
166 | LONG_S $0, PT_R0(sp) | 170 | LONG_S $0, PT_R0(sp) |
167 | mfc0 v1, CP0_STATUS | 171 | mfc0 v1, CP0_STATUS |
168 | LONG_S $2, PT_R2(sp) | 172 | LONG_S $2, PT_R2(sp) |
169 | LONG_S v1, PT_STATUS(sp) | ||
170 | #ifdef CONFIG_MIPS_MT_SMTC | 173 | #ifdef CONFIG_MIPS_MT_SMTC |
171 | /* | 174 | /* |
172 | * Ideally, these instructions would be shuffled in | 175 | * Ideally, these instructions would be shuffled in |
@@ -178,20 +181,21 @@ | |||
178 | LONG_S v1, PT_TCSTATUS(sp) | 181 | LONG_S v1, PT_TCSTATUS(sp) |
179 | #endif /* CONFIG_MIPS_MT_SMTC */ | 182 | #endif /* CONFIG_MIPS_MT_SMTC */ |
180 | LONG_S $4, PT_R4(sp) | 183 | LONG_S $4, PT_R4(sp) |
181 | mfc0 v1, CP0_CAUSE | ||
182 | LONG_S $5, PT_R5(sp) | 184 | LONG_S $5, PT_R5(sp) |
183 | LONG_S v1, PT_CAUSE(sp) | 185 | LONG_S v1, PT_STATUS(sp) |
186 | mfc0 v1, CP0_CAUSE | ||
184 | LONG_S $6, PT_R6(sp) | 187 | LONG_S $6, PT_R6(sp) |
185 | MFC0 v1, CP0_EPC | ||
186 | LONG_S $7, PT_R7(sp) | 188 | LONG_S $7, PT_R7(sp) |
189 | LONG_S v1, PT_CAUSE(sp) | ||
190 | MFC0 v1, CP0_EPC | ||
187 | #ifdef CONFIG_64BIT | 191 | #ifdef CONFIG_64BIT |
188 | LONG_S $8, PT_R8(sp) | 192 | LONG_S $8, PT_R8(sp) |
189 | LONG_S $9, PT_R9(sp) | 193 | LONG_S $9, PT_R9(sp) |
190 | #endif | 194 | #endif |
191 | LONG_S v1, PT_EPC(sp) | ||
192 | LONG_S $25, PT_R25(sp) | 195 | LONG_S $25, PT_R25(sp) |
193 | LONG_S $28, PT_R28(sp) | 196 | LONG_S $28, PT_R28(sp) |
194 | LONG_S $31, PT_R31(sp) | 197 | LONG_S $31, PT_R31(sp) |
198 | LONG_S v1, PT_EPC(sp) | ||
195 | ori $28, sp, _THREAD_MASK | 199 | ori $28, sp, _THREAD_MASK |
196 | xori $28, _THREAD_MASK | 200 | xori $28, _THREAD_MASK |
197 | #ifdef CONFIG_CPU_CAVIUM_OCTEON | 201 | #ifdef CONFIG_CPU_CAVIUM_OCTEON |