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authorFlorian Fainelli <florian@openwrt.org>2011-11-16 13:11:12 -0500
committerRalf Baechle <ralf@linux-mips.org>2011-12-07 17:03:04 -0500
commite1c96c8620539f056291fe42f742f331f5d291b1 (patch)
treebcb161d447e8029bf8be300254afbbc9e63af7c6 /arch/mips
parentd61fcfe2bbb27d4da18c609cf279627ae1b74151 (diff)
MIPS: BCM63xx: Remove BCM6345 hacks to read base boot address
Though BCM6345 does not technically have the same MPI register layout than the other SoCs, reading the chip-select registers is done the same way, and particularly for chip-select 0, which is the boot flash. Signed-off-by: Florian Fainelli <florian@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/3009/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips')
-rw-r--r--arch/mips/bcm63xx/boards/board_bcm963xx.c21
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h2
2 files changed, 7 insertions, 16 deletions
diff --git a/arch/mips/bcm63xx/boards/board_bcm963xx.c b/arch/mips/bcm63xx/boards/board_bcm963xx.c
index 40b223b603be..ac948c25c9f0 100644
--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
+++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
@@ -709,15 +709,9 @@ void __init board_prom_init(void)
709 char cfe_version[32]; 709 char cfe_version[32];
710 u32 val; 710 u32 val;
711 711
712 /* read base address of boot chip select (0) 712 /* read base address of boot chip select (0) */
713 * 6345 does not have MPI but boots from standard 713 val = bcm_mpi_readl(MPI_CSBASE_REG(0));
714 * MIPS Flash address */ 714 val &= MPI_CSBASE_BASE_MASK;
715 if (BCMCPU_IS_6345())
716 val = 0x1fc00000;
717 else {
718 val = bcm_mpi_readl(MPI_CSBASE_REG(0));
719 val &= MPI_CSBASE_BASE_MASK;
720 }
721 boot_addr = (u8 *)KSEG1ADDR(val); 715 boot_addr = (u8 *)KSEG1ADDR(val);
722 716
723 /* dump cfe version */ 717 /* dump cfe version */
@@ -893,12 +887,9 @@ int __init board_register_devices(void)
893 bcm63xx_dsp_register(&board.dsp); 887 bcm63xx_dsp_register(&board.dsp);
894 888
895 /* read base address of boot chip select (0) */ 889 /* read base address of boot chip select (0) */
896 if (BCMCPU_IS_6345()) 890 val = bcm_mpi_readl(MPI_CSBASE_REG(0));
897 val = 0x1fc00000; 891 val &= MPI_CSBASE_BASE_MASK;
898 else { 892
899 val = bcm_mpi_readl(MPI_CSBASE_REG(0));
900 val &= MPI_CSBASE_BASE_MASK;
901 }
902 mtd_resources[0].start = val; 893 mtd_resources[0].start = val;
903 mtd_resources[0].end = 0x1FFFFFFF; 894 mtd_resources[0].end = 0x1FFFFFFF;
904 895
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
index 23403a32c158..5b8d15bb5fe8 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
@@ -215,7 +215,7 @@ enum bcm63xx_regs_set {
215#define BCM_6345_ENETDMAS_BASE (0xfffe2a00) 215#define BCM_6345_ENETDMAS_BASE (0xfffe2a00)
216#define BCM_6345_ENETSW_BASE (0xdeadbeef) 216#define BCM_6345_ENETSW_BASE (0xdeadbeef)
217#define BCM_6345_PCMCIA_BASE (0xfffe2028) 217#define BCM_6345_PCMCIA_BASE (0xfffe2028)
218#define BCM_6345_MPI_BASE (0xdeadbeef) 218#define BCM_6345_MPI_BASE (0xfffe2000)
219#define BCM_6345_OHCI0_BASE (0xfffe2100) 219#define BCM_6345_OHCI0_BASE (0xfffe2100)
220#define BCM_6345_OHCI_PRIV_BASE (0xfffe2200) 220#define BCM_6345_OHCI_PRIV_BASE (0xfffe2200)
221#define BCM_6345_USBH_PRIV_BASE (0xdeadbeef) 221#define BCM_6345_USBH_PRIV_BASE (0xdeadbeef)