diff options
| author | Thomas Gleixner <tglx@linutronix.de> | 2011-03-23 17:08:46 -0400 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2011-03-25 13:45:15 -0400 |
| commit | 41d735e8705c5a2cffe64bc56624a4bb0519c1da (patch) | |
| tree | aa1809b37c27d9274511f8be063edf0d55638a13 /arch/mips | |
| parent | d24c1a26ca952264d92ccf6acafe38912e05b1f8 (diff) | |
MIPS: AR7: Convert to new irq_chip functions
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
To: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/2174/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips')
| -rw-r--r-- | arch/mips/ar7/irq.c | 42 |
1 files changed, 21 insertions, 21 deletions
diff --git a/arch/mips/ar7/irq.c b/arch/mips/ar7/irq.c index 4ec2642c568f..a6484b60642f 100644 --- a/arch/mips/ar7/irq.c +++ b/arch/mips/ar7/irq.c | |||
| @@ -49,51 +49,51 @@ | |||
| 49 | 49 | ||
| 50 | static int ar7_irq_base; | 50 | static int ar7_irq_base; |
| 51 | 51 | ||
| 52 | static void ar7_unmask_irq(unsigned int irq) | 52 | static void ar7_unmask_irq(struct irq_data *d) |
| 53 | { | 53 | { |
| 54 | writel(1 << ((irq - ar7_irq_base) % 32), | 54 | writel(1 << ((d->irq - ar7_irq_base) % 32), |
| 55 | REG(ESR_OFFSET(irq - ar7_irq_base))); | 55 | REG(ESR_OFFSET(d->irq - ar7_irq_base))); |
| 56 | } | 56 | } |
| 57 | 57 | ||
| 58 | static void ar7_mask_irq(unsigned int irq) | 58 | static void ar7_mask_irq(struct irq_data *d) |
| 59 | { | 59 | { |
| 60 | writel(1 << ((irq - ar7_irq_base) % 32), | 60 | writel(1 << ((d->irq - ar7_irq_base) % 32), |
| 61 | REG(ECR_OFFSET(irq - ar7_irq_base))); | 61 | REG(ECR_OFFSET(d->irq - ar7_irq_base))); |
| 62 | } | 62 | } |
| 63 | 63 | ||
| 64 | static void ar7_ack_irq(unsigned int irq) | 64 | static void ar7_ack_irq(struct irq_data *d) |
| 65 | { | 65 | { |
| 66 | writel(1 << ((irq - ar7_irq_base) % 32), | 66 | writel(1 << ((d->irq - ar7_irq_base) % 32), |
| 67 | REG(CR_OFFSET(irq - ar7_irq_base))); | 67 | REG(CR_OFFSET(d->irq - ar7_irq_base))); |
| 68 | } | 68 | } |
| 69 | 69 | ||
| 70 | static void ar7_unmask_sec_irq(unsigned int irq) | 70 | static void ar7_unmask_sec_irq(struct irq_data *d) |
| 71 | { | 71 | { |
| 72 | writel(1 << (irq - ar7_irq_base - 40), REG(SEC_ESR_OFFSET)); | 72 | writel(1 << (d->irq - ar7_irq_base - 40), REG(SEC_ESR_OFFSET)); |
| 73 | } | 73 | } |
| 74 | 74 | ||
| 75 | static void ar7_mask_sec_irq(unsigned int irq) | 75 | static void ar7_mask_sec_irq(struct irq_data *d) |
| 76 | { | 76 | { |
| 77 | writel(1 << (irq - ar7_irq_base - 40), REG(SEC_ECR_OFFSET)); | 77 | writel(1 << (d->irq - ar7_irq_base - 40), REG(SEC_ECR_OFFSET)); |
| 78 | } | 78 | } |
| 79 | 79 | ||
| 80 | static void ar7_ack_sec_irq(unsigned int irq) | 80 | static void ar7_ack_sec_irq(struct irq_data *d) |
| 81 | { | 81 | { |
| 82 | writel(1 << (irq - ar7_irq_base - 40), REG(SEC_CR_OFFSET)); | 82 | writel(1 << (d->irq - ar7_irq_base - 40), REG(SEC_CR_OFFSET)); |
| 83 | } | 83 | } |
| 84 | 84 | ||
| 85 | static struct irq_chip ar7_irq_type = { | 85 | static struct irq_chip ar7_irq_type = { |
| 86 | .name = "AR7", | 86 | .name = "AR7", |
| 87 | .unmask = ar7_unmask_irq, | 87 | .irq_unmask = ar7_unmask_irq, |
| 88 | .mask = ar7_mask_irq, | 88 | .irq_mask = ar7_mask_irq, |
| 89 | .ack = ar7_ack_irq | 89 | .irq_ack = ar7_ack_irq |
| 90 | }; | 90 | }; |
| 91 | 91 | ||
| 92 | static struct irq_chip ar7_sec_irq_type = { | 92 | static struct irq_chip ar7_sec_irq_type = { |
| 93 | .name = "AR7", | 93 | .name = "AR7", |
| 94 | .unmask = ar7_unmask_sec_irq, | 94 | .irq_unmask = ar7_unmask_sec_irq, |
| 95 | .mask = ar7_mask_sec_irq, | 95 | .irq_mask = ar7_mask_sec_irq, |
| 96 | .ack = ar7_ack_sec_irq, | 96 | .irq_ack = ar7_ack_sec_irq, |
| 97 | }; | 97 | }; |
| 98 | 98 | ||
| 99 | static struct irqaction ar7_cascade_action = { | 99 | static struct irqaction ar7_cascade_action = { |