Merge branch 'lantiq' of git://dev.phrozen.org/mips-next into mips-for-linux-next

13 files changed, 287 insertions, 220 deletions

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 386ff651ecaf..c0cbde6c1770 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -242,6 +242,8 @@ config LANTIQ
         select HAVE_MACH_CLKDEV
         select CLKDEV_LOOKUP
         select USE_OF
+        select PINCTRL
+        select PINCTRL_LANTIQ
 
 config LASAT
         bool "LASAT Networks platforms"
diff --git a/arch/mips/include/asm/mach-lantiq/falcon/falcon_irq.h b/arch/mips/include/asm/mach-lantiq/falcon/falcon_irq.h
index 318f982f04ff..c6b63a409641 100644
--- a/arch/mips/include/asm/mach-lantiq/falcon/falcon_irq.h
+++ b/arch/mips/include/asm/mach-lantiq/falcon/falcon_irq.h
@@ -20,4 +20,6 @@
 
 #define MIPS_CPU_TIMER_IRQ                      7
 
+#define MAX_IM                  5
+
 #endif /* _FALCON_IRQ__ */
diff --git a/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h b/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h
index b385252584ee..fccac3592651 100644
--- a/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h
+++ b/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h
@@ -57,6 +57,10 @@ extern __iomem void *ltq_sys1_membase;
 #define ltq_sys1_w32_mask(clear, set, reg)   \
         ltq_sys1_w32((ltq_sys1_r32(reg) & ~(clear)) | (set), reg)
 
+/* allow the gpio and pinctrl drivers to talk to eachother */
+extern int pinctrl_falcon_get_range_size(int id);
+extern void pinctrl_falcon_add_gpio_range(struct pinctrl_gpio_range *range);
+
 /*
  * to keep the irq code generic we need to define this to 0 as falcon
  * has no EIU/EBU
diff --git a/arch/mips/include/asm/mach-lantiq/gpio.h b/arch/mips/include/asm/mach-lantiq/gpio.h
index f79505b43609..9ba1caebca5f 100644
--- a/arch/mips/include/asm/mach-lantiq/gpio.h
+++ b/arch/mips/include/asm/mach-lantiq/gpio.h
@@ -1,10 +1,7 @@
 #ifndef __ASM_MIPS_MACH_LANTIQ_GPIO_H
 #define __ASM_MIPS_MACH_LANTIQ_GPIO_H
 
-static inline int gpio_to_irq(unsigned int gpio)
-{
-        return -1;
-}
+#define gpio_to_irq __gpio_to_irq
 
 #define gpio_get_value __gpio_get_value
 #define gpio_set_value __gpio_set_value
diff --git a/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h b/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h
index aa0b3b866f84..5eadfe582529 100644
--- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h
+++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h
@@ -21,4 +21,6 @@
 
 #define MIPS_CPU_TIMER_IRQ      7
 
+#define MAX_IM                  5
+
 #endif
diff --git a/arch/mips/lantiq/Kconfig b/arch/mips/lantiq/Kconfig
index 20bdf40b3efa..d84f361f1e45 100644
--- a/arch/mips/lantiq/Kconfig
+++ b/arch/mips/lantiq/Kconfig
@@ -2,6 +2,7 @@ if LANTIQ
 
 config SOC_TYPE_XWAY
         bool
+        select PINCTRL_XWAY
         default n
 
 choice
@@ -19,6 +20,7 @@ config SOC_XWAY
 
 config SOC_FALCON
         bool "FALCON"
+        select PINCTRL_FALCON
 
 endchoice
 
diff --git a/arch/mips/lantiq/falcon/prom.c b/arch/mips/lantiq/falcon/prom.c
index c1d278f05a3a..aa9497947859 100644
--- a/arch/mips/lantiq/falcon/prom.c
+++ b/arch/mips/lantiq/falcon/prom.c
@@ -8,6 +8,8 @@
  */
 
 #include <linux/kernel.h>
+#include <asm/cacheflush.h>
+#include <asm/traps.h>
 #include <asm/io.h>
 
 #include <lantiq_soc.h>
@@ -84,4 +86,7 @@ void __init ltq_soc_detect(struct ltq_soc_info *i)
                 unreachable();
                 break;
         }
+
+        board_nmi_handler_setup = ltq_soc_nmi_setup;
+        board_ejtag_handler_setup = ltq_soc_ejtag_setup;
 }
diff --git a/arch/mips/lantiq/falcon/sysctrl.c b/arch/mips/lantiq/falcon/sysctrl.c
index ba0123d13d40..2d4ced332b37 100644
--- a/arch/mips/lantiq/falcon/sysctrl.c
+++ b/arch/mips/lantiq/falcon/sysctrl.c
@@ -171,6 +171,7 @@ static inline void clkdev_add_sys(const char *dev, unsigned int module,
         clk->cl.con_id = NULL;
         clk->cl.clk = clk;
         clk->module = module;
+        clk->bits = bits;
         clk->activate = sysctl_activate;
         clk->deactivate = sysctl_deactivate;
         clk->enable = sysctl_clken;
diff --git a/arch/mips/lantiq/irq.c b/arch/mips/lantiq/irq.c
index 57c1a4e51408..f36acd1b3808 100644
--- a/arch/mips/lantiq/irq.c
+++ b/arch/mips/lantiq/irq.c
@@ -55,8 +55,8 @@
  */
 #define LTQ_ICU_EBU_IRQ         22
 
-#define ltq_icu_w32(x, y)       ltq_w32((x), ltq_icu_membase + (y))
-#define ltq_icu_r32(x)          ltq_r32(ltq_icu_membase + (x))
+#define ltq_icu_w32(m, x, y)    ltq_w32((x), ltq_icu_membase[m] + (y))
+#define ltq_icu_r32(m, x)       ltq_r32(ltq_icu_membase[m] + (x))
 
 #define ltq_eiu_w32(x, y)       ltq_w32((x), ltq_eiu_membase + (y))
 #define ltq_eiu_r32(x)          ltq_r32(ltq_eiu_membase + (x))
@@ -82,17 +82,18 @@ static unsigned short ltq_eiu_irq[MAX_EIU] = {
 };
 
 static int exin_avail;
-static void __iomem *ltq_icu_membase;
+static void __iomem *ltq_icu_membase[MAX_IM];
 static void __iomem *ltq_eiu_membase;
+static struct irq_domain *ltq_domain;
 
 void ltq_disable_irq(struct irq_data *d)
 {
         u32 ier = LTQ_ICU_IM0_IER;
         int offset = d->hwirq - MIPS_CPU_IRQ_CASCADE;
+        int im = offset / INT_NUM_IM_OFFSET;
 
-        ier += LTQ_ICU_OFFSET * (offset / INT_NUM_IM_OFFSET);
         offset %= INT_NUM_IM_OFFSET;
-        ltq_icu_w32(ltq_icu_r32(ier) & ~BIT(offset), ier);
+        ltq_icu_w32(im, ltq_icu_r32(im, ier) & ~BIT(offset), ier);
 }
 
 void ltq_mask_and_ack_irq(struct irq_data *d)
@@ -100,32 +101,31 @@ void ltq_mask_and_ack_irq(struct irq_data *d)
         u32 ier = LTQ_ICU_IM0_IER;
         u32 isr = LTQ_ICU_IM0_ISR;
         int offset = d->hwirq - MIPS_CPU_IRQ_CASCADE;
+        int im = offset / INT_NUM_IM_OFFSET;
 
-        ier += LTQ_ICU_OFFSET * (offset / INT_NUM_IM_OFFSET);
-        isr += LTQ_ICU_OFFSET * (offset / INT_NUM_IM_OFFSET);
         offset %= INT_NUM_IM_OFFSET;
-        ltq_icu_w32(ltq_icu_r32(ier) & ~BIT(offset), ier);
-        ltq_icu_w32(BIT(offset), isr);
+        ltq_icu_w32(im, ltq_icu_r32(im, ier) & ~BIT(offset), ier);
+        ltq_icu_w32(im, BIT(offset), isr);
 }
 
 static void ltq_ack_irq(struct irq_data *d)
 {
         u32 isr = LTQ_ICU_IM0_ISR;
         int offset = d->hwirq - MIPS_CPU_IRQ_CASCADE;
+        int im = offset / INT_NUM_IM_OFFSET;
 
-        isr += LTQ_ICU_OFFSET * (offset / INT_NUM_IM_OFFSET);
         offset %= INT_NUM_IM_OFFSET;
-        ltq_icu_w32(BIT(offset), isr);
+        ltq_icu_w32(im, BIT(offset), isr);
 }
 
 void ltq_enable_irq(struct irq_data *d)
 {
         u32 ier = LTQ_ICU_IM0_IER;
         int offset = d->hwirq - MIPS_CPU_IRQ_CASCADE;
+        int im = offset / INT_NUM_IM_OFFSET;
 
-        ier += LTQ_ICU_OFFSET  * (offset / INT_NUM_IM_OFFSET);
         offset %= INT_NUM_IM_OFFSET;
-        ltq_icu_w32(ltq_icu_r32(ier) | BIT(offset), ier);
+        ltq_icu_w32(im, ltq_icu_r32(im, ier) | BIT(offset), ier);
 }
 
 static unsigned int ltq_startup_eiu_irq(struct irq_data *d)
@@ -192,7 +192,7 @@ static void ltq_hw_irqdispatch(int module)
 {
         u32 irq;
 
-        irq = ltq_icu_r32(LTQ_ICU_IM0_IOSR + (module * LTQ_ICU_OFFSET));
+        irq = ltq_icu_r32(module, LTQ_ICU_IM0_IOSR);
         if (irq == 0)
                 return;
 
@@ -220,10 +220,14 @@ DEFINE_HWx_IRQDISPATCH(2)
 DEFINE_HWx_IRQDISPATCH(3)
 DEFINE_HWx_IRQDISPATCH(4)
 
+#if MIPS_CPU_TIMER_IRQ == 7
 static void ltq_hw5_irqdispatch(void)
 {
         do_IRQ(MIPS_CPU_TIMER_IRQ);
 }
+#else
+DEFINE_HWx_IRQDISPATCH(5)
+#endif
 
 #ifdef CONFIG_MIPS_MT_SMP
 void __init arch_init_ipiirq(int irq, struct irqaction *action)
@@ -271,11 +275,11 @@ asmlinkage void plat_irq_dispatch(void)
         unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
         unsigned int i;
 
-        if (pending & CAUSEF_IP7) {
+        if ((MIPS_CPU_TIMER_IRQ == 7) && (pending & CAUSEF_IP7)) {
                 do_IRQ(MIPS_CPU_TIMER_IRQ);
                 goto out;
         } else {
-                for (i = 0; i < 5; i++) {
+                for (i = 0; i < MAX_IM; i++) {
                         if (pending & (CAUSEF_IP2 << i)) {
                                 ltq_hw_irqdispatch(i);
                                 goto out;
@@ -293,6 +297,9 @@ static int icu_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
         struct irq_chip *chip = &ltq_irq_type;
         int i;
 
+        if (hw < MIPS_CPU_IRQ_CASCADE)
+                return 0;
+
         for (i = 0; i < exin_avail; i++)
                 if (hw == ltq_eiu_irq[i])
                         chip = &ltq_eiu_type;
@@ -318,19 +325,23 @@ int __init icu_of_init(struct device_node *node, struct device_node *parent)
         struct resource res;
         int i;
 
-        if (of_address_to_resource(node, 0, &res))
-                panic("Failed to get icu memory range");
+        for (i = 0; i < MAX_IM; i++) {
+                if (of_address_to_resource(node, i, &res))
+                        panic("Failed to get icu memory range");
 
-        if (request_mem_region(res.start, resource_size(&res), res.name) < 0)
-                pr_err("Failed to request icu memory");
+                if (request_mem_region(res.start, resource_size(&res),
+                                        res.name) < 0)
+                        pr_err("Failed to request icu memory");
 
-        ltq_icu_membase = ioremap_nocache(res.start, resource_size(&res));
-        if (!ltq_icu_membase)
-                panic("Failed to remap icu memory");
+                ltq_icu_membase[i] = ioremap_nocache(res.start,
+                                        resource_size(&res));
+                if (!ltq_icu_membase[i])
+                        panic("Failed to remap icu memory");
+        }
 
         /* the external interrupts are optional and xway only */
         eiu_node = of_find_compatible_node(NULL, NULL, "lantiq,eiu");
-        if (eiu_node && of_address_to_resource(eiu_node, 0, &res)) {
+        if (eiu_node && !of_address_to_resource(eiu_node, 0, &res)) {
                 /* find out how many external irq sources we have */
                 const __be32 *count = of_get_property(node,
                                                         "lantiq,count", NULL);
@@ -351,17 +362,17 @@ int __init icu_of_init(struct device_node *node, struct device_node *parent)
         }
 
         /* turn off all irqs by default */
-        for (i = 0; i < 5; i++) {
+        for (i = 0; i < MAX_IM; i++) {
                 /* make sure all irqs are turned off by default */
-                ltq_icu_w32(0, LTQ_ICU_IM0_IER + (i * LTQ_ICU_OFFSET));
+                ltq_icu_w32(i, 0, LTQ_ICU_IM0_IER);
                 /* clear all possibly pending interrupts */
-                ltq_icu_w32(~0, LTQ_ICU_IM0_ISR + (i * LTQ_ICU_OFFSET));
+                ltq_icu_w32(i, ~0, LTQ_ICU_IM0_ISR);
         }
 
         mips_cpu_irq_init();
 
-        for (i = 2; i <= 6; i++)
-                setup_irq(i, &cascade);
+        for (i = 0; i < MAX_IM; i++)
+                setup_irq(i + 2, &cascade);
 
         if (cpu_has_vint) {
                 pr_info("Setting up vectored interrupts\n");
@@ -373,7 +384,8 @@ int __init icu_of_init(struct device_node *node, struct device_node *parent)
                 set_vi_handler(7, ltq_hw5_irqdispatch);
         }
 
-        irq_domain_add_linear(node, 6 * INT_NUM_IM_OFFSET,
+        ltq_domain = irq_domain_add_linear(node,
+                (MAX_IM * INT_NUM_IM_OFFSET) + MIPS_CPU_IRQ_CASCADE,
                 &irq_domain_ops, 0);
 
 #if defined(CONFIG_MIPS_MT_SMP)
@@ -397,12 +409,20 @@ int __init icu_of_init(struct device_node *node, struct device_node *parent)
 
         /* tell oprofile which irq to use */
         cp0_perfcount_irq = LTQ_PERF_IRQ;
+
+        /*
+         * if the timer irq is not one of the mips irqs we need to
+         * create a mapping
+         */
+        if (MIPS_CPU_TIMER_IRQ != 7)
+                irq_create_mapping(ltq_domain, MIPS_CPU_TIMER_IRQ);
+
         return 0;
 }
 
 unsigned int __cpuinit get_c0_compare_int(void)
 {
-        return CP0_LEGACY_COMPARE_IRQ;
+        return MIPS_CPU_TIMER_IRQ;
 }
 
 static struct of_device_id __initdata of_irq_ids[] = {
diff --git a/arch/mips/lantiq/xway/Makefile b/arch/mips/lantiq/xway/Makefile
index dc3194f6ee42..70a58c747bd0 100644
--- a/arch/mips/lantiq/xway/Makefile
+++ b/arch/mips/lantiq/xway/Makefile
@@ -1 +1 @@
-obj-y := prom.o sysctrl.o clk.o reset.o gpio.o dma.o
+obj-y := prom.o sysctrl.o clk.o reset.o dma.o gptu.o
diff --git a/arch/mips/lantiq/xway/gpio.c b/arch/mips/lantiq/xway/gpio.c
deleted file mode 100644
index 2ab39e93d9be..000000000000
--- a/arch/mips/lantiq/xway/gpio.c
+++ /dev/null
@@ -1,183 +0,0 @@
-/*
- *  This program is free software; you can redistribute it and/or modify it
- *  under the terms of the GNU General Public License version 2 as published
- *  by the Free Software Foundation.
- *
- *  Copyright (C) 2010 John Crispin <blogic@openwrt.org>
- */
-
-#include <linux/slab.h>
-#include <linux/export.h>
-#include <linux/platform_device.h>
-#include <linux/gpio.h>
-#include <linux/ioport.h>
-#include <linux/io.h>
-
-#include <lantiq_soc.h>
-
-#define LTQ_GPIO_OUT            0x00
-#define LTQ_GPIO_IN             0x04
-#define LTQ_GPIO_DIR            0x08
-#define LTQ_GPIO_ALTSEL0        0x0C
-#define LTQ_GPIO_ALTSEL1        0x10
-#define LTQ_GPIO_OD             0x14
-
-#define PINS_PER_PORT           16
-#define MAX_PORTS               3
-
-#define ltq_gpio_getbit(m, r, p)        (!!(ltq_r32(m + r) & (1 << p)))
-#define ltq_gpio_setbit(m, r, p)        ltq_w32_mask(0, (1 << p), m + r)
-#define ltq_gpio_clearbit(m, r, p)      ltq_w32_mask((1 << p), 0, m + r)
-
-struct ltq_gpio {
-        void __iomem *membase;
-        struct gpio_chip chip;
-};
-
-static struct ltq_gpio ltq_gpio_port[MAX_PORTS];
-
-int ltq_gpio_request(unsigned int pin, unsigned int alt0,
-        unsigned int alt1, unsigned int dir, const char *name)
-{
-        int id = 0;
-
-        if (pin >= (MAX_PORTS * PINS_PER_PORT))
-                return -EINVAL;
-        if (gpio_request(pin, name)) {
-                pr_err("failed to setup lantiq gpio: %s\n", name);
-                return -EBUSY;
-        }
-        if (dir)
-                gpio_direction_output(pin, 1);
-        else
-                gpio_direction_input(pin);
-        while (pin >= PINS_PER_PORT) {
-                pin -= PINS_PER_PORT;
-                id++;
-        }
-        if (alt0)
-                ltq_gpio_setbit(ltq_gpio_port[id].membase,
-                        LTQ_GPIO_ALTSEL0, pin);
-        else
-                ltq_gpio_clearbit(ltq_gpio_port[id].membase,
-                        LTQ_GPIO_ALTSEL0, pin);
-        if (alt1)
-                ltq_gpio_setbit(ltq_gpio_port[id].membase,
-                        LTQ_GPIO_ALTSEL1, pin);
-        else
-                ltq_gpio_clearbit(ltq_gpio_port[id].membase,
-                        LTQ_GPIO_ALTSEL1, pin);
-        return 0;
-}
-EXPORT_SYMBOL(ltq_gpio_request);
-
-static void ltq_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
-{
-        struct ltq_gpio *ltq_gpio = container_of(chip, struct ltq_gpio, chip);
-
-        if (value)
-                ltq_gpio_setbit(ltq_gpio->membase, LTQ_GPIO_OUT, offset);
-        else
-                ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_OUT, offset);
-}
-
-static int ltq_gpio_get(struct gpio_chip *chip, unsigned int offset)
-{
-        struct ltq_gpio *ltq_gpio = container_of(chip, struct ltq_gpio, chip);
-
-        return ltq_gpio_getbit(ltq_gpio->membase, LTQ_GPIO_IN, offset);
-}
-
-static int ltq_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
-{
-        struct ltq_gpio *ltq_gpio = container_of(chip, struct ltq_gpio, chip);
-
-        ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_OD, offset);
-        ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_DIR, offset);
-
-        return 0;
-}
-
-static int ltq_gpio_direction_output(struct gpio_chip *chip,
-        unsigned int offset, int value)
-{
-        struct ltq_gpio *ltq_gpio = container_of(chip, struct ltq_gpio, chip);
-
-        ltq_gpio_setbit(ltq_gpio->membase, LTQ_GPIO_OD, offset);
-        ltq_gpio_setbit(ltq_gpio->membase, LTQ_GPIO_DIR, offset);
-        ltq_gpio_set(chip, offset, value);
-
-        return 0;
-}
-
-static int ltq_gpio_req(struct gpio_chip *chip, unsigned offset)
-{
-        struct ltq_gpio *ltq_gpio = container_of(chip, struct ltq_gpio, chip);
-
-        ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_ALTSEL0, offset);
-        ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_ALTSEL1, offset);
-        return 0;
-}
-
-static int ltq_gpio_probe(struct platform_device *pdev)
-{
-        struct resource *res;
-
-        if (pdev->id >= MAX_PORTS) {
-                dev_err(&pdev->dev, "invalid gpio port %d\n",
-                        pdev->id);
-                return -EINVAL;
-        }
-        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-        if (!res) {
-                dev_err(&pdev->dev, "failed to get memory for gpio port %d\n",
-                        pdev->id);
-                return -ENOENT;
-        }
-        res = devm_request_mem_region(&pdev->dev, res->start,
-                resource_size(res), dev_name(&pdev->dev));
-        if (!res) {
-                dev_err(&pdev->dev,
-                        "failed to request memory for gpio port %d\n",
-                        pdev->id);
-                return -EBUSY;
-        }
-        ltq_gpio_port[pdev->id].membase = devm_ioremap_nocache(&pdev->dev,
-                res->start, resource_size(res));
-        if (!ltq_gpio_port[pdev->id].membase) {
-                dev_err(&pdev->dev, "failed to remap memory for gpio port %d\n",
-                        pdev->id);
-                return -ENOMEM;
-        }
-        ltq_gpio_port[pdev->id].chip.label = "ltq_gpio";
-        ltq_gpio_port[pdev->id].chip.direction_input = ltq_gpio_direction_input;
-        ltq_gpio_port[pdev->id].chip.direction_output =
-                ltq_gpio_direction_output;
-        ltq_gpio_port[pdev->id].chip.get = ltq_gpio_get;
-        ltq_gpio_port[pdev->id].chip.set = ltq_gpio_set;
-        ltq_gpio_port[pdev->id].chip.request = ltq_gpio_req;
-        ltq_gpio_port[pdev->id].chip.base = PINS_PER_PORT * pdev->id;
-        ltq_gpio_port[pdev->id].chip.ngpio = PINS_PER_PORT;
-        platform_set_drvdata(pdev, &ltq_gpio_port[pdev->id]);
-        return gpiochip_add(&ltq_gpio_port[pdev->id].chip);
-}
-
-static struct platform_driver
-ltq_gpio_driver = {
-        .probe = ltq_gpio_probe,
-        .driver = {
-                .name = "ltq_gpio",
-                .owner = THIS_MODULE,
-        },
-};
-
-int __init ltq_gpio_init(void)
-{
-        int ret = platform_driver_register(&ltq_gpio_driver);
-
-        if (ret)
-                pr_info("ltq_gpio : Error registering platform driver!");
-        return ret;
-}
-
-postcore_initcall(ltq_gpio_init);
diff --git a/arch/mips/lantiq/xway/gptu.c b/arch/mips/lantiq/xway/gptu.c
new file mode 100644
index 000000000000..cbb56fc022bc
--- /dev/null
+++ b/arch/mips/lantiq/xway/gptu.c
@@ -0,0 +1,214 @@
+/*
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ *
+ *  Copyright (C) 2012 John Crispin <blogic@openwrt.org>
+ *  Copyright (C) 2012 Lantiq GmbH
+ */
+
+#include <linux/interrupt.h>
+#include <linux/ioport.h>
+#include <linux/module.h>
+#include <linux/of_platform.h>
+#include <linux/of_irq.h>
+
+#include <lantiq_soc.h>
+#include "../clk.h"
+
+/* the magic ID byte of the core */
+#define GPTU_MAGIC      0x59
+/* clock control register */
+#define GPTU_CLC        0x00
+/* id register */
+#define GPTU_ID         0x08
+/* interrupt node enable */
+#define GPTU_IRNEN      0xf4
+/* interrupt control register */
+#define GPTU_IRCR       0xf8
+/* interrupt capture register */
+#define GPTU_IRNCR      0xfc
+/* there are 3 identical blocks of 2 timers. calculate register offsets */
+#define GPTU_SHIFT(x)   (x % 2 ? 4 : 0)
+#define GPTU_BASE(x)    (((x >> 1) * 0x20) + 0x10)
+/* timer control register */
+#define GPTU_CON(x)     (GPTU_BASE(x) + GPTU_SHIFT(x) + 0x00)
+/* timer auto reload register */
+#define GPTU_RUN(x)     (GPTU_BASE(x) + GPTU_SHIFT(x) + 0x08)
+/* timer manual reload register */
+#define GPTU_RLD(x)     (GPTU_BASE(x) + GPTU_SHIFT(x) + 0x10)
+/* timer count register */
+#define GPTU_CNT(x)     (GPTU_BASE(x) + GPTU_SHIFT(x) + 0x18)
+
+/* GPTU_CON(x) */
+#define CON_CNT         BIT(2)
+#define CON_EDGE_ANY    (BIT(7) | BIT(6))
+#define CON_SYNC        BIT(8)
+#define CON_CLK_INT     BIT(10)
+
+/* GPTU_RUN(x) */
+#define RUN_SEN         BIT(0)
+#define RUN_RL          BIT(2)
+
+/* set clock to runmode */
+#define CLC_RMC         BIT(8)
+/* bring core out of suspend */
+#define CLC_SUSPEND     BIT(4)
+/* the disable bit */
+#define CLC_DISABLE     BIT(0)
+
+#define gptu_w32(x, y)  ltq_w32((x), gptu_membase + (y))
+#define gptu_r32(x)     ltq_r32(gptu_membase + (x))
+
+enum gptu_timer {
+        TIMER1A = 0,
+        TIMER1B,
+        TIMER2A,
+        TIMER2B,
+        TIMER3A,
+        TIMER3B
+};
+
+static void __iomem *gptu_membase;
+static struct resource irqres[6];
+
+static irqreturn_t timer_irq_handler(int irq, void *priv)
+{
+        int timer = irq - irqres[0].start;
+        gptu_w32(1 << timer, GPTU_IRNCR);
+        return IRQ_HANDLED;
+}
+
+static void gptu_hwinit(void)
+{
+        gptu_w32(0x00, GPTU_IRNEN);
+        gptu_w32(0xff, GPTU_IRNCR);
+        gptu_w32(CLC_RMC | CLC_SUSPEND, GPTU_CLC);
+}
+
+static void gptu_hwexit(void)
+{
+        gptu_w32(0x00, GPTU_IRNEN);
+        gptu_w32(0xff, GPTU_IRNCR);
+        gptu_w32(CLC_DISABLE, GPTU_CLC);
+}
+
+static int gptu_enable(struct clk *clk)
+{
+        int ret = request_irq(irqres[clk->bits].start, timer_irq_handler,
+                IRQF_TIMER, "gtpu", NULL);
+        if (ret) {
+                pr_err("gptu: failed to request irq\n");
+                return ret;
+        }
+
+        gptu_w32(CON_CNT | CON_EDGE_ANY | CON_SYNC | CON_CLK_INT,
+                GPTU_CON(clk->bits));
+        gptu_w32(1, GPTU_RLD(clk->bits));
+        gptu_w32(gptu_r32(GPTU_IRNEN) | BIT(clk->bits), GPTU_IRNEN);
+        gptu_w32(RUN_SEN | RUN_RL, GPTU_RUN(clk->bits));
+        return 0;
+}
+
+static void gptu_disable(struct clk *clk)
+{
+        gptu_w32(0, GPTU_RUN(clk->bits));
+        gptu_w32(0, GPTU_CON(clk->bits));
+        gptu_w32(0, GPTU_RLD(clk->bits));
+        gptu_w32(gptu_r32(GPTU_IRNEN) & ~BIT(clk->bits), GPTU_IRNEN);
+        free_irq(irqres[clk->bits].start, NULL);
+}
+
+static inline void clkdev_add_gptu(struct device *dev, const char *con,
+                                                        unsigned int timer)
+{
+        struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL);
+
+        clk->cl.dev_id = dev_name(dev);
+        clk->cl.con_id = con;
+        clk->cl.clk = clk;
+        clk->enable = gptu_enable;
+        clk->disable = gptu_disable;
+        clk->bits = timer;
+        clkdev_add(&clk->cl);
+}
+
+static int __devinit gptu_probe(struct platform_device *pdev)
+{
+        struct clk *clk;
+        struct resource *res;
+
+        if (of_irq_to_resource_table(pdev->dev.of_node, irqres, 6) != 6) {
+                dev_err(&pdev->dev, "Failed to get IRQ list\n");
+                return -EINVAL;
+        }
+
+        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        if (!res) {
+                dev_err(&pdev->dev, "Failed to get resource\n");
+                return -ENOMEM;
+        }
+
+        /* remap gptu register range */
+        gptu_membase = devm_request_and_ioremap(&pdev->dev, res);
+        if (!gptu_membase) {
+                dev_err(&pdev->dev, "Failed to remap resource\n");
+                return -ENOMEM;
+        }
+
+        /* enable our clock */
+        clk = clk_get(&pdev->dev, NULL);
+        if (IS_ERR(clk)) {
+                dev_err(&pdev->dev, "Failed to get clock\n");
+                return -ENOENT;
+        }
+        clk_enable(clk);
+
+        /* power up the core */
+        gptu_hwinit();
+
+        /* the gptu has a ID register */
+        if (((gptu_r32(GPTU_ID) >> 8) & 0xff) != GPTU_MAGIC) {
+                dev_err(&pdev->dev, "Failed to find magic\n");
+                gptu_hwexit();
+                return -ENAVAIL;
+        }
+
+        /* register the clocks */
+        clkdev_add_gptu(&pdev->dev, "timer1a", TIMER1A);
+        clkdev_add_gptu(&pdev->dev, "timer1b", TIMER1B);
+        clkdev_add_gptu(&pdev->dev, "timer2a", TIMER2A);
+        clkdev_add_gptu(&pdev->dev, "timer2b", TIMER2B);
+        clkdev_add_gptu(&pdev->dev, "timer3a", TIMER3A);
+        clkdev_add_gptu(&pdev->dev, "timer3b", TIMER3B);
+
+        dev_info(&pdev->dev, "gptu: 6 timers loaded\n");
+
+        return 0;
+}
+
+static const struct of_device_id gptu_match[] = {
+        { .compatible = "lantiq,gptu-xway" },
+        {},
+};
+MODULE_DEVICE_TABLE(of, dma_match);
+
+static struct platform_driver dma_driver = {
+        .probe = gptu_probe,
+        .driver = {
+                .name = "gptu-xway",
+                .owner = THIS_MODULE,
+                .of_match_table = gptu_match,
+        },
+};
+
+int __init gptu_init(void)
+{
+        int ret = platform_driver_register(&dma_driver);
+
+        if (ret)
+                pr_info("gptu: Error registering platform driver\n");
+        return ret;
+}
+
+arch_initcall(gptu_init);
diff --git a/arch/mips/lantiq/xway/sysctrl.c b/arch/mips/lantiq/xway/sysctrl.c
index befbb760ab76..67c3a91e54e7 100644
--- a/arch/mips/lantiq/xway/sysctrl.c
+++ b/arch/mips/lantiq/xway/sysctrl.c
@@ -145,7 +145,8 @@ static int pci_enable(struct clk *clk)
 {
         unsigned int val = ltq_cgu_r32(ifccr);
         /* set bus clock speed */
-        if (of_machine_is_compatible("lantiq,ar9")) {
+        if (of_machine_is_compatible("lantiq,ar9") ||
+                        of_machine_is_compatible("lantiq,vr9")) {
                 val &= ~0x1f00000;
                 if (clk->rate == CLOCK_33M)
                         val |= 0xe00000;