diff options
| author | Ralf Baechle <ralf@linux-mips.org> | 2010-02-27 06:53:31 -0500 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2010-02-27 06:53:31 -0500 |
| commit | f2c194a00516f8ea4340975c25276fd0dfd47c31 (patch) | |
| tree | 6c8b36bc9280b8a9a7286db82e45aef5ece9eaa6 /arch/mips | |
| parent | 4a41abe5960b6a4d496aab94264beee06bc0ab7e (diff) | |
MIPS: GT641xx: Convert IRQ controller lock to raw spinlock.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips')
| -rw-r--r-- | arch/mips/kernel/irq-gt641xx.c | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/arch/mips/kernel/irq-gt641xx.c b/arch/mips/kernel/irq-gt641xx.c index ebcc5f7ad9c2..42ef81461bfc 100644 --- a/arch/mips/kernel/irq-gt641xx.c +++ b/arch/mips/kernel/irq-gt641xx.c | |||
| @@ -27,18 +27,18 @@ | |||
| 27 | 27 | ||
| 28 | #define GT641XX_IRQ_TO_BIT(irq) (1U << (irq - GT641XX_IRQ_BASE)) | 28 | #define GT641XX_IRQ_TO_BIT(irq) (1U << (irq - GT641XX_IRQ_BASE)) |
| 29 | 29 | ||
| 30 | static DEFINE_SPINLOCK(gt641xx_irq_lock); | 30 | static DEFINE_RAW_SPINLOCK(gt641xx_irq_lock); |
| 31 | 31 | ||
| 32 | static void ack_gt641xx_irq(unsigned int irq) | 32 | static void ack_gt641xx_irq(unsigned int irq) |
| 33 | { | 33 | { |
| 34 | unsigned long flags; | 34 | unsigned long flags; |
| 35 | u32 cause; | 35 | u32 cause; |
| 36 | 36 | ||
| 37 | spin_lock_irqsave(>641xx_irq_lock, flags); | 37 | raw_spin_lock_irqsave(>641xx_irq_lock, flags); |
| 38 | cause = GT_READ(GT_INTRCAUSE_OFS); | 38 | cause = GT_READ(GT_INTRCAUSE_OFS); |
| 39 | cause &= ~GT641XX_IRQ_TO_BIT(irq); | 39 | cause &= ~GT641XX_IRQ_TO_BIT(irq); |
| 40 | GT_WRITE(GT_INTRCAUSE_OFS, cause); | 40 | GT_WRITE(GT_INTRCAUSE_OFS, cause); |
| 41 | spin_unlock_irqrestore(>641xx_irq_lock, flags); | 41 | raw_spin_unlock_irqrestore(>641xx_irq_lock, flags); |
| 42 | } | 42 | } |
| 43 | 43 | ||
| 44 | static void mask_gt641xx_irq(unsigned int irq) | 44 | static void mask_gt641xx_irq(unsigned int irq) |
| @@ -46,11 +46,11 @@ static void mask_gt641xx_irq(unsigned int irq) | |||
| 46 | unsigned long flags; | 46 | unsigned long flags; |
| 47 | u32 mask; | 47 | u32 mask; |
| 48 | 48 | ||
| 49 | spin_lock_irqsave(>641xx_irq_lock, flags); | 49 | raw_spin_lock_irqsave(>641xx_irq_lock, flags); |
| 50 | mask = GT_READ(GT_INTRMASK_OFS); | 50 | mask = GT_READ(GT_INTRMASK_OFS); |
| 51 | mask &= ~GT641XX_IRQ_TO_BIT(irq); | 51 | mask &= ~GT641XX_IRQ_TO_BIT(irq); |
| 52 | GT_WRITE(GT_INTRMASK_OFS, mask); | 52 | GT_WRITE(GT_INTRMASK_OFS, mask); |
| 53 | spin_unlock_irqrestore(>641xx_irq_lock, flags); | 53 | raw_spin_unlock_irqrestore(>641xx_irq_lock, flags); |
| 54 | } | 54 | } |
| 55 | 55 | ||
| 56 | static void mask_ack_gt641xx_irq(unsigned int irq) | 56 | static void mask_ack_gt641xx_irq(unsigned int irq) |
| @@ -58,7 +58,7 @@ static void mask_ack_gt641xx_irq(unsigned int irq) | |||
| 58 | unsigned long flags; | 58 | unsigned long flags; |
| 59 | u32 cause, mask; | 59 | u32 cause, mask; |
| 60 | 60 | ||
| 61 | spin_lock_irqsave(>641xx_irq_lock, flags); | 61 | raw_spin_lock_irqsave(>641xx_irq_lock, flags); |
| 62 | mask = GT_READ(GT_INTRMASK_OFS); | 62 | mask = GT_READ(GT_INTRMASK_OFS); |
| 63 | mask &= ~GT641XX_IRQ_TO_BIT(irq); | 63 | mask &= ~GT641XX_IRQ_TO_BIT(irq); |
| 64 | GT_WRITE(GT_INTRMASK_OFS, mask); | 64 | GT_WRITE(GT_INTRMASK_OFS, mask); |
| @@ -66,7 +66,7 @@ static void mask_ack_gt641xx_irq(unsigned int irq) | |||
| 66 | cause = GT_READ(GT_INTRCAUSE_OFS); | 66 | cause = GT_READ(GT_INTRCAUSE_OFS); |
| 67 | cause &= ~GT641XX_IRQ_TO_BIT(irq); | 67 | cause &= ~GT641XX_IRQ_TO_BIT(irq); |
| 68 | GT_WRITE(GT_INTRCAUSE_OFS, cause); | 68 | GT_WRITE(GT_INTRCAUSE_OFS, cause); |
| 69 | spin_unlock_irqrestore(>641xx_irq_lock, flags); | 69 | raw_spin_unlock_irqrestore(>641xx_irq_lock, flags); |
| 70 | } | 70 | } |
| 71 | 71 | ||
| 72 | static void unmask_gt641xx_irq(unsigned int irq) | 72 | static void unmask_gt641xx_irq(unsigned int irq) |
| @@ -74,11 +74,11 @@ static void unmask_gt641xx_irq(unsigned int irq) | |||
| 74 | unsigned long flags; | 74 | unsigned long flags; |
| 75 | u32 mask; | 75 | u32 mask; |
| 76 | 76 | ||
| 77 | spin_lock_irqsave(>641xx_irq_lock, flags); | 77 | raw_spin_lock_irqsave(>641xx_irq_lock, flags); |
| 78 | mask = GT_READ(GT_INTRMASK_OFS); | 78 | mask = GT_READ(GT_INTRMASK_OFS); |
| 79 | mask |= GT641XX_IRQ_TO_BIT(irq); | 79 | mask |= GT641XX_IRQ_TO_BIT(irq); |
| 80 | GT_WRITE(GT_INTRMASK_OFS, mask); | 80 | GT_WRITE(GT_INTRMASK_OFS, mask); |
| 81 | spin_unlock_irqrestore(>641xx_irq_lock, flags); | 81 | raw_spin_unlock_irqrestore(>641xx_irq_lock, flags); |
| 82 | } | 82 | } |
| 83 | 83 | ||
| 84 | static struct irq_chip gt641xx_irq_chip = { | 84 | static struct irq_chip gt641xx_irq_chip = { |