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authorShane McDonald <mcdonald.shane@gmail.com>2010-05-07 02:02:09 -0400
committerRalf Baechle <ralf@linux-mips.org>2010-05-21 16:31:17 -0400
commit3f135530448104c01153fe048024366203196798 (patch)
treeb7b9b5bec5cba35276930bfa5f3022ea81785649 /arch/mips
parentc197da9163a42e6faeb051f331868b9245836eef (diff)
MIPS: Coding style cleanups of access of FCSR rounding mode bits
Replaces references to the magic number 0x3 with constants and macros indicating the real purpose of those bits. They are the rounding mode bits of the FCSR register. Signed-off-by: Shane McDonald <mcdonald.shane@gmail.com> To: anemo@mba.ocn.ne.jp To: kevink@paralogos.com To: linux-mips@linux-mips.org To: sshtylyov@mvista.com Patchwork: http://patchwork.linux-mips.org/patch/1206/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips')
-rw-r--r--arch/mips/math-emu/cp1emu.c11
1 files changed, 6 insertions, 5 deletions
diff --git a/arch/mips/math-emu/cp1emu.c b/arch/mips/math-emu/cp1emu.c
index f2338d1c0b48..47842b7d26ae 100644
--- a/arch/mips/math-emu/cp1emu.c
+++ b/arch/mips/math-emu/cp1emu.c
@@ -354,7 +354,8 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx)
354 354
355 if (MIPSInst_RD(ir) == FPCREG_CSR) { 355 if (MIPSInst_RD(ir) == FPCREG_CSR) {
356 value = ctx->fcr31; 356 value = ctx->fcr31;
357 value = (value & ~0x3) | mips_rm[value & 0x3]; 357 value = (value & ~FPU_CSR_RM) |
358 mips_rm[modeindex(value)];
358#ifdef CSRTRACE 359#ifdef CSRTRACE
359 printk("%p gpr[%d]<-csr=%08x\n", 360 printk("%p gpr[%d]<-csr=%08x\n",
360 (void *) (xcp->cp0_epc), 361 (void *) (xcp->cp0_epc),
@@ -907,7 +908,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
907 ieee754sp fs; 908 ieee754sp fs;
908 909
909 SPFROMREG(fs, MIPSInst_FS(ir)); 910 SPFROMREG(fs, MIPSInst_FS(ir));
910 ieee754_csr.rm = ieee_rm[MIPSInst_FUNC(ir) & 0x3]; 911 ieee754_csr.rm = ieee_rm[modeindex(MIPSInst_FUNC(ir))];
911 rv.w = ieee754sp_tint(fs); 912 rv.w = ieee754sp_tint(fs);
912 ieee754_csr.rm = oldrm; 913 ieee754_csr.rm = oldrm;
913 rfmt = w_fmt; 914 rfmt = w_fmt;
@@ -933,7 +934,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
933 ieee754sp fs; 934 ieee754sp fs;
934 935
935 SPFROMREG(fs, MIPSInst_FS(ir)); 936 SPFROMREG(fs, MIPSInst_FS(ir));
936 ieee754_csr.rm = ieee_rm[MIPSInst_FUNC(ir) & 0x3]; 937 ieee754_csr.rm = ieee_rm[modeindex(MIPSInst_FUNC(ir))];
937 rv.l = ieee754sp_tlong(fs); 938 rv.l = ieee754sp_tlong(fs);
938 ieee754_csr.rm = oldrm; 939 ieee754_csr.rm = oldrm;
939 rfmt = l_fmt; 940 rfmt = l_fmt;
@@ -1081,7 +1082,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
1081 ieee754dp fs; 1082 ieee754dp fs;
1082 1083
1083 DPFROMREG(fs, MIPSInst_FS(ir)); 1084 DPFROMREG(fs, MIPSInst_FS(ir));
1084 ieee754_csr.rm = ieee_rm[MIPSInst_FUNC(ir) & 0x3]; 1085 ieee754_csr.rm = ieee_rm[modeindex(MIPSInst_FUNC(ir))];
1085 rv.w = ieee754dp_tint(fs); 1086 rv.w = ieee754dp_tint(fs);
1086 ieee754_csr.rm = oldrm; 1087 ieee754_csr.rm = oldrm;
1087 rfmt = w_fmt; 1088 rfmt = w_fmt;
@@ -1107,7 +1108,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
1107 ieee754dp fs; 1108 ieee754dp fs;
1108 1109
1109 DPFROMREG(fs, MIPSInst_FS(ir)); 1110 DPFROMREG(fs, MIPSInst_FS(ir));
1110 ieee754_csr.rm = ieee_rm[MIPSInst_FUNC(ir) & 0x3]; 1111 ieee754_csr.rm = ieee_rm[modeindex(MIPSInst_FUNC(ir))];
1111 rv.l = ieee754dp_tlong(fs); 1112 rv.l = ieee754dp_tlong(fs);
1112 ieee754_csr.rm = oldrm; 1113 ieee754_csr.rm = oldrm;
1113 rfmt = l_fmt; 1114 rfmt = l_fmt;