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authorAtsushi Nemoto <anemo@mba.ocn.ne.jp>2008-07-23 11:25:15 -0400
committerRalf Baechle <ralf@linux-mips.org>2008-07-30 16:54:38 -0400
commit07517529225ae4ce770271f83d8cd1004733a01d (patch)
treeb033a54238d5fc65faa81c6cb40cba90a7984a52 /arch/mips
parent47a5c976486e407fc0d0bc8fa165132b6f9bec26 (diff)
[MIPS] TXx9: Add some pci options
Add pci options for backplane type, clock selection, error handling, timeout values. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips')
-rw-r--r--arch/mips/pci/ops-tx4927.c22
-rw-r--r--arch/mips/txx9/generic/pci.c36
-rw-r--r--arch/mips/txx9/generic/setup.c4
-rw-r--r--arch/mips/txx9/rbtx4927/setup.c1
-rw-r--r--arch/mips/txx9/rbtx4938/setup.c1
5 files changed, 64 insertions, 0 deletions
diff --git a/arch/mips/pci/ops-tx4927.c b/arch/mips/pci/ops-tx4927.c
index 6d844094ef5d..038e311b069d 100644
--- a/arch/mips/pci/ops-tx4927.c
+++ b/arch/mips/pci/ops-tx4927.c
@@ -194,6 +194,28 @@ static struct {
194 .gbwc = 0xfe0, /* 4064 GBUSCLK for CCFG.GTOT=0b11 */ 194 .gbwc = 0xfe0, /* 4064 GBUSCLK for CCFG.GTOT=0b11 */
195}; 195};
196 196
197char *__devinit tx4927_pcibios_setup(char *str)
198{
199 unsigned long val;
200
201 if (!strncmp(str, "trdyto=", 7)) {
202 if (strict_strtoul(str + 7, 0, &val) == 0)
203 tx4927_pci_opts.trdyto = val;
204 return NULL;
205 }
206 if (!strncmp(str, "retryto=", 8)) {
207 if (strict_strtoul(str + 8, 0, &val) == 0)
208 tx4927_pci_opts.retryto = val;
209 return NULL;
210 }
211 if (!strncmp(str, "gbwc=", 5)) {
212 if (strict_strtoul(str + 5, 0, &val) == 0)
213 tx4927_pci_opts.gbwc = val;
214 return NULL;
215 }
216 return str;
217}
218
197void __init tx4927_pcic_setup(struct tx4927_pcic_reg __iomem *pcicptr, 219void __init tx4927_pcic_setup(struct tx4927_pcic_reg __iomem *pcicptr,
198 struct pci_controller *channel, int extarb) 220 struct pci_controller *channel, int extarb)
199{ 221{
diff --git a/arch/mips/txx9/generic/pci.c b/arch/mips/txx9/generic/pci.c
index 0b92d8c13208..7b637a7c0e66 100644
--- a/arch/mips/txx9/generic/pci.c
+++ b/arch/mips/txx9/generic/pci.c
@@ -386,3 +386,39 @@ int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
386{ 386{
387 return txx9_board_vec->pci_map_irq(dev, slot, pin); 387 return txx9_board_vec->pci_map_irq(dev, slot, pin);
388} 388}
389
390char * (*txx9_board_pcibios_setup)(char *str) __devinitdata;
391
392char *__devinit txx9_pcibios_setup(char *str)
393{
394 if (txx9_board_pcibios_setup && !txx9_board_pcibios_setup(str))
395 return NULL;
396 if (!strcmp(str, "picmg")) {
397 /* PICMG compliant backplane (TOSHIBA JMB-PICMG-ATX
398 (5V or 3.3V), JMB-PICMG-L2 (5V only), etc.) */
399 txx9_pci_option |= TXX9_PCI_OPT_PICMG;
400 return NULL;
401 } else if (!strcmp(str, "nopicmg")) {
402 /* non-PICMG compliant backplane (TOSHIBA
403 RBHBK4100,RBHBK4200, Interface PCM-PCM05, etc.) */
404 txx9_pci_option &= ~TXX9_PCI_OPT_PICMG;
405 return NULL;
406 } else if (!strncmp(str, "clk=", 4)) {
407 char *val = str + 4;
408 txx9_pci_option &= ~TXX9_PCI_OPT_CLK_MASK;
409 if (strcmp(val, "33") == 0)
410 txx9_pci_option |= TXX9_PCI_OPT_CLK_33;
411 else if (strcmp(val, "66") == 0)
412 txx9_pci_option |= TXX9_PCI_OPT_CLK_66;
413 else /* "auto" */
414 txx9_pci_option |= TXX9_PCI_OPT_CLK_AUTO;
415 return NULL;
416 } else if (!strncmp(str, "err=", 4)) {
417 if (!strcmp(str + 4, "panic"))
418 txx9_pci_err_action = TXX9_PCI_ERR_PANIC;
419 else if (!strcmp(str + 4, "ignore"))
420 txx9_pci_err_action = TXX9_PCI_ERR_IGNORE;
421 return NULL;
422 }
423 return str;
424}
diff --git a/arch/mips/txx9/generic/setup.c b/arch/mips/txx9/generic/setup.c
index 8c60c78b9a9e..4fbd7baa7037 100644
--- a/arch/mips/txx9/generic/setup.c
+++ b/arch/mips/txx9/generic/setup.c
@@ -23,6 +23,7 @@
23#include <asm/bootinfo.h> 23#include <asm/bootinfo.h>
24#include <asm/time.h> 24#include <asm/time.h>
25#include <asm/txx9/generic.h> 25#include <asm/txx9/generic.h>
26#include <asm/txx9/pci.h>
26#ifdef CONFIG_CPU_TX49XX 27#ifdef CONFIG_CPU_TX49XX
27#include <asm/txx9/tx4938.h> 28#include <asm/txx9/tx4938.h>
28#endif 29#endif
@@ -194,6 +195,9 @@ void __init plat_mem_setup(void)
194 ioport_resource.end = ~0UL; /* no limit */ 195 ioport_resource.end = ~0UL; /* no limit */
195 iomem_resource.start = 0; 196 iomem_resource.start = 0;
196 iomem_resource.end = ~0UL; /* no limit */ 197 iomem_resource.end = ~0UL; /* no limit */
198#ifdef CONFIG_PCI
199 pcibios_plat_setup = txx9_pcibios_setup;
200#endif
197 txx9_board_vec->mem_setup(); 201 txx9_board_vec->mem_setup();
198} 202}
199 203
diff --git a/arch/mips/txx9/rbtx4927/setup.c b/arch/mips/txx9/rbtx4927/setup.c
index 3da20ea3e55c..88c05ccee3b2 100644
--- a/arch/mips/txx9/rbtx4927/setup.c
+++ b/arch/mips/txx9/rbtx4927/setup.c
@@ -238,6 +238,7 @@ static void __init rbtx4927_mem_setup(void)
238 txx9_alloc_pci_controller(&txx9_primary_pcic, 238 txx9_alloc_pci_controller(&txx9_primary_pcic,
239 RBTX4927_PCIMEM, RBTX4927_PCIMEM_SIZE, 239 RBTX4927_PCIMEM, RBTX4927_PCIMEM_SIZE,
240 RBTX4927_PCIIO, RBTX4927_PCIIO_SIZE); 240 RBTX4927_PCIIO, RBTX4927_PCIIO_SIZE);
241 txx9_board_pcibios_setup = tx4927_pcibios_setup;
241#else 242#else
242 set_io_port_base(KSEG1 + RBTX4927_ISA_IO_OFFSET); 243 set_io_port_base(KSEG1 + RBTX4927_ISA_IO_OFFSET);
243#endif 244#endif
diff --git a/arch/mips/txx9/rbtx4938/setup.c b/arch/mips/txx9/rbtx4938/setup.c
index 6c2b99bb8af6..fc9034db526e 100644
--- a/arch/mips/txx9/rbtx4938/setup.c
+++ b/arch/mips/txx9/rbtx4938/setup.c
@@ -193,6 +193,7 @@ static void __init rbtx4938_mem_setup(void)
193 193
194#ifdef CONFIG_PCI 194#ifdef CONFIG_PCI
195 txx9_alloc_pci_controller(&txx9_primary_pcic, 0, 0, 0, 0); 195 txx9_alloc_pci_controller(&txx9_primary_pcic, 0, 0, 0, 0);
196 txx9_board_pcibios_setup = tx4927_pcibios_setup;
196#else 197#else
197 set_io_port_base(RBTX4938_ETHER_BASE); 198 set_io_port_base(RBTX4938_ETHER_BASE);
198#endif 199#endif