aboutsummaryrefslogtreecommitdiffstats
path: root/arch/mips
diff options
context:
space:
mode:
authorLinus Torvalds <torvalds@linux-foundation.org>2014-01-30 20:20:32 -0500
committerLinus Torvalds <torvalds@linux-foundation.org>2014-01-30 20:20:32 -0500
commitcdfc83075fb76369a31e6c187d0cebcab9f8b9c8 (patch)
tree33d1cdca3e2cb610451ed30943189f55652bac4c /arch/mips
parent04a24ae45d018e177db7e4ae2d03a70f79149782 (diff)
parentb26a21c1eacdb7daf22a304fa857413df2650cfe (diff)
Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus
Pull MIPS updates from Ralf Baechle: "The most notable new addition inside this pull request is the support for MIPS's latest and greatest core called "inter/proAptiv". The patch series describes this core as follows. "The interAptiv is a power-efficient multi-core microprocessor for use in system-on-chip (SoC) applications. The interAptiv combines a multi-threading pipeline with a coherence manager to deliver improved computational throughput and power efficiency. The interAptiv can contain one to four MIPS32R3 interAptiv cores, system level coherence manager with L2 cache, optional coherent I/O port, and optional floating point unit." The platform specific patches touch all 3 Broadcom families. It adds support for the new Broadcom/Netlogix XLP9xx Soc, building a common BCM63XX SMP kernel for all BCM63XX SoCs regardless of core type/count and full gpio button/led descriptions for BCM47xx. The rest of the series are cleanups and bug fixes that are MIPS generic and consist largely of changes that Imgtec/MIPS had published in their linux-mti-3.10.git stable tree. Random other cleanups and patches preparing code to be merged in 3.15" * 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (139 commits) mips: select ARCH_MIGHT_HAVE_PC_SERIO mips: delete non-required instances of include <linux/init.h> MIPS: KVM: remove shadow_tlb code MIPS: KVM: use common EHINV aware UNIQUE_ENTRYHI mips/ide: flush dcache also if icache does not snoop dcache MIPS: BCM47XX: fix position of cpu_wait disabling MIPS: BCM63XX: select correct MIPS_L1_CACHE_SHIFT value MIPS: update MIPS_L1_CACHE_SHIFT based on MIPS_L1_CACHE_SHIFT_<N> MIPS: introduce MIPS_L1_CACHE_SHIFT_<N> MIPS: ZBOOT: gather string functions into string.c arch/mips/pci: don't check resource with devm_ioremap_resource arch/mips/lantiq/xway: don't check resource with devm_ioremap_resource bcma: gpio: don't cast u32 to unsigned long ssb: gpio: add own IRQ domain MIPS: BCM47XX: fix sparse warnings in board.c MIPS: BCM47XX: add board detection for Linksys WRT54GS V1 MIPS: BCM47XX: fix detection for some boards MIPS: BCM47XX: Enable buttons support on SSB MIPS: BCM47XX: Convert WNDR4500 to new syntax MIPS: BCM47XX: Use "timer" trigger for status LEDs ...
Diffstat (limited to 'arch/mips')
-rw-r--r--arch/mips/Kconfig221
-rw-r--r--arch/mips/Makefile2
-rw-r--r--arch/mips/alchemy/common/power.c1
-rw-r--r--arch/mips/ar7/time.c1
-rw-r--r--arch/mips/ath79/common.h1
-rw-r--r--arch/mips/bcm47xx/Kconfig4
-rw-r--r--arch/mips/bcm47xx/Makefile3
-rw-r--r--arch/mips/bcm47xx/bcm47xx_private.h12
-rw-r--r--arch/mips/bcm47xx/board.c34
-rw-r--r--arch/mips/bcm47xx/buttons.c531
-rw-r--r--arch/mips/bcm47xx/irq.c25
-rw-r--r--arch/mips/bcm47xx/leds.c542
-rw-r--r--arch/mips/bcm47xx/nvram.c3
-rw-r--r--arch/mips/bcm47xx/prom.c127
-rw-r--r--arch/mips/bcm47xx/serial.c6
-rw-r--r--arch/mips/bcm47xx/setup.c35
-rw-r--r--arch/mips/bcm47xx/sprom.c18
-rw-r--r--arch/mips/bcm47xx/wgt634u.c174
-rw-r--r--arch/mips/bcm63xx/Kconfig8
-rw-r--r--arch/mips/bcm63xx/Makefile4
-rw-r--r--arch/mips/bcm63xx/boards/board_bcm963xx.c3
-rw-r--r--arch/mips/bcm63xx/clk.c42
-rw-r--r--arch/mips/bcm63xx/cpu.c6
-rw-r--r--arch/mips/bcm63xx/dev-hsspi.c47
-rw-r--r--arch/mips/bcm63xx/early_printk.c3
-rw-r--r--arch/mips/bcm63xx/prom.c14
-rw-r--r--arch/mips/boot/compressed/Makefile4
-rw-r--r--arch/mips/boot/compressed/dbg.c1
-rw-r--r--arch/mips/boot/compressed/decompress.c22
-rw-r--r--arch/mips/boot/compressed/string.c28
-rw-r--r--arch/mips/boot/compressed/uart-16550.c5
-rw-r--r--arch/mips/cavium-octeon/executive/cvmx-cmd-queue.c1
-rw-r--r--arch/mips/cavium-octeon/executive/cvmx-helper-board.c27
-rw-r--r--arch/mips/cavium-octeon/executive/cvmx-helper-util.c4
-rw-r--r--arch/mips/cavium-octeon/executive/cvmx-helper.c10
-rw-r--r--arch/mips/cavium-octeon/executive/cvmx-pko.c3
-rw-r--r--arch/mips/cavium-octeon/executive/cvmx-spi.c1
-rw-r--r--arch/mips/cavium-octeon/octeon-platform.c38
-rw-r--r--arch/mips/cavium-octeon/octeon_3xxx.dts19
-rw-r--r--arch/mips/cavium-octeon/smp.c1
-rw-r--r--arch/mips/configs/ar7_defconfig1
-rw-r--r--arch/mips/configs/bcm47xx_defconfig623
-rw-r--r--arch/mips/configs/bcm63xx_defconfig1
-rw-r--r--arch/mips/configs/cobalt_defconfig1
-rw-r--r--arch/mips/configs/gpr_defconfig1
-rw-r--r--arch/mips/configs/jmr3927_defconfig1
-rw-r--r--arch/mips/configs/lasat_defconfig1
-rw-r--r--arch/mips/configs/maltasmvp_defconfig3
-rw-r--r--arch/mips/configs/markeins_defconfig1
-rw-r--r--arch/mips/configs/mtx1_defconfig1
-rw-r--r--arch/mips/configs/pnx8335_stb225_defconfig1
-rw-r--r--arch/mips/configs/qi_lb60_defconfig188
-rw-r--r--arch/mips/configs/rb532_defconfig1
-rw-r--r--arch/mips/configs/rbtx49xx_defconfig1
-rw-r--r--arch/mips/fw/arc/file.c1
-rw-r--r--arch/mips/include/asm/amon.h15
-rw-r--r--arch/mips/include/asm/asmmacro-32.h42
-rw-r--r--arch/mips/include/asm/asmmacro-64.h96
-rw-r--r--arch/mips/include/asm/asmmacro.h107
-rw-r--r--arch/mips/include/asm/bmips.h29
-rw-r--r--arch/mips/include/asm/cpu-features.h7
-rw-r--r--arch/mips/include/asm/cpu-info.h3
-rw-r--r--arch/mips/include/asm/cpu-type.h15
-rw-r--r--arch/mips/include/asm/cpu.h12
-rw-r--r--arch/mips/include/asm/dma-coherence.h9
-rw-r--r--arch/mips/include/asm/elf.h31
-rw-r--r--arch/mips/include/asm/fpu.h104
-rw-r--r--arch/mips/include/asm/highmem.h1
-rw-r--r--arch/mips/include/asm/kvm_host.h7
-rw-r--r--arch/mips/include/asm/mach-ath79/ar71xx_regs.h1
-rw-r--r--arch/mips/include/asm/mach-bcm47xx/bcm47xx.h2
-rw-r--r--arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h1
-rw-r--r--arch/mips/include/asm/mach-bcm47xx/cpu-feature-overrides.h82
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h18
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_hsspi.h8
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h120
-rw-r--r--arch/mips/include/asm/mach-generic/dma-coherence.h4
-rw-r--r--arch/mips/include/asm/mach-generic/floppy.h1
-rw-r--r--arch/mips/include/asm/mach-generic/ide.h6
-rw-r--r--arch/mips/include/asm/mach-jazz/floppy.h1
-rw-r--r--arch/mips/include/asm/mach-jz4740/platform.h1
-rw-r--r--arch/mips/include/asm/mach-netlogic/irq.h3
-rw-r--r--arch/mips/include/asm/mach-netlogic/multi-node.h33
-rw-r--r--arch/mips/include/asm/mach-netlogic/topology.h20
-rw-r--r--arch/mips/include/asm/mips-boards/piix4.h7
-rw-r--r--arch/mips/include/asm/mipsregs.h85
-rw-r--r--arch/mips/include/asm/netlogic/common.h24
-rw-r--r--arch/mips/include/asm/netlogic/mips-extns.h7
-rw-r--r--arch/mips/include/asm/netlogic/xlp-hal/bridge.h69
-rw-r--r--arch/mips/include/asm/netlogic/xlp-hal/iomap.h48
-rw-r--r--arch/mips/include/asm/netlogic/xlp-hal/pcibus.h41
-rw-r--r--arch/mips/include/asm/netlogic/xlp-hal/pic.h77
-rw-r--r--arch/mips/include/asm/netlogic/xlp-hal/sys.h18
-rw-r--r--arch/mips/include/asm/netlogic/xlp-hal/uart.h3
-rw-r--r--arch/mips/include/asm/netlogic/xlp-hal/xlp.h38
-rw-r--r--arch/mips/include/asm/netlogic/xlr/xlr.h5
-rw-r--r--arch/mips/include/asm/octeon/cvmx-helper-board.h9
-rw-r--r--arch/mips/include/asm/page.h25
-rw-r--r--arch/mips/include/asm/rtlx.h49
-rw-r--r--arch/mips/include/asm/switch_to.h16
-rw-r--r--arch/mips/include/asm/syscall.h2
-rw-r--r--arch/mips/include/asm/thread_info.h4
-rw-r--r--arch/mips/include/asm/tlb.h4
-rw-r--r--arch/mips/include/asm/vpe.h131
-rw-r--r--arch/mips/include/uapi/asm/inst.h7
-rw-r--r--arch/mips/jz4740/board-qi_lb60.c1
-rw-r--r--arch/mips/jz4740/platform.c41
-rw-r--r--arch/mips/kernel/Makefile5
-rw-r--r--arch/mips/kernel/binfmt_elfo32.c14
-rw-r--r--arch/mips/kernel/bmips_vec.S56
-rw-r--r--arch/mips/kernel/cpu-probe.c103
-rw-r--r--arch/mips/kernel/crash.c1
-rw-r--r--arch/mips/kernel/genex.S1
-rw-r--r--arch/mips/kernel/idle.c2
-rw-r--r--arch/mips/kernel/proc.c48
-rw-r--r--arch/mips/kernel/process.c6
-rw-r--r--arch/mips/kernel/ptrace.c60
-rw-r--r--arch/mips/kernel/ptrace32.c53
-rw-r--r--arch/mips/kernel/r4k_fpu.S74
-rw-r--r--arch/mips/kernel/r4k_switch.S45
-rw-r--r--arch/mips/kernel/rtlx-cmp.c116
-rw-r--r--arch/mips/kernel/rtlx-mt.c148
-rw-r--r--arch/mips/kernel/rtlx.c273
-rw-r--r--arch/mips/kernel/segment.c110
-rw-r--r--arch/mips/kernel/signal.c10
-rw-r--r--arch/mips/kernel/signal32.c10
-rw-r--r--arch/mips/kernel/smp-bmips.c312
-rw-r--r--arch/mips/kernel/smp-cmp.c3
-rw-r--r--arch/mips/kernel/smp-mt.c28
-rw-r--r--arch/mips/kernel/spram.c3
-rw-r--r--arch/mips/kernel/sync-r4k.c1
-rw-r--r--arch/mips/kernel/traps.c71
-rw-r--r--arch/mips/kernel/vpe-cmp.c180
-rw-r--r--arch/mips/kernel/vpe-mt.c523
-rw-r--r--arch/mips/kernel/vpe.c882
-rw-r--r--arch/mips/kvm/kvm_mips.c1
-rw-r--r--arch/mips/kvm/kvm_tlb.c135
-rw-r--r--arch/mips/lantiq/xway/clk.c1
-rw-r--r--arch/mips/lantiq/xway/dma.c4
-rw-r--r--arch/mips/lasat/at93c.c1
-rw-r--r--arch/mips/lasat/picvue.c1
-rw-r--r--arch/mips/lib/uncached.c1
-rw-r--r--arch/mips/loongson/lemote-2f/clock.c1
-rw-r--r--arch/mips/math-emu/cp1emu.c42
-rw-r--r--arch/mips/math-emu/kernel_linkage.c6
-rw-r--r--arch/mips/mm/c-octeon.c1
-rw-r--r--arch/mips/mm/c-r3k.c1
-rw-r--r--arch/mips/mm/c-r4k.c26
-rw-r--r--arch/mips/mm/cache.c1
-rw-r--r--arch/mips/mm/cex-sb1.S1
-rw-r--r--arch/mips/mm/dma-default.c2
-rw-r--r--arch/mips/mm/hugetlbpage.c1
-rw-r--r--arch/mips/mm/init.c2
-rw-r--r--arch/mips/mm/page.c1
-rw-r--r--arch/mips/mm/sc-mips.c2
-rw-r--r--arch/mips/mm/sc-rm7k.c1
-rw-r--r--arch/mips/mm/tlb-r3k.c1
-rw-r--r--arch/mips/mm/tlb-r4k.c48
-rw-r--r--arch/mips/mm/tlb-r8k.c1
-rw-r--r--arch/mips/mm/tlbex.c2
-rw-r--r--arch/mips/mm/uasm-micromips.c1
-rw-r--r--arch/mips/mm/uasm-mips.c1
-rw-r--r--arch/mips/mti-malta/Makefile2
-rw-r--r--arch/mips/mti-malta/malta-amon.c49
-rw-r--r--arch/mips/mti-malta/malta-console.c47
-rw-r--r--arch/mips/mti-malta/malta-init.c58
-rw-r--r--arch/mips/mti-malta/malta-int.c127
-rw-r--r--arch/mips/mti-malta/malta-platform.c2
-rw-r--r--arch/mips/mti-malta/malta-time.c16
-rw-r--r--arch/mips/mti-sead3/Makefile2
-rw-r--r--arch/mips/mti-sead3/sead3-pic32-bus.c1
-rw-r--r--arch/mips/mti-sead3/sead3-setup.c84
-rw-r--r--arch/mips/mti-sead3/sead3-time.c4
-rw-r--r--arch/mips/mti-sead3/sead3.dts4
-rw-r--r--arch/mips/netlogic/Kconfig9
-rw-r--r--arch/mips/netlogic/common/earlycons.c2
-rw-r--r--arch/mips/netlogic/common/irq.c72
-rw-r--r--arch/mips/netlogic/common/reset.S63
-rw-r--r--arch/mips/netlogic/common/smp.c8
-rw-r--r--arch/mips/netlogic/common/smpboot.S4
-rw-r--r--arch/mips/netlogic/dts/Makefile1
-rw-r--r--arch/mips/netlogic/dts/xlp_gvp.dts76
-rw-r--r--arch/mips/netlogic/xlp/dt.c7
-rw-r--r--arch/mips/netlogic/xlp/nlm_hal.c71
-rw-r--r--arch/mips/netlogic/xlp/setup.c25
-rw-r--r--arch/mips/netlogic/xlp/usb-init-xlp2.c88
-rw-r--r--arch/mips/netlogic/xlp/wakeup.c92
-rw-r--r--arch/mips/netlogic/xlr/platform.c4
-rw-r--r--arch/mips/netlogic/xlr/setup.c20
-rw-r--r--arch/mips/netlogic/xlr/wakeup.c3
-rw-r--r--arch/mips/oprofile/common.c2
-rw-r--r--arch/mips/oprofile/op_model_mipsxx.c8
-rw-r--r--arch/mips/pci/Makefile1
-rw-r--r--arch/mips/pci/fixup-malta.c11
-rw-r--r--arch/mips/pci/fixup-rc32434.c1
-rw-r--r--arch/mips/pci/fixup-sb1250.c1
-rw-r--r--arch/mips/pci/msi-xlp.c494
-rw-r--r--arch/mips/pci/ops-bcm63xx.c1
-rw-r--r--arch/mips/pci/ops-bonito64.c1
-rw-r--r--arch/mips/pci/ops-lantiq.c1
-rw-r--r--arch/mips/pci/ops-loongson2.c1
-rw-r--r--arch/mips/pci/ops-mace.c1
-rw-r--r--arch/mips/pci/ops-msc.c1
-rw-r--r--arch/mips/pci/ops-nile4.c1
-rw-r--r--arch/mips/pci/ops-rc32434.c1
-rw-r--r--arch/mips/pci/pci-ip27.c1
-rw-r--r--arch/mips/pci/pci-malta.c6
-rw-r--r--arch/mips/pci/pci-rt3883.c3
-rw-r--r--arch/mips/pci/pci-xlp.c110
-rw-r--r--arch/mips/pmcs-msp71xx/Kconfig1
-rw-r--r--arch/mips/ralink/Kconfig1
-rw-r--r--arch/mips/sgi-ip27/ip27-console.c1
-rw-r--r--arch/mips/sgi-ip27/ip27-irq-pci.c1
-rw-r--r--arch/mips/sgi-ip27/ip27-klconfig.c1
-rw-r--r--arch/mips/sgi-ip27/ip27-xtalk.c1
215 files changed, 6077 insertions, 3287 deletions
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index c02f1c03a22e..dcae3a7035db 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -116,7 +116,6 @@ config BCM47XX
116 select CEVT_R4K 116 select CEVT_R4K
117 select CSRC_R4K 117 select CSRC_R4K
118 select DMA_NONCOHERENT 118 select DMA_NONCOHERENT
119 select FW_CFE
120 select HW_HAS_PCI 119 select HW_HAS_PCI
121 select IRQ_CPU 120 select IRQ_CPU
122 select SYS_HAS_CPU_MIPS32_R1 121 select SYS_HAS_CPU_MIPS32_R1
@@ -124,6 +123,7 @@ config BCM47XX
124 select SYS_SUPPORTS_32BIT_KERNEL 123 select SYS_SUPPORTS_32BIT_KERNEL
125 select SYS_SUPPORTS_LITTLE_ENDIAN 124 select SYS_SUPPORTS_LITTLE_ENDIAN
126 select SYS_HAS_EARLY_PRINTK 125 select SYS_HAS_EARLY_PRINTK
126 select EARLY_PRINTK_8250 if EARLY_PRINTK
127 help 127 help
128 Support for BCM47XX based boards 128 Support for BCM47XX based boards
129 129
@@ -134,14 +134,13 @@ config BCM63XX
134 select CSRC_R4K 134 select CSRC_R4K
135 select DMA_NONCOHERENT 135 select DMA_NONCOHERENT
136 select IRQ_CPU 136 select IRQ_CPU
137 select SYS_HAS_CPU_MIPS32_R1
138 select SYS_HAS_CPU_BMIPS4350 if !BCM63XX_CPU_6338 && !BCM63XX_CPU_6345 && !BCM63XX_CPU_6348
139 select SYS_SUPPORTS_32BIT_KERNEL 137 select SYS_SUPPORTS_32BIT_KERNEL
140 select SYS_SUPPORTS_BIG_ENDIAN 138 select SYS_SUPPORTS_BIG_ENDIAN
141 select SYS_HAS_EARLY_PRINTK 139 select SYS_HAS_EARLY_PRINTK
142 select SWAP_IO_SPACE 140 select SWAP_IO_SPACE
143 select ARCH_REQUIRE_GPIOLIB 141 select ARCH_REQUIRE_GPIOLIB
144 select HAVE_CLK 142 select HAVE_CLK
143 select MIPS_L1_CACHE_SHIFT_4
145 help 144 help
146 Support for BCM63XX based boards 145 Support for BCM63XX based boards
147 146
@@ -186,6 +185,7 @@ config MACH_DECSTATION
186 select SYS_SUPPORTS_128HZ 185 select SYS_SUPPORTS_128HZ
187 select SYS_SUPPORTS_256HZ 186 select SYS_SUPPORTS_256HZ
188 select SYS_SUPPORTS_1024HZ 187 select SYS_SUPPORTS_1024HZ
188 select MIPS_L1_CACHE_SHIFT_4
189 help 189 help
190 This enables support for DEC's MIPS based workstations. For details 190 This enables support for DEC's MIPS based workstations. For details
191 see the Linux/MIPS FAQ on <http://www.linux-mips.org/> and the 191 see the Linux/MIPS FAQ on <http://www.linux-mips.org/> and the
@@ -305,7 +305,7 @@ config MIPS_MALTA
305 select CEVT_R4K 305 select CEVT_R4K
306 select CSRC_R4K 306 select CSRC_R4K
307 select CSRC_GIC 307 select CSRC_GIC
308 select DMA_NONCOHERENT 308 select DMA_MAYBE_COHERENT
309 select GENERIC_ISA_DMA 309 select GENERIC_ISA_DMA
310 select HAVE_PCSPKR_PLATFORM 310 select HAVE_PCSPKR_PLATFORM
311 select IRQ_CPU 311 select IRQ_CPU
@@ -324,7 +324,6 @@ config MIPS_MALTA
324 select SYS_HAS_CPU_MIPS64_R2 324 select SYS_HAS_CPU_MIPS64_R2
325 select SYS_HAS_CPU_NEVADA 325 select SYS_HAS_CPU_NEVADA
326 select SYS_HAS_CPU_RM7000 326 select SYS_HAS_CPU_RM7000
327 select SYS_HAS_EARLY_PRINTK
328 select SYS_SUPPORTS_32BIT_KERNEL 327 select SYS_SUPPORTS_32BIT_KERNEL
329 select SYS_SUPPORTS_64BIT_KERNEL 328 select SYS_SUPPORTS_64BIT_KERNEL
330 select SYS_SUPPORTS_BIG_ENDIAN 329 select SYS_SUPPORTS_BIG_ENDIAN
@@ -349,6 +348,7 @@ config MIPS_SEAD3
349 select DMA_NONCOHERENT 348 select DMA_NONCOHERENT
350 select IRQ_CPU 349 select IRQ_CPU
351 select IRQ_GIC 350 select IRQ_GIC
351 select LIBFDT
352 select MIPS_MSC 352 select MIPS_MSC
353 select SYS_HAS_CPU_MIPS32_R1 353 select SYS_HAS_CPU_MIPS32_R1
354 select SYS_HAS_CPU_MIPS32_R2 354 select SYS_HAS_CPU_MIPS32_R2
@@ -471,6 +471,7 @@ config SGI_IP22
471 select SYS_SUPPORTS_32BIT_KERNEL 471 select SYS_SUPPORTS_32BIT_KERNEL
472 select SYS_SUPPORTS_64BIT_KERNEL 472 select SYS_SUPPORTS_64BIT_KERNEL
473 select SYS_SUPPORTS_BIG_ENDIAN 473 select SYS_SUPPORTS_BIG_ENDIAN
474 select MIPS_L1_CACHE_SHIFT_7
474 help 475 help
475 This are the SGI Indy, Challenge S and Indigo2, as well as certain 476 This are the SGI Indy, Challenge S and Indigo2, as well as certain
476 OEM variants like the Tandem CMN B006S. To compile a Linux kernel 477 OEM variants like the Tandem CMN B006S. To compile a Linux kernel
@@ -491,6 +492,7 @@ config SGI_IP27
491 select SYS_SUPPORTS_BIG_ENDIAN 492 select SYS_SUPPORTS_BIG_ENDIAN
492 select SYS_SUPPORTS_NUMA 493 select SYS_SUPPORTS_NUMA
493 select SYS_SUPPORTS_SMP 494 select SYS_SUPPORTS_SMP
495 select MIPS_L1_CACHE_SHIFT_7
494 help 496 help
495 This are the SGI Origin 200, Origin 2000 and Onyx 2 Graphics 497 This are the SGI Origin 200, Origin 2000 and Onyx 2 Graphics
496 workstations. To compile a Linux kernel that runs on these, say Y 498 workstations. To compile a Linux kernel that runs on these, say Y
@@ -697,6 +699,7 @@ config MIKROTIK_RB532
697 select SWAP_IO_SPACE 699 select SWAP_IO_SPACE
698 select BOOT_RAW 700 select BOOT_RAW
699 select ARCH_REQUIRE_GPIOLIB 701 select ARCH_REQUIRE_GPIOLIB
702 select MIPS_L1_CACHE_SHIFT_4
700 help 703 help
701 Support the Mikrotik(tm) RouterBoard 532 series, 704 Support the Mikrotik(tm) RouterBoard 532 series,
702 based on the IDT RC32434 SoC. 705 based on the IDT RC32434 SoC.
@@ -779,6 +782,7 @@ config NLM_XLP_BOARD
779 select CEVT_R4K 782 select CEVT_R4K
780 select CSRC_R4K 783 select CSRC_R4K
781 select IRQ_CPU 784 select IRQ_CPU
785 select ARCH_SUPPORTS_MSI
782 select ZONE_DMA32 if 64BIT 786 select ZONE_DMA32 if 64BIT
783 select SYNC_R4K 787 select SYNC_R4K
784 select SYS_HAS_EARLY_PRINTK 788 select SYS_HAS_EARLY_PRINTK
@@ -897,6 +901,10 @@ config FW_CFE
897config ARCH_DMA_ADDR_T_64BIT 901config ARCH_DMA_ADDR_T_64BIT
898 def_bool (HIGHMEM && 64BIT_PHYS_ADDR) || 64BIT 902 def_bool (HIGHMEM && 64BIT_PHYS_ADDR) || 64BIT
899 903
904config DMA_MAYBE_COHERENT
905 select DMA_NONCOHERENT
906 bool
907
900config DMA_COHERENT 908config DMA_COHERENT
901 bool 909 bool
902 910
@@ -1091,11 +1099,24 @@ config FW_SNIPROM
1091config BOOT_ELF32 1099config BOOT_ELF32
1092 bool 1100 bool
1093 1101
1102config MIPS_L1_CACHE_SHIFT_4
1103 bool
1104
1105config MIPS_L1_CACHE_SHIFT_5
1106 bool
1107
1108config MIPS_L1_CACHE_SHIFT_6
1109 bool
1110
1111config MIPS_L1_CACHE_SHIFT_7
1112 bool
1113
1094config MIPS_L1_CACHE_SHIFT 1114config MIPS_L1_CACHE_SHIFT
1095 int 1115 int
1096 default "4" if MACH_DECSTATION || MIKROTIK_RB532 || PMC_MSP4200_EVAL || SOC_RT288X 1116 default "4" if MIPS_L1_CACHE_SHIFT_4
1097 default "6" if MIPS_CPU_SCACHE 1117 default "5" if MIPS_L1_CACHE_SHIFT_5
1098 default "7" if SGI_IP22 || SGI_IP27 || SGI_IP28 || SNI_RM || CPU_CAVIUM_OCTEON 1118 default "6" if MIPS_L1_CACHE_SHIFT_6
1119 default "7" if MIPS_L1_CACHE_SHIFT_7
1099 default "5" 1120 default "5"
1100 1121
1101config HAVE_STD_PC_SERIAL_PORT 1122config HAVE_STD_PC_SERIAL_PORT
@@ -1375,47 +1396,31 @@ config CPU_CAVIUM_OCTEON
1375 select LIBFDT 1396 select LIBFDT
1376 select USE_OF 1397 select USE_OF
1377 select USB_EHCI_BIG_ENDIAN_MMIO 1398 select USB_EHCI_BIG_ENDIAN_MMIO
1399 select SYS_HAS_DMA_OPS
1400 select MIPS_L1_CACHE_SHIFT_7
1378 help 1401 help
1379 The Cavium Octeon processor is a highly integrated chip containing 1402 The Cavium Octeon processor is a highly integrated chip containing
1380 many ethernet hardware widgets for networking tasks. The processor 1403 many ethernet hardware widgets for networking tasks. The processor
1381 can have up to 16 Mips64v2 cores and 8 integrated gigabit ethernets. 1404 can have up to 16 Mips64v2 cores and 8 integrated gigabit ethernets.
1382 Full details can be found at http://www.caviumnetworks.com. 1405 Full details can be found at http://www.caviumnetworks.com.
1383 1406
1384config CPU_BMIPS3300 1407config CPU_BMIPS
1385 bool "BMIPS3300" 1408 bool "Broadcom BMIPS"
1386 depends on SYS_HAS_CPU_BMIPS3300 1409 depends on SYS_HAS_CPU_BMIPS
1387 select CPU_BMIPS 1410 select CPU_MIPS32
1388 help 1411 select CPU_BMIPS32_3300 if SYS_HAS_CPU_BMIPS32_3300
1389 Broadcom BMIPS3300 processors. 1412 select CPU_BMIPS4350 if SYS_HAS_CPU_BMIPS4350
1390 1413 select CPU_BMIPS4380 if SYS_HAS_CPU_BMIPS4380
1391config CPU_BMIPS4350 1414 select CPU_BMIPS5000 if SYS_HAS_CPU_BMIPS5000
1392 bool "BMIPS4350" 1415 select CPU_SUPPORTS_32BIT_KERNEL
1393 depends on SYS_HAS_CPU_BMIPS4350 1416 select DMA_NONCOHERENT
1394 select CPU_BMIPS 1417 select IRQ_CPU
1395 select SYS_SUPPORTS_SMP 1418 select SWAP_IO_SPACE
1396 select SYS_SUPPORTS_HOTPLUG_CPU 1419 select WEAK_ORDERING
1397 help
1398 Broadcom BMIPS4350 ("VIPER") processors.
1399
1400config CPU_BMIPS4380
1401 bool "BMIPS4380"
1402 depends on SYS_HAS_CPU_BMIPS4380
1403 select CPU_BMIPS
1404 select SYS_SUPPORTS_SMP
1405 select SYS_SUPPORTS_HOTPLUG_CPU
1406 help
1407 Broadcom BMIPS4380 processors.
1408
1409config CPU_BMIPS5000
1410 bool "BMIPS5000"
1411 depends on SYS_HAS_CPU_BMIPS5000
1412 select CPU_BMIPS
1413 select CPU_SUPPORTS_HIGHMEM 1420 select CPU_SUPPORTS_HIGHMEM
1414 select MIPS_CPU_SCACHE 1421 select CPU_HAS_PREFETCH
1415 select SYS_SUPPORTS_SMP
1416 select SYS_SUPPORTS_HOTPLUG_CPU
1417 help 1422 help
1418 Broadcom BMIPS5000 processors. 1423 Support for BMIPS32/3300/4350/4380 and BMIPS5000 processors.
1419 1424
1420config CPU_XLR 1425config CPU_XLR
1421 bool "Netlogic XLR SoC" 1426 bool "Netlogic XLR SoC"
@@ -1498,14 +1503,25 @@ config CPU_LOONGSON1
1498 select CPU_SUPPORTS_32BIT_KERNEL 1503 select CPU_SUPPORTS_32BIT_KERNEL
1499 select CPU_SUPPORTS_HIGHMEM 1504 select CPU_SUPPORTS_HIGHMEM
1500 1505
1501config CPU_BMIPS 1506config CPU_BMIPS32_3300
1507 select SMP_UP if SMP
1502 bool 1508 bool
1503 select CPU_MIPS32 1509
1504 select CPU_SUPPORTS_32BIT_KERNEL 1510config CPU_BMIPS4350
1505 select DMA_NONCOHERENT 1511 bool
1506 select IRQ_CPU 1512 select SYS_SUPPORTS_SMP
1507 select SWAP_IO_SPACE 1513 select SYS_SUPPORTS_HOTPLUG_CPU
1508 select WEAK_ORDERING 1514
1515config CPU_BMIPS4380
1516 bool
1517 select SYS_SUPPORTS_SMP
1518 select SYS_SUPPORTS_HOTPLUG_CPU
1519
1520config CPU_BMIPS5000
1521 bool
1522 select MIPS_CPU_SCACHE
1523 select SYS_SUPPORTS_SMP
1524 select SYS_SUPPORTS_HOTPLUG_CPU
1509 1525
1510config SYS_HAS_CPU_LOONGSON2E 1526config SYS_HAS_CPU_LOONGSON2E
1511 bool 1527 bool
@@ -1579,17 +1595,24 @@ config SYS_HAS_CPU_SB1
1579config SYS_HAS_CPU_CAVIUM_OCTEON 1595config SYS_HAS_CPU_CAVIUM_OCTEON
1580 bool 1596 bool
1581 1597
1582config SYS_HAS_CPU_BMIPS3300 1598config SYS_HAS_CPU_BMIPS
1599 bool
1600
1601config SYS_HAS_CPU_BMIPS32_3300
1583 bool 1602 bool
1603 select SYS_HAS_CPU_BMIPS
1584 1604
1585config SYS_HAS_CPU_BMIPS4350 1605config SYS_HAS_CPU_BMIPS4350
1586 bool 1606 bool
1607 select SYS_HAS_CPU_BMIPS
1587 1608
1588config SYS_HAS_CPU_BMIPS4380 1609config SYS_HAS_CPU_BMIPS4380
1589 bool 1610 bool
1611 select SYS_HAS_CPU_BMIPS
1590 1612
1591config SYS_HAS_CPU_BMIPS5000 1613config SYS_HAS_CPU_BMIPS5000
1592 bool 1614 bool
1615 select SYS_HAS_CPU_BMIPS
1593 1616
1594config SYS_HAS_CPU_XLR 1617config SYS_HAS_CPU_XLR
1595 bool 1618 bool
@@ -1797,6 +1820,7 @@ config IP22_CPU_SCACHE
1797config MIPS_CPU_SCACHE 1820config MIPS_CPU_SCACHE
1798 bool 1821 bool
1799 select BOARD_SCACHE 1822 select BOARD_SCACHE
1823 select MIPS_L1_CACHE_SHIFT_6
1800 1824
1801config R5000_CPU_SCACHE 1825config R5000_CPU_SCACHE
1802 bool 1826 bool
@@ -1833,59 +1857,48 @@ choice
1833 prompt "MIPS MT options" 1857 prompt "MIPS MT options"
1834 1858
1835config MIPS_MT_DISABLED 1859config MIPS_MT_DISABLED
1836 bool "Disable multithreading support." 1860 bool "Disable multithreading support"
1837 help 1861 help
1838 Use this option if your workload can't take advantage of 1862 Use this option if your platform does not support the MT ASE
1839 MIPS hardware multithreading support. On systems that don't have 1863 which is hardware multithreading support. On systems without
1840 the option of an MT-enabled processor this option will be the only 1864 an MT-enabled processor, this will be the only option that is
1841 option in this menu. 1865 available in this menu.
1842 1866
1843config MIPS_MT_SMP 1867config MIPS_MT_SMP
1844 bool "Use 1 TC on each available VPE for SMP" 1868 bool "Use 1 TC on each available VPE for SMP"
1845 depends on SYS_SUPPORTS_MULTITHREADING 1869 depends on SYS_SUPPORTS_MULTITHREADING
1846 select CPU_MIPSR2_IRQ_VI 1870 select CPU_MIPSR2_IRQ_VI
1847 select CPU_MIPSR2_IRQ_EI 1871 select CPU_MIPSR2_IRQ_EI
1872 select SYNC_R4K
1848 select MIPS_MT 1873 select MIPS_MT
1849 select SMP 1874 select SMP
1850 select SYS_SUPPORTS_SCHED_SMT if SMP
1851 select SYS_SUPPORTS_SMP
1852 select SMP_UP 1875 select SMP_UP
1876 select SYS_SUPPORTS_SMP
1877 select SYS_SUPPORTS_SCHED_SMT
1853 select MIPS_PERF_SHARED_TC_COUNTERS 1878 select MIPS_PERF_SHARED_TC_COUNTERS
1854 help 1879 help
1855 This is a kernel model which is known a VSMP but lately has been 1880 This is a kernel model which is known as SMVP. This is supported
1856 marketesed into SMVP. 1881 on cores with the MT ASE and uses the available VPEs to implement
1857 Virtual SMP uses the processor's VPEs to implement virtual 1882 virtual processors which supports SMP. This is equivalent to the
1858 processors. In currently available configuration of the 34K processor 1883 Intel Hyperthreading feature. For further information go to
1859 this allows for a dual processor. Both processors will share the same 1884 <http://www.imgtec.com/mips/mips-multithreading.asp>.
1860 primary caches; each will obtain the half of the TLB for it's own
1861 exclusive use. For a layman this model can be described as similar to
1862 what Intel calls Hyperthreading.
1863
1864 For further information see http://www.linux-mips.org/wiki/34K#VSMP
1865 1885
1866config MIPS_MT_SMTC 1886config MIPS_MT_SMTC
1867 bool "SMTC: Use all TCs on all VPEs for SMP" 1887 bool "Use all TCs on all VPEs for SMP (DEPRECATED)"
1868 depends on CPU_MIPS32_R2 1888 depends on CPU_MIPS32_R2
1869 #depends on CPU_MIPS64_R2 # once there is hardware ...
1870 depends on SYS_SUPPORTS_MULTITHREADING 1889 depends on SYS_SUPPORTS_MULTITHREADING
1871 select CPU_MIPSR2_IRQ_VI 1890 select CPU_MIPSR2_IRQ_VI
1872 select CPU_MIPSR2_IRQ_EI 1891 select CPU_MIPSR2_IRQ_EI
1873 select MIPS_MT 1892 select MIPS_MT
1874 select NR_CPUS_DEFAULT_8
1875 select SMP 1893 select SMP
1876 select SYS_SUPPORTS_SMP
1877 select SMP_UP 1894 select SMP_UP
1895 select SYS_SUPPORTS_SMP
1896 select NR_CPUS_DEFAULT_8
1878 help 1897 help
1879 This is a kernel model which is known a SMTC or lately has been 1898 This is a kernel model which is known as SMTC. This is
1880 marketesed into SMVP. 1899 supported on cores with the MT ASE and presents all TCs
1881 is presenting the available TC's of the core as processors to Linux. 1900 available on all VPEs to support SMP. For further
1882 On currently available 34K processors this means a Linux system will 1901 information see <http://www.linux-mips.org/wiki/34K#SMTC>.
1883 see up to 5 processors. The implementation of the SMTC kernel differs
1884 significantly from VSMP and cannot efficiently coexist in the same
1885 kernel binary so the choice between VSMP and SMTC is a compile time
1886 decision.
1887
1888 For further information see http://www.linux-mips.org/wiki/34K#SMTC
1889 1902
1890endchoice 1903endchoice
1891 1904
@@ -1922,6 +1935,16 @@ config MIPS_VPE_LOADER
1922 Includes a loader for loading an elf relocatable object 1935 Includes a loader for loading an elf relocatable object
1923 onto another VPE and running it. 1936 onto another VPE and running it.
1924 1937
1938config MIPS_VPE_LOADER_CMP
1939 bool
1940 default "y"
1941 depends on MIPS_VPE_LOADER && MIPS_CMP
1942
1943config MIPS_VPE_LOADER_MT
1944 bool
1945 default "y"
1946 depends on MIPS_VPE_LOADER && !MIPS_CMP
1947
1925config MIPS_MT_SMTC_IM_BACKSTOP 1948config MIPS_MT_SMTC_IM_BACKSTOP
1926 bool "Use per-TC register bits as backstop for inhibited IM bits" 1949 bool "Use per-TC register bits as backstop for inhibited IM bits"
1927 depends on MIPS_MT_SMTC 1950 depends on MIPS_MT_SMTC
@@ -1955,24 +1978,29 @@ config MIPS_VPE_LOADER_TOM
1955 you to ensure the amount you put in the option and the space your 1978 you to ensure the amount you put in the option and the space your
1956 program requires is less or equal to the amount physically present. 1979 program requires is less or equal to the amount physically present.
1957 1980
1958# this should possibly be in drivers/char, but it is rather cpu related. Hmmm
1959config MIPS_VPE_APSP_API 1981config MIPS_VPE_APSP_API
1960 bool "Enable support for AP/SP API (RTLX)" 1982 bool "Enable support for AP/SP API (RTLX)"
1961 depends on MIPS_VPE_LOADER 1983 depends on MIPS_VPE_LOADER
1962 help 1984 help
1963 1985
1986config MIPS_VPE_APSP_API_CMP
1987 bool
1988 default "y"
1989 depends on MIPS_VPE_APSP_API && MIPS_CMP
1990
1991config MIPS_VPE_APSP_API_MT
1992 bool
1993 default "y"
1994 depends on MIPS_VPE_APSP_API && !MIPS_CMP
1995
1964config MIPS_CMP 1996config MIPS_CMP
1965 bool "MIPS CMP framework support" 1997 bool "MIPS CMP support"
1966 depends on SYS_SUPPORTS_MIPS_CMP 1998 depends on SYS_SUPPORTS_MIPS_CMP && MIPS_MT_SMP
1967 select SMP
1968 select SYNC_R4K 1999 select SYNC_R4K
1969 select SYS_SUPPORTS_SMP
1970 select SYS_SUPPORTS_SCHED_SMT if SMP
1971 select WEAK_ORDERING 2000 select WEAK_ORDERING
1972 default n 2001 default n
1973 help 2002 help
1974 This is a placeholder option for the GCMP work. It will need to 2003 Enable Coherency Manager processor (CMP) support.
1975 be handled differently...
1976 2004
1977config SB1_PASS_1_WORKAROUNDS 2005config SB1_PASS_1_WORKAROUNDS
1978 bool 2006 bool
@@ -2324,6 +2352,23 @@ config SECCOMP
2324 2352
2325 If unsure, say Y. Only embedded should say N here. 2353 If unsure, say Y. Only embedded should say N here.
2326 2354
2355config MIPS_O32_FP64_SUPPORT
2356 bool "Support for O32 binaries using 64-bit FP"
2357 depends on 32BIT || MIPS32_O32
2358 default y
2359 help
2360 When this is enabled, the kernel will support use of 64-bit floating
2361 point registers with binaries using the O32 ABI along with the
2362 EF_MIPS_FP64 ELF header flag (typically built with -mfp64). On
2363 32-bit MIPS systems this support is at the cost of increasing the
2364 size and complexity of the compiled FPU emulator. Thus if you are
2365 running a MIPS32 system and know that none of your userland binaries
2366 will require 64-bit floating point, you may wish to reduce the size
2367 of your kernel & potentially improve FP emulation performance by
2368 saying N here.
2369
2370 If unsure, say Y.
2371
2327config USE_OF 2372config USE_OF
2328 bool 2373 bool
2329 select OF 2374 select OF
diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index efe50787cd89..9b8556de9993 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -114,7 +114,7 @@ cflags-$(CONFIG_CPU_BIG_ENDIAN) += $(shell $(CC) -dumpmachine |grep -q 'mips.*e
114cflags-$(CONFIG_CPU_LITTLE_ENDIAN) += $(shell $(CC) -dumpmachine |grep -q 'mips.*el-.*' || echo -EL $(undef-all) $(predef-le)) 114cflags-$(CONFIG_CPU_LITTLE_ENDIAN) += $(shell $(CC) -dumpmachine |grep -q 'mips.*el-.*' || echo -EL $(undef-all) $(predef-le))
115 115
116cflags-$(CONFIG_CPU_HAS_SMARTMIPS) += $(call cc-option,-msmartmips) 116cflags-$(CONFIG_CPU_HAS_SMARTMIPS) += $(call cc-option,-msmartmips)
117cflags-$(CONFIG_CPU_MICROMIPS) += $(call cc-option,-mmicromips -mno-jals) 117cflags-$(CONFIG_CPU_MICROMIPS) += $(call cc-option,-mmicromips)
118 118
119cflags-$(CONFIG_SB1XXX_CORELIS) += $(call cc-option,-mno-sched-prolog) \ 119cflags-$(CONFIG_SB1XXX_CORELIS) += $(call cc-option,-mno-sched-prolog) \
120 -fno-omit-frame-pointer 120 -fno-omit-frame-pointer
diff --git a/arch/mips/alchemy/common/power.c b/arch/mips/alchemy/common/power.c
index 0c7fce2a3c12..bdb28dee8fdd 100644
--- a/arch/mips/alchemy/common/power.c
+++ b/arch/mips/alchemy/common/power.c
@@ -29,7 +29,6 @@
29 * 675 Mass Ave, Cambridge, MA 02139, USA. 29 * 675 Mass Ave, Cambridge, MA 02139, USA.
30 */ 30 */
31 31
32#include <linux/init.h>
33#include <linux/pm.h> 32#include <linux/pm.h>
34#include <linux/sysctl.h> 33#include <linux/sysctl.h>
35#include <linux/jiffies.h> 34#include <linux/jiffies.h>
diff --git a/arch/mips/ar7/time.c b/arch/mips/ar7/time.c
index 22c93213b233..1dc6c3b37f91 100644
--- a/arch/mips/ar7/time.c
+++ b/arch/mips/ar7/time.c
@@ -18,7 +18,6 @@
18 * Setting up the clock on the MIPS boards. 18 * Setting up the clock on the MIPS boards.
19 */ 19 */
20 20
21#include <linux/init.h>
22#include <linux/time.h> 21#include <linux/time.h>
23#include <linux/err.h> 22#include <linux/err.h>
24#include <linux/clk.h> 23#include <linux/clk.h>
diff --git a/arch/mips/ath79/common.h b/arch/mips/ath79/common.h
index 648d2dafbc56..a3120714f0b7 100644
--- a/arch/mips/ath79/common.h
+++ b/arch/mips/ath79/common.h
@@ -15,7 +15,6 @@
15#define __ATH79_COMMON_H 15#define __ATH79_COMMON_H
16 16
17#include <linux/types.h> 17#include <linux/types.h>
18#include <linux/init.h>
19 18
20#define ATH79_MEM_SIZE_MIN (2 * 1024 * 1024) 19#define ATH79_MEM_SIZE_MIN (2 * 1024 * 1024)
21#define ATH79_MEM_SIZE_MAX (128 * 1024 * 1024) 20#define ATH79_MEM_SIZE_MAX (128 * 1024 * 1024)
diff --git a/arch/mips/bcm47xx/Kconfig b/arch/mips/bcm47xx/Kconfig
index 2b8b118398c4..09cb6f7aa3db 100644
--- a/arch/mips/bcm47xx/Kconfig
+++ b/arch/mips/bcm47xx/Kconfig
@@ -2,6 +2,7 @@ if BCM47XX
2 2
3config BCM47XX_SSB 3config BCM47XX_SSB
4 bool "SSB Support for Broadcom BCM47XX" 4 bool "SSB Support for Broadcom BCM47XX"
5 select SYS_HAS_CPU_BMIPS32_3300
5 select SSB 6 select SSB
6 select SSB_DRIVER_MIPS 7 select SSB_DRIVER_MIPS
7 select SSB_DRIVER_EXTIF 8 select SSB_DRIVER_EXTIF
@@ -11,6 +12,7 @@ config BCM47XX_SSB
11 select SSB_PCICORE_HOSTMODE if PCI 12 select SSB_PCICORE_HOSTMODE if PCI
12 select SSB_DRIVER_GPIO 13 select SSB_DRIVER_GPIO
13 select GPIOLIB 14 select GPIOLIB
15 select LEDS_GPIO_REGISTER
14 default y 16 default y
15 help 17 help
16 Add support for old Broadcom BCM47xx boards with Sonics Silicon Backplane support. 18 Add support for old Broadcom BCM47xx boards with Sonics Silicon Backplane support.
@@ -20,6 +22,7 @@ config BCM47XX_SSB
20config BCM47XX_BCMA 22config BCM47XX_BCMA
21 bool "BCMA Support for Broadcom BCM47XX" 23 bool "BCMA Support for Broadcom BCM47XX"
22 select SYS_HAS_CPU_MIPS32_R2 24 select SYS_HAS_CPU_MIPS32_R2
25 select CPU_MIPSR2_IRQ_VI
23 select BCMA 26 select BCMA
24 select BCMA_HOST_SOC 27 select BCMA_HOST_SOC
25 select BCMA_DRIVER_MIPS 28 select BCMA_DRIVER_MIPS
@@ -27,6 +30,7 @@ config BCM47XX_BCMA
27 select BCMA_DRIVER_PCI_HOSTMODE if PCI 30 select BCMA_DRIVER_PCI_HOSTMODE if PCI
28 select BCMA_DRIVER_GPIO 31 select BCMA_DRIVER_GPIO
29 select GPIOLIB 32 select GPIOLIB
33 select LEDS_GPIO_REGISTER
30 default y 34 default y
31 help 35 help
32 Add support for new Broadcom BCM47xx boards with Broadcom specific Advanced Microcontroller Bus. 36 Add support for new Broadcom BCM47xx boards with Broadcom specific Advanced Microcontroller Bus.
diff --git a/arch/mips/bcm47xx/Makefile b/arch/mips/bcm47xx/Makefile
index c52daf9b05c6..4688b6a6211b 100644
--- a/arch/mips/bcm47xx/Makefile
+++ b/arch/mips/bcm47xx/Makefile
@@ -4,5 +4,4 @@
4# 4#
5 5
6obj-y += irq.o nvram.o prom.o serial.o setup.o time.o sprom.o 6obj-y += irq.o nvram.o prom.o serial.o setup.o time.o sprom.o
7obj-y += board.o 7obj-y += board.o buttons.o leds.o
8obj-$(CONFIG_BCM47XX_SSB) += wgt634u.o
diff --git a/arch/mips/bcm47xx/bcm47xx_private.h b/arch/mips/bcm47xx/bcm47xx_private.h
new file mode 100644
index 000000000000..5c94acebf76a
--- /dev/null
+++ b/arch/mips/bcm47xx/bcm47xx_private.h
@@ -0,0 +1,12 @@
1#ifndef LINUX_BCM47XX_PRIVATE_H_
2#define LINUX_BCM47XX_PRIVATE_H_
3
4#include <linux/kernel.h>
5
6/* buttons.c */
7int __init bcm47xx_buttons_register(void);
8
9/* leds.c */
10void __init bcm47xx_leds_register(void);
11
12#endif
diff --git a/arch/mips/bcm47xx/board.c b/arch/mips/bcm47xx/board.c
index f3f6bfe68a2a..6d612e2b949b 100644
--- a/arch/mips/bcm47xx/board.c
+++ b/arch/mips/bcm47xx/board.c
@@ -36,26 +36,32 @@ static const
36struct bcm47xx_board_type_list1 bcm47xx_board_list_model_name[] __initconst = { 36struct bcm47xx_board_type_list1 bcm47xx_board_list_model_name[] __initconst = {
37 {{BCM47XX_BOARD_DLINK_DIR130, "D-Link DIR-130"}, "DIR-130"}, 37 {{BCM47XX_BOARD_DLINK_DIR130, "D-Link DIR-130"}, "DIR-130"},
38 {{BCM47XX_BOARD_DLINK_DIR330, "D-Link DIR-330"}, "DIR-330"}, 38 {{BCM47XX_BOARD_DLINK_DIR330, "D-Link DIR-330"}, "DIR-330"},
39 { {0}, 0}, 39 { {0}, NULL},
40}; 40};
41 41
42/* model_no */ 42/* model_no */
43static const 43static const
44struct bcm47xx_board_type_list1 bcm47xx_board_list_model_no[] __initconst = { 44struct bcm47xx_board_type_list1 bcm47xx_board_list_model_no[] __initconst = {
45 {{BCM47XX_BOARD_ASUS_WL700GE, "Asus WL700"}, "WL700"}, 45 {{BCM47XX_BOARD_ASUS_WL700GE, "Asus WL700"}, "WL700"},
46 { {0}, 0}, 46 { {0}, NULL},
47}; 47};
48 48
49/* machine_name */ 49/* machine_name */
50static const 50static const
51struct bcm47xx_board_type_list1 bcm47xx_board_list_machine_name[] __initconst = { 51struct bcm47xx_board_type_list1 bcm47xx_board_list_machine_name[] __initconst = {
52 {{BCM47XX_BOARD_LINKSYS_WRTSL54GS, "Linksys WRTSL54GS"}, "WRTSL54GS"}, 52 {{BCM47XX_BOARD_LINKSYS_WRTSL54GS, "Linksys WRTSL54GS"}, "WRTSL54GS"},
53 { {0}, 0}, 53 { {0}, NULL},
54}; 54};
55 55
56/* hardware_version */ 56/* hardware_version */
57static const 57static const
58struct bcm47xx_board_type_list1 bcm47xx_board_list_hardware_version[] __initconst = { 58struct bcm47xx_board_type_list1 bcm47xx_board_list_hardware_version[] __initconst = {
59 {{BCM47XX_BOARD_ASUS_RTN10U, "Asus RT-N10U"}, "RTN10U"},
60 {{BCM47XX_BOARD_ASUS_RTN12, "Asus RT-N12"}, "RT-N12"},
61 {{BCM47XX_BOARD_ASUS_RTN12B1, "Asus RT-N12B1"}, "RTN12B1"},
62 {{BCM47XX_BOARD_ASUS_RTN12C1, "Asus RT-N12C1"}, "RTN12C1"},
63 {{BCM47XX_BOARD_ASUS_RTN12D1, "Asus RT-N12D1"}, "RTN12D1"},
64 {{BCM47XX_BOARD_ASUS_RTN12HP, "Asus RT-N12HP"}, "RTN12HP"},
59 {{BCM47XX_BOARD_ASUS_RTN16, "Asus RT-N16"}, "RT-N16-"}, 65 {{BCM47XX_BOARD_ASUS_RTN16, "Asus RT-N16"}, "RT-N16-"},
60 {{BCM47XX_BOARD_ASUS_WL320GE, "Asus WL320GE"}, "WL320G-"}, 66 {{BCM47XX_BOARD_ASUS_WL320GE, "Asus WL320GE"}, "WL320G-"},
61 {{BCM47XX_BOARD_ASUS_WL330GE, "Asus WL330GE"}, "WL330GE-"}, 67 {{BCM47XX_BOARD_ASUS_WL330GE, "Asus WL330GE"}, "WL330GE-"},
@@ -66,7 +72,7 @@ struct bcm47xx_board_type_list1 bcm47xx_board_list_hardware_version[] __initcons
66 {{BCM47XX_BOARD_ASUS_WL520GC, "Asus WL520GC"}, "WL520GC-"}, 72 {{BCM47XX_BOARD_ASUS_WL520GC, "Asus WL520GC"}, "WL520GC-"},
67 {{BCM47XX_BOARD_ASUS_WL520GU, "Asus WL520GU"}, "WL520GU-"}, 73 {{BCM47XX_BOARD_ASUS_WL520GU, "Asus WL520GU"}, "WL520GU-"},
68 {{BCM47XX_BOARD_BELKIN_F7D4301, "Belkin F7D4301"}, "F7D4301"}, 74 {{BCM47XX_BOARD_BELKIN_F7D4301, "Belkin F7D4301"}, "F7D4301"},
69 { {0}, 0}, 75 { {0}, NULL},
70}; 76};
71 77
72/* productid */ 78/* productid */
@@ -75,19 +81,13 @@ struct bcm47xx_board_type_list1 bcm47xx_board_list_productid[] __initconst = {
75 {{BCM47XX_BOARD_ASUS_RTAC66U, "Asus RT-AC66U"}, "RT-AC66U"}, 81 {{BCM47XX_BOARD_ASUS_RTAC66U, "Asus RT-AC66U"}, "RT-AC66U"},
76 {{BCM47XX_BOARD_ASUS_RTN10, "Asus RT-N10"}, "RT-N10"}, 82 {{BCM47XX_BOARD_ASUS_RTN10, "Asus RT-N10"}, "RT-N10"},
77 {{BCM47XX_BOARD_ASUS_RTN10D, "Asus RT-N10D"}, "RT-N10D"}, 83 {{BCM47XX_BOARD_ASUS_RTN10D, "Asus RT-N10D"}, "RT-N10D"},
78 {{BCM47XX_BOARD_ASUS_RTN10U, "Asus RT-N10U"}, "RT-N10U"},
79 {{BCM47XX_BOARD_ASUS_RTN12, "Asus RT-N12"}, "RT-N12"},
80 {{BCM47XX_BOARD_ASUS_RTN12B1, "Asus RT-N12B1"}, "RT-N12B1"},
81 {{BCM47XX_BOARD_ASUS_RTN12C1, "Asus RT-N12C1"}, "RT-N12C1"},
82 {{BCM47XX_BOARD_ASUS_RTN12D1, "Asus RT-N12D1"}, "RT-N12D1"},
83 {{BCM47XX_BOARD_ASUS_RTN12HP, "Asus RT-N12HP"}, "RT-N12HP"},
84 {{BCM47XX_BOARD_ASUS_RTN15U, "Asus RT-N15U"}, "RT-N15U"}, 84 {{BCM47XX_BOARD_ASUS_RTN15U, "Asus RT-N15U"}, "RT-N15U"},
85 {{BCM47XX_BOARD_ASUS_RTN16, "Asus RT-N16"}, "RT-N16"}, 85 {{BCM47XX_BOARD_ASUS_RTN16, "Asus RT-N16"}, "RT-N16"},
86 {{BCM47XX_BOARD_ASUS_RTN53, "Asus RT-N53"}, "RT-N53"}, 86 {{BCM47XX_BOARD_ASUS_RTN53, "Asus RT-N53"}, "RT-N53"},
87 {{BCM47XX_BOARD_ASUS_RTN66U, "Asus RT-N66U"}, "RT-N66U"}, 87 {{BCM47XX_BOARD_ASUS_RTN66U, "Asus RT-N66U"}, "RT-N66U"},
88 {{BCM47XX_BOARD_ASUS_WL300G, "Asus WL300G"}, "WL300g"}, 88 {{BCM47XX_BOARD_ASUS_WL300G, "Asus WL300G"}, "WL300g"},
89 {{BCM47XX_BOARD_ASUS_WLHDD, "Asus WLHDD"}, "WLHDD"}, 89 {{BCM47XX_BOARD_ASUS_WLHDD, "Asus WLHDD"}, "WLHDD"},
90 { {0}, 0}, 90 { {0}, NULL},
91}; 91};
92 92
93/* ModelId */ 93/* ModelId */
@@ -97,7 +97,7 @@ struct bcm47xx_board_type_list1 bcm47xx_board_list_ModelId[] __initconst = {
97 {{BCM47XX_BOARD_MOTOROLA_WE800G, "Motorola WE800G"}, "WE800G"}, 97 {{BCM47XX_BOARD_MOTOROLA_WE800G, "Motorola WE800G"}, "WE800G"},
98 {{BCM47XX_BOARD_MOTOROLA_WR850GP, "Motorola WR850GP"}, "WR850GP"}, 98 {{BCM47XX_BOARD_MOTOROLA_WR850GP, "Motorola WR850GP"}, "WR850GP"},
99 {{BCM47XX_BOARD_MOTOROLA_WR850GV2V3, "Motorola WR850G"}, "WR850G"}, 99 {{BCM47XX_BOARD_MOTOROLA_WR850GV2V3, "Motorola WR850G"}, "WR850G"},
100 { {0}, 0}, 100 { {0}, NULL},
101}; 101};
102 102
103/* melco_id or buf1falo_id */ 103/* melco_id or buf1falo_id */
@@ -112,7 +112,7 @@ struct bcm47xx_board_type_list1 bcm47xx_board_list_melco_id[] __initconst = {
112 {{BCM47XX_BOARD_BUFFALO_WZR_G300N, "Buffalo WZR-G300N"}, "31120"}, 112 {{BCM47XX_BOARD_BUFFALO_WZR_G300N, "Buffalo WZR-G300N"}, "31120"},
113 {{BCM47XX_BOARD_BUFFALO_WZR_RS_G54, "Buffalo WZR-RS-G54"}, "30083"}, 113 {{BCM47XX_BOARD_BUFFALO_WZR_RS_G54, "Buffalo WZR-RS-G54"}, "30083"},
114 {{BCM47XX_BOARD_BUFFALO_WZR_RS_G54HP, "Buffalo WZR-RS-G54HP"}, "30103"}, 114 {{BCM47XX_BOARD_BUFFALO_WZR_RS_G54HP, "Buffalo WZR-RS-G54HP"}, "30103"},
115 { {0}, 0}, 115 { {0}, NULL},
116}; 116};
117 117
118/* boot_hw_model, boot_hw_ver */ 118/* boot_hw_model, boot_hw_ver */
@@ -143,7 +143,7 @@ struct bcm47xx_board_type_list2 bcm47xx_board_list_boot_hw[] __initconst = {
143 {{BCM47XX_BOARD_LINKSYS_WRT54G3GV2, "Linksys WRT54G3GV2-VF"}, "WRT54G3GV2-VF", "1.0"}, 143 {{BCM47XX_BOARD_LINKSYS_WRT54G3GV2, "Linksys WRT54G3GV2-VF"}, "WRT54G3GV2-VF", "1.0"},
144 {{BCM47XX_BOARD_LINKSYS_WRT610NV1, "Linksys WRT610N V1"}, "WRT610N", "1.0"}, 144 {{BCM47XX_BOARD_LINKSYS_WRT610NV1, "Linksys WRT610N V1"}, "WRT610N", "1.0"},
145 {{BCM47XX_BOARD_LINKSYS_WRT610NV2, "Linksys WRT610N V2"}, "WRT610N", "2.0"}, 145 {{BCM47XX_BOARD_LINKSYS_WRT610NV2, "Linksys WRT610N V2"}, "WRT610N", "2.0"},
146 { {0}, 0}, 146 { {0}, NULL},
147}; 147};
148 148
149/* board_id */ 149/* board_id */
@@ -165,7 +165,7 @@ struct bcm47xx_board_type_list1 bcm47xx_board_list_board_id[] __initconst = {
165 {{BCM47XX_BOARD_NETGEAR_WNR3500V2, "Netgear WNR3500 V2"}, "U12H127T00_NETGEAR"}, 165 {{BCM47XX_BOARD_NETGEAR_WNR3500V2, "Netgear WNR3500 V2"}, "U12H127T00_NETGEAR"},
166 {{BCM47XX_BOARD_NETGEAR_WNR3500V2VC, "Netgear WNR3500 V2vc"}, "U12H127T70_NETGEAR"}, 166 {{BCM47XX_BOARD_NETGEAR_WNR3500V2VC, "Netgear WNR3500 V2vc"}, "U12H127T70_NETGEAR"},
167 {{BCM47XX_BOARD_NETGEAR_WNR834BV2, "Netgear WNR834B V2"}, "U12H081T00_NETGEAR"}, 167 {{BCM47XX_BOARD_NETGEAR_WNR834BV2, "Netgear WNR834B V2"}, "U12H081T00_NETGEAR"},
168 { {0}, 0}, 168 { {0}, NULL},
169}; 169};
170 170
171/* boardtype, boardnum, boardrev */ 171/* boardtype, boardnum, boardrev */
@@ -174,7 +174,9 @@ struct bcm47xx_board_type_list3 bcm47xx_board_list_board[] __initconst = {
174 {{BCM47XX_BOARD_HUAWEI_E970, "Huawei E970"}, "0x048e", "0x5347", "0x11"}, 174 {{BCM47XX_BOARD_HUAWEI_E970, "Huawei E970"}, "0x048e", "0x5347", "0x11"},
175 {{BCM47XX_BOARD_PHICOMM_M1, "Phicomm M1"}, "0x0590", "80", "0x1104"}, 175 {{BCM47XX_BOARD_PHICOMM_M1, "Phicomm M1"}, "0x0590", "80", "0x1104"},
176 {{BCM47XX_BOARD_ZTE_H218N, "ZTE H218N"}, "0x053d", "1234", "0x1305"}, 176 {{BCM47XX_BOARD_ZTE_H218N, "ZTE H218N"}, "0x053d", "1234", "0x1305"},
177 { {0}, 0}, 177 {{BCM47XX_BOARD_NETGEAR_WNR3500L, "Netgear WNR3500L"}, "0x04CF", "3500", "02"},
178 {{BCM47XX_BOARD_LINKSYS_WRT54GSV1, "Linksys WRT54GS V1"}, "0x0101", "42", "0x10"},
179 { {0}, NULL},
178}; 180};
179 181
180static const 182static const
diff --git a/arch/mips/bcm47xx/buttons.c b/arch/mips/bcm47xx/buttons.c
new file mode 100644
index 000000000000..872c62e93e0e
--- /dev/null
+++ b/arch/mips/bcm47xx/buttons.c
@@ -0,0 +1,531 @@
1#include "bcm47xx_private.h"
2
3#include <linux/input.h>
4#include <linux/gpio_keys.h>
5#include <linux/interrupt.h>
6#include <bcm47xx_board.h>
7#include <bcm47xx.h>
8
9/**************************************************
10 * Database
11 **************************************************/
12
13#define BCM47XX_GPIO_KEY(_gpio, _code) \
14 { \
15 .code = _code, \
16 .gpio = _gpio, \
17 .active_low = 1, \
18 }
19
20/* Asus */
21
22static const struct gpio_keys_button
23bcm47xx_buttons_asus_rtn12[] __initconst = {
24 BCM47XX_GPIO_KEY(0, KEY_WPS_BUTTON),
25 BCM47XX_GPIO_KEY(1, KEY_RESTART),
26 BCM47XX_GPIO_KEY(4, BTN_0), /* Router mode */
27 BCM47XX_GPIO_KEY(5, BTN_1), /* Repeater mode */
28 BCM47XX_GPIO_KEY(6, BTN_2), /* AP mode */
29};
30
31static const struct gpio_keys_button
32bcm47xx_buttons_asus_rtn16[] __initconst = {
33 BCM47XX_GPIO_KEY(6, KEY_WPS_BUTTON),
34 BCM47XX_GPIO_KEY(8, KEY_RESTART),
35};
36
37static const struct gpio_keys_button
38bcm47xx_buttons_asus_rtn66u[] __initconst = {
39 BCM47XX_GPIO_KEY(4, KEY_WPS_BUTTON),
40 BCM47XX_GPIO_KEY(9, KEY_RESTART),
41};
42
43static const struct gpio_keys_button
44bcm47xx_buttons_asus_wl300g[] __initconst = {
45 BCM47XX_GPIO_KEY(6, KEY_RESTART),
46};
47
48static const struct gpio_keys_button
49bcm47xx_buttons_asus_wl320ge[] __initconst = {
50 BCM47XX_GPIO_KEY(6, KEY_RESTART),
51};
52
53static const struct gpio_keys_button
54bcm47xx_buttons_asus_wl330ge[] __initconst = {
55 BCM47XX_GPIO_KEY(2, KEY_RESTART),
56};
57
58static const struct gpio_keys_button
59bcm47xx_buttons_asus_wl500gd[] __initconst = {
60 BCM47XX_GPIO_KEY(6, KEY_RESTART),
61};
62
63static const struct gpio_keys_button
64bcm47xx_buttons_asus_wl500gpv1[] __initconst = {
65 BCM47XX_GPIO_KEY(0, KEY_RESTART),
66 BCM47XX_GPIO_KEY(4, KEY_WPS_BUTTON),
67};
68
69static const struct gpio_keys_button
70bcm47xx_buttons_asus_wl500gpv2[] __initconst = {
71 BCM47XX_GPIO_KEY(2, KEY_RESTART),
72 BCM47XX_GPIO_KEY(3, KEY_WPS_BUTTON),
73};
74
75static const struct gpio_keys_button
76bcm47xx_buttons_asus_wl500w[] __initconst = {
77 BCM47XX_GPIO_KEY(6, KEY_RESTART),
78 BCM47XX_GPIO_KEY(7, KEY_WPS_BUTTON),
79};
80
81static const struct gpio_keys_button
82bcm47xx_buttons_asus_wl520gc[] __initconst = {
83 BCM47XX_GPIO_KEY(2, KEY_RESTART),
84 BCM47XX_GPIO_KEY(3, KEY_WPS_BUTTON),
85};
86
87static const struct gpio_keys_button
88bcm47xx_buttons_asus_wl520gu[] __initconst = {
89 BCM47XX_GPIO_KEY(2, KEY_RESTART),
90 BCM47XX_GPIO_KEY(3, KEY_WPS_BUTTON),
91};
92
93static const struct gpio_keys_button
94bcm47xx_buttons_asus_wl700ge[] __initconst = {
95 BCM47XX_GPIO_KEY(0, KEY_POWER), /* Hard disk power switch */
96 BCM47XX_GPIO_KEY(4, KEY_WPS_BUTTON), /* EZSetup */
97 BCM47XX_GPIO_KEY(6, KEY_COPY), /* Copy data from USB to internal disk */
98 BCM47XX_GPIO_KEY(7, KEY_RESTART), /* Hard reset */
99};
100
101static const struct gpio_keys_button
102bcm47xx_buttons_asus_wlhdd[] __initconst = {
103 BCM47XX_GPIO_KEY(6, KEY_RESTART),
104};
105
106/* Huawei */
107
108static const struct gpio_keys_button
109bcm47xx_buttons_huawei_e970[] __initconst = {
110 BCM47XX_GPIO_KEY(6, KEY_RESTART),
111};
112
113/* Belkin */
114
115static const struct gpio_keys_button
116bcm47xx_buttons_belkin_f7d4301[] __initconst = {
117 BCM47XX_GPIO_KEY(6, KEY_RESTART),
118 BCM47XX_GPIO_KEY(8, KEY_WPS_BUTTON),
119};
120
121/* Buffalo */
122
123static const struct gpio_keys_button
124bcm47xx_buttons_buffalo_whr2_a54g54[] __initconst = {
125 BCM47XX_GPIO_KEY(4, KEY_RESTART),
126};
127
128static const struct gpio_keys_button
129bcm47xx_buttons_buffalo_whr_g125[] __initconst = {
130 BCM47XX_GPIO_KEY(0, KEY_WPS_BUTTON),
131 BCM47XX_GPIO_KEY(4, KEY_RESTART),
132 BCM47XX_GPIO_KEY(5, BTN_0), /* Router / AP mode swtich */
133};
134
135static const struct gpio_keys_button
136bcm47xx_buttons_buffalo_whr_g54s[] __initconst = {
137 BCM47XX_GPIO_KEY(0, KEY_WPS_BUTTON),
138 BCM47XX_GPIO_KEY(4, KEY_RESTART),
139 BCM47XX_GPIO_KEY(5, BTN_0), /* Router / AP mode swtich */
140};
141
142static const struct gpio_keys_button
143bcm47xx_buttons_buffalo_whr_hp_g54[] __initconst = {
144 BCM47XX_GPIO_KEY(0, KEY_WPS_BUTTON),
145 BCM47XX_GPIO_KEY(4, KEY_RESTART),
146 BCM47XX_GPIO_KEY(5, BTN_0), /* Router / AP mode swtich */
147};
148
149static const struct gpio_keys_button
150bcm47xx_buttons_buffalo_wzr_g300n[] __initconst = {
151 BCM47XX_GPIO_KEY(4, KEY_RESTART),
152};
153
154static const struct gpio_keys_button
155bcm47xx_buttons_buffalo_wzr_rs_g54[] __initconst = {
156 BCM47XX_GPIO_KEY(0, KEY_WPS_BUTTON),
157 BCM47XX_GPIO_KEY(4, KEY_RESTART),
158};
159
160static const struct gpio_keys_button
161bcm47xx_buttons_buffalo_wzr_rs_g54hp[] __initconst = {
162 BCM47XX_GPIO_KEY(0, KEY_WPS_BUTTON),
163 BCM47XX_GPIO_KEY(4, KEY_RESTART),
164};
165
166/* Dell */
167
168static const struct gpio_keys_button
169bcm47xx_buttons_dell_tm2300[] __initconst = {
170 BCM47XX_GPIO_KEY(0, KEY_RESTART),
171};
172
173/* D-Link */
174
175static const struct gpio_keys_button
176bcm47xx_buttons_dlink_dir130[] __initconst = {
177 BCM47XX_GPIO_KEY(3, KEY_RESTART),
178 BCM47XX_GPIO_KEY(7, KEY_UNKNOWN),
179};
180
181static const struct gpio_keys_button
182bcm47xx_buttons_dlink_dir330[] __initconst = {
183 BCM47XX_GPIO_KEY(3, KEY_RESTART),
184 BCM47XX_GPIO_KEY(7, KEY_UNKNOWN),
185};
186
187/* Linksys */
188
189static const struct gpio_keys_button
190bcm47xx_buttons_linksys_e1000v1[] __initconst = {
191 BCM47XX_GPIO_KEY(5, KEY_WPS_BUTTON),
192 BCM47XX_GPIO_KEY(6, KEY_RESTART),
193};
194
195static const struct gpio_keys_button
196bcm47xx_buttons_linksys_e1000v21[] __initconst = {
197 BCM47XX_GPIO_KEY(9, KEY_WPS_BUTTON),
198 BCM47XX_GPIO_KEY(10, KEY_RESTART),
199};
200
201static const struct gpio_keys_button
202bcm47xx_buttons_linksys_e2000v1[] __initconst = {
203 BCM47XX_GPIO_KEY(5, KEY_WPS_BUTTON),
204 BCM47XX_GPIO_KEY(8, KEY_RESTART),
205};
206
207static const struct gpio_keys_button
208bcm47xx_buttons_linksys_e3000v1[] __initconst = {
209 BCM47XX_GPIO_KEY(4, KEY_WPS_BUTTON),
210 BCM47XX_GPIO_KEY(6, KEY_RESTART),
211};
212
213static const struct gpio_keys_button
214bcm47xx_buttons_linksys_e3200v1[] __initconst = {
215 BCM47XX_GPIO_KEY(5, KEY_RESTART),
216 BCM47XX_GPIO_KEY(8, KEY_WPS_BUTTON),
217};
218
219static const struct gpio_keys_button
220bcm47xx_buttons_linksys_e4200v1[] __initconst = {
221 BCM47XX_GPIO_KEY(4, KEY_WPS_BUTTON),
222 BCM47XX_GPIO_KEY(6, KEY_RESTART),
223};
224
225static const struct gpio_keys_button
226bcm47xx_buttons_linksys_wrt150nv1[] __initconst = {
227 BCM47XX_GPIO_KEY(4, KEY_WPS_BUTTON),
228 BCM47XX_GPIO_KEY(6, KEY_RESTART),
229};
230
231static const struct gpio_keys_button
232bcm47xx_buttons_linksys_wrt150nv11[] __initconst = {
233 BCM47XX_GPIO_KEY(4, KEY_WPS_BUTTON),
234 BCM47XX_GPIO_KEY(6, KEY_RESTART),
235};
236
237static const struct gpio_keys_button
238bcm47xx_buttons_linksys_wrt160nv1[] __initconst = {
239 BCM47XX_GPIO_KEY(4, KEY_WPS_BUTTON),
240 BCM47XX_GPIO_KEY(6, KEY_RESTART),
241};
242
243static const struct gpio_keys_button
244bcm47xx_buttons_linksys_wrt160nv3[] __initconst = {
245 BCM47XX_GPIO_KEY(5, KEY_WPS_BUTTON),
246 BCM47XX_GPIO_KEY(6, KEY_RESTART),
247};
248
249static const struct gpio_keys_button
250bcm47xx_buttons_linksys_wrt300nv11[] __initconst = {
251 BCM47XX_GPIO_KEY(4, KEY_UNKNOWN),
252 BCM47XX_GPIO_KEY(6, KEY_RESTART),
253};
254
255static const struct gpio_keys_button
256bcm47xx_buttons_linksys_wrt310nv1[] __initconst = {
257 BCM47XX_GPIO_KEY(6, KEY_RESTART),
258 BCM47XX_GPIO_KEY(8, KEY_UNKNOWN),
259};
260
261static const struct gpio_keys_button
262bcm47xx_buttons_linksys_wrt610nv1[] __initconst = {
263 BCM47XX_GPIO_KEY(6, KEY_RESTART),
264 BCM47XX_GPIO_KEY(8, KEY_WPS_BUTTON),
265};
266
267static const struct gpio_keys_button
268bcm47xx_buttons_linksys_wrt610nv2[] __initconst = {
269 BCM47XX_GPIO_KEY(4, KEY_WPS_BUTTON),
270 BCM47XX_GPIO_KEY(6, KEY_RESTART),
271};
272
273/* Motorola */
274
275static const struct gpio_keys_button
276bcm47xx_buttons_motorola_we800g[] __initconst = {
277 BCM47XX_GPIO_KEY(0, KEY_RESTART),
278};
279
280static const struct gpio_keys_button
281bcm47xx_buttons_motorola_wr850gp[] __initconst = {
282 BCM47XX_GPIO_KEY(5, KEY_RESTART),
283};
284
285static const struct gpio_keys_button
286bcm47xx_buttons_motorola_wr850gv2v3[] __initconst = {
287 BCM47XX_GPIO_KEY(5, KEY_RESTART),
288};
289
290/* Netgear */
291
292static const struct gpio_keys_button
293bcm47xx_buttons_netgear_wndr3400v1[] __initconst = {
294 BCM47XX_GPIO_KEY(4, KEY_RESTART),
295 BCM47XX_GPIO_KEY(6, KEY_WPS_BUTTON),
296 BCM47XX_GPIO_KEY(8, KEY_RFKILL),
297};
298
299static const struct gpio_keys_button
300bcm47xx_buttons_netgear_wndr3700v3[] __initconst = {
301 BCM47XX_GPIO_KEY(2, KEY_RFKILL),
302 BCM47XX_GPIO_KEY(3, KEY_RESTART),
303 BCM47XX_GPIO_KEY(4, KEY_WPS_BUTTON),
304};
305
306static const struct gpio_keys_button
307bcm47xx_buttons_netgear_wndr4500v1[] __initconst = {
308 BCM47XX_GPIO_KEY(4, KEY_WPS_BUTTON),
309 BCM47XX_GPIO_KEY(5, KEY_RFKILL),
310 BCM47XX_GPIO_KEY(6, KEY_RESTART),
311};
312
313static const struct gpio_keys_button
314bcm47xx_buttons_netgear_wnr834bv2[] __initconst = {
315 BCM47XX_GPIO_KEY(6, KEY_RESTART),
316};
317
318/* SimpleTech */
319
320static const struct gpio_keys_button
321bcm47xx_buttons_simpletech_simpleshare[] __initconst = {
322 BCM47XX_GPIO_KEY(0, KEY_RESTART),
323};
324
325/**************************************************
326 * Init
327 **************************************************/
328
329static struct gpio_keys_platform_data bcm47xx_button_pdata;
330
331static struct platform_device bcm47xx_buttons_gpio_keys = {
332 .name = "gpio-keys",
333 .dev = {
334 .platform_data = &bcm47xx_button_pdata,
335 }
336};
337
338/* Copy data from __initconst */
339static int __init bcm47xx_buttons_copy(const struct gpio_keys_button *buttons,
340 size_t nbuttons)
341{
342 size_t size = nbuttons * sizeof(*buttons);
343
344 bcm47xx_button_pdata.buttons = kmalloc(size, GFP_KERNEL);
345 if (!bcm47xx_button_pdata.buttons)
346 return -ENOMEM;
347 memcpy(bcm47xx_button_pdata.buttons, buttons, size);
348 bcm47xx_button_pdata.nbuttons = nbuttons;
349
350 return 0;
351}
352
353#define bcm47xx_copy_bdata(dev_buttons) \
354 bcm47xx_buttons_copy(dev_buttons, ARRAY_SIZE(dev_buttons));
355
356int __init bcm47xx_buttons_register(void)
357{
358 enum bcm47xx_board board = bcm47xx_board_get();
359 int err;
360
361 switch (board) {
362 case BCM47XX_BOARD_ASUS_RTN12:
363 err = bcm47xx_copy_bdata(bcm47xx_buttons_asus_rtn12);
364 break;
365 case BCM47XX_BOARD_ASUS_RTN16:
366 err = bcm47xx_copy_bdata(bcm47xx_buttons_asus_rtn16);
367 break;
368 case BCM47XX_BOARD_ASUS_RTN66U:
369 err = bcm47xx_copy_bdata(bcm47xx_buttons_asus_rtn66u);
370 break;
371 case BCM47XX_BOARD_ASUS_WL300G:
372 err = bcm47xx_copy_bdata(bcm47xx_buttons_asus_wl300g);
373 break;
374 case BCM47XX_BOARD_ASUS_WL320GE:
375 err = bcm47xx_copy_bdata(bcm47xx_buttons_asus_wl320ge);
376 break;
377 case BCM47XX_BOARD_ASUS_WL330GE:
378 err = bcm47xx_copy_bdata(bcm47xx_buttons_asus_wl330ge);
379 break;
380 case BCM47XX_BOARD_ASUS_WL500GD:
381 err = bcm47xx_copy_bdata(bcm47xx_buttons_asus_wl500gd);
382 break;
383 case BCM47XX_BOARD_ASUS_WL500GPV1:
384 err = bcm47xx_copy_bdata(bcm47xx_buttons_asus_wl500gpv1);
385 break;
386 case BCM47XX_BOARD_ASUS_WL500GPV2:
387 err = bcm47xx_copy_bdata(bcm47xx_buttons_asus_wl500gpv2);
388 break;
389 case BCM47XX_BOARD_ASUS_WL500W:
390 err = bcm47xx_copy_bdata(bcm47xx_buttons_asus_wl500w);
391 break;
392 case BCM47XX_BOARD_ASUS_WL520GC:
393 err = bcm47xx_copy_bdata(bcm47xx_buttons_asus_wl520gc);
394 break;
395 case BCM47XX_BOARD_ASUS_WL520GU:
396 err = bcm47xx_copy_bdata(bcm47xx_buttons_asus_wl520gu);
397 break;
398 case BCM47XX_BOARD_ASUS_WL700GE:
399 err = bcm47xx_copy_bdata(bcm47xx_buttons_asus_wl700ge);
400 break;
401 case BCM47XX_BOARD_ASUS_WLHDD:
402 err = bcm47xx_copy_bdata(bcm47xx_buttons_asus_wlhdd);
403 break;
404
405 case BCM47XX_BOARD_BELKIN_F7D4301:
406 err = bcm47xx_copy_bdata(bcm47xx_buttons_belkin_f7d4301);
407 break;
408
409 case BCM47XX_BOARD_BUFFALO_WHR2_A54G54:
410 err = bcm47xx_copy_bdata(bcm47xx_buttons_buffalo_whr2_a54g54);
411 break;
412 case BCM47XX_BOARD_BUFFALO_WHR_G125:
413 err = bcm47xx_copy_bdata(bcm47xx_buttons_buffalo_whr_g125);
414 break;
415 case BCM47XX_BOARD_BUFFALO_WHR_G54S:
416 err = bcm47xx_copy_bdata(bcm47xx_buttons_buffalo_whr_g54s);
417 break;
418 case BCM47XX_BOARD_BUFFALO_WHR_HP_G54:
419 err = bcm47xx_copy_bdata(bcm47xx_buttons_buffalo_whr_hp_g54);
420 break;
421 case BCM47XX_BOARD_BUFFALO_WZR_G300N:
422 err = bcm47xx_copy_bdata(bcm47xx_buttons_buffalo_wzr_g300n);
423 break;
424 case BCM47XX_BOARD_BUFFALO_WZR_RS_G54:
425 err = bcm47xx_copy_bdata(bcm47xx_buttons_buffalo_wzr_rs_g54);
426 break;
427 case BCM47XX_BOARD_BUFFALO_WZR_RS_G54HP:
428 err = bcm47xx_copy_bdata(bcm47xx_buttons_buffalo_wzr_rs_g54hp);
429 break;
430
431 case BCM47XX_BOARD_DELL_TM2300:
432 err = bcm47xx_copy_bdata(bcm47xx_buttons_dell_tm2300);
433 break;
434
435 case BCM47XX_BOARD_DLINK_DIR130:
436 err = bcm47xx_copy_bdata(bcm47xx_buttons_dlink_dir130);
437 break;
438 case BCM47XX_BOARD_DLINK_DIR330:
439 err = bcm47xx_copy_bdata(bcm47xx_buttons_dlink_dir330);
440 break;
441
442 case BCM47XX_BOARD_HUAWEI_E970:
443 err = bcm47xx_copy_bdata(bcm47xx_buttons_huawei_e970);
444 break;
445
446 case BCM47XX_BOARD_LINKSYS_E1000V1:
447 err = bcm47xx_copy_bdata(bcm47xx_buttons_linksys_e1000v1);
448 break;
449 case BCM47XX_BOARD_LINKSYS_E1000V21:
450 err = bcm47xx_copy_bdata(bcm47xx_buttons_linksys_e1000v21);
451 break;
452 case BCM47XX_BOARD_LINKSYS_E2000V1:
453 err = bcm47xx_copy_bdata(bcm47xx_buttons_linksys_e2000v1);
454 break;
455 case BCM47XX_BOARD_LINKSYS_E3000V1:
456 err = bcm47xx_copy_bdata(bcm47xx_buttons_linksys_e3000v1);
457 break;
458 case BCM47XX_BOARD_LINKSYS_E3200V1:
459 err = bcm47xx_copy_bdata(bcm47xx_buttons_linksys_e3200v1);
460 break;
461 case BCM47XX_BOARD_LINKSYS_E4200V1:
462 err = bcm47xx_copy_bdata(bcm47xx_buttons_linksys_e4200v1);
463 break;
464 case BCM47XX_BOARD_LINKSYS_WRT150NV1:
465 err = bcm47xx_copy_bdata(bcm47xx_buttons_linksys_wrt150nv1);
466 break;
467 case BCM47XX_BOARD_LINKSYS_WRT150NV11:
468 err = bcm47xx_copy_bdata(bcm47xx_buttons_linksys_wrt150nv11);
469 break;
470 case BCM47XX_BOARD_LINKSYS_WRT160NV1:
471 err = bcm47xx_copy_bdata(bcm47xx_buttons_linksys_wrt160nv1);
472 break;
473 case BCM47XX_BOARD_LINKSYS_WRT160NV3:
474 err = bcm47xx_copy_bdata(bcm47xx_buttons_linksys_wrt160nv3);
475 break;
476 case BCM47XX_BOARD_LINKSYS_WRT300NV11:
477 err = bcm47xx_copy_bdata(bcm47xx_buttons_linksys_wrt300nv11);
478 break;
479 case BCM47XX_BOARD_LINKSYS_WRT310NV1:
480 err = bcm47xx_copy_bdata(bcm47xx_buttons_linksys_wrt310nv1);
481 break;
482 case BCM47XX_BOARD_LINKSYS_WRT610NV1:
483 err = bcm47xx_copy_bdata(bcm47xx_buttons_linksys_wrt610nv1);
484 break;
485 case BCM47XX_BOARD_LINKSYS_WRT610NV2:
486 err = bcm47xx_copy_bdata(bcm47xx_buttons_linksys_wrt610nv2);
487 break;
488
489 case BCM47XX_BOARD_MOTOROLA_WE800G:
490 err = bcm47xx_copy_bdata(bcm47xx_buttons_motorola_we800g);
491 break;
492 case BCM47XX_BOARD_MOTOROLA_WR850GP:
493 err = bcm47xx_copy_bdata(bcm47xx_buttons_motorola_wr850gp);
494 break;
495 case BCM47XX_BOARD_MOTOROLA_WR850GV2V3:
496 err = bcm47xx_copy_bdata(bcm47xx_buttons_motorola_wr850gv2v3);
497 break;
498
499 case BCM47XX_BOARD_NETGEAR_WNDR3400V1:
500 err = bcm47xx_copy_bdata(bcm47xx_buttons_netgear_wndr3400v1);
501 break;
502 case BCM47XX_BOARD_NETGEAR_WNDR3700V3:
503 err = bcm47xx_copy_bdata(bcm47xx_buttons_netgear_wndr3700v3);
504 break;
505 case BCM47XX_BOARD_NETGEAR_WNDR4500V1:
506 err = bcm47xx_copy_bdata(bcm47xx_buttons_netgear_wndr4500v1);
507 break;
508 case BCM47XX_BOARD_NETGEAR_WNR834BV2:
509 err = bcm47xx_copy_bdata(bcm47xx_buttons_netgear_wnr834bv2);
510 break;
511
512 case BCM47XX_BOARD_SIMPLETECH_SIMPLESHARE:
513 err = bcm47xx_copy_bdata(bcm47xx_buttons_simpletech_simpleshare);
514 break;
515
516 default:
517 pr_debug("No buttons configuration found for this device\n");
518 return -ENOTSUPP;
519 }
520
521 if (err)
522 return -ENOMEM;
523
524 err = platform_device_register(&bcm47xx_buttons_gpio_keys);
525 if (err) {
526 pr_err("Failed to register platform device: %d\n", err);
527 return err;
528 }
529
530 return 0;
531}
diff --git a/arch/mips/bcm47xx/irq.c b/arch/mips/bcm47xx/irq.c
index 8cf3833b2d29..e0585b76ec19 100644
--- a/arch/mips/bcm47xx/irq.c
+++ b/arch/mips/bcm47xx/irq.c
@@ -25,10 +25,11 @@
25#include <linux/types.h> 25#include <linux/types.h>
26#include <linux/interrupt.h> 26#include <linux/interrupt.h>
27#include <linux/irq.h> 27#include <linux/irq.h>
28#include <asm/setup.h>
28#include <asm/irq_cpu.h> 29#include <asm/irq_cpu.h>
29#include <bcm47xx.h> 30#include <bcm47xx.h>
30 31
31void plat_irq_dispatch(void) 32asmlinkage void plat_irq_dispatch(void)
32{ 33{
33 u32 cause; 34 u32 cause;
34 35
@@ -50,6 +51,18 @@ void plat_irq_dispatch(void)
50 do_IRQ(6); 51 do_IRQ(6);
51} 52}
52 53
54#define DEFINE_HWx_IRQDISPATCH(x) \
55 static void bcm47xx_hw ## x ## _irqdispatch(void) \
56 { \
57 do_IRQ(x); \
58 }
59DEFINE_HWx_IRQDISPATCH(2)
60DEFINE_HWx_IRQDISPATCH(3)
61DEFINE_HWx_IRQDISPATCH(4)
62DEFINE_HWx_IRQDISPATCH(5)
63DEFINE_HWx_IRQDISPATCH(6)
64DEFINE_HWx_IRQDISPATCH(7)
65
53void __init arch_init_irq(void) 66void __init arch_init_irq(void)
54{ 67{
55#ifdef CONFIG_BCM47XX_BCMA 68#ifdef CONFIG_BCM47XX_BCMA
@@ -64,4 +77,14 @@ void __init arch_init_irq(void)
64 } 77 }
65#endif 78#endif
66 mips_cpu_irq_init(); 79 mips_cpu_irq_init();
80
81 if (cpu_has_vint) {
82 pr_info("Setting up vectored interrupts\n");
83 set_vi_handler(2, bcm47xx_hw2_irqdispatch);
84 set_vi_handler(3, bcm47xx_hw3_irqdispatch);
85 set_vi_handler(4, bcm47xx_hw4_irqdispatch);
86 set_vi_handler(5, bcm47xx_hw5_irqdispatch);
87 set_vi_handler(6, bcm47xx_hw6_irqdispatch);
88 set_vi_handler(7, bcm47xx_hw7_irqdispatch);
89 }
67} 90}
diff --git a/arch/mips/bcm47xx/leds.c b/arch/mips/bcm47xx/leds.c
new file mode 100644
index 000000000000..647d15527066
--- /dev/null
+++ b/arch/mips/bcm47xx/leds.c
@@ -0,0 +1,542 @@
1#include "bcm47xx_private.h"
2
3#include <linux/leds.h>
4#include <bcm47xx_board.h>
5
6/**************************************************
7 * Database
8 **************************************************/
9
10#define BCM47XX_GPIO_LED(_gpio, _color, _function, _active_low, \
11 _default_state) \
12 { \
13 .name = "bcm47xx:" _color ":" _function, \
14 .gpio = _gpio, \
15 .active_low = _active_low, \
16 .default_state = _default_state, \
17 }
18
19#define BCM47XX_GPIO_LED_TRIGGER(_gpio, _color, _function, _active_low, \
20 _default_trigger) \
21 { \
22 .name = "bcm47xx:" _color ":" _function, \
23 .gpio = _gpio, \
24 .active_low = _active_low, \
25 .default_state = LEDS_GPIO_DEFSTATE_OFF, \
26 .default_trigger = _default_trigger, \
27 }
28
29/* Asus */
30
31static const struct gpio_led
32bcm47xx_leds_asus_rtn12[] __initconst = {
33 BCM47XX_GPIO_LED(2, "unk", "power", 1, LEDS_GPIO_DEFSTATE_ON),
34 BCM47XX_GPIO_LED(7, "unk", "wlan", 0, LEDS_GPIO_DEFSTATE_OFF),
35};
36
37static const struct gpio_led
38bcm47xx_leds_asus_rtn16[] __initconst = {
39 BCM47XX_GPIO_LED(1, "blue", "power", 1, LEDS_GPIO_DEFSTATE_ON),
40 BCM47XX_GPIO_LED(7, "blue", "wlan", 0, LEDS_GPIO_DEFSTATE_OFF),
41};
42
43static const struct gpio_led
44bcm47xx_leds_asus_rtn66u[] __initconst = {
45 BCM47XX_GPIO_LED(12, "unk", "power", 1, LEDS_GPIO_DEFSTATE_ON),
46 BCM47XX_GPIO_LED(15, "unk", "usb", 1, LEDS_GPIO_DEFSTATE_OFF),
47};
48
49static const struct gpio_led
50bcm47xx_leds_asus_wl300g[] __initconst = {
51 BCM47XX_GPIO_LED(0, "unk", "power", 1, LEDS_GPIO_DEFSTATE_ON),
52};
53
54static const struct gpio_led
55bcm47xx_leds_asus_wl320ge[] __initconst = {
56 BCM47XX_GPIO_LED(0, "unk", "wlan", 1, LEDS_GPIO_DEFSTATE_OFF),
57 BCM47XX_GPIO_LED(2, "unk", "power", 1, LEDS_GPIO_DEFSTATE_ON),
58 BCM47XX_GPIO_LED(11, "unk", "link", 1, LEDS_GPIO_DEFSTATE_OFF),
59};
60
61static const struct gpio_led
62bcm47xx_leds_asus_wl330ge[] __initconst = {
63 BCM47XX_GPIO_LED(0, "unk", "power", 1, LEDS_GPIO_DEFSTATE_ON),
64};
65
66static const struct gpio_led
67bcm47xx_leds_asus_wl500gd[] __initconst = {
68 BCM47XX_GPIO_LED(0, "unk", "power", 1, LEDS_GPIO_DEFSTATE_ON),
69};
70
71static const struct gpio_led
72bcm47xx_leds_asus_wl500gpv1[] __initconst = {
73 BCM47XX_GPIO_LED(1, "unk", "power", 1, LEDS_GPIO_DEFSTATE_ON),
74};
75
76static const struct gpio_led
77bcm47xx_leds_asus_wl500gpv2[] __initconst = {
78 BCM47XX_GPIO_LED(0, "unk", "power", 1, LEDS_GPIO_DEFSTATE_ON),
79 BCM47XX_GPIO_LED(1, "unk", "wlan", 1, LEDS_GPIO_DEFSTATE_OFF),
80};
81
82static const struct gpio_led
83bcm47xx_leds_asus_wl500w[] __initconst = {
84 BCM47XX_GPIO_LED(5, "unk", "power", 1, LEDS_GPIO_DEFSTATE_ON),
85};
86
87static const struct gpio_led
88bcm47xx_leds_asus_wl520gc[] __initconst = {
89 BCM47XX_GPIO_LED(0, "unk", "power", 1, LEDS_GPIO_DEFSTATE_ON),
90 BCM47XX_GPIO_LED(1, "unk", "wlan", 1, LEDS_GPIO_DEFSTATE_OFF),
91};
92
93static const struct gpio_led
94bcm47xx_leds_asus_wl520gu[] __initconst = {
95 BCM47XX_GPIO_LED(0, "unk", "power", 1, LEDS_GPIO_DEFSTATE_ON),
96 BCM47XX_GPIO_LED(1, "unk", "wlan", 1, LEDS_GPIO_DEFSTATE_OFF),
97};
98
99static const struct gpio_led
100bcm47xx_leds_asus_wl700ge[] __initconst = {
101 BCM47XX_GPIO_LED(1, "unk", "power", 1, LEDS_GPIO_DEFSTATE_ON), /* Labeled "READY" (there is no "power" LED). Originally ON, flashing on USB activity. */
102};
103
104static const struct gpio_led
105bcm47xx_leds_asus_wlhdd[] __initconst = {
106 BCM47XX_GPIO_LED(0, "unk", "power", 1, LEDS_GPIO_DEFSTATE_ON),
107 BCM47XX_GPIO_LED(2, "unk", "usb", 1, LEDS_GPIO_DEFSTATE_OFF),
108};
109
110/* Belkin */
111
112static const struct gpio_led
113bcm47xx_leds_belkin_f7d4301[] __initconst = {
114 BCM47XX_GPIO_LED(10, "green", "power", 1, LEDS_GPIO_DEFSTATE_ON),
115 BCM47XX_GPIO_LED(11, "amber", "power", 1, LEDS_GPIO_DEFSTATE_OFF),
116 BCM47XX_GPIO_LED(12, "unk", "wps", 1, LEDS_GPIO_DEFSTATE_OFF),
117 BCM47XX_GPIO_LED(13, "unk", "wlan", 1, LEDS_GPIO_DEFSTATE_OFF),
118 BCM47XX_GPIO_LED(14, "unk", "usb0", 1, LEDS_GPIO_DEFSTATE_OFF),
119 BCM47XX_GPIO_LED(15, "unk", "usb1", 1, LEDS_GPIO_DEFSTATE_OFF),
120};
121
122/* Buffalo */
123
124static const struct gpio_led
125bcm47xx_leds_buffalo_whr2_a54g54[] __initconst = {
126 BCM47XX_GPIO_LED(7, "unk", "diag", 1, LEDS_GPIO_DEFSTATE_OFF),
127};
128
129static const struct gpio_led
130bcm47xx_leds_buffalo_whr_g125[] __initconst = {
131 BCM47XX_GPIO_LED(1, "unk", "bridge", 1, LEDS_GPIO_DEFSTATE_OFF),
132 BCM47XX_GPIO_LED(2, "unk", "wlan", 1, LEDS_GPIO_DEFSTATE_OFF),
133 BCM47XX_GPIO_LED(3, "unk", "internal", 1, LEDS_GPIO_DEFSTATE_OFF),
134 BCM47XX_GPIO_LED(6, "unk", "wps", 1, LEDS_GPIO_DEFSTATE_OFF),
135 BCM47XX_GPIO_LED(7, "unk", "diag", 1, LEDS_GPIO_DEFSTATE_OFF),
136};
137
138static const struct gpio_led
139bcm47xx_leds_buffalo_whr_g54s[] __initconst = {
140 BCM47XX_GPIO_LED(1, "unk", "bridge", 1, LEDS_GPIO_DEFSTATE_OFF),
141 BCM47XX_GPIO_LED(2, "unk", "wlan", 1, LEDS_GPIO_DEFSTATE_OFF),
142 BCM47XX_GPIO_LED(3, "unk", "internal", 1, LEDS_GPIO_DEFSTATE_OFF),
143 BCM47XX_GPIO_LED(6, "unk", "wps", 1, LEDS_GPIO_DEFSTATE_OFF),
144 BCM47XX_GPIO_LED(7, "unk", "diag", 1, LEDS_GPIO_DEFSTATE_OFF),
145};
146
147static const struct gpio_led
148bcm47xx_leds_buffalo_whr_hp_g54[] __initconst = {
149 BCM47XX_GPIO_LED(1, "unk", "bridge", 1, LEDS_GPIO_DEFSTATE_OFF),
150 BCM47XX_GPIO_LED(2, "unk", "wlan", 1, LEDS_GPIO_DEFSTATE_OFF),
151 BCM47XX_GPIO_LED(3, "unk", "internal", 1, LEDS_GPIO_DEFSTATE_OFF),
152 BCM47XX_GPIO_LED(6, "unk", "wps", 1, LEDS_GPIO_DEFSTATE_OFF),
153 BCM47XX_GPIO_LED(7, "unk", "diag", 1, LEDS_GPIO_DEFSTATE_OFF),
154};
155
156static const struct gpio_led
157bcm47xx_leds_buffalo_wzr_g300n[] __initconst = {
158 BCM47XX_GPIO_LED(1, "unk", "bridge", 1, LEDS_GPIO_DEFSTATE_OFF),
159 BCM47XX_GPIO_LED(6, "unk", "wps", 1, LEDS_GPIO_DEFSTATE_OFF),
160 BCM47XX_GPIO_LED(7, "unk", "diag", 1, LEDS_GPIO_DEFSTATE_OFF),
161};
162
163static const struct gpio_led
164bcm47xx_leds_buffalo_wzr_rs_g54[] __initconst = {
165 BCM47XX_GPIO_LED(6, "unk", "wps", 1, LEDS_GPIO_DEFSTATE_OFF),
166 BCM47XX_GPIO_LED(1, "unk", "vpn", 1, LEDS_GPIO_DEFSTATE_OFF),
167 BCM47XX_GPIO_LED(7, "unk", "diag", 1, LEDS_GPIO_DEFSTATE_OFF),
168};
169
170static const struct gpio_led
171bcm47xx_leds_buffalo_wzr_rs_g54hp[] __initconst = {
172 BCM47XX_GPIO_LED(6, "unk", "wps", 1, LEDS_GPIO_DEFSTATE_OFF),
173 BCM47XX_GPIO_LED(1, "unk", "vpn", 1, LEDS_GPIO_DEFSTATE_OFF),
174 BCM47XX_GPIO_LED(7, "unk", "diag", 1, LEDS_GPIO_DEFSTATE_OFF),
175};
176
177/* Dell */
178
179static const struct gpio_led
180bcm47xx_leds_dell_tm2300[] __initconst = {
181 BCM47XX_GPIO_LED(6, "unk", "wlan", 1, LEDS_GPIO_DEFSTATE_OFF),
182 BCM47XX_GPIO_LED(7, "unk", "power", 1, LEDS_GPIO_DEFSTATE_ON),
183};
184
185/* D-Link */
186
187static const struct gpio_led
188bcm47xx_leds_dlink_dir130[] __initconst = {
189 BCM47XX_GPIO_LED_TRIGGER(0, "green", "status", 1, "timer"), /* Originally blinking when device is ready, separated from "power" LED */
190 BCM47XX_GPIO_LED(6, "blue", "unk", 1, LEDS_GPIO_DEFSTATE_OFF),
191};
192
193static const struct gpio_led
194bcm47xx_leds_dlink_dir330[] __initconst = {
195 BCM47XX_GPIO_LED_TRIGGER(0, "green", "status", 1, "timer"), /* Originally blinking when device is ready, separated from "power" LED */
196 BCM47XX_GPIO_LED(4, "unk", "usb", 1, LEDS_GPIO_DEFSTATE_OFF),
197 BCM47XX_GPIO_LED(6, "blue", "unk", 1, LEDS_GPIO_DEFSTATE_OFF),
198};
199
200/* Huawei */
201
202static const struct gpio_led
203bcm47xx_leds_huawei_e970[] __initconst = {
204 BCM47XX_GPIO_LED(0, "unk", "wlan", 0, LEDS_GPIO_DEFSTATE_OFF),
205};
206
207/* Linksys */
208
209static const struct gpio_led
210bcm47xx_leds_linksys_e1000v1[] __initconst = {
211 BCM47XX_GPIO_LED(0, "blue", "wlan", 0, LEDS_GPIO_DEFSTATE_OFF),
212 BCM47XX_GPIO_LED(1, "blue", "power", 0, LEDS_GPIO_DEFSTATE_ON),
213 BCM47XX_GPIO_LED(2, "amber", "wps", 1, LEDS_GPIO_DEFSTATE_OFF),
214 BCM47XX_GPIO_LED(4, "blue", "wps", 1, LEDS_GPIO_DEFSTATE_OFF),
215};
216
217static const struct gpio_led
218bcm47xx_leds_linksys_e1000v21[] __initconst = {
219 BCM47XX_GPIO_LED(5, "unk", "wlan", 0, LEDS_GPIO_DEFSTATE_OFF),
220 BCM47XX_GPIO_LED(6, "unk", "power", 1, LEDS_GPIO_DEFSTATE_ON),
221 BCM47XX_GPIO_LED(7, "amber", "wps", 0, LEDS_GPIO_DEFSTATE_OFF),
222 BCM47XX_GPIO_LED(8, "blue", "wps", 0, LEDS_GPIO_DEFSTATE_OFF),
223};
224
225static const struct gpio_led
226bcm47xx_leds_linksys_e2000v1[] __initconst = {
227 BCM47XX_GPIO_LED(1, "blue", "wlan", 0, LEDS_GPIO_DEFSTATE_OFF),
228 BCM47XX_GPIO_LED(2, "blue", "power", 0, LEDS_GPIO_DEFSTATE_ON),
229 BCM47XX_GPIO_LED(3, "blue", "wps", 1, LEDS_GPIO_DEFSTATE_OFF),
230 BCM47XX_GPIO_LED(4, "amber", "wps", 1, LEDS_GPIO_DEFSTATE_OFF),
231};
232
233static const struct gpio_led
234bcm47xx_leds_linksys_e3000v1[] __initconst = {
235 BCM47XX_GPIO_LED(0, "amber", "wps", 1, LEDS_GPIO_DEFSTATE_OFF),
236 BCM47XX_GPIO_LED(1, "unk", "wlan", 0, LEDS_GPIO_DEFSTATE_OFF),
237 BCM47XX_GPIO_LED(3, "blue", "wps", 1, LEDS_GPIO_DEFSTATE_OFF),
238 BCM47XX_GPIO_LED(5, "unk", "power", 0, LEDS_GPIO_DEFSTATE_ON),
239 BCM47XX_GPIO_LED(7, "unk", "usb", 0, LEDS_GPIO_DEFSTATE_OFF),
240};
241
242static const struct gpio_led
243bcm47xx_leds_linksys_e3200v1[] __initconst = {
244 BCM47XX_GPIO_LED(3, "green", "power", 1, LEDS_GPIO_DEFSTATE_ON),
245};
246
247static const struct gpio_led
248bcm47xx_leds_linksys_e4200v1[] __initconst = {
249 BCM47XX_GPIO_LED(5, "white", "power", 1, LEDS_GPIO_DEFSTATE_ON),
250};
251
252static const struct gpio_led
253bcm47xx_leds_linksys_wrt150nv1[] __initconst = {
254 BCM47XX_GPIO_LED(1, "unk", "power", 0, LEDS_GPIO_DEFSTATE_ON),
255 BCM47XX_GPIO_LED(3, "amber", "wps", 1, LEDS_GPIO_DEFSTATE_OFF),
256 BCM47XX_GPIO_LED(5, "green", "wps", 1, LEDS_GPIO_DEFSTATE_OFF),
257};
258
259static const struct gpio_led
260bcm47xx_leds_linksys_wrt150nv11[] __initconst = {
261 BCM47XX_GPIO_LED(1, "unk", "power", 0, LEDS_GPIO_DEFSTATE_ON),
262 BCM47XX_GPIO_LED(3, "amber", "wps", 1, LEDS_GPIO_DEFSTATE_OFF),
263 BCM47XX_GPIO_LED(5, "green", "wps", 1, LEDS_GPIO_DEFSTATE_OFF),
264};
265
266static const struct gpio_led
267bcm47xx_leds_linksys_wrt160nv1[] __initconst = {
268 BCM47XX_GPIO_LED(1, "unk", "power", 0, LEDS_GPIO_DEFSTATE_ON),
269 BCM47XX_GPIO_LED(3, "amber", "wps", 1, LEDS_GPIO_DEFSTATE_OFF),
270 BCM47XX_GPIO_LED(5, "blue", "wps", 1, LEDS_GPIO_DEFSTATE_OFF),
271};
272
273static const struct gpio_led
274bcm47xx_leds_linksys_wrt160nv3[] __initconst = {
275 BCM47XX_GPIO_LED(1, "unk", "power", 0, LEDS_GPIO_DEFSTATE_ON),
276 BCM47XX_GPIO_LED(2, "amber", "wps", 1, LEDS_GPIO_DEFSTATE_OFF),
277 BCM47XX_GPIO_LED(4, "blue", "wps", 1, LEDS_GPIO_DEFSTATE_OFF),
278};
279
280static const struct gpio_led
281bcm47xx_leds_linksys_wrt300nv11[] __initconst = {
282 BCM47XX_GPIO_LED(1, "unk", "power", 0, LEDS_GPIO_DEFSTATE_ON),
283 BCM47XX_GPIO_LED(3, "amber", "wps", 1, LEDS_GPIO_DEFSTATE_OFF),
284 BCM47XX_GPIO_LED(5, "green", "wps", 1, LEDS_GPIO_DEFSTATE_OFF),
285};
286
287static const struct gpio_led
288bcm47xx_leds_linksys_wrt310nv1[] __initconst = {
289 BCM47XX_GPIO_LED(1, "blue", "power", 0, LEDS_GPIO_DEFSTATE_ON),
290 BCM47XX_GPIO_LED(3, "amber", "wps", 1, LEDS_GPIO_DEFSTATE_OFF),
291 BCM47XX_GPIO_LED(9, "blue", "wps", 1, LEDS_GPIO_DEFSTATE_OFF),
292};
293
294static const struct gpio_led
295bcm47xx_leds_linksys_wrt610nv1[] __initconst = {
296 BCM47XX_GPIO_LED(0, "unk", "usb", 1, LEDS_GPIO_DEFSTATE_OFF),
297 BCM47XX_GPIO_LED(1, "unk", "power", 0, LEDS_GPIO_DEFSTATE_OFF),
298 BCM47XX_GPIO_LED(3, "amber", "wps", 1, LEDS_GPIO_DEFSTATE_OFF),
299 BCM47XX_GPIO_LED(9, "blue", "wps", 1, LEDS_GPIO_DEFSTATE_OFF),
300};
301
302static const struct gpio_led
303bcm47xx_leds_linksys_wrt610nv2[] __initconst = {
304 BCM47XX_GPIO_LED(0, "amber", "wps", 1, LEDS_GPIO_DEFSTATE_OFF),
305 BCM47XX_GPIO_LED(1, "unk", "wlan", 0, LEDS_GPIO_DEFSTATE_OFF),
306 BCM47XX_GPIO_LED(3, "blue", "wps", 1, LEDS_GPIO_DEFSTATE_OFF),
307 BCM47XX_GPIO_LED(5, "unk", "power", 0, LEDS_GPIO_DEFSTATE_ON),
308 BCM47XX_GPIO_LED(7, "unk", "usb", 0, LEDS_GPIO_DEFSTATE_OFF),
309};
310
311/* Motorola */
312
313static const struct gpio_led
314bcm47xx_leds_motorola_we800g[] __initconst = {
315 BCM47XX_GPIO_LED(1, "amber", "wlan", 0, LEDS_GPIO_DEFSTATE_OFF),
316 BCM47XX_GPIO_LED(2, "unk", "unk", 1, LEDS_GPIO_DEFSTATE_OFF), /* There are only 3 LEDs: Power, Wireless and Device (ethernet) */
317 BCM47XX_GPIO_LED(4, "green", "power", 0, LEDS_GPIO_DEFSTATE_ON),
318};
319
320static const struct gpio_led
321bcm47xx_leds_motorola_wr850gp[] __initconst = {
322 BCM47XX_GPIO_LED(0, "unk", "wlan", 1, LEDS_GPIO_DEFSTATE_OFF),
323 BCM47XX_GPIO_LED(1, "unk", "power", 0, LEDS_GPIO_DEFSTATE_ON),
324 BCM47XX_GPIO_LED(6, "unk", "dmz", 1, LEDS_GPIO_DEFSTATE_OFF),
325 BCM47XX_GPIO_LED(7, "unk", "diag", 1, LEDS_GPIO_DEFSTATE_OFF),
326};
327
328static const struct gpio_led
329bcm47xx_leds_motorola_wr850gv2v3[] __initconst = {
330 BCM47XX_GPIO_LED(0, "unk", "wlan", 1, LEDS_GPIO_DEFSTATE_OFF),
331 BCM47XX_GPIO_LED(1, "unk", "power", 0, LEDS_GPIO_DEFSTATE_ON),
332 BCM47XX_GPIO_LED(7, "unk", "diag", 1, LEDS_GPIO_DEFSTATE_OFF),
333};
334
335/* Netgear */
336
337static const struct gpio_led
338bcm47xx_leds_netgear_wndr3400v1[] __initconst = {
339 BCM47XX_GPIO_LED(2, "green", "usb", 1, LEDS_GPIO_DEFSTATE_OFF),
340 BCM47XX_GPIO_LED(3, "green", "power", 0, LEDS_GPIO_DEFSTATE_ON),
341 BCM47XX_GPIO_LED(7, "amber", "power", 0, LEDS_GPIO_DEFSTATE_OFF),
342};
343
344static const struct gpio_led
345bcm47xx_leds_netgear_wndr4500v1[] __initconst = {
346 BCM47XX_GPIO_LED(1, "green", "wps", 1, LEDS_GPIO_DEFSTATE_OFF),
347 BCM47XX_GPIO_LED(2, "green", "power", 1, LEDS_GPIO_DEFSTATE_ON),
348 BCM47XX_GPIO_LED(3, "amber", "power", 1, LEDS_GPIO_DEFSTATE_OFF),
349 BCM47XX_GPIO_LED(8, "green", "usb1", 1, LEDS_GPIO_DEFSTATE_OFF),
350 BCM47XX_GPIO_LED(9, "green", "2ghz", 1, LEDS_GPIO_DEFSTATE_OFF),
351 BCM47XX_GPIO_LED(11, "blue", "5ghz", 1, LEDS_GPIO_DEFSTATE_OFF),
352 BCM47XX_GPIO_LED(14, "green", "usb2", 1, LEDS_GPIO_DEFSTATE_OFF),
353};
354
355static const struct gpio_led
356bcm47xx_leds_netgear_wnr834bv2[] __initconst = {
357 BCM47XX_GPIO_LED(2, "green", "power", 0, LEDS_GPIO_DEFSTATE_ON),
358 BCM47XX_GPIO_LED(3, "amber", "power", 0, LEDS_GPIO_DEFSTATE_OFF),
359 BCM47XX_GPIO_LED(7, "unk", "connected", 0, LEDS_GPIO_DEFSTATE_OFF),
360};
361
362/* SimpleTech */
363
364static const struct gpio_led
365bcm47xx_leds_simpletech_simpleshare[] __initconst = {
366 BCM47XX_GPIO_LED(1, "unk", "status", 1, LEDS_GPIO_DEFSTATE_OFF), /* "Ready" LED */
367};
368
369/**************************************************
370 * Init
371 **************************************************/
372
373static struct gpio_led_platform_data bcm47xx_leds_pdata;
374
375#define bcm47xx_set_pdata(dev_leds) do { \
376 bcm47xx_leds_pdata.leds = dev_leds; \
377 bcm47xx_leds_pdata.num_leds = ARRAY_SIZE(dev_leds); \
378} while (0)
379
380void __init bcm47xx_leds_register(void)
381{
382 enum bcm47xx_board board = bcm47xx_board_get();
383
384 switch (board) {
385 case BCM47XX_BOARD_ASUS_RTN12:
386 bcm47xx_set_pdata(bcm47xx_leds_asus_rtn12);
387 break;
388 case BCM47XX_BOARD_ASUS_RTN16:
389 bcm47xx_set_pdata(bcm47xx_leds_asus_rtn16);
390 break;
391 case BCM47XX_BOARD_ASUS_RTN66U:
392 bcm47xx_set_pdata(bcm47xx_leds_asus_rtn66u);
393 break;
394 case BCM47XX_BOARD_ASUS_WL300G:
395 bcm47xx_set_pdata(bcm47xx_leds_asus_wl300g);
396 break;
397 case BCM47XX_BOARD_ASUS_WL320GE:
398 bcm47xx_set_pdata(bcm47xx_leds_asus_wl320ge);
399 break;
400 case BCM47XX_BOARD_ASUS_WL330GE:
401 bcm47xx_set_pdata(bcm47xx_leds_asus_wl330ge);
402 break;
403 case BCM47XX_BOARD_ASUS_WL500GD:
404 bcm47xx_set_pdata(bcm47xx_leds_asus_wl500gd);
405 break;
406 case BCM47XX_BOARD_ASUS_WL500GPV1:
407 bcm47xx_set_pdata(bcm47xx_leds_asus_wl500gpv1);
408 break;
409 case BCM47XX_BOARD_ASUS_WL500GPV2:
410 bcm47xx_set_pdata(bcm47xx_leds_asus_wl500gpv2);
411 break;
412 case BCM47XX_BOARD_ASUS_WL500W:
413 bcm47xx_set_pdata(bcm47xx_leds_asus_wl500w);
414 break;
415 case BCM47XX_BOARD_ASUS_WL520GC:
416 bcm47xx_set_pdata(bcm47xx_leds_asus_wl520gc);
417 break;
418 case BCM47XX_BOARD_ASUS_WL520GU:
419 bcm47xx_set_pdata(bcm47xx_leds_asus_wl520gu);
420 break;
421 case BCM47XX_BOARD_ASUS_WL700GE:
422 bcm47xx_set_pdata(bcm47xx_leds_asus_wl700ge);
423 break;
424 case BCM47XX_BOARD_ASUS_WLHDD:
425 bcm47xx_set_pdata(bcm47xx_leds_asus_wlhdd);
426 break;
427
428 case BCM47XX_BOARD_BELKIN_F7D4301:
429 bcm47xx_set_pdata(bcm47xx_leds_belkin_f7d4301);
430 break;
431
432 case BCM47XX_BOARD_BUFFALO_WHR2_A54G54:
433 bcm47xx_set_pdata(bcm47xx_leds_buffalo_whr2_a54g54);
434 break;
435 case BCM47XX_BOARD_BUFFALO_WHR_G125:
436 bcm47xx_set_pdata(bcm47xx_leds_buffalo_whr_g125);
437 break;
438 case BCM47XX_BOARD_BUFFALO_WHR_G54S:
439 bcm47xx_set_pdata(bcm47xx_leds_buffalo_whr_g54s);
440 break;
441 case BCM47XX_BOARD_BUFFALO_WHR_HP_G54:
442 bcm47xx_set_pdata(bcm47xx_leds_buffalo_whr_hp_g54);
443 break;
444 case BCM47XX_BOARD_BUFFALO_WZR_G300N:
445 bcm47xx_set_pdata(bcm47xx_leds_buffalo_wzr_g300n);
446 break;
447 case BCM47XX_BOARD_BUFFALO_WZR_RS_G54:
448 bcm47xx_set_pdata(bcm47xx_leds_buffalo_wzr_rs_g54);
449 break;
450 case BCM47XX_BOARD_BUFFALO_WZR_RS_G54HP:
451 bcm47xx_set_pdata(bcm47xx_leds_buffalo_wzr_rs_g54hp);
452 break;
453
454 case BCM47XX_BOARD_DELL_TM2300:
455 bcm47xx_set_pdata(bcm47xx_leds_dell_tm2300);
456 break;
457
458 case BCM47XX_BOARD_DLINK_DIR130:
459 bcm47xx_set_pdata(bcm47xx_leds_dlink_dir130);
460 break;
461 case BCM47XX_BOARD_DLINK_DIR330:
462 bcm47xx_set_pdata(bcm47xx_leds_dlink_dir330);
463 break;
464
465 case BCM47XX_BOARD_HUAWEI_E970:
466 bcm47xx_set_pdata(bcm47xx_leds_huawei_e970);
467 break;
468
469 case BCM47XX_BOARD_LINKSYS_E1000V1:
470 bcm47xx_set_pdata(bcm47xx_leds_linksys_e1000v1);
471 break;
472 case BCM47XX_BOARD_LINKSYS_E1000V21:
473 bcm47xx_set_pdata(bcm47xx_leds_linksys_e1000v21);
474 break;
475 case BCM47XX_BOARD_LINKSYS_E2000V1:
476 bcm47xx_set_pdata(bcm47xx_leds_linksys_e2000v1);
477 break;
478 case BCM47XX_BOARD_LINKSYS_E3000V1:
479 bcm47xx_set_pdata(bcm47xx_leds_linksys_e3000v1);
480 break;
481 case BCM47XX_BOARD_LINKSYS_E3200V1:
482 bcm47xx_set_pdata(bcm47xx_leds_linksys_e3200v1);
483 break;
484 case BCM47XX_BOARD_LINKSYS_E4200V1:
485 bcm47xx_set_pdata(bcm47xx_leds_linksys_e4200v1);
486 break;
487 case BCM47XX_BOARD_LINKSYS_WRT150NV1:
488 bcm47xx_set_pdata(bcm47xx_leds_linksys_wrt150nv1);
489 break;
490 case BCM47XX_BOARD_LINKSYS_WRT150NV11:
491 bcm47xx_set_pdata(bcm47xx_leds_linksys_wrt150nv11);
492 break;
493 case BCM47XX_BOARD_LINKSYS_WRT160NV1:
494 bcm47xx_set_pdata(bcm47xx_leds_linksys_wrt160nv1);
495 break;
496 case BCM47XX_BOARD_LINKSYS_WRT160NV3:
497 bcm47xx_set_pdata(bcm47xx_leds_linksys_wrt160nv3);
498 break;
499 case BCM47XX_BOARD_LINKSYS_WRT300NV11:
500 bcm47xx_set_pdata(bcm47xx_leds_linksys_wrt300nv11);
501 break;
502 case BCM47XX_BOARD_LINKSYS_WRT310NV1:
503 bcm47xx_set_pdata(bcm47xx_leds_linksys_wrt310nv1);
504 break;
505 case BCM47XX_BOARD_LINKSYS_WRT610NV1:
506 bcm47xx_set_pdata(bcm47xx_leds_linksys_wrt610nv1);
507 break;
508 case BCM47XX_BOARD_LINKSYS_WRT610NV2:
509 bcm47xx_set_pdata(bcm47xx_leds_linksys_wrt610nv2);
510 break;
511
512 case BCM47XX_BOARD_MOTOROLA_WE800G:
513 bcm47xx_set_pdata(bcm47xx_leds_motorola_we800g);
514 break;
515 case BCM47XX_BOARD_MOTOROLA_WR850GP:
516 bcm47xx_set_pdata(bcm47xx_leds_motorola_wr850gp);
517 break;
518 case BCM47XX_BOARD_MOTOROLA_WR850GV2V3:
519 bcm47xx_set_pdata(bcm47xx_leds_motorola_wr850gv2v3);
520 break;
521
522 case BCM47XX_BOARD_NETGEAR_WNDR3400V1:
523 bcm47xx_set_pdata(bcm47xx_leds_netgear_wndr3400v1);
524 break;
525 case BCM47XX_BOARD_NETGEAR_WNDR4500V1:
526 bcm47xx_set_pdata(bcm47xx_leds_netgear_wndr4500v1);
527 break;
528 case BCM47XX_BOARD_NETGEAR_WNR834BV2:
529 bcm47xx_set_pdata(bcm47xx_leds_netgear_wnr834bv2);
530 break;
531
532 case BCM47XX_BOARD_SIMPLETECH_SIMPLESHARE:
533 bcm47xx_set_pdata(bcm47xx_leds_simpletech_simpleshare);
534 break;
535
536 default:
537 pr_debug("No LEDs configuration found for this device\n");
538 return;
539 }
540
541 gpio_led_register_device(-1, &bcm47xx_leds_pdata);
542}
diff --git a/arch/mips/bcm47xx/nvram.c b/arch/mips/bcm47xx/nvram.c
index b4c585b1c62e..6decb27cf48b 100644
--- a/arch/mips/bcm47xx/nvram.c
+++ b/arch/mips/bcm47xx/nvram.c
@@ -11,7 +11,6 @@
11 * option) any later version. 11 * option) any later version.
12 */ 12 */
13 13
14#include <linux/init.h>
15#include <linux/types.h> 14#include <linux/types.h>
16#include <linux/module.h> 15#include <linux/module.h>
17#include <linux/ssb/ssb.h> 16#include <linux/ssb/ssb.h>
@@ -22,11 +21,11 @@
22#include <asm/mach-bcm47xx/bcm47xx.h> 21#include <asm/mach-bcm47xx/bcm47xx.h>
23 22
24static char nvram_buf[NVRAM_SPACE]; 23static char nvram_buf[NVRAM_SPACE];
24static const u32 nvram_sizes[] = {0x8000, 0xF000, 0x10000};
25 25
26static u32 find_nvram_size(u32 end) 26static u32 find_nvram_size(u32 end)
27{ 27{
28 struct nvram_header *header; 28 struct nvram_header *header;
29 u32 nvram_sizes[] = {0x8000, 0xF000, 0x10000};
30 int i; 29 int i;
31 30
32 for (i = 0; i < ARRAY_SIZE(nvram_sizes); i++) { 31 for (i = 0; i < ARRAY_SIZE(nvram_sizes); i++) {
diff --git a/arch/mips/bcm47xx/prom.c b/arch/mips/bcm47xx/prom.c
index 5cba318bc1cd..0af808dfd1ca 100644
--- a/arch/mips/bcm47xx/prom.c
+++ b/arch/mips/bcm47xx/prom.c
@@ -28,126 +28,27 @@
28#include <linux/types.h> 28#include <linux/types.h>
29#include <linux/kernel.h> 29#include <linux/kernel.h>
30#include <linux/spinlock.h> 30#include <linux/spinlock.h>
31#include <linux/ssb/ssb_driver_chipcommon.h>
32#include <linux/ssb/ssb_regs.h>
31#include <linux/smp.h> 33#include <linux/smp.h>
32#include <asm/bootinfo.h> 34#include <asm/bootinfo.h>
33#include <asm/fw/cfe/cfe_api.h>
34#include <asm/fw/cfe/cfe_error.h>
35#include <bcm47xx.h> 35#include <bcm47xx.h>
36#include <bcm47xx_board.h> 36#include <bcm47xx_board.h>
37 37
38static int cfe_cons_handle;
39 38
40static u16 get_chip_id(void) 39static char bcm47xx_system_type[20] = "Broadcom BCM47XX";
41{
42 switch (bcm47xx_bus_type) {
43#ifdef CONFIG_BCM47XX_SSB
44 case BCM47XX_BUS_TYPE_SSB:
45 return bcm47xx_bus.ssb.chip_id;
46#endif
47#ifdef CONFIG_BCM47XX_BCMA
48 case BCM47XX_BUS_TYPE_BCMA:
49 return bcm47xx_bus.bcma.bus.chipinfo.id;
50#endif
51 }
52 return 0;
53}
54 40
55const char *get_system_type(void) 41const char *get_system_type(void)
56{ 42{
57 static char buf[50]; 43 return bcm47xx_system_type;
58 u16 chip_id = get_chip_id();
59
60 snprintf(buf, sizeof(buf),
61 (chip_id > 0x9999) ? "Broadcom BCM%d (%s)" :
62 "Broadcom BCM%04X (%s)",
63 chip_id, bcm47xx_board_get_name());
64
65 return buf;
66}
67
68void prom_putchar(char c)
69{
70 while (cfe_write(cfe_cons_handle, &c, 1) == 0)
71 ;
72} 44}
73 45
74static __init void prom_init_cfe(void) 46__init void bcm47xx_set_system_type(u16 chip_id)
75{ 47{
76 uint32_t cfe_ept; 48 snprintf(bcm47xx_system_type, sizeof(bcm47xx_system_type),
77 uint32_t cfe_handle; 49 (chip_id > 0x9999) ? "Broadcom BCM%d" :
78 uint32_t cfe_eptseal; 50 "Broadcom BCM%04X",
79 int argc = fw_arg0; 51 chip_id);
80 char **envp = (char **) fw_arg2;
81 int *prom_vec = (int *) fw_arg3;
82
83 /*
84 * Check if a loader was used; if NOT, the 4 arguments are
85 * what CFE gives us (handle, 0, EPT and EPTSEAL)
86 */
87 if (argc < 0) {
88 cfe_handle = (uint32_t)argc;
89 cfe_ept = (uint32_t)envp;
90 cfe_eptseal = (uint32_t)prom_vec;
91 } else {
92 if ((int)prom_vec < 0) {
93 /*
94 * Old loader; all it gives us is the handle,
95 * so use the "known" entrypoint and assume
96 * the seal.
97 */
98 cfe_handle = (uint32_t)prom_vec;
99 cfe_ept = 0xBFC00500;
100 cfe_eptseal = CFE_EPTSEAL;
101 } else {
102 /*
103 * Newer loaders bundle the handle/ept/eptseal
104 * Note: prom_vec is in the loader's useg
105 * which is still alive in the TLB.
106 */
107 cfe_handle = prom_vec[0];
108 cfe_ept = prom_vec[2];
109 cfe_eptseal = prom_vec[3];
110 }
111 }
112
113 if (cfe_eptseal != CFE_EPTSEAL) {
114 /* too early for panic to do any good */
115 printk(KERN_ERR "CFE's entrypoint seal doesn't match.");
116 while (1) ;
117 }
118
119 cfe_init(cfe_handle, cfe_ept);
120}
121
122static __init void prom_init_console(void)
123{
124 /* Initialize CFE console */
125 cfe_cons_handle = cfe_getstdhandle(CFE_STDHANDLE_CONSOLE);
126}
127
128static __init void prom_init_cmdline(void)
129{
130 static char buf[COMMAND_LINE_SIZE] __initdata;
131
132 /* Get the kernel command line from CFE */
133 if (cfe_getenv("LINUX_CMDLINE", buf, COMMAND_LINE_SIZE) >= 0) {
134 buf[COMMAND_LINE_SIZE - 1] = 0;
135 strcpy(arcs_cmdline, buf);
136 }
137
138 /* Force a console handover by adding a console= argument if needed,
139 * as CFE is not available anymore later in the boot process. */
140 if ((strstr(arcs_cmdline, "console=")) == NULL) {
141 /* Try to read the default serial port used by CFE */
142 if ((cfe_getenv("BOOT_CONSOLE", buf, COMMAND_LINE_SIZE) < 0)
143 || (strncmp("uart", buf, 4)))
144 /* Default to uart0 */
145 strcpy(buf, "uart0");
146
147 /* Compute the new command line */
148 snprintf(arcs_cmdline, COMMAND_LINE_SIZE, "%s console=ttyS%c,115200",
149 arcs_cmdline, buf[4]);
150 }
151} 52}
152 53
153static __init void prom_init_mem(void) 54static __init void prom_init_mem(void)
@@ -195,12 +96,16 @@ static __init void prom_init_mem(void)
195 add_memory_region(0, mem, BOOT_MEM_RAM); 96 add_memory_region(0, mem, BOOT_MEM_RAM);
196} 97}
197 98
99/*
100 * This is the first serial on the chip common core, it is at this position
101 * for sb (ssb) and ai (bcma) bus.
102 */
103#define BCM47XX_SERIAL_ADDR (SSB_ENUM_BASE + SSB_CHIPCO_UART0_DATA)
104
198void __init prom_init(void) 105void __init prom_init(void)
199{ 106{
200 prom_init_cfe();
201 prom_init_console();
202 prom_init_cmdline();
203 prom_init_mem(); 107 prom_init_mem();
108 setup_8250_early_printk_port(CKSEG1ADDR(BCM47XX_SERIAL_ADDR), 0, 0);
204} 109}
205 110
206void __init prom_free_prom_memory(void) 111void __init prom_free_prom_memory(void)
diff --git a/arch/mips/bcm47xx/serial.c b/arch/mips/bcm47xx/serial.c
index b8ef965705cf..2f5bbd68e9a0 100644
--- a/arch/mips/bcm47xx/serial.c
+++ b/arch/mips/bcm47xx/serial.c
@@ -31,7 +31,8 @@ static int __init uart8250_init_ssb(void)
31 31
32 memset(&uart8250_data, 0, sizeof(uart8250_data)); 32 memset(&uart8250_data, 0, sizeof(uart8250_data));
33 33
34 for (i = 0; i < mcore->nr_serial_ports; i++) { 34 for (i = 0; i < mcore->nr_serial_ports &&
35 i < ARRAY_SIZE(uart8250_data) - 1; i++) {
35 struct plat_serial8250_port *p = &(uart8250_data[i]); 36 struct plat_serial8250_port *p = &(uart8250_data[i]);
36 struct ssb_serial_port *ssb_port = &(mcore->serial_ports[i]); 37 struct ssb_serial_port *ssb_port = &(mcore->serial_ports[i]);
37 38
@@ -55,7 +56,8 @@ static int __init uart8250_init_bcma(void)
55 56
56 memset(&uart8250_data, 0, sizeof(uart8250_data)); 57 memset(&uart8250_data, 0, sizeof(uart8250_data));
57 58
58 for (i = 0; i < cc->nr_serial_ports; i++) { 59 for (i = 0; i < cc->nr_serial_ports &&
60 i < ARRAY_SIZE(uart8250_data) - 1; i++) {
59 struct plat_serial8250_port *p = &(uart8250_data[i]); 61 struct plat_serial8250_port *p = &(uart8250_data[i]);
60 struct bcma_serial_port *bcma_port; 62 struct bcma_serial_port *bcma_port;
61 bcma_port = &(cc->serial_ports[i]); 63 bcma_port = &(cc->serial_ports[i]);
diff --git a/arch/mips/bcm47xx/setup.c b/arch/mips/bcm47xx/setup.c
index 9057728ac56b..025be218ea15 100644
--- a/arch/mips/bcm47xx/setup.c
+++ b/arch/mips/bcm47xx/setup.c
@@ -26,6 +26,8 @@
26 * 675 Mass Ave, Cambridge, MA 02139, USA. 26 * 675 Mass Ave, Cambridge, MA 02139, USA.
27 */ 27 */
28 28
29#include "bcm47xx_private.h"
30
29#include <linux/export.h> 31#include <linux/export.h>
30#include <linux/types.h> 32#include <linux/types.h>
31#include <linux/ethtool.h> 33#include <linux/ethtool.h>
@@ -35,6 +37,8 @@
35#include <linux/ssb/ssb_embedded.h> 37#include <linux/ssb/ssb_embedded.h>
36#include <linux/bcma/bcma_soc.h> 38#include <linux/bcma/bcma_soc.h>
37#include <asm/bootinfo.h> 39#include <asm/bootinfo.h>
40#include <asm/idle.h>
41#include <asm/prom.h>
38#include <asm/reboot.h> 42#include <asm/reboot.h>
39#include <asm/time.h> 43#include <asm/time.h>
40#include <bcm47xx.h> 44#include <bcm47xx.h>
@@ -213,12 +217,14 @@ void __init plat_mem_setup(void)
213#ifdef CONFIG_BCM47XX_BCMA 217#ifdef CONFIG_BCM47XX_BCMA
214 bcm47xx_bus_type = BCM47XX_BUS_TYPE_BCMA; 218 bcm47xx_bus_type = BCM47XX_BUS_TYPE_BCMA;
215 bcm47xx_register_bcma(); 219 bcm47xx_register_bcma();
220 bcm47xx_set_system_type(bcm47xx_bus.bcma.bus.chipinfo.id);
216#endif 221#endif
217 } else { 222 } else {
218 printk(KERN_INFO "bcm47xx: using ssb bus\n"); 223 printk(KERN_INFO "bcm47xx: using ssb bus\n");
219#ifdef CONFIG_BCM47XX_SSB 224#ifdef CONFIG_BCM47XX_SSB
220 bcm47xx_bus_type = BCM47XX_BUS_TYPE_SSB; 225 bcm47xx_bus_type = BCM47XX_BUS_TYPE_SSB;
221 bcm47xx_register_ssb(); 226 bcm47xx_register_ssb();
227 bcm47xx_set_system_type(bcm47xx_bus.ssb.chip_id);
222#endif 228#endif
223 } 229 }
224 230
@@ -226,8 +232,34 @@ void __init plat_mem_setup(void)
226 _machine_halt = bcm47xx_machine_halt; 232 _machine_halt = bcm47xx_machine_halt;
227 pm_power_off = bcm47xx_machine_halt; 233 pm_power_off = bcm47xx_machine_halt;
228 bcm47xx_board_detect(); 234 bcm47xx_board_detect();
235 mips_set_machine_name(bcm47xx_board_get_name());
229} 236}
230 237
238static int __init bcm47xx_cpu_fixes(void)
239{
240 switch (bcm47xx_bus_type) {
241#ifdef CONFIG_BCM47XX_SSB
242 case BCM47XX_BUS_TYPE_SSB:
243 /* Nothing to do */
244 break;
245#endif
246#ifdef CONFIG_BCM47XX_BCMA
247 case BCM47XX_BUS_TYPE_BCMA:
248 /* The BCM4706 has a problem with the CPU wait instruction.
249 * When r4k_wait or r4k_wait_irqoff is used will just hang and
250 * not return from a msleep(). Removing the cpu_wait
251 * functionality is a workaround for this problem. The BCM4716
252 * does not have this problem.
253 */
254 if (bcm47xx_bus.bcma.bus.chipinfo.id == BCMA_CHIP_ID_BCM4706)
255 cpu_wait = NULL;
256 break;
257#endif
258 }
259 return 0;
260}
261arch_initcall(bcm47xx_cpu_fixes);
262
231static struct fixed_phy_status bcm47xx_fixed_phy_status __initdata = { 263static struct fixed_phy_status bcm47xx_fixed_phy_status __initdata = {
232 .link = 1, 264 .link = 1,
233 .speed = SPEED_100, 265 .speed = SPEED_100,
@@ -248,6 +280,9 @@ static int __init bcm47xx_register_bus_complete(void)
248 break; 280 break;
249#endif 281#endif
250 } 282 }
283 bcm47xx_buttons_register();
284 bcm47xx_leds_register();
285
251 fixed_phy_add(PHY_POLL, 0, &bcm47xx_fixed_phy_status); 286 fixed_phy_add(PHY_POLL, 0, &bcm47xx_fixed_phy_status);
252 return 0; 287 return 0;
253} 288}
diff --git a/arch/mips/bcm47xx/sprom.c b/arch/mips/bcm47xx/sprom.c
index ad03c931b905..a8b5408dd349 100644
--- a/arch/mips/bcm47xx/sprom.c
+++ b/arch/mips/bcm47xx/sprom.c
@@ -135,7 +135,7 @@ static void nvram_read_leddc(const char *prefix, const char *name,
135} 135}
136 136
137static void nvram_read_macaddr(const char *prefix, const char *name, 137static void nvram_read_macaddr(const char *prefix, const char *name,
138 u8 (*val)[6], bool fallback) 138 u8 val[6], bool fallback)
139{ 139{
140 char buf[100]; 140 char buf[100];
141 int err; 141 int err;
@@ -144,11 +144,11 @@ static void nvram_read_macaddr(const char *prefix, const char *name,
144 if (err < 0) 144 if (err < 0)
145 return; 145 return;
146 146
147 bcm47xx_nvram_parse_macaddr(buf, *val); 147 bcm47xx_nvram_parse_macaddr(buf, val);
148} 148}
149 149
150static void nvram_read_alpha2(const char *prefix, const char *name, 150static void nvram_read_alpha2(const char *prefix, const char *name,
151 char (*val)[2], bool fallback) 151 char val[2], bool fallback)
152{ 152{
153 char buf[10]; 153 char buf[10];
154 int err; 154 int err;
@@ -162,7 +162,7 @@ static void nvram_read_alpha2(const char *prefix, const char *name,
162 pr_warn("alpha2 is too long %s\n", buf); 162 pr_warn("alpha2 is too long %s\n", buf);
163 return; 163 return;
164 } 164 }
165 memcpy(val, buf, sizeof(val)); 165 memcpy(val, buf, 2);
166} 166}
167 167
168static void bcm47xx_fill_sprom_r1234589(struct ssb_sprom *sprom, 168static void bcm47xx_fill_sprom_r1234589(struct ssb_sprom *sprom,
@@ -180,7 +180,7 @@ static void bcm47xx_fill_sprom_r1234589(struct ssb_sprom *sprom,
180 fallback); 180 fallback);
181 nvram_read_s8(prefix, NULL, "ag1", &sprom->antenna_gain.a1, 0, 181 nvram_read_s8(prefix, NULL, "ag1", &sprom->antenna_gain.a1, 0,
182 fallback); 182 fallback);
183 nvram_read_alpha2(prefix, "ccode", &sprom->alpha2, fallback); 183 nvram_read_alpha2(prefix, "ccode", sprom->alpha2, fallback);
184} 184}
185 185
186static void bcm47xx_fill_sprom_r12389(struct ssb_sprom *sprom, 186static void bcm47xx_fill_sprom_r12389(struct ssb_sprom *sprom,
@@ -633,20 +633,20 @@ static void bcm47xx_fill_sprom_path_r45(struct ssb_sprom *sprom,
633static void bcm47xx_fill_sprom_ethernet(struct ssb_sprom *sprom, 633static void bcm47xx_fill_sprom_ethernet(struct ssb_sprom *sprom,
634 const char *prefix, bool fallback) 634 const char *prefix, bool fallback)
635{ 635{
636 nvram_read_macaddr(prefix, "et0macaddr", &sprom->et0mac, fallback); 636 nvram_read_macaddr(prefix, "et0macaddr", sprom->et0mac, fallback);
637 nvram_read_u8(prefix, NULL, "et0mdcport", &sprom->et0mdcport, 0, 637 nvram_read_u8(prefix, NULL, "et0mdcport", &sprom->et0mdcport, 0,
638 fallback); 638 fallback);
639 nvram_read_u8(prefix, NULL, "et0phyaddr", &sprom->et0phyaddr, 0, 639 nvram_read_u8(prefix, NULL, "et0phyaddr", &sprom->et0phyaddr, 0,
640 fallback); 640 fallback);
641 641
642 nvram_read_macaddr(prefix, "et1macaddr", &sprom->et1mac, fallback); 642 nvram_read_macaddr(prefix, "et1macaddr", sprom->et1mac, fallback);
643 nvram_read_u8(prefix, NULL, "et1mdcport", &sprom->et1mdcport, 0, 643 nvram_read_u8(prefix, NULL, "et1mdcport", &sprom->et1mdcport, 0,
644 fallback); 644 fallback);
645 nvram_read_u8(prefix, NULL, "et1phyaddr", &sprom->et1phyaddr, 0, 645 nvram_read_u8(prefix, NULL, "et1phyaddr", &sprom->et1phyaddr, 0,
646 fallback); 646 fallback);
647 647
648 nvram_read_macaddr(prefix, "macaddr", &sprom->il0mac, fallback); 648 nvram_read_macaddr(prefix, "macaddr", sprom->il0mac, fallback);
649 nvram_read_macaddr(prefix, "il0macaddr", &sprom->il0mac, fallback); 649 nvram_read_macaddr(prefix, "il0macaddr", sprom->il0mac, fallback);
650} 650}
651 651
652static void bcm47xx_fill_board_data(struct ssb_sprom *sprom, const char *prefix, 652static void bcm47xx_fill_board_data(struct ssb_sprom *sprom, const char *prefix,
diff --git a/arch/mips/bcm47xx/wgt634u.c b/arch/mips/bcm47xx/wgt634u.c
deleted file mode 100644
index c63a4c287b5c..000000000000
--- a/arch/mips/bcm47xx/wgt634u.c
+++ /dev/null
@@ -1,174 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2007 Aurelien Jarno <aurelien@aurel32.net>
7 */
8
9#include <linux/platform_device.h>
10#include <linux/module.h>
11#include <linux/leds.h>
12#include <linux/mtd/physmap.h>
13#include <linux/ssb/ssb.h>
14#include <linux/ssb/ssb_embedded.h>
15#include <linux/interrupt.h>
16#include <linux/reboot.h>
17#include <linux/gpio.h>
18#include <asm/mach-bcm47xx/bcm47xx.h>
19
20/* GPIO definitions for the WGT634U */
21#define WGT634U_GPIO_LED 3
22#define WGT634U_GPIO_RESET 2
23#define WGT634U_GPIO_TP1 7
24#define WGT634U_GPIO_TP2 6
25#define WGT634U_GPIO_TP3 5
26#define WGT634U_GPIO_TP4 4
27#define WGT634U_GPIO_TP5 1
28
29static struct gpio_led wgt634u_leds[] = {
30 {
31 .name = "power",
32 .gpio = WGT634U_GPIO_LED,
33 .active_low = 1,
34 .default_trigger = "heartbeat",
35 },
36};
37
38static struct gpio_led_platform_data wgt634u_led_data = {
39 .num_leds = ARRAY_SIZE(wgt634u_leds),
40 .leds = wgt634u_leds,
41};
42
43static struct platform_device wgt634u_gpio_leds = {
44 .name = "leds-gpio",
45 .id = -1,
46 .dev = {
47 .platform_data = &wgt634u_led_data,
48 }
49};
50
51
52/* 8MiB flash. The struct mtd_partition matches original Netgear WGT634U
53 firmware. */
54static struct mtd_partition wgt634u_partitions[] = {
55 {
56 .name = "cfe",
57 .offset = 0,
58 .size = 0x60000, /* 384k */
59 .mask_flags = MTD_WRITEABLE /* force read-only */
60 },
61 {
62 .name = "config",
63 .offset = 0x60000,
64 .size = 0x20000 /* 128k */
65 },
66 {
67 .name = "linux",
68 .offset = 0x80000,
69 .size = 0x140000 /* 1280k */
70 },
71 {
72 .name = "jffs",
73 .offset = 0x1c0000,
74 .size = 0x620000 /* 6272k */
75 },
76 {
77 .name = "nvram",
78 .offset = 0x7e0000,
79 .size = 0x20000 /* 128k */
80 },
81};
82
83static struct physmap_flash_data wgt634u_flash_data = {
84 .parts = wgt634u_partitions,
85 .nr_parts = ARRAY_SIZE(wgt634u_partitions)
86};
87
88static struct resource wgt634u_flash_resource = {
89 .flags = IORESOURCE_MEM,
90};
91
92static struct platform_device wgt634u_flash = {
93 .name = "physmap-flash",
94 .id = 0,
95 .dev = { .platform_data = &wgt634u_flash_data, },
96 .resource = &wgt634u_flash_resource,
97 .num_resources = 1,
98};
99
100/* Platform devices */
101static struct platform_device *wgt634u_devices[] __initdata = {
102 &wgt634u_flash,
103 &wgt634u_gpio_leds,
104};
105
106static irqreturn_t gpio_interrupt(int irq, void *ignored)
107{
108 int state;
109
110 /* Interrupts are shared, check if the current one is
111 a GPIO interrupt. */
112 if (!ssb_chipco_irq_status(&bcm47xx_bus.ssb.chipco,
113 SSB_CHIPCO_IRQ_GPIO))
114 return IRQ_NONE;
115
116 state = gpio_get_value(WGT634U_GPIO_RESET);
117
118 /* Interrupt are level triggered, revert the interrupt polarity
119 to clear the interrupt. */
120 ssb_gpio_polarity(&bcm47xx_bus.ssb, 1 << WGT634U_GPIO_RESET,
121 state ? 1 << WGT634U_GPIO_RESET : 0);
122
123 if (!state) {
124 printk(KERN_INFO "Reset button pressed");
125 ctrl_alt_del();
126 }
127
128 return IRQ_HANDLED;
129}
130
131static int __init wgt634u_init(void)
132{
133 /* There is no easy way to detect that we are running on a WGT634U
134 * machine. Use the MAC address as an heuristic. Netgear Inc. has
135 * been allocated ranges 00:09:5b:xx:xx:xx and 00:0f:b5:xx:xx:xx.
136 */
137 u8 *et0mac;
138
139 if (bcm47xx_bus_type != BCM47XX_BUS_TYPE_SSB)
140 return -ENODEV;
141
142 et0mac = bcm47xx_bus.ssb.sprom.et0mac;
143
144 if (et0mac[0] == 0x00 &&
145 ((et0mac[1] == 0x09 && et0mac[2] == 0x5b) ||
146 (et0mac[1] == 0x0f && et0mac[2] == 0xb5))) {
147 struct ssb_mipscore *mcore = &bcm47xx_bus.ssb.mipscore;
148
149 printk(KERN_INFO "WGT634U machine detected.\n");
150
151 if (!request_irq(gpio_to_irq(WGT634U_GPIO_RESET),
152 gpio_interrupt, IRQF_SHARED,
153 "WGT634U GPIO", &bcm47xx_bus.ssb.chipco)) {
154 gpio_direction_input(WGT634U_GPIO_RESET);
155 ssb_gpio_intmask(&bcm47xx_bus.ssb,
156 1 << WGT634U_GPIO_RESET,
157 1 << WGT634U_GPIO_RESET);
158 ssb_chipco_irq_mask(&bcm47xx_bus.ssb.chipco,
159 SSB_CHIPCO_IRQ_GPIO,
160 SSB_CHIPCO_IRQ_GPIO);
161 }
162
163 wgt634u_flash_data.width = mcore->pflash.buswidth;
164 wgt634u_flash_resource.start = mcore->pflash.window;
165 wgt634u_flash_resource.end = mcore->pflash.window
166 + mcore->pflash.window_size
167 - 1;
168 return platform_add_devices(wgt634u_devices,
169 ARRAY_SIZE(wgt634u_devices));
170 } else
171 return -ENODEV;
172}
173
174module_init(wgt634u_init);
diff --git a/arch/mips/bcm63xx/Kconfig b/arch/mips/bcm63xx/Kconfig
index b78306ce56c7..a057fdf111c6 100644
--- a/arch/mips/bcm63xx/Kconfig
+++ b/arch/mips/bcm63xx/Kconfig
@@ -3,33 +3,41 @@ menu "CPU support"
3 3
4config BCM63XX_CPU_3368 4config BCM63XX_CPU_3368
5 bool "support 3368 CPU" 5 bool "support 3368 CPU"
6 select SYS_HAS_CPU_BMIPS4350
6 select HW_HAS_PCI 7 select HW_HAS_PCI
7 8
8config BCM63XX_CPU_6328 9config BCM63XX_CPU_6328
9 bool "support 6328 CPU" 10 bool "support 6328 CPU"
11 select SYS_HAS_CPU_BMIPS4350
10 select HW_HAS_PCI 12 select HW_HAS_PCI
11 13
12config BCM63XX_CPU_6338 14config BCM63XX_CPU_6338
13 bool "support 6338 CPU" 15 bool "support 6338 CPU"
16 select SYS_HAS_CPU_BMIPS32_3300
14 select HW_HAS_PCI 17 select HW_HAS_PCI
15 18
16config BCM63XX_CPU_6345 19config BCM63XX_CPU_6345
17 bool "support 6345 CPU" 20 bool "support 6345 CPU"
21 select SYS_HAS_CPU_BMIPS32_3300
18 22
19config BCM63XX_CPU_6348 23config BCM63XX_CPU_6348
20 bool "support 6348 CPU" 24 bool "support 6348 CPU"
25 select SYS_HAS_CPU_BMIPS32_3300
21 select HW_HAS_PCI 26 select HW_HAS_PCI
22 27
23config BCM63XX_CPU_6358 28config BCM63XX_CPU_6358
24 bool "support 6358 CPU" 29 bool "support 6358 CPU"
30 select SYS_HAS_CPU_BMIPS4350
25 select HW_HAS_PCI 31 select HW_HAS_PCI
26 32
27config BCM63XX_CPU_6362 33config BCM63XX_CPU_6362
28 bool "support 6362 CPU" 34 bool "support 6362 CPU"
35 select SYS_HAS_CPU_BMIPS4350
29 select HW_HAS_PCI 36 select HW_HAS_PCI
30 37
31config BCM63XX_CPU_6368 38config BCM63XX_CPU_6368
32 bool "support 6368 CPU" 39 bool "support 6368 CPU"
40 select SYS_HAS_CPU_BMIPS4350
33 select HW_HAS_PCI 41 select HW_HAS_PCI
34endmenu 42endmenu
35 43
diff --git a/arch/mips/bcm63xx/Makefile b/arch/mips/bcm63xx/Makefile
index ac2807397c1c..9019f54aee69 100644
--- a/arch/mips/bcm63xx/Makefile
+++ b/arch/mips/bcm63xx/Makefile
@@ -1,7 +1,7 @@
1obj-y += clk.o cpu.o cs.o gpio.o irq.o nvram.o prom.o reset.o \ 1obj-y += clk.o cpu.o cs.o gpio.o irq.o nvram.o prom.o reset.o \
2 setup.o timer.o dev-dsp.o dev-enet.o dev-flash.o \ 2 setup.o timer.o dev-dsp.o dev-enet.o dev-flash.o \
3 dev-pcmcia.o dev-rng.o dev-spi.o dev-uart.o dev-wdt.o \ 3 dev-pcmcia.o dev-rng.o dev-spi.o dev-hsspi.o dev-uart.o \
4 dev-usb-usbd.o 4 dev-wdt.o dev-usb-usbd.o
5obj-$(CONFIG_EARLY_PRINTK) += early_printk.o 5obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
6 6
7obj-y += boards/ 7obj-y += boards/
diff --git a/arch/mips/bcm63xx/boards/board_bcm963xx.c b/arch/mips/bcm63xx/boards/board_bcm963xx.c
index 5b974eb125fc..33727e7f0c79 100644
--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
+++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
@@ -23,6 +23,7 @@
23#include <bcm63xx_dev_enet.h> 23#include <bcm63xx_dev_enet.h>
24#include <bcm63xx_dev_dsp.h> 24#include <bcm63xx_dev_dsp.h>
25#include <bcm63xx_dev_flash.h> 25#include <bcm63xx_dev_flash.h>
26#include <bcm63xx_dev_hsspi.h>
26#include <bcm63xx_dev_pcmcia.h> 27#include <bcm63xx_dev_pcmcia.h>
27#include <bcm63xx_dev_spi.h> 28#include <bcm63xx_dev_spi.h>
28#include <bcm63xx_dev_usb_usbd.h> 29#include <bcm63xx_dev_usb_usbd.h>
@@ -915,6 +916,8 @@ int __init board_register_devices(void)
915 916
916 bcm63xx_spi_register(); 917 bcm63xx_spi_register();
917 918
919 bcm63xx_hsspi_register();
920
918 bcm63xx_flash_register(); 921 bcm63xx_flash_register();
919 922
920 bcm63xx_led_data.num_leds = ARRAY_SIZE(board.leds); 923 bcm63xx_led_data.num_leds = ARRAY_SIZE(board.leds);
diff --git a/arch/mips/bcm63xx/clk.c b/arch/mips/bcm63xx/clk.c
index 43da4ae04cc2..637565284732 100644
--- a/arch/mips/bcm63xx/clk.c
+++ b/arch/mips/bcm63xx/clk.c
@@ -226,6 +226,28 @@ static struct clk clk_spi = {
226}; 226};
227 227
228/* 228/*
229 * HSSPI clock
230 */
231static void hsspi_set(struct clk *clk, int enable)
232{
233 u32 mask;
234
235 if (BCMCPU_IS_6328())
236 mask = CKCTL_6328_HSSPI_EN;
237 else if (BCMCPU_IS_6362())
238 mask = CKCTL_6362_HSSPI_EN;
239 else
240 return;
241
242 bcm_hwclock_set(mask, enable);
243}
244
245static struct clk clk_hsspi = {
246 .set = hsspi_set,
247};
248
249
250/*
229 * XTM clock 251 * XTM clock
230 */ 252 */
231static void xtm_set(struct clk *clk, int enable) 253static void xtm_set(struct clk *clk, int enable)
@@ -346,6 +368,8 @@ struct clk *clk_get(struct device *dev, const char *id)
346 return &clk_usbd; 368 return &clk_usbd;
347 if (!strcmp(id, "spi")) 369 if (!strcmp(id, "spi"))
348 return &clk_spi; 370 return &clk_spi;
371 if (!strcmp(id, "hsspi"))
372 return &clk_hsspi;
349 if (!strcmp(id, "xtm")) 373 if (!strcmp(id, "xtm"))
350 return &clk_xtm; 374 return &clk_xtm;
351 if (!strcmp(id, "periph")) 375 if (!strcmp(id, "periph"))
@@ -366,3 +390,21 @@ void clk_put(struct clk *clk)
366} 390}
367 391
368EXPORT_SYMBOL(clk_put); 392EXPORT_SYMBOL(clk_put);
393
394#define HSSPI_PLL_HZ_6328 133333333
395#define HSSPI_PLL_HZ_6362 400000000
396
397static int __init bcm63xx_clk_init(void)
398{
399 switch (bcm63xx_get_cpu_id()) {
400 case BCM6328_CPU_ID:
401 clk_hsspi.rate = HSSPI_PLL_HZ_6328;
402 break;
403 case BCM6362_CPU_ID:
404 clk_hsspi.rate = HSSPI_PLL_HZ_6362;
405 break;
406 }
407
408 return 0;
409}
410arch_initcall(bcm63xx_clk_init);
diff --git a/arch/mips/bcm63xx/cpu.c b/arch/mips/bcm63xx/cpu.c
index b713cd64b087..1b1b8a89959b 100644
--- a/arch/mips/bcm63xx/cpu.c
+++ b/arch/mips/bcm63xx/cpu.c
@@ -123,7 +123,9 @@ unsigned int bcm63xx_get_memory_size(void)
123 123
124static unsigned int detect_cpu_clock(void) 124static unsigned int detect_cpu_clock(void)
125{ 125{
126 switch (bcm63xx_get_cpu_id()) { 126 u16 cpu_id = bcm63xx_get_cpu_id();
127
128 switch (cpu_id) {
127 case BCM3368_CPU_ID: 129 case BCM3368_CPU_ID:
128 return 300000000; 130 return 300000000;
129 131
@@ -249,7 +251,7 @@ static unsigned int detect_cpu_clock(void)
249 } 251 }
250 252
251 default: 253 default:
252 BUG(); 254 panic("Failed to detect clock for CPU with id=%04X\n", cpu_id);
253 } 255 }
254} 256}
255 257
diff --git a/arch/mips/bcm63xx/dev-hsspi.c b/arch/mips/bcm63xx/dev-hsspi.c
new file mode 100644
index 000000000000..696abc48e3c8
--- /dev/null
+++ b/arch/mips/bcm63xx/dev-hsspi.c
@@ -0,0 +1,47 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2012 Jonas Gorski <jonas.gorski@gmail.com>
7 */
8
9#include <linux/init.h>
10#include <linux/kernel.h>
11#include <linux/platform_device.h>
12
13#include <bcm63xx_cpu.h>
14#include <bcm63xx_dev_hsspi.h>
15#include <bcm63xx_regs.h>
16
17static struct resource spi_resources[] = {
18 {
19 .start = -1, /* filled at runtime */
20 .end = -1, /* filled at runtime */
21 .flags = IORESOURCE_MEM,
22 },
23 {
24 .start = -1, /* filled at runtime */
25 .flags = IORESOURCE_IRQ,
26 },
27};
28
29static struct platform_device bcm63xx_hsspi_device = {
30 .name = "bcm63xx-hsspi",
31 .id = 0,
32 .num_resources = ARRAY_SIZE(spi_resources),
33 .resource = spi_resources,
34};
35
36int __init bcm63xx_hsspi_register(void)
37{
38 if (!BCMCPU_IS_6328() && !BCMCPU_IS_6362())
39 return -ENODEV;
40
41 spi_resources[0].start = bcm63xx_regset_address(RSET_HSSPI);
42 spi_resources[0].end = spi_resources[0].start;
43 spi_resources[0].end += RSET_HSSPI_SIZE - 1;
44 spi_resources[1].start = bcm63xx_get_irq_number(IRQ_HSSPI);
45
46 return platform_device_register(&bcm63xx_hsspi_device);
47}
diff --git a/arch/mips/bcm63xx/early_printk.c b/arch/mips/bcm63xx/early_printk.c
index aa8f7f9cc7a4..6092226a6d76 100644
--- a/arch/mips/bcm63xx/early_printk.c
+++ b/arch/mips/bcm63xx/early_printk.c
@@ -6,9 +6,8 @@
6 * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr> 6 * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
7 */ 7 */
8 8
9#include <linux/init.h>
10#include <bcm63xx_io.h> 9#include <bcm63xx_io.h>
11#include <bcm63xx_regs.h> 10#include <linux/serial_bcm63xx.h>
12 11
13static void wait_xfered(void) 12static void wait_xfered(void)
14{ 13{
diff --git a/arch/mips/bcm63xx/prom.c b/arch/mips/bcm63xx/prom.c
index 8ac4e095e68e..e1f27d653f60 100644
--- a/arch/mips/bcm63xx/prom.c
+++ b/arch/mips/bcm63xx/prom.c
@@ -59,14 +59,12 @@ void __init prom_init(void)
59 /* do low level board init */ 59 /* do low level board init */
60 board_prom_init(); 60 board_prom_init();
61 61
62 if (IS_ENABLED(CONFIG_CPU_BMIPS4350) && IS_ENABLED(CONFIG_SMP)) { 62 /* set up SMP */
63 /* set up SMP */ 63 if (!register_bmips_smp_ops()) {
64 register_smp_ops(&bmips_smp_ops);
65
66 /* 64 /*
67 * BCM6328 might not have its second CPU enabled, while BCM6358 65 * BCM6328 might not have its second CPU enabled, while BCM3368
68 * needs special handling for its shared TLB, so disable SMP 66 * and BCM6358 need special handling for their shared TLB, so
69 * for now. 67 * disable SMP for now.
70 */ 68 */
71 if (BCMCPU_IS_6328()) { 69 if (BCMCPU_IS_6328()) {
72 reg = bcm_readl(BCM_6328_OTP_BASE + 70 reg = bcm_readl(BCM_6328_OTP_BASE +
@@ -74,7 +72,7 @@ void __init prom_init(void)
74 72
75 if (reg & OTP_6328_REG3_TP1_DISABLED) 73 if (reg & OTP_6328_REG3_TP1_DISABLED)
76 bmips_smp_enabled = 0; 74 bmips_smp_enabled = 0;
77 } else if (BCMCPU_IS_6358()) { 75 } else if (BCMCPU_IS_3368() || BCMCPU_IS_6358()) {
78 bmips_smp_enabled = 0; 76 bmips_smp_enabled = 0;
79 } 77 }
80 78
diff --git a/arch/mips/boot/compressed/Makefile b/arch/mips/boot/compressed/Makefile
index ca0c343c9ea5..61af6b6ab13d 100644
--- a/arch/mips/boot/compressed/Makefile
+++ b/arch/mips/boot/compressed/Makefile
@@ -27,10 +27,10 @@ KBUILD_AFLAGS := $(LINUXINCLUDE) $(KBUILD_AFLAGS) -D__ASSEMBLY__ \
27 -DBOOT_HEAP_SIZE=$(BOOT_HEAP_SIZE) \ 27 -DBOOT_HEAP_SIZE=$(BOOT_HEAP_SIZE) \
28 -DKERNEL_ENTRY=$(VMLINUX_ENTRY_ADDRESS) 28 -DKERNEL_ENTRY=$(VMLINUX_ENTRY_ADDRESS)
29 29
30targets := head.o decompress.o dbg.o uart-16550.o uart-alchemy.o 30targets := head.o decompress.o string.o dbg.o uart-16550.o uart-alchemy.o
31 31
32# decompressor objects (linked with vmlinuz) 32# decompressor objects (linked with vmlinuz)
33vmlinuzobjs-y := $(obj)/head.o $(obj)/decompress.o $(obj)/dbg.o 33vmlinuzobjs-y := $(obj)/head.o $(obj)/decompress.o $(obj)/string.o $(obj)/dbg.o
34 34
35ifdef CONFIG_DEBUG_ZBOOT 35ifdef CONFIG_DEBUG_ZBOOT
36vmlinuzobjs-$(CONFIG_SYS_SUPPORTS_ZBOOT_UART16550) += $(obj)/uart-16550.o 36vmlinuzobjs-$(CONFIG_SYS_SUPPORTS_ZBOOT_UART16550) += $(obj)/uart-16550.o
diff --git a/arch/mips/boot/compressed/dbg.c b/arch/mips/boot/compressed/dbg.c
index 134a6162e394..06c6a5bd175d 100644
--- a/arch/mips/boot/compressed/dbg.c
+++ b/arch/mips/boot/compressed/dbg.c
@@ -6,7 +6,6 @@
6 * need to implement your own putc(). 6 * need to implement your own putc().
7 */ 7 */
8#include <linux/compiler.h> 8#include <linux/compiler.h>
9#include <linux/init.h>
10#include <linux/types.h> 9#include <linux/types.h>
11 10
12void __weak putc(char c) 11void __weak putc(char c)
diff --git a/arch/mips/boot/compressed/decompress.c b/arch/mips/boot/compressed/decompress.c
index a8c6fd6a4406..c00c4ddf4514 100644
--- a/arch/mips/boot/compressed/decompress.c
+++ b/arch/mips/boot/compressed/decompress.c
@@ -43,33 +43,11 @@ void error(char *x)
43/* activate the code for pre-boot environment */ 43/* activate the code for pre-boot environment */
44#define STATIC static 44#define STATIC static
45 45
46#if defined(CONFIG_KERNEL_GZIP) || defined(CONFIG_KERNEL_XZ) || \
47 defined(CONFIG_KERNEL_LZ4)
48void *memcpy(void *dest, const void *src, size_t n)
49{
50 int i;
51 const char *s = src;
52 char *d = dest;
53
54 for (i = 0; i < n; i++)
55 d[i] = s[i];
56 return dest;
57}
58#endif
59#ifdef CONFIG_KERNEL_GZIP 46#ifdef CONFIG_KERNEL_GZIP
60#include "../../../../lib/decompress_inflate.c" 47#include "../../../../lib/decompress_inflate.c"
61#endif 48#endif
62 49
63#ifdef CONFIG_KERNEL_BZIP2 50#ifdef CONFIG_KERNEL_BZIP2
64void *memset(void *s, int c, size_t n)
65{
66 int i;
67 char *ss = s;
68
69 for (i = 0; i < n; i++)
70 ss[i] = c;
71 return s;
72}
73#include "../../../../lib/decompress_bunzip2.c" 51#include "../../../../lib/decompress_bunzip2.c"
74#endif 52#endif
75 53
diff --git a/arch/mips/boot/compressed/string.c b/arch/mips/boot/compressed/string.c
new file mode 100644
index 000000000000..9de9885acd0d
--- /dev/null
+++ b/arch/mips/boot/compressed/string.c
@@ -0,0 +1,28 @@
1/*
2 * arch/mips/boot/compressed/string.c
3 *
4 * Very small subset of simple string routines
5 */
6
7#include <linux/types.h>
8
9void *memcpy(void *dest, const void *src, size_t n)
10{
11 int i;
12 const char *s = src;
13 char *d = dest;
14
15 for (i = 0; i < n; i++)
16 d[i] = s[i];
17 return dest;
18}
19
20void *memset(void *s, int c, size_t n)
21{
22 int i;
23 char *ss = s;
24
25 for (i = 0; i < n; i++)
26 ss[i] = c;
27 return s;
28}
diff --git a/arch/mips/boot/compressed/uart-16550.c b/arch/mips/boot/compressed/uart-16550.c
index c01d343ce6ad..237494b7a21a 100644
--- a/arch/mips/boot/compressed/uart-16550.c
+++ b/arch/mips/boot/compressed/uart-16550.c
@@ -4,7 +4,6 @@
4 4
5#include <linux/types.h> 5#include <linux/types.h>
6#include <linux/serial_reg.h> 6#include <linux/serial_reg.h>
7#include <linux/init.h>
8 7
9#include <asm/addrspace.h> 8#include <asm/addrspace.h>
10 9
@@ -19,8 +18,8 @@
19#endif 18#endif
20 19
21#ifdef CONFIG_MACH_JZ4740 20#ifdef CONFIG_MACH_JZ4740
22#define UART0_BASE 0xB0030000 21#include <asm/mach-jz4740/base.h>
23#define PORT(offset) (UART0_BASE + (4 * offset)) 22#define PORT(offset) (CKSEG1ADDR(JZ4740_UART0_BASE_ADDR) + (4 * offset))
24#endif 23#endif
25 24
26#ifdef CONFIG_CPU_XLR 25#ifdef CONFIG_CPU_XLR
diff --git a/arch/mips/cavium-octeon/executive/cvmx-cmd-queue.c b/arch/mips/cavium-octeon/executive/cvmx-cmd-queue.c
index 132bccc66a93..8241fc6aa17d 100644
--- a/arch/mips/cavium-octeon/executive/cvmx-cmd-queue.c
+++ b/arch/mips/cavium-octeon/executive/cvmx-cmd-queue.c
@@ -47,6 +47,7 @@
47 * state. It points to a bootmem named block. 47 * state. It points to a bootmem named block.
48 */ 48 */
49__cvmx_cmd_queue_all_state_t *__cvmx_cmd_queue_state_ptr; 49__cvmx_cmd_queue_all_state_t *__cvmx_cmd_queue_state_ptr;
50EXPORT_SYMBOL_GPL(__cvmx_cmd_queue_state_ptr);
50 51
51/** 52/**
52 * Initialize the Global queue state pointer. 53 * Initialize the Global queue state pointer.
diff --git a/arch/mips/cavium-octeon/executive/cvmx-helper-board.c b/arch/mips/cavium-octeon/executive/cvmx-helper-board.c
index 0a1283ce47f5..b764df64be40 100644
--- a/arch/mips/cavium-octeon/executive/cvmx-helper-board.c
+++ b/arch/mips/cavium-octeon/executive/cvmx-helper-board.c
@@ -722,3 +722,30 @@ int __cvmx_helper_board_hardware_enable(int interface)
722 } 722 }
723 return 0; 723 return 0;
724} 724}
725
726/**
727 * Get the clock type used for the USB block based on board type.
728 * Used by the USB code for auto configuration of clock type.
729 *
730 * Return USB clock type enumeration
731 */
732enum cvmx_helper_board_usb_clock_types __cvmx_helper_board_usb_get_clock_type(void)
733{
734 switch (cvmx_sysinfo_get()->board_type) {
735 case CVMX_BOARD_TYPE_BBGW_REF:
736 case CVMX_BOARD_TYPE_LANAI2_A:
737 case CVMX_BOARD_TYPE_LANAI2_U:
738 case CVMX_BOARD_TYPE_LANAI2_G:
739 case CVMX_BOARD_TYPE_NIC10E_66:
740 case CVMX_BOARD_TYPE_UBNT_E100:
741 return USB_CLOCK_TYPE_CRYSTAL_12;
742 case CVMX_BOARD_TYPE_NIC10E:
743 return USB_CLOCK_TYPE_REF_12;
744 default:
745 break;
746 }
747 /* Most boards except NIC10e use a 12MHz crystal */
748 if (OCTEON_IS_MODEL(OCTEON_FAM_2))
749 return USB_CLOCK_TYPE_CRYSTAL_12;
750 return USB_CLOCK_TYPE_REF_48;
751}
diff --git a/arch/mips/cavium-octeon/executive/cvmx-helper-util.c b/arch/mips/cavium-octeon/executive/cvmx-helper-util.c
index 65d2bc9a0bde..453d7f66459a 100644
--- a/arch/mips/cavium-octeon/executive/cvmx-helper-util.c
+++ b/arch/mips/cavium-octeon/executive/cvmx-helper-util.c
@@ -251,6 +251,7 @@ int cvmx_helper_setup_red(int pass_thresh, int drop_thresh)
251 251
252 return 0; 252 return 0;
253} 253}
254EXPORT_SYMBOL_GPL(cvmx_helper_setup_red);
254 255
255/** 256/**
256 * Setup the common GMX settings that determine the number of 257 * Setup the common GMX settings that determine the number of
@@ -384,6 +385,7 @@ int cvmx_helper_get_ipd_port(int interface, int port)
384 } 385 }
385 return -1; 386 return -1;
386} 387}
388EXPORT_SYMBOL_GPL(cvmx_helper_get_ipd_port);
387 389
388/** 390/**
389 * Returns the interface number for an IPD/PKO port number. 391 * Returns the interface number for an IPD/PKO port number.
@@ -408,6 +410,7 @@ int cvmx_helper_get_interface_num(int ipd_port)
408 410
409 return -1; 411 return -1;
410} 412}
413EXPORT_SYMBOL_GPL(cvmx_helper_get_interface_num);
411 414
412/** 415/**
413 * Returns the interface index number for an IPD/PKO port 416 * Returns the interface index number for an IPD/PKO port
@@ -431,3 +434,4 @@ int cvmx_helper_get_interface_index_num(int ipd_port)
431 434
432 return -1; 435 return -1;
433} 436}
437EXPORT_SYMBOL_GPL(cvmx_helper_get_interface_index_num);
diff --git a/arch/mips/cavium-octeon/executive/cvmx-helper.c b/arch/mips/cavium-octeon/executive/cvmx-helper.c
index d63d20dfbfb0..8553ad5c72b6 100644
--- a/arch/mips/cavium-octeon/executive/cvmx-helper.c
+++ b/arch/mips/cavium-octeon/executive/cvmx-helper.c
@@ -67,7 +67,7 @@ void (*cvmx_override_pko_queue_priority) (int pko_port,
67void (*cvmx_override_ipd_port_setup) (int ipd_port); 67void (*cvmx_override_ipd_port_setup) (int ipd_port);
68 68
69/* Port count per interface */ 69/* Port count per interface */
70static int interface_port_count[4] = { 0, 0, 0, 0 }; 70static int interface_port_count[5];
71 71
72/* Port last configured link info index by IPD/PKO port */ 72/* Port last configured link info index by IPD/PKO port */
73static cvmx_helper_link_info_t 73static cvmx_helper_link_info_t
@@ -88,6 +88,7 @@ int cvmx_helper_get_number_of_interfaces(void)
88 else 88 else
89 return 3; 89 return 3;
90} 90}
91EXPORT_SYMBOL_GPL(cvmx_helper_get_number_of_interfaces);
91 92
92/** 93/**
93 * Return the number of ports on an interface. Depending on the 94 * Return the number of ports on an interface. Depending on the
@@ -102,6 +103,7 @@ int cvmx_helper_ports_on_interface(int interface)
102{ 103{
103 return interface_port_count[interface]; 104 return interface_port_count[interface];
104} 105}
106EXPORT_SYMBOL_GPL(cvmx_helper_ports_on_interface);
105 107
106/** 108/**
107 * Get the operating mode of an interface. Depending on the Octeon 109 * Get the operating mode of an interface. Depending on the Octeon
@@ -179,6 +181,7 @@ cvmx_helper_interface_mode_t cvmx_helper_interface_get_mode(int interface)
179 return CVMX_HELPER_INTERFACE_MODE_RGMII; 181 return CVMX_HELPER_INTERFACE_MODE_RGMII;
180 } 182 }
181} 183}
184EXPORT_SYMBOL_GPL(cvmx_helper_interface_get_mode);
182 185
183/** 186/**
184 * Configure the IPD/PIP tagging and QoS options for a specific 187 * Configure the IPD/PIP tagging and QoS options for a specific
@@ -825,6 +828,7 @@ int cvmx_helper_ipd_and_packet_input_enable(void)
825 __cvmx_helper_errata_fix_ipd_ptr_alignment(); 828 __cvmx_helper_errata_fix_ipd_ptr_alignment();
826 return 0; 829 return 0;
827} 830}
831EXPORT_SYMBOL_GPL(cvmx_helper_ipd_and_packet_input_enable);
828 832
829/** 833/**
830 * Initialize the PIP, IPD, and PKO hardware to support 834 * Initialize the PIP, IPD, and PKO hardware to support
@@ -903,6 +907,7 @@ int cvmx_helper_initialize_packet_io_global(void)
903#endif 907#endif
904 return result; 908 return result;
905} 909}
910EXPORT_SYMBOL_GPL(cvmx_helper_initialize_packet_io_global);
906 911
907/** 912/**
908 * Does core local initialization for packet io 913 * Does core local initialization for packet io
@@ -947,6 +952,7 @@ cvmx_helper_link_info_t cvmx_helper_link_autoconf(int ipd_port)
947 */ 952 */
948 return port_link_info[ipd_port]; 953 return port_link_info[ipd_port];
949} 954}
955EXPORT_SYMBOL_GPL(cvmx_helper_link_autoconf);
950 956
951/** 957/**
952 * Return the link state of an IPD/PKO port as returned by 958 * Return the link state of an IPD/PKO port as returned by
@@ -1005,6 +1011,7 @@ cvmx_helper_link_info_t cvmx_helper_link_get(int ipd_port)
1005 } 1011 }
1006 return result; 1012 return result;
1007} 1013}
1014EXPORT_SYMBOL_GPL(cvmx_helper_link_get);
1008 1015
1009/** 1016/**
1010 * Configure an IPD/PKO port for the specified link state. This 1017 * Configure an IPD/PKO port for the specified link state. This
@@ -1060,6 +1067,7 @@ int cvmx_helper_link_set(int ipd_port, cvmx_helper_link_info_t link_info)
1060 port_link_info[ipd_port].u64 = link_info.u64; 1067 port_link_info[ipd_port].u64 = link_info.u64;
1061 return result; 1068 return result;
1062} 1069}
1070EXPORT_SYMBOL_GPL(cvmx_helper_link_set);
1063 1071
1064/** 1072/**
1065 * Configure a port for internal and/or external loopback. Internal loopback 1073 * Configure a port for internal and/or external loopback. Internal loopback
diff --git a/arch/mips/cavium-octeon/executive/cvmx-pko.c b/arch/mips/cavium-octeon/executive/cvmx-pko.c
index f2c877541597..008b881cdf64 100644
--- a/arch/mips/cavium-octeon/executive/cvmx-pko.c
+++ b/arch/mips/cavium-octeon/executive/cvmx-pko.c
@@ -140,7 +140,7 @@ void cvmx_pko_disable(void)
140 pko_reg_flags.s.ena_pko = 0; 140 pko_reg_flags.s.ena_pko = 0;
141 cvmx_write_csr(CVMX_PKO_REG_FLAGS, pko_reg_flags.u64); 141 cvmx_write_csr(CVMX_PKO_REG_FLAGS, pko_reg_flags.u64);
142} 142}
143 143EXPORT_SYMBOL_GPL(cvmx_pko_disable);
144 144
145/** 145/**
146 * Reset the packet output. 146 * Reset the packet output.
@@ -182,6 +182,7 @@ void cvmx_pko_shutdown(void)
182 } 182 }
183 __cvmx_pko_reset(); 183 __cvmx_pko_reset();
184} 184}
185EXPORT_SYMBOL_GPL(cvmx_pko_shutdown);
185 186
186/** 187/**
187 * Configure a output port and the associated queues for use. 188 * Configure a output port and the associated queues for use.
diff --git a/arch/mips/cavium-octeon/executive/cvmx-spi.c b/arch/mips/cavium-octeon/executive/cvmx-spi.c
index ef5198d13a0e..459e3b1eb61f 100644
--- a/arch/mips/cavium-octeon/executive/cvmx-spi.c
+++ b/arch/mips/cavium-octeon/executive/cvmx-spi.c
@@ -177,6 +177,7 @@ int cvmx_spi_restart_interface(int interface, cvmx_spi_mode_t mode, int timeout)
177 177
178 return res; 178 return res;
179} 179}
180EXPORT_SYMBOL_GPL(cvmx_spi_restart_interface);
180 181
181/** 182/**
182 * Callback to perform SPI4 reset 183 * Callback to perform SPI4 reset
diff --git a/arch/mips/cavium-octeon/octeon-platform.c b/arch/mips/cavium-octeon/octeon-platform.c
index 1830874ff1e2..6df0f4d8f197 100644
--- a/arch/mips/cavium-octeon/octeon-platform.c
+++ b/arch/mips/cavium-octeon/octeon-platform.c
@@ -171,6 +171,7 @@ device_initcall(octeon_ohci_device_init);
171static struct of_device_id __initdata octeon_ids[] = { 171static struct of_device_id __initdata octeon_ids[] = {
172 { .compatible = "simple-bus", }, 172 { .compatible = "simple-bus", },
173 { .compatible = "cavium,octeon-6335-uctl", }, 173 { .compatible = "cavium,octeon-6335-uctl", },
174 { .compatible = "cavium,octeon-5750-usbn", },
174 { .compatible = "cavium,octeon-3860-bootbus", }, 175 { .compatible = "cavium,octeon-3860-bootbus", },
175 { .compatible = "cavium,mdio-mux", }, 176 { .compatible = "cavium,mdio-mux", },
176 { .compatible = "gpio-leds", }, 177 { .compatible = "gpio-leds", },
@@ -336,14 +337,14 @@ static void __init octeon_fdt_pip_iface(int pip, int idx, u64 *pmac)
336 int p; 337 int p;
337 int count = 0; 338 int count = 0;
338 339
339 if (cvmx_helper_interface_enumerate(idx) == 0)
340 count = cvmx_helper_ports_on_interface(idx);
341
342 snprintf(name_buffer, sizeof(name_buffer), "interface@%d", idx); 340 snprintf(name_buffer, sizeof(name_buffer), "interface@%d", idx);
343 iface = fdt_subnode_offset(initial_boot_params, pip, name_buffer); 341 iface = fdt_subnode_offset(initial_boot_params, pip, name_buffer);
344 if (iface < 0) 342 if (iface < 0)
345 return; 343 return;
346 344
345 if (cvmx_helper_interface_enumerate(idx) == 0)
346 count = cvmx_helper_ports_on_interface(idx);
347
347 for (p = 0; p < 16; p++) 348 for (p = 0; p < 16; p++)
348 octeon_fdt_pip_port(iface, idx, p, count - 1, pmac); 349 octeon_fdt_pip_port(iface, idx, p, count - 1, pmac);
349} 350}
@@ -682,6 +683,37 @@ end_led:
682 } 683 }
683 } 684 }
684 685
686 /* DWC2 USB */
687 alias_prop = fdt_getprop(initial_boot_params, aliases,
688 "usbn", NULL);
689 if (alias_prop) {
690 int usbn = fdt_path_offset(initial_boot_params, alias_prop);
691
692 if (usbn >= 0 && (current_cpu_type() == CPU_CAVIUM_OCTEON2 ||
693 !octeon_has_feature(OCTEON_FEATURE_USB))) {
694 pr_debug("Deleting usbn\n");
695 fdt_nop_node(initial_boot_params, usbn);
696 fdt_nop_property(initial_boot_params, aliases, "usbn");
697 } else {
698 __be32 new_f[1];
699 enum cvmx_helper_board_usb_clock_types c;
700 c = __cvmx_helper_board_usb_get_clock_type();
701 switch (c) {
702 case USB_CLOCK_TYPE_REF_48:
703 new_f[0] = cpu_to_be32(48000000);
704 fdt_setprop_inplace(initial_boot_params, usbn,
705 "refclk-frequency", new_f, sizeof(new_f));
706 /* Fall through ...*/
707 case USB_CLOCK_TYPE_REF_12:
708 /* Missing "refclk-type" defaults to external. */
709 fdt_nop_property(initial_boot_params, usbn, "refclk-type");
710 break;
711 default:
712 break;
713 }
714 }
715 }
716
685 return 0; 717 return 0;
686} 718}
687 719
diff --git a/arch/mips/cavium-octeon/octeon_3xxx.dts b/arch/mips/cavium-octeon/octeon_3xxx.dts
index 88cb42d4cc49..fa33115bde33 100644
--- a/arch/mips/cavium-octeon/octeon_3xxx.dts
+++ b/arch/mips/cavium-octeon/octeon_3xxx.dts
@@ -550,6 +550,24 @@
550 big-endian-regs; 550 big-endian-regs;
551 }; 551 };
552 }; 552 };
553
554 usbn: usbn@1180068000000 {
555 compatible = "cavium,octeon-5750-usbn";
556 reg = <0x11800 0x68000000 0x0 0x1000>;
557 ranges; /* Direct mapping */
558 #address-cells = <2>;
559 #size-cells = <2>;
560 /* 12MHz, 24MHz and 48MHz allowed */
561 refclk-frequency = <12000000>;
562 /* Either "crystal" or "external" */
563 refclk-type = "crystal";
564
565 usbc@16f0010000000 {
566 compatible = "cavium,octeon-5750-usbc";
567 reg = <0x16f00 0x10000000 0x0 0x80000>;
568 interrupts = <0 56>;
569 };
570 };
553 }; 571 };
554 572
555 aliases { 573 aliases {
@@ -566,6 +584,7 @@
566 flash0 = &flash0; 584 flash0 = &flash0;
567 cf0 = &cf0; 585 cf0 = &cf0;
568 uctl = &uctl; 586 uctl = &uctl;
587 usbn = &usbn;
569 led0 = &led0; 588 led0 = &led0;
570 }; 589 };
571 }; 590 };
diff --git a/arch/mips/cavium-octeon/smp.c b/arch/mips/cavium-octeon/smp.c
index 24a2167db778..67a078ffc464 100644
--- a/arch/mips/cavium-octeon/smp.c
+++ b/arch/mips/cavium-octeon/smp.c
@@ -6,7 +6,6 @@
6 * Copyright (C) 2004-2008, 2009, 2010 Cavium Networks 6 * Copyright (C) 2004-2008, 2009, 2010 Cavium Networks
7 */ 7 */
8#include <linux/cpu.h> 8#include <linux/cpu.h>
9#include <linux/init.h>
10#include <linux/delay.h> 9#include <linux/delay.h>
11#include <linux/smp.h> 10#include <linux/smp.h>
12#include <linux/interrupt.h> 11#include <linux/interrupt.h>
diff --git a/arch/mips/configs/ar7_defconfig b/arch/mips/configs/ar7_defconfig
index 80e012fa409c..320772caf054 100644
--- a/arch/mips/configs/ar7_defconfig
+++ b/arch/mips/configs/ar7_defconfig
@@ -86,7 +86,6 @@ CONFIG_MAC80211_RC_DEFAULT_PID=y
86CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" 86CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
87# CONFIG_FIRMWARE_IN_KERNEL is not set 87# CONFIG_FIRMWARE_IN_KERNEL is not set
88CONFIG_MTD=y 88CONFIG_MTD=y
89CONFIG_MTD_PARTITIONS=y
90CONFIG_MTD_CHAR=y 89CONFIG_MTD_CHAR=y
91CONFIG_MTD_BLOCK=y 90CONFIG_MTD_BLOCK=y
92CONFIG_MTD_CFI=y 91CONFIG_MTD_CFI=y
diff --git a/arch/mips/configs/bcm47xx_defconfig b/arch/mips/configs/bcm47xx_defconfig
index 4ca8e5c99225..0db4eb319e0a 100644
--- a/arch/mips/configs/bcm47xx_defconfig
+++ b/arch/mips/configs/bcm47xx_defconfig
@@ -1,623 +1,86 @@
1CONFIG_BCM47XX=y 1CONFIG_BCM47XX=y
2CONFIG_NO_HZ=y
3CONFIG_HIGH_RES_TIMERS=y
4CONFIG_KEXEC=y
5# CONFIG_SECCOMP is not set
6CONFIG_EXPERIMENTAL=y
7# CONFIG_LOCALVERSION_AUTO is not set
8CONFIG_SYSVIPC=y 2CONFIG_SYSVIPC=y
9CONFIG_POSIX_MQUEUE=y 3CONFIG_HIGH_RES_TIMERS=y
10CONFIG_BSD_PROCESS_ACCT=y 4CONFIG_UIDGID_STRICT_TYPE_CHECKS=y
11CONFIG_BSD_PROCESS_ACCT_V3=y
12CONFIG_TASKSTATS=y
13CONFIG_TASK_DELAY_ACCT=y
14CONFIG_TASK_XACCT=y
15CONFIG_TASK_IO_ACCOUNTING=y
16CONFIG_AUDIT=y
17CONFIG_TINY_RCU=y
18CONFIG_CGROUPS=y
19CONFIG_CGROUP_CPUACCT=y
20CONFIG_RELAY=y
21CONFIG_BLK_DEV_INITRD=y 5CONFIG_BLK_DEV_INITRD=y
22CONFIG_RD_LZMA=y 6CONFIG_CC_OPTIMIZE_FOR_SIZE=y
23CONFIG_EXPERT=y 7CONFIG_EMBEDDED=y
24CONFIG_SLAB=y 8CONFIG_SLAB=y
25CONFIG_MODULES=y 9CONFIG_MODULES=y
26CONFIG_MODULE_UNLOAD=y 10CONFIG_MODULE_UNLOAD=y
27CONFIG_MODULE_FORCE_UNLOAD=y 11CONFIG_PARTITION_ADVANCED=y
28CONFIG_MODVERSIONS=y
29# CONFIG_BLK_DEV_BSG is not set
30CONFIG_PCI=y 12CONFIG_PCI=y
31CONFIG_BINFMT_MISC=m 13# CONFIG_SUSPEND is not set
32CONFIG_NET=y 14CONFIG_NET=y
33CONFIG_PACKET=y 15CONFIG_PACKET=y
34CONFIG_UNIX=y 16CONFIG_UNIX=y
35CONFIG_XFRM_USER=m
36CONFIG_NET_KEY=m
37CONFIG_INET=y 17CONFIG_INET=y
38CONFIG_IP_MULTICAST=y 18CONFIG_IP_MULTICAST=y
39CONFIG_IP_ADVANCED_ROUTER=y 19CONFIG_IP_ADVANCED_ROUTER=y
40CONFIG_IP_MULTIPLE_TABLES=y 20CONFIG_IP_MULTIPLE_TABLES=y
41CONFIG_IP_ROUTE_MULTIPATH=y 21CONFIG_IP_ROUTE_MULTIPATH=y
42CONFIG_IP_ROUTE_VERBOSE=y
43CONFIG_NET_IPIP=m
44CONFIG_NET_IPGRE=m
45CONFIG_NET_IPGRE_BROADCAST=y
46CONFIG_IP_MROUTE=y 22CONFIG_IP_MROUTE=y
47CONFIG_IP_PIMSM_V1=y 23CONFIG_IP_MROUTE_MULTIPLE_TABLES=y
48CONFIG_IP_PIMSM_V2=y
49CONFIG_SYN_COOKIES=y 24CONFIG_SYN_COOKIES=y
50CONFIG_INET_AH=m
51CONFIG_INET_ESP=m
52CONFIG_INET_IPCOMP=m
53CONFIG_INET_XFRM_MODE_TRANSPORT=m
54CONFIG_INET_XFRM_MODE_TUNNEL=m
55CONFIG_INET_XFRM_MODE_BEET=m
56CONFIG_INET_DIAG=m
57CONFIG_TCP_CONG_ADVANCED=y 25CONFIG_TCP_CONG_ADVANCED=y
58CONFIG_TCP_CONG_BIC=y
59CONFIG_TCP_CONG_CUBIC=m
60CONFIG_TCP_CONG_HSTCP=m
61CONFIG_TCP_CONG_HYBLA=m
62CONFIG_TCP_CONG_SCALABLE=m
63CONFIG_TCP_CONG_LP=m
64CONFIG_TCP_CONG_VENO=m
65CONFIG_TCP_CONG_YEAH=m
66CONFIG_TCP_CONG_ILLINOIS=m
67CONFIG_IPV6_PRIVACY=y 26CONFIG_IPV6_PRIVACY=y
68CONFIG_INET6_AH=m
69CONFIG_INET6_ESP=m
70CONFIG_INET6_IPCOMP=m
71CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m
72CONFIG_IPV6_TUNNEL=m
73CONFIG_IPV6_MULTIPLE_TABLES=y 27CONFIG_IPV6_MULTIPLE_TABLES=y
74CONFIG_IPV6_SUBTREES=y 28CONFIG_IPV6_SUBTREES=y
75CONFIG_NETWORK_SECMARK=y 29CONFIG_IPV6_MROUTE=y
76CONFIG_NETFILTER=y 30CONFIG_NETFILTER=y
77CONFIG_NETFILTER_NETLINK_QUEUE=m 31CONFIG_VLAN_8021Q=y
78CONFIG_NF_CONNTRACK=m
79CONFIG_NF_CONNTRACK_SECMARK=y
80CONFIG_NF_CONNTRACK_EVENTS=y
81CONFIG_NF_CT_PROTO_UDPLITE=m
82CONFIG_NF_CONNTRACK_AMANDA=m
83CONFIG_NF_CONNTRACK_FTP=m
84CONFIG_NF_CONNTRACK_H323=m
85CONFIG_NF_CONNTRACK_IRC=m
86CONFIG_NF_CONNTRACK_NETBIOS_NS=m
87CONFIG_NF_CONNTRACK_PPTP=m
88CONFIG_NF_CONNTRACK_SANE=m
89CONFIG_NF_CONNTRACK_SIP=m
90CONFIG_NF_CONNTRACK_TFTP=m
91CONFIG_NF_CT_NETLINK=m
92CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
93CONFIG_NETFILTER_XT_TARGET_CONNMARK=m
94CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=m
95CONFIG_NETFILTER_XT_TARGET_DSCP=m
96CONFIG_NETFILTER_XT_TARGET_MARK=m
97CONFIG_NETFILTER_XT_TARGET_NFLOG=m
98CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
99CONFIG_NETFILTER_XT_TARGET_TRACE=m
100CONFIG_NETFILTER_XT_TARGET_SECMARK=m
101CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
102CONFIG_NETFILTER_XT_MATCH_COMMENT=m
103CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
104CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m
105CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
106CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
107CONFIG_NETFILTER_XT_MATCH_DSCP=m
108CONFIG_NETFILTER_XT_MATCH_ESP=m
109CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
110CONFIG_NETFILTER_XT_MATCH_HELPER=m
111CONFIG_NETFILTER_XT_MATCH_LENGTH=m
112CONFIG_NETFILTER_XT_MATCH_LIMIT=m
113CONFIG_NETFILTER_XT_MATCH_MAC=m
114CONFIG_NETFILTER_XT_MATCH_MARK=m
115CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
116CONFIG_NETFILTER_XT_MATCH_POLICY=m
117CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m
118CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
119CONFIG_NETFILTER_XT_MATCH_QUOTA=m
120CONFIG_NETFILTER_XT_MATCH_REALM=m
121CONFIG_NETFILTER_XT_MATCH_STATE=m
122CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
123CONFIG_NETFILTER_XT_MATCH_STRING=m
124CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
125CONFIG_NETFILTER_XT_MATCH_TIME=m
126CONFIG_NETFILTER_XT_MATCH_U32=m
127CONFIG_IP_VS=m
128CONFIG_IP_VS_PROTO_TCP=y
129CONFIG_IP_VS_PROTO_UDP=y
130CONFIG_IP_VS_PROTO_ESP=y
131CONFIG_IP_VS_PROTO_AH=y
132CONFIG_IP_VS_RR=m
133CONFIG_IP_VS_WRR=m
134CONFIG_IP_VS_LC=m
135CONFIG_IP_VS_WLC=m
136CONFIG_IP_VS_LBLC=m
137CONFIG_IP_VS_LBLCR=m
138CONFIG_IP_VS_DH=m
139CONFIG_IP_VS_SH=m
140CONFIG_IP_VS_SED=m
141CONFIG_IP_VS_NQ=m
142CONFIG_IP_VS_FTP=m
143CONFIG_NF_CONNTRACK_IPV4=m
144CONFIG_IP_NF_QUEUE=m
145CONFIG_IP_NF_IPTABLES=m
146CONFIG_IP_NF_MATCH_ADDRTYPE=m
147CONFIG_IP_NF_MATCH_AH=m
148CONFIG_IP_NF_MATCH_ECN=m
149CONFIG_IP_NF_MATCH_TTL=m
150CONFIG_IP_NF_FILTER=m
151CONFIG_IP_NF_TARGET_REJECT=m
152CONFIG_IP_NF_TARGET_LOG=m
153CONFIG_IP_NF_TARGET_ULOG=m
154CONFIG_NF_NAT=m
155CONFIG_IP_NF_TARGET_MASQUERADE=m
156CONFIG_IP_NF_TARGET_NETMAP=m
157CONFIG_IP_NF_TARGET_REDIRECT=m
158CONFIG_NF_NAT_SNMP_BASIC=m
159CONFIG_IP_NF_MANGLE=m
160CONFIG_IP_NF_TARGET_CLUSTERIP=m
161CONFIG_IP_NF_TARGET_ECN=m
162CONFIG_IP_NF_TARGET_TTL=m
163CONFIG_IP_NF_RAW=m
164CONFIG_IP_NF_ARPTABLES=m
165CONFIG_IP_NF_ARPFILTER=m
166CONFIG_IP_NF_ARP_MANGLE=m
167CONFIG_NF_CONNTRACK_IPV6=m
168CONFIG_IP6_NF_QUEUE=m
169CONFIG_IP6_NF_IPTABLES=m
170CONFIG_IP6_NF_MATCH_AH=m
171CONFIG_IP6_NF_MATCH_EUI64=m
172CONFIG_IP6_NF_MATCH_FRAG=m
173CONFIG_IP6_NF_MATCH_OPTS=m
174CONFIG_IP6_NF_MATCH_HL=m
175CONFIG_IP6_NF_MATCH_IPV6HEADER=m
176CONFIG_IP6_NF_MATCH_MH=m
177CONFIG_IP6_NF_MATCH_RT=m
178CONFIG_IP6_NF_TARGET_HL=m
179CONFIG_IP6_NF_TARGET_LOG=m
180CONFIG_IP6_NF_FILTER=m
181CONFIG_IP6_NF_TARGET_REJECT=m
182CONFIG_IP6_NF_MANGLE=m
183CONFIG_IP6_NF_RAW=m
184CONFIG_BRIDGE_NF_EBTABLES=m
185CONFIG_BRIDGE_EBT_BROUTE=m
186CONFIG_BRIDGE_EBT_T_FILTER=m
187CONFIG_BRIDGE_EBT_T_NAT=m
188CONFIG_BRIDGE_EBT_802_3=m
189CONFIG_BRIDGE_EBT_AMONG=m
190CONFIG_BRIDGE_EBT_ARP=m
191CONFIG_BRIDGE_EBT_IP=m
192CONFIG_BRIDGE_EBT_LIMIT=m
193CONFIG_BRIDGE_EBT_MARK=m
194CONFIG_BRIDGE_EBT_PKTTYPE=m
195CONFIG_BRIDGE_EBT_STP=m
196CONFIG_BRIDGE_EBT_VLAN=m
197CONFIG_BRIDGE_EBT_ARPREPLY=m
198CONFIG_BRIDGE_EBT_DNAT=m
199CONFIG_BRIDGE_EBT_MARK_T=m
200CONFIG_BRIDGE_EBT_REDIRECT=m
201CONFIG_BRIDGE_EBT_SNAT=m
202CONFIG_BRIDGE_EBT_LOG=m
203CONFIG_BRIDGE_EBT_ULOG=m
204CONFIG_IP_DCCP=m
205CONFIG_TIPC=m
206CONFIG_TIPC_ADVANCED=y
207CONFIG_ATM=m
208CONFIG_ATM_CLIP=m
209CONFIG_ATM_LANE=m
210CONFIG_ATM_MPOA=m
211CONFIG_ATM_BR2684=m
212CONFIG_BRIDGE=m
213CONFIG_VLAN_8021Q=m
214CONFIG_NET_SCHED=y 32CONFIG_NET_SCHED=y
215CONFIG_NET_SCH_CBQ=m 33CONFIG_NET_SCH_FQ_CODEL=y
216CONFIG_NET_SCH_HTB=m 34CONFIG_HAMRADIO=y
217CONFIG_NET_SCH_HFSC=m 35CONFIG_CFG80211=y
218CONFIG_NET_SCH_ATM=m 36CONFIG_MAC80211=y
219CONFIG_NET_SCH_PRIO=m
220CONFIG_NET_SCH_RED=m
221CONFIG_NET_SCH_SFQ=m
222CONFIG_NET_SCH_TEQL=m
223CONFIG_NET_SCH_TBF=m
224CONFIG_NET_SCH_GRED=m
225CONFIG_NET_SCH_DSMARK=m
226CONFIG_NET_SCH_NETEM=m
227CONFIG_NET_SCH_INGRESS=m
228CONFIG_NET_CLS_BASIC=m
229CONFIG_NET_CLS_TCINDEX=m
230CONFIG_NET_CLS_ROUTE4=m
231CONFIG_NET_CLS_FW=m
232CONFIG_NET_CLS_U32=m
233CONFIG_CLS_U32_PERF=y
234CONFIG_CLS_U32_MARK=y
235CONFIG_NET_CLS_RSVP=m
236CONFIG_NET_CLS_RSVP6=m
237CONFIG_NET_EMATCH=y
238CONFIG_NET_EMATCH_CMP=m
239CONFIG_NET_EMATCH_NBYTE=m
240CONFIG_NET_EMATCH_U32=m
241CONFIG_NET_EMATCH_META=m
242CONFIG_NET_EMATCH_TEXT=m
243CONFIG_NET_CLS_ACT=y
244CONFIG_NET_ACT_POLICE=m
245CONFIG_NET_ACT_GACT=m
246CONFIG_GACT_PROB=y
247CONFIG_NET_ACT_MIRRED=m
248CONFIG_NET_ACT_IPT=m
249CONFIG_NET_ACT_NAT=m
250CONFIG_NET_ACT_PEDIT=m
251CONFIG_NET_ACT_SIMP=m
252CONFIG_NET_CLS_IND=y
253CONFIG_NET_PKTGEN=m
254CONFIG_BT=m
255CONFIG_BT_HCIUART=m
256CONFIG_BT_HCIUART_H4=y
257CONFIG_BT_HCIUART_BCSP=y
258CONFIG_BT_HCIUART_LL=y
259CONFIG_BT_HCIBCM203X=m
260CONFIG_BT_HCIBPA10X=m
261CONFIG_BT_HCIBFUSB=m
262CONFIG_BT_HCIVHCI=m
263CONFIG_CFG80211=m
264CONFIG_MAC80211=m
265CONFIG_MAC80211_RC_PID=y
266CONFIG_MAC80211_RC_DEFAULT_PID=y
267CONFIG_MAC80211_MESH=y
268CONFIG_RFKILL=m
269CONFIG_RFKILL_INPUT=y
270CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
271CONFIG_FW_LOADER=m
272CONFIG_CONNECTOR=m
273CONFIG_MTD=y 37CONFIG_MTD=y
274CONFIG_MTD_CONCAT=y 38CONFIG_MTD_BCM47XX_PARTS=y
275CONFIG_MTD_PARTITIONS=y
276CONFIG_MTD_CHAR=y
277CONFIG_MTD_BLOCK=y 39CONFIG_MTD_BLOCK=y
278CONFIG_MTD_CFI=y 40CONFIG_MTD_CFI=y
279CONFIG_MTD_CFI_INTELEXT=y 41CONFIG_MTD_CFI_INTELEXT=y
280CONFIG_MTD_CFI_AMDSTD=y 42CONFIG_MTD_CFI_AMDSTD=y
281CONFIG_MTD_CFI_STAA=y 43CONFIG_MTD_COMPLEX_MAPPINGS=y
282CONFIG_MTD_RAM=y
283CONFIG_MTD_ROM=y
284CONFIG_MTD_ABSENT=y
285CONFIG_MTD_PHYSMAP=y 44CONFIG_MTD_PHYSMAP=y
286CONFIG_BLK_DEV_LOOP=m 45CONFIG_MTD_BCM47XXSFLASH=y
287CONFIG_BLK_DEV_CRYPTOLOOP=m 46CONFIG_MTD_NAND=y
288CONFIG_BLK_DEV_NBD=m 47CONFIG_MTD_NAND_BCM47XXNFLASH=y
289CONFIG_BLK_DEV_RAM=y
290CONFIG_BLK_DEV_RAM_SIZE=16384
291CONFIG_ATA_OVER_ETH=m
292CONFIG_RAID_ATTRS=m
293CONFIG_SCSI=y
294CONFIG_SCSI_TGT=m
295CONFIG_BLK_DEV_SD=y
296CONFIG_CHR_DEV_ST=m
297CONFIG_CHR_DEV_OSST=m
298CONFIG_BLK_DEV_SR=m
299CONFIG_BLK_DEV_SR_VENDOR=y
300CONFIG_CHR_DEV_SG=m
301CONFIG_CHR_DEV_SCH=m
302CONFIG_SCSI_MULTI_LUN=y
303CONFIG_SCSI_CONSTANTS=y
304CONFIG_SCSI_LOGGING=y
305CONFIG_SCSI_SCAN_ASYNC=y
306CONFIG_ISCSI_TCP=m
307CONFIG_NETDEVICES=y 48CONFIG_NETDEVICES=y
308CONFIG_DUMMY=m
309CONFIG_EQUALIZER=m
310CONFIG_TUN=m
311CONFIG_VETH=m
312CONFIG_PHYLIB=m
313CONFIG_MARVELL_PHY=m
314CONFIG_DAVICOM_PHY=m
315CONFIG_QSEMI_PHY=m
316CONFIG_LXT_PHY=m
317CONFIG_CICADA_PHY=m
318CONFIG_VITESSE_PHY=m
319CONFIG_SMSC_PHY=m
320CONFIG_BROADCOM_PHY=m
321CONFIG_ICPLUS_PHY=m
322CONFIG_MDIO_BITBANG=m
323CONFIG_NET_ETHERNET=y
324CONFIG_NET_PCI=y
325CONFIG_B44=y 49CONFIG_B44=y
326# CONFIG_NETDEV_1000 is not set 50CONFIG_TIGON3=y
327# CONFIG_NETDEV_10000 is not set 51CONFIG_BGMAC=y
328CONFIG_ATH_COMMON=m 52CONFIG_ATH_CARDS=y
329CONFIG_ATH5K=m 53CONFIG_ATH5K=y
330CONFIG_B43=m 54CONFIG_B43=y
331CONFIG_B43LEGACY=m 55CONFIG_B43LEGACY=y
332CONFIG_ZD1211RW=m 56CONFIG_BRCMSMAC=y
333CONFIG_USB_CATC=m 57CONFIG_ISDN=y
334CONFIG_USB_KAWETH=m
335CONFIG_USB_PEGASUS=m
336CONFIG_USB_RTL8150=m
337CONFIG_USB_USBNET=m
338CONFIG_USB_NET_DM9601=m
339CONFIG_USB_NET_GL620A=m
340CONFIG_USB_NET_PLUSB=m
341CONFIG_USB_NET_MCS7830=m
342CONFIG_USB_NET_RNDIS_HOST=m
343CONFIG_USB_ALI_M5632=y
344CONFIG_USB_AN2720=y
345CONFIG_USB_EPSON2888=y
346CONFIG_USB_KC2190=y
347CONFIG_USB_SIERRA_NET=m
348CONFIG_ATM_DUMMY=m
349CONFIG_ATM_TCP=m
350CONFIG_PPP=m
351CONFIG_PPP_ASYNC=m
352CONFIG_PPP_DEFLATE=m
353CONFIG_PPP_BSDCOMP=m
354CONFIG_PPP_MPPE=m
355CONFIG_PPPOE=m
356CONFIG_PPPOATM=m
357CONFIG_SLIP=m
358CONFIG_INPUT_EVDEV=m
359# CONFIG_INPUT_KEYBOARD is not set
360# CONFIG_INPUT_MOUSE is not set
361# CONFIG_SERIO is not set
362# CONFIG_VT is not set
363CONFIG_SERIAL_8250=y 58CONFIG_SERIAL_8250=y
59# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set
364CONFIG_SERIAL_8250_CONSOLE=y 60CONFIG_SERIAL_8250_CONSOLE=y
365# CONFIG_SERIAL_8250_PCI is not set 61# CONFIG_SERIAL_8250_PCI is not set
366CONFIG_SERIAL_8250_NR_UARTS=2 62CONFIG_SERIAL_8250_NR_UARTS=2
367CONFIG_SERIAL_8250_RUNTIME_UARTS=2 63CONFIG_SERIAL_8250_RUNTIME_UARTS=2
368# CONFIG_LEGACY_PTYS is not set 64CONFIG_SERIAL_8250_EXTENDED=y
369# CONFIG_HW_RANDOM is not set 65CONFIG_SERIAL_8250_SHARE_IRQ=y
370CONFIG_W1=m 66CONFIG_HW_RANDOM=y
371CONFIG_W1_MASTER_MATROX=m 67CONFIG_GPIO_SYSFS=y
372CONFIG_W1_MASTER_DS2490=m
373CONFIG_W1_SLAVE_THERM=m
374CONFIG_W1_SLAVE_SMEM=m
375CONFIG_W1_SLAVE_DS2433=m
376CONFIG_W1_SLAVE_DS2760=m
377# CONFIG_HWMON is not set
378CONFIG_THERMAL=y
379CONFIG_WATCHDOG=y 68CONFIG_WATCHDOG=y
380CONFIG_WATCHDOG_NOWAYOUT=y
381CONFIG_BCM47XX_WDT=y 69CONFIG_BCM47XX_WDT=y
70CONFIG_SSB_DEBUG=y
382CONFIG_SSB_DRIVER_GIGE=y 71CONFIG_SSB_DRIVER_GIGE=y
383CONFIG_DISPLAY_SUPPORT=m 72CONFIG_BCMA_DRIVER_GMAC_CMN=y
384CONFIG_SOUND=m
385CONFIG_SND=m
386CONFIG_SND_SEQUENCER=m
387CONFIG_SND_SEQ_DUMMY=m
388CONFIG_SND_MIXER_OSS=m
389CONFIG_SND_PCM_OSS=m
390CONFIG_SND_SEQUENCER_OSS=y
391CONFIG_SND_DUMMY=m
392CONFIG_SND_VIRMIDI=m
393CONFIG_SND_USB_AUDIO=m
394CONFIG_HID=m
395CONFIG_USB_HID=m
396CONFIG_USB_HIDDEV=y
397CONFIG_USB=y 73CONFIG_USB=y
398CONFIG_USB_DEVICEFS=y 74CONFIG_USB_HCD_BCMA=y
399# CONFIG_USB_DEVICE_CLASS is not set 75CONFIG_USB_HCD_SSB=y
400CONFIG_USB_EHCI_HCD=y
401CONFIG_USB_EHCI_ROOT_HUB_TT=y
402CONFIG_USB_OHCI_HCD=y
403CONFIG_USB_U132_HCD=m
404CONFIG_USB_R8A66597_HCD=m
405CONFIG_USB_ACM=m
406CONFIG_USB_PRINTER=m
407CONFIG_USB_STORAGE=y
408CONFIG_USB_STORAGE_DATAFAB=y
409CONFIG_USB_STORAGE_FREECOM=y
410CONFIG_USB_STORAGE_USBAT=y
411CONFIG_USB_STORAGE_SDDR09=y
412CONFIG_USB_STORAGE_SDDR55=y
413CONFIG_USB_STORAGE_JUMPSHOT=y
414CONFIG_USB_STORAGE_ALAUDA=y
415CONFIG_USB_STORAGE_ONETOUCH=y
416CONFIG_USB_STORAGE_KARMA=y
417CONFIG_USB_MDC800=m
418CONFIG_USB_MICROTEK=m
419CONFIG_USB_SERIAL=m
420CONFIG_USB_SERIAL_GENERIC=y
421CONFIG_USB_SERIAL_AIRCABLE=m
422CONFIG_USB_SERIAL_ARK3116=m
423CONFIG_USB_SERIAL_BELKIN=m
424CONFIG_USB_SERIAL_CH341=m
425CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m
426CONFIG_USB_SERIAL_CYPRESS_M8=m
427CONFIG_USB_SERIAL_EMPEG=m
428CONFIG_USB_SERIAL_FTDI_SIO=m
429CONFIG_USB_SERIAL_FUNSOFT=m
430CONFIG_USB_SERIAL_VISOR=m
431CONFIG_USB_SERIAL_IPAQ=m
432CONFIG_USB_SERIAL_IR=m
433CONFIG_USB_SERIAL_GARMIN=m
434CONFIG_USB_SERIAL_IPW=m
435CONFIG_USB_SERIAL_KEYSPAN_PDA=m
436CONFIG_USB_SERIAL_KLSI=m
437CONFIG_USB_SERIAL_KOBIL_SCT=m
438CONFIG_USB_SERIAL_MCT_U232=m
439CONFIG_USB_SERIAL_MOS7720=m
440CONFIG_USB_SERIAL_MOS7840=m
441CONFIG_USB_SERIAL_NAVMAN=m
442CONFIG_USB_SERIAL_PL2303=m
443CONFIG_USB_SERIAL_OTI6858=m
444CONFIG_USB_SERIAL_HP4X=m
445CONFIG_USB_SERIAL_SAFE=m
446CONFIG_USB_SERIAL_SIERRAWIRELESS=m
447CONFIG_USB_SERIAL_CYBERJACK=m
448CONFIG_USB_SERIAL_XIRCOM=m
449CONFIG_USB_SERIAL_OPTION=m
450CONFIG_USB_SERIAL_OMNINET=m
451CONFIG_USB_SERIAL_DEBUG=m
452CONFIG_USB_ADUTUX=m
453CONFIG_USB_RIO500=m
454CONFIG_USB_LEGOTOWER=m
455CONFIG_USB_LCD=m
456CONFIG_USB_LED=m
457CONFIG_USB_CYPRESS_CY7C63=m
458CONFIG_USB_CYTHERM=m
459CONFIG_USB_IDMOUSE=m
460CONFIG_USB_FTDI_ELAN=m
461CONFIG_USB_SISUSBVGA=m
462CONFIG_USB_LD=m
463CONFIG_USB_TRANCEVIBRATOR=m
464CONFIG_USB_IOWARRIOR=m
465CONFIG_USB_TEST=m
466CONFIG_USB_ATM=m
467CONFIG_USB_SPEEDTOUCH=m
468CONFIG_USB_CXACRU=m
469CONFIG_USB_UEAGLEATM=m
470CONFIG_USB_XUSBATM=m
471CONFIG_USB_GADGET=m
472CONFIG_USB_GADGET_NET2280=y
473CONFIG_USB_ZERO=m
474CONFIG_USB_ETH=m
475CONFIG_USB_GADGETFS=m
476CONFIG_USB_MASS_STORAGE=m
477CONFIG_USB_G_SERIAL=m
478CONFIG_USB_MIDI_GADGET=m
479CONFIG_LEDS_CLASS=y
480CONFIG_LEDS_GPIO=y
481CONFIG_LEDS_TRIGGER_TIMER=y 76CONFIG_LEDS_TRIGGER_TIMER=y
482CONFIG_LEDS_TRIGGER_HEARTBEAT=y
483CONFIG_LEDS_TRIGGER_DEFAULT_ON=y 77CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
484CONFIG_EXT2_FS=y 78CONFIG_PRINTK_TIME=y
485CONFIG_EXT2_FS_XATTR=y 79CONFIG_DEBUG_INFO=y
486CONFIG_EXT2_FS_POSIX_ACL=y 80CONFIG_DEBUG_INFO_REDUCED=y
487CONFIG_EXT2_FS_SECURITY=y 81CONFIG_STRIP_ASM_SYMS=y
488CONFIG_EXT3_FS=y
489# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
490CONFIG_EXT3_FS_POSIX_ACL=y
491CONFIG_EXT3_FS_SECURITY=y
492CONFIG_REISERFS_FS=m
493CONFIG_REISERFS_FS_XATTR=y
494CONFIG_REISERFS_FS_POSIX_ACL=y
495CONFIG_REISERFS_FS_SECURITY=y
496CONFIG_JFS_FS=m
497CONFIG_JFS_POSIX_ACL=y
498CONFIG_JFS_SECURITY=y
499CONFIG_XFS_FS=m
500CONFIG_XFS_QUOTA=y
501CONFIG_XFS_POSIX_ACL=y
502CONFIG_XFS_RT=y
503CONFIG_GFS2_FS=m
504CONFIG_QUOTA=y
505CONFIG_QUOTA_NETLINK_INTERFACE=y
506CONFIG_QFMT_V1=m
507CONFIG_QFMT_V2=m
508CONFIG_AUTOFS_FS=m
509CONFIG_AUTOFS4_FS=m
510CONFIG_FUSE_FS=m
511CONFIG_ISO9660_FS=m
512CONFIG_JOLIET=y
513CONFIG_ZISOFS=y
514CONFIG_UDF_FS=m
515CONFIG_MSDOS_FS=m
516CONFIG_VFAT_FS=m
517CONFIG_NTFS_FS=m
518CONFIG_NTFS_RW=y
519CONFIG_PROC_KCORE=y
520CONFIG_TMPFS=y
521CONFIG_TMPFS_POSIX_ACL=y
522CONFIG_ADFS_FS=m
523CONFIG_AFFS_FS=m
524CONFIG_HFS_FS=m
525CONFIG_HFSPLUS_FS=m
526CONFIG_BEFS_FS=m
527CONFIG_BFS_FS=m
528CONFIG_EFS_FS=m
529CONFIG_JFFS2_FS=m
530CONFIG_JFFS2_FS_XATTR=y
531CONFIG_CRAMFS=m
532CONFIG_VXFS_FS=m
533CONFIG_MINIX_FS=m
534CONFIG_HPFS_FS=m
535CONFIG_QNX4FS_FS=m
536CONFIG_ROMFS_FS=m
537CONFIG_SYSV_FS=m
538CONFIG_UFS_FS=m
539CONFIG_NFS_FS=m
540CONFIG_NFS_V3=y
541CONFIG_NFS_V3_ACL=y
542CONFIG_NFS_V4=y
543CONFIG_NFSD=m
544CONFIG_NFSD_V3_ACL=y
545CONFIG_NFSD_V4=y
546CONFIG_RPCSEC_GSS_SPKM3=m
547CONFIG_CIFS=m
548CONFIG_CIFS_XATTR=y
549CONFIG_CIFS_POSIX=y
550CONFIG_NCP_FS=m
551CONFIG_NCPFS_NFS_NS=y
552CONFIG_NCPFS_OS2_NS=y
553CONFIG_NCPFS_NLS=y
554CONFIG_NCPFS_EXTRAS=y
555CONFIG_CODA_FS=m
556CONFIG_PARTITION_ADVANCED=y
557CONFIG_KARMA_PARTITION=y
558CONFIG_NLS_CODEPAGE_437=m
559CONFIG_NLS_CODEPAGE_737=m
560CONFIG_NLS_CODEPAGE_775=m
561CONFIG_NLS_CODEPAGE_850=m
562CONFIG_NLS_CODEPAGE_852=m
563CONFIG_NLS_CODEPAGE_855=m
564CONFIG_NLS_CODEPAGE_857=m
565CONFIG_NLS_CODEPAGE_860=m
566CONFIG_NLS_CODEPAGE_861=m
567CONFIG_NLS_CODEPAGE_862=m
568CONFIG_NLS_CODEPAGE_863=m
569CONFIG_NLS_CODEPAGE_864=m
570CONFIG_NLS_CODEPAGE_865=m
571CONFIG_NLS_CODEPAGE_866=m
572CONFIG_NLS_CODEPAGE_869=m
573CONFIG_NLS_CODEPAGE_936=m
574CONFIG_NLS_CODEPAGE_950=m
575CONFIG_NLS_CODEPAGE_932=m
576CONFIG_NLS_CODEPAGE_949=m
577CONFIG_NLS_CODEPAGE_874=m
578CONFIG_NLS_ISO8859_8=m
579CONFIG_NLS_CODEPAGE_1250=m
580CONFIG_NLS_CODEPAGE_1251=m
581CONFIG_NLS_ASCII=m
582CONFIG_NLS_ISO8859_1=m
583CONFIG_NLS_ISO8859_2=m
584CONFIG_NLS_ISO8859_3=m
585CONFIG_NLS_ISO8859_4=m
586CONFIG_NLS_ISO8859_5=m
587CONFIG_NLS_ISO8859_6=m
588CONFIG_NLS_ISO8859_7=m
589CONFIG_NLS_ISO8859_9=m
590CONFIG_NLS_ISO8859_13=m
591CONFIG_NLS_ISO8859_14=m
592CONFIG_NLS_ISO8859_15=m
593CONFIG_NLS_KOI8_R=m
594CONFIG_NLS_KOI8_U=m
595CONFIG_DLM=m
596CONFIG_DLM_DEBUG=y
597CONFIG_DEBUG_FS=y 82CONFIG_DEBUG_FS=y
598CONFIG_CRYPTO_NULL=m 83CONFIG_MAGIC_SYSRQ=y
599CONFIG_CRYPTO_TEST=m 84CONFIG_CMDLINE_BOOL=y
600CONFIG_CRYPTO_LRW=m 85CONFIG_CMDLINE="console=ttyS0,115200"
601CONFIG_CRYPTO_PCBC=m 86CONFIG_CRC32_SARWATE=y
602CONFIG_CRYPTO_XTS=m
603CONFIG_CRYPTO_HMAC=y
604CONFIG_CRYPTO_XCBC=m
605CONFIG_CRYPTO_MD4=m
606CONFIG_CRYPTO_MD5=y
607CONFIG_CRYPTO_MICHAEL_MIC=m
608CONFIG_CRYPTO_SHA256=m
609CONFIG_CRYPTO_SHA512=m
610CONFIG_CRYPTO_TGR192=m
611CONFIG_CRYPTO_WP512=m
612CONFIG_CRYPTO_ANUBIS=m
613CONFIG_CRYPTO_BLOWFISH=m
614CONFIG_CRYPTO_CAMELLIA=m
615CONFIG_CRYPTO_CAST6=m
616CONFIG_CRYPTO_FCRYPT=m
617CONFIG_CRYPTO_KHAZAD=m
618CONFIG_CRYPTO_SEED=m
619CONFIG_CRYPTO_SERPENT=m
620CONFIG_CRYPTO_TEA=m
621CONFIG_CRYPTO_TWOFISH=m
622CONFIG_CRC16=m
623CONFIG_CRC7=m
diff --git a/arch/mips/configs/bcm63xx_defconfig b/arch/mips/configs/bcm63xx_defconfig
index 919005139f5a..3fec26410f34 100644
--- a/arch/mips/configs/bcm63xx_defconfig
+++ b/arch/mips/configs/bcm63xx_defconfig
@@ -44,7 +44,6 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
44# CONFIG_STANDALONE is not set 44# CONFIG_STANDALONE is not set
45# CONFIG_PREVENT_FIRMWARE_BUILD is not set 45# CONFIG_PREVENT_FIRMWARE_BUILD is not set
46CONFIG_MTD=y 46CONFIG_MTD=y
47CONFIG_MTD_PARTITIONS=y
48CONFIG_MTD_CFI=y 47CONFIG_MTD_CFI=y
49CONFIG_MTD_CFI_INTELEXT=y 48CONFIG_MTD_CFI_INTELEXT=y
50CONFIG_MTD_CFI_AMDSTD=y 49CONFIG_MTD_CFI_AMDSTD=y
diff --git a/arch/mips/configs/cobalt_defconfig b/arch/mips/configs/cobalt_defconfig
index 5419adb219a8..23b66934e18d 100644
--- a/arch/mips/configs/cobalt_defconfig
+++ b/arch/mips/configs/cobalt_defconfig
@@ -19,7 +19,6 @@ CONFIG_INET=y
19# CONFIG_IPV6 is not set 19# CONFIG_IPV6 is not set
20CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" 20CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
21CONFIG_MTD=y 21CONFIG_MTD=y
22CONFIG_MTD_PARTITIONS=y
23CONFIG_MTD_CHAR=y 22CONFIG_MTD_CHAR=y
24CONFIG_MTD_BLKDEVS=y 23CONFIG_MTD_BLKDEVS=y
25CONFIG_MTD_JEDECPROBE=y 24CONFIG_MTD_JEDECPROBE=y
diff --git a/arch/mips/configs/gpr_defconfig b/arch/mips/configs/gpr_defconfig
index fb64589015fc..8f219dac9598 100644
--- a/arch/mips/configs/gpr_defconfig
+++ b/arch/mips/configs/gpr_defconfig
@@ -165,7 +165,6 @@ CONFIG_YAM=m
165CONFIG_CFG80211=y 165CONFIG_CFG80211=y
166CONFIG_MAC80211=y 166CONFIG_MAC80211=y
167CONFIG_MTD=y 167CONFIG_MTD=y
168CONFIG_MTD_PARTITIONS=y
169CONFIG_MTD_CHAR=y 168CONFIG_MTD_CHAR=y
170CONFIG_MTD_BLOCK=y 169CONFIG_MTD_BLOCK=y
171CONFIG_MTD_CFI=y 170CONFIG_MTD_CFI=y
diff --git a/arch/mips/configs/jmr3927_defconfig b/arch/mips/configs/jmr3927_defconfig
index db5705e18b36..9bc08f275120 100644
--- a/arch/mips/configs/jmr3927_defconfig
+++ b/arch/mips/configs/jmr3927_defconfig
@@ -22,7 +22,6 @@ CONFIG_IP_PNP_BOOTP=y
22# CONFIG_INET_DIAG is not set 22# CONFIG_INET_DIAG is not set
23# CONFIG_IPV6 is not set 23# CONFIG_IPV6 is not set
24CONFIG_MTD=y 24CONFIG_MTD=y
25CONFIG_MTD_PARTITIONS=y
26CONFIG_MTD_CMDLINE_PARTS=y 25CONFIG_MTD_CMDLINE_PARTS=y
27CONFIG_MTD_CHAR=y 26CONFIG_MTD_CHAR=y
28CONFIG_MTD_CFI=y 27CONFIG_MTD_CFI=y
diff --git a/arch/mips/configs/lasat_defconfig b/arch/mips/configs/lasat_defconfig
index d9f3db29ab95..0179c7fa014f 100644
--- a/arch/mips/configs/lasat_defconfig
+++ b/arch/mips/configs/lasat_defconfig
@@ -31,7 +31,6 @@ CONFIG_INET=y
31# CONFIG_INET_DIAG is not set 31# CONFIG_INET_DIAG is not set
32# CONFIG_IPV6 is not set 32# CONFIG_IPV6 is not set
33CONFIG_MTD=y 33CONFIG_MTD=y
34CONFIG_MTD_PARTITIONS=y
35CONFIG_MTD_CHAR=y 34CONFIG_MTD_CHAR=y
36CONFIG_MTD_BLOCK=y 35CONFIG_MTD_BLOCK=y
37CONFIG_MTD_CFI=y 36CONFIG_MTD_CFI=y
diff --git a/arch/mips/configs/maltasmvp_defconfig b/arch/mips/configs/maltasmvp_defconfig
index 8a666021b870..d75931850392 100644
--- a/arch/mips/configs/maltasmvp_defconfig
+++ b/arch/mips/configs/maltasmvp_defconfig
@@ -4,7 +4,7 @@ CONFIG_CPU_MIPS32_R2=y
4CONFIG_MIPS_MT_SMP=y 4CONFIG_MIPS_MT_SMP=y
5CONFIG_SCHED_SMT=y 5CONFIG_SCHED_SMT=y
6CONFIG_MIPS_CMP=y 6CONFIG_MIPS_CMP=y
7CONFIG_NR_CPUS=8 7CONFIG_NR_CPUS=2
8CONFIG_HZ_100=y 8CONFIG_HZ_100=y
9CONFIG_LOCALVERSION="cmp" 9CONFIG_LOCALVERSION="cmp"
10CONFIG_SYSVIPC=y 10CONFIG_SYSVIPC=y
@@ -58,7 +58,6 @@ CONFIG_ATALK=m
58CONFIG_DEV_APPLETALK=m 58CONFIG_DEV_APPLETALK=m
59CONFIG_IPDDP=m 59CONFIG_IPDDP=m
60CONFIG_IPDDP_ENCAP=y 60CONFIG_IPDDP_ENCAP=y
61CONFIG_IPDDP_DECAP=y
62CONFIG_NET_SCHED=y 61CONFIG_NET_SCHED=y
63CONFIG_NET_SCH_CBQ=m 62CONFIG_NET_SCH_CBQ=m
64CONFIG_NET_SCH_HTB=m 63CONFIG_NET_SCH_HTB=m
diff --git a/arch/mips/configs/markeins_defconfig b/arch/mips/configs/markeins_defconfig
index 636f82b89fd3..4c2c0c4b9bb1 100644
--- a/arch/mips/configs/markeins_defconfig
+++ b/arch/mips/configs/markeins_defconfig
@@ -124,7 +124,6 @@ CONFIG_IP6_NF_MANGLE=m
124CONFIG_IP6_NF_RAW=m 124CONFIG_IP6_NF_RAW=m
125CONFIG_FW_LOADER=m 125CONFIG_FW_LOADER=m
126CONFIG_MTD=y 126CONFIG_MTD=y
127CONFIG_MTD_PARTITIONS=y
128CONFIG_MTD_CMDLINE_PARTS=y 127CONFIG_MTD_CMDLINE_PARTS=y
129CONFIG_MTD_CHAR=y 128CONFIG_MTD_CHAR=y
130CONFIG_MTD_BLOCK=y 129CONFIG_MTD_BLOCK=y
diff --git a/arch/mips/configs/mtx1_defconfig b/arch/mips/configs/mtx1_defconfig
index 9fa8f16068d8..593946afc483 100644
--- a/arch/mips/configs/mtx1_defconfig
+++ b/arch/mips/configs/mtx1_defconfig
@@ -246,7 +246,6 @@ CONFIG_BT_HCIBTUART=m
246CONFIG_BT_HCIVHCI=m 246CONFIG_BT_HCIVHCI=m
247CONFIG_CONNECTOR=m 247CONFIG_CONNECTOR=m
248CONFIG_MTD=y 248CONFIG_MTD=y
249CONFIG_MTD_PARTITIONS=y
250CONFIG_MTD_CHAR=y 249CONFIG_MTD_CHAR=y
251CONFIG_MTD_BLOCK=y 250CONFIG_MTD_BLOCK=y
252CONFIG_MTD_CFI=y 251CONFIG_MTD_CFI=y
diff --git a/arch/mips/configs/pnx8335_stb225_defconfig b/arch/mips/configs/pnx8335_stb225_defconfig
index f2925769dfa3..c887066ecc2a 100644
--- a/arch/mips/configs/pnx8335_stb225_defconfig
+++ b/arch/mips/configs/pnx8335_stb225_defconfig
@@ -31,7 +31,6 @@ CONFIG_INET_AH=y
31# CONFIG_IPV6 is not set 31# CONFIG_IPV6 is not set
32CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" 32CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
33CONFIG_MTD=y 33CONFIG_MTD=y
34CONFIG_MTD_PARTITIONS=y
35CONFIG_MTD_CMDLINE_PARTS=y 34CONFIG_MTD_CMDLINE_PARTS=y
36CONFIG_MTD_CHAR=y 35CONFIG_MTD_CHAR=y
37CONFIG_MTD_BLOCK=y 36CONFIG_MTD_BLOCK=y
diff --git a/arch/mips/configs/qi_lb60_defconfig b/arch/mips/configs/qi_lb60_defconfig
new file mode 100644
index 000000000000..2b965470c35b
--- /dev/null
+++ b/arch/mips/configs/qi_lb60_defconfig
@@ -0,0 +1,188 @@
1CONFIG_MACH_JZ4740=y
2# CONFIG_COMPACTION is not set
3# CONFIG_CROSS_MEMORY_ATTACH is not set
4CONFIG_HZ_100=y
5CONFIG_PREEMPT=y
6# CONFIG_SECCOMP is not set
7# CONFIG_LOCALVERSION_AUTO is not set
8CONFIG_SYSVIPC=y
9CONFIG_LOG_BUF_SHIFT=14
10CONFIG_SYSCTL_SYSCALL=y
11CONFIG_KALLSYMS_ALL=y
12CONFIG_EMBEDDED=y
13# CONFIG_VM_EVENT_COUNTERS is not set
14# CONFIG_COMPAT_BRK is not set
15CONFIG_SLAB=y
16CONFIG_MODULES=y
17CONFIG_MODULE_UNLOAD=y
18# CONFIG_BLK_DEV_BSG is not set
19CONFIG_PARTITION_ADVANCED=y
20# CONFIG_EFI_PARTITION is not set
21# CONFIG_IOSCHED_CFQ is not set
22# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
23CONFIG_NET=y
24CONFIG_PACKET=y
25CONFIG_UNIX=y
26CONFIG_INET=y
27CONFIG_IP_MULTICAST=y
28CONFIG_IP_ADVANCED_ROUTER=y
29CONFIG_IP_MULTIPLE_TABLES=y
30CONFIG_IP_ROUTE_MULTIPATH=y
31CONFIG_IP_ROUTE_VERBOSE=y
32CONFIG_IP_MROUTE=y
33CONFIG_IP_MROUTE_MULTIPLE_TABLES=y
34# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
35# CONFIG_INET_XFRM_MODE_TUNNEL is not set
36# CONFIG_INET_XFRM_MODE_BEET is not set
37# CONFIG_INET_LRO is not set
38# CONFIG_INET_DIAG is not set
39CONFIG_TCP_CONG_ADVANCED=y
40# CONFIG_TCP_CONG_BIC is not set
41# CONFIG_TCP_CONG_CUBIC is not set
42CONFIG_TCP_CONG_WESTWOOD=y
43# CONFIG_TCP_CONG_HTCP is not set
44# CONFIG_IPV6 is not set
45CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
46# CONFIG_FIRMWARE_IN_KERNEL is not set
47CONFIG_MTD=y
48CONFIG_MTD_BLOCK=y
49CONFIG_MTD_NAND=y
50CONFIG_MTD_NAND_JZ4740=y
51CONFIG_MTD_UBI=y
52CONFIG_NETDEVICES=y
53# CONFIG_WLAN is not set
54# CONFIG_INPUT_MOUSEDEV is not set
55CONFIG_INPUT_EVDEV=y
56# CONFIG_KEYBOARD_ATKBD is not set
57CONFIG_KEYBOARD_GPIO=y
58CONFIG_KEYBOARD_MATRIX=y
59# CONFIG_INPUT_MOUSE is not set
60CONFIG_INPUT_MISC=y
61# CONFIG_SERIO is not set
62CONFIG_LEGACY_PTY_COUNT=2
63# CONFIG_DEVKMEM is not set
64CONFIG_SERIAL_8250=y
65CONFIG_SERIAL_8250_CONSOLE=y
66# CONFIG_SERIAL_8250_DMA is not set
67CONFIG_SERIAL_8250_NR_UARTS=2
68CONFIG_SERIAL_8250_RUNTIME_UARTS=2
69# CONFIG_HW_RANDOM is not set
70CONFIG_SPI=y
71CONFIG_SPI_GPIO=y
72CONFIG_POWER_SUPPLY=y
73CONFIG_BATTERY_JZ4740=y
74CONFIG_CHARGER_GPIO=y
75# CONFIG_HWMON is not set
76CONFIG_MFD_JZ4740_ADC=y
77CONFIG_REGULATOR=y
78CONFIG_REGULATOR_FIXED_VOLTAGE=y
79CONFIG_FB=y
80CONFIG_FB_JZ4740=y
81CONFIG_BACKLIGHT_LCD_SUPPORT=y
82CONFIG_LCD_CLASS_DEVICE=y
83# CONFIG_BACKLIGHT_CLASS_DEVICE is not set
84# CONFIG_VGA_CONSOLE is not set
85CONFIG_FRAMEBUFFER_CONSOLE=y
86CONFIG_LOGO=y
87# CONFIG_LOGO_LINUX_MONO is not set
88# CONFIG_LOGO_LINUX_VGA16 is not set
89# CONFIG_LOGO_LINUX_CLUT224 is not set
90CONFIG_SOUND=y
91CONFIG_SND=y
92# CONFIG_SND_SUPPORT_OLD_API is not set
93# CONFIG_SND_VERBOSE_PROCFS is not set
94# CONFIG_SND_DRIVERS is not set
95# CONFIG_SND_SPI is not set
96# CONFIG_SND_MIPS is not set
97CONFIG_SND_SOC=y
98CONFIG_SND_JZ4740_SOC=y
99CONFIG_SND_JZ4740_SOC_QI_LB60=y
100CONFIG_USB=y
101CONFIG_USB_OTG_BLACKLIST_HUB=y
102CONFIG_USB_MUSB_HDRC=y
103CONFIG_USB_MUSB_GADGET=y
104CONFIG_USB_MUSB_JZ4740=y
105CONFIG_NOP_USB_XCEIV=y
106CONFIG_USB_GADGET=y
107CONFIG_USB_GADGET_DEBUG=y
108CONFIG_USB_ETH=y
109# CONFIG_USB_ETH_RNDIS is not set
110CONFIG_MMC=y
111CONFIG_MMC_UNSAFE_RESUME=y
112# CONFIG_MMC_BLOCK_BOUNCE is not set
113CONFIG_MMC_JZ4740=y
114CONFIG_RTC_CLASS=y
115CONFIG_RTC_DRV_JZ4740=y
116CONFIG_DMADEVICES=y
117CONFIG_DMA_JZ4740=y
118CONFIG_PWM=y
119CONFIG_PWM_JZ4740=y
120CONFIG_EXT2_FS=y
121CONFIG_EXT3_FS=y
122# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
123# CONFIG_EXT3_FS_XATTR is not set
124# CONFIG_DNOTIFY is not set
125CONFIG_VFAT_FS=y
126CONFIG_PROC_KCORE=y
127# CONFIG_PROC_PAGE_MONITOR is not set
128CONFIG_TMPFS=y
129CONFIG_JFFS2_FS=y
130CONFIG_JFFS2_SUMMARY=y
131CONFIG_JFFS2_COMPRESSION_OPTIONS=y
132# CONFIG_JFFS2_ZLIB is not set
133CONFIG_UBIFS_FS=y
134CONFIG_UBIFS_FS_ADVANCED_COMPR=y
135# CONFIG_NETWORK_FILESYSTEMS is not set
136CONFIG_NLS_CODEPAGE_437=y
137CONFIG_NLS_CODEPAGE_737=y
138CONFIG_NLS_CODEPAGE_775=y
139CONFIG_NLS_CODEPAGE_850=y
140CONFIG_NLS_CODEPAGE_852=y
141CONFIG_NLS_CODEPAGE_855=y
142CONFIG_NLS_CODEPAGE_857=y
143CONFIG_NLS_CODEPAGE_860=y
144CONFIG_NLS_CODEPAGE_861=y
145CONFIG_NLS_CODEPAGE_862=y
146CONFIG_NLS_CODEPAGE_863=y
147CONFIG_NLS_CODEPAGE_864=y
148CONFIG_NLS_CODEPAGE_865=y
149CONFIG_NLS_CODEPAGE_866=y
150CONFIG_NLS_CODEPAGE_869=y
151CONFIG_NLS_CODEPAGE_936=y
152CONFIG_NLS_CODEPAGE_950=y
153CONFIG_NLS_CODEPAGE_932=y
154CONFIG_NLS_CODEPAGE_949=y
155CONFIG_NLS_CODEPAGE_874=y
156CONFIG_NLS_ISO8859_8=y
157CONFIG_NLS_CODEPAGE_1250=y
158CONFIG_NLS_CODEPAGE_1251=y
159CONFIG_NLS_ASCII=y
160CONFIG_NLS_ISO8859_1=y
161CONFIG_NLS_ISO8859_2=y
162CONFIG_NLS_ISO8859_3=y
163CONFIG_NLS_ISO8859_4=y
164CONFIG_NLS_ISO8859_5=y
165CONFIG_NLS_ISO8859_6=y
166CONFIG_NLS_ISO8859_7=y
167CONFIG_NLS_ISO8859_9=y
168CONFIG_NLS_ISO8859_13=y
169CONFIG_NLS_ISO8859_14=y
170CONFIG_NLS_ISO8859_15=y
171CONFIG_NLS_KOI8_R=y
172CONFIG_NLS_KOI8_U=y
173CONFIG_NLS_UTF8=y
174CONFIG_PRINTK_TIME=y
175CONFIG_DEBUG_INFO=y
176CONFIG_STRIP_ASM_SYMS=y
177CONFIG_READABLE_ASM=y
178CONFIG_DEBUG_KMEMLEAK=y
179CONFIG_DEBUG_MEMORY_INIT=y
180CONFIG_DEBUG_STACKOVERFLOW=y
181CONFIG_PANIC_ON_OOPS=y
182# CONFIG_FTRACE is not set
183CONFIG_KGDB=y
184CONFIG_RUNTIME_DEBUG=y
185CONFIG_CRYPTO_ZLIB=y
186# CONFIG_CRYPTO_ANSI_CPRNG is not set
187CONFIG_FONTS=y
188CONFIG_FONT_SUN8x16=y
diff --git a/arch/mips/configs/rb532_defconfig b/arch/mips/configs/rb532_defconfig
index b85b121397c8..5d9d708e12e5 100644
--- a/arch/mips/configs/rb532_defconfig
+++ b/arch/mips/configs/rb532_defconfig
@@ -114,7 +114,6 @@ CONFIG_NET_CLS_IND=y
114CONFIG_HAMRADIO=y 114CONFIG_HAMRADIO=y
115CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" 115CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
116CONFIG_MTD=y 116CONFIG_MTD=y
117CONFIG_MTD_PARTITIONS=y
118CONFIG_MTD_CHAR=y 117CONFIG_MTD_CHAR=y
119CONFIG_MTD_BLOCK=y 118CONFIG_MTD_BLOCK=y
120CONFIG_MTD_BLOCK2MTD=y 119CONFIG_MTD_BLOCK2MTD=y
diff --git a/arch/mips/configs/rbtx49xx_defconfig b/arch/mips/configs/rbtx49xx_defconfig
index 9cba856277ff..f8bf9b4c1343 100644
--- a/arch/mips/configs/rbtx49xx_defconfig
+++ b/arch/mips/configs/rbtx49xx_defconfig
@@ -35,7 +35,6 @@ CONFIG_IP_PNP=y
35# CONFIG_IPV6 is not set 35# CONFIG_IPV6 is not set
36# CONFIG_WIRELESS is not set 36# CONFIG_WIRELESS is not set
37CONFIG_MTD=y 37CONFIG_MTD=y
38CONFIG_MTD_PARTITIONS=y
39CONFIG_MTD_CMDLINE_PARTS=y 38CONFIG_MTD_CMDLINE_PARTS=y
40CONFIG_MTD_CHAR=y 39CONFIG_MTD_CHAR=y
41CONFIG_MTD_BLOCK=m 40CONFIG_MTD_BLOCK=m
diff --git a/arch/mips/fw/arc/file.c b/arch/mips/fw/arc/file.c
index a8b08032348f..49fd3ff13fe5 100644
--- a/arch/mips/fw/arc/file.c
+++ b/arch/mips/fw/arc/file.c
@@ -8,7 +8,6 @@
8 * Copyright (C) 1994, 1995, 1996, 1999 Ralf Baechle 8 * Copyright (C) 1994, 1995, 1996, 1999 Ralf Baechle
9 * Copyright (C) 1999 Silicon Graphics, Inc. 9 * Copyright (C) 1999 Silicon Graphics, Inc.
10 */ 10 */
11#include <linux/init.h>
12 11
13#include <asm/fw/arc/types.h> 12#include <asm/fw/arc/types.h>
14#include <asm/sgialib.h> 13#include <asm/sgialib.h>
diff --git a/arch/mips/include/asm/amon.h b/arch/mips/include/asm/amon.h
index c3dc1a68dd8d..3cc03c64a9c7 100644
--- a/arch/mips/include/asm/amon.h
+++ b/arch/mips/include/asm/amon.h
@@ -1,7 +1,12 @@
1/* 1/*
2 * Amon support 2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2013 Imagination Technologies Ltd.
7 *
8 * Arbitrary Monitor Support (AMON)
3 */ 9 */
4 10int amon_cpu_avail(int cpu);
5int amon_cpu_avail(int); 11int amon_cpu_start(int cpu, unsigned long pc, unsigned long sp,
6void amon_cpu_start(int, unsigned long, unsigned long, 12 unsigned long gp, unsigned long a0);
7 unsigned long, unsigned long);
diff --git a/arch/mips/include/asm/asmmacro-32.h b/arch/mips/include/asm/asmmacro-32.h
index 2413afe21b33..70e1f176f123 100644
--- a/arch/mips/include/asm/asmmacro-32.h
+++ b/arch/mips/include/asm/asmmacro-32.h
@@ -12,27 +12,6 @@
12#include <asm/fpregdef.h> 12#include <asm/fpregdef.h>
13#include <asm/mipsregs.h> 13#include <asm/mipsregs.h>
14 14
15 .macro fpu_save_double thread status tmp1=t0
16 cfc1 \tmp1, fcr31
17 sdc1 $f0, THREAD_FPR0(\thread)
18 sdc1 $f2, THREAD_FPR2(\thread)
19 sdc1 $f4, THREAD_FPR4(\thread)
20 sdc1 $f6, THREAD_FPR6(\thread)
21 sdc1 $f8, THREAD_FPR8(\thread)
22 sdc1 $f10, THREAD_FPR10(\thread)
23 sdc1 $f12, THREAD_FPR12(\thread)
24 sdc1 $f14, THREAD_FPR14(\thread)
25 sdc1 $f16, THREAD_FPR16(\thread)
26 sdc1 $f18, THREAD_FPR18(\thread)
27 sdc1 $f20, THREAD_FPR20(\thread)
28 sdc1 $f22, THREAD_FPR22(\thread)
29 sdc1 $f24, THREAD_FPR24(\thread)
30 sdc1 $f26, THREAD_FPR26(\thread)
31 sdc1 $f28, THREAD_FPR28(\thread)
32 sdc1 $f30, THREAD_FPR30(\thread)
33 sw \tmp1, THREAD_FCR31(\thread)
34 .endm
35
36 .macro fpu_save_single thread tmp=t0 15 .macro fpu_save_single thread tmp=t0
37 cfc1 \tmp, fcr31 16 cfc1 \tmp, fcr31
38 swc1 $f0, THREAD_FPR0(\thread) 17 swc1 $f0, THREAD_FPR0(\thread)
@@ -70,27 +49,6 @@
70 sw \tmp, THREAD_FCR31(\thread) 49 sw \tmp, THREAD_FCR31(\thread)
71 .endm 50 .endm
72 51
73 .macro fpu_restore_double thread status tmp=t0
74 lw \tmp, THREAD_FCR31(\thread)
75 ldc1 $f0, THREAD_FPR0(\thread)
76 ldc1 $f2, THREAD_FPR2(\thread)
77 ldc1 $f4, THREAD_FPR4(\thread)
78 ldc1 $f6, THREAD_FPR6(\thread)
79 ldc1 $f8, THREAD_FPR8(\thread)
80 ldc1 $f10, THREAD_FPR10(\thread)
81 ldc1 $f12, THREAD_FPR12(\thread)
82 ldc1 $f14, THREAD_FPR14(\thread)
83 ldc1 $f16, THREAD_FPR16(\thread)
84 ldc1 $f18, THREAD_FPR18(\thread)
85 ldc1 $f20, THREAD_FPR20(\thread)
86 ldc1 $f22, THREAD_FPR22(\thread)
87 ldc1 $f24, THREAD_FPR24(\thread)
88 ldc1 $f26, THREAD_FPR26(\thread)
89 ldc1 $f28, THREAD_FPR28(\thread)
90 ldc1 $f30, THREAD_FPR30(\thread)
91 ctc1 \tmp, fcr31
92 .endm
93
94 .macro fpu_restore_single thread tmp=t0 52 .macro fpu_restore_single thread tmp=t0
95 lw \tmp, THREAD_FCR31(\thread) 53 lw \tmp, THREAD_FCR31(\thread)
96 lwc1 $f0, THREAD_FPR0(\thread) 54 lwc1 $f0, THREAD_FPR0(\thread)
diff --git a/arch/mips/include/asm/asmmacro-64.h b/arch/mips/include/asm/asmmacro-64.h
index 08a527dfe4a3..38ea609465b1 100644
--- a/arch/mips/include/asm/asmmacro-64.h
+++ b/arch/mips/include/asm/asmmacro-64.h
@@ -13,102 +13,6 @@
13#include <asm/fpregdef.h> 13#include <asm/fpregdef.h>
14#include <asm/mipsregs.h> 14#include <asm/mipsregs.h>
15 15
16 .macro fpu_save_16even thread tmp=t0
17 cfc1 \tmp, fcr31
18 sdc1 $f0, THREAD_FPR0(\thread)
19 sdc1 $f2, THREAD_FPR2(\thread)
20 sdc1 $f4, THREAD_FPR4(\thread)
21 sdc1 $f6, THREAD_FPR6(\thread)
22 sdc1 $f8, THREAD_FPR8(\thread)
23 sdc1 $f10, THREAD_FPR10(\thread)
24 sdc1 $f12, THREAD_FPR12(\thread)
25 sdc1 $f14, THREAD_FPR14(\thread)
26 sdc1 $f16, THREAD_FPR16(\thread)
27 sdc1 $f18, THREAD_FPR18(\thread)
28 sdc1 $f20, THREAD_FPR20(\thread)
29 sdc1 $f22, THREAD_FPR22(\thread)
30 sdc1 $f24, THREAD_FPR24(\thread)
31 sdc1 $f26, THREAD_FPR26(\thread)
32 sdc1 $f28, THREAD_FPR28(\thread)
33 sdc1 $f30, THREAD_FPR30(\thread)
34 sw \tmp, THREAD_FCR31(\thread)
35 .endm
36
37 .macro fpu_save_16odd thread
38 sdc1 $f1, THREAD_FPR1(\thread)
39 sdc1 $f3, THREAD_FPR3(\thread)
40 sdc1 $f5, THREAD_FPR5(\thread)
41 sdc1 $f7, THREAD_FPR7(\thread)
42 sdc1 $f9, THREAD_FPR9(\thread)
43 sdc1 $f11, THREAD_FPR11(\thread)
44 sdc1 $f13, THREAD_FPR13(\thread)
45 sdc1 $f15, THREAD_FPR15(\thread)
46 sdc1 $f17, THREAD_FPR17(\thread)
47 sdc1 $f19, THREAD_FPR19(\thread)
48 sdc1 $f21, THREAD_FPR21(\thread)
49 sdc1 $f23, THREAD_FPR23(\thread)
50 sdc1 $f25, THREAD_FPR25(\thread)
51 sdc1 $f27, THREAD_FPR27(\thread)
52 sdc1 $f29, THREAD_FPR29(\thread)
53 sdc1 $f31, THREAD_FPR31(\thread)
54 .endm
55
56 .macro fpu_save_double thread status tmp
57 sll \tmp, \status, 5
58 bgez \tmp, 2f
59 fpu_save_16odd \thread
602:
61 fpu_save_16even \thread \tmp
62 .endm
63
64 .macro fpu_restore_16even thread tmp=t0
65 lw \tmp, THREAD_FCR31(\thread)
66 ldc1 $f0, THREAD_FPR0(\thread)
67 ldc1 $f2, THREAD_FPR2(\thread)
68 ldc1 $f4, THREAD_FPR4(\thread)
69 ldc1 $f6, THREAD_FPR6(\thread)
70 ldc1 $f8, THREAD_FPR8(\thread)
71 ldc1 $f10, THREAD_FPR10(\thread)
72 ldc1 $f12, THREAD_FPR12(\thread)
73 ldc1 $f14, THREAD_FPR14(\thread)
74 ldc1 $f16, THREAD_FPR16(\thread)
75 ldc1 $f18, THREAD_FPR18(\thread)
76 ldc1 $f20, THREAD_FPR20(\thread)
77 ldc1 $f22, THREAD_FPR22(\thread)
78 ldc1 $f24, THREAD_FPR24(\thread)
79 ldc1 $f26, THREAD_FPR26(\thread)
80 ldc1 $f28, THREAD_FPR28(\thread)
81 ldc1 $f30, THREAD_FPR30(\thread)
82 ctc1 \tmp, fcr31
83 .endm
84
85 .macro fpu_restore_16odd thread
86 ldc1 $f1, THREAD_FPR1(\thread)
87 ldc1 $f3, THREAD_FPR3(\thread)
88 ldc1 $f5, THREAD_FPR5(\thread)
89 ldc1 $f7, THREAD_FPR7(\thread)
90 ldc1 $f9, THREAD_FPR9(\thread)
91 ldc1 $f11, THREAD_FPR11(\thread)
92 ldc1 $f13, THREAD_FPR13(\thread)
93 ldc1 $f15, THREAD_FPR15(\thread)
94 ldc1 $f17, THREAD_FPR17(\thread)
95 ldc1 $f19, THREAD_FPR19(\thread)
96 ldc1 $f21, THREAD_FPR21(\thread)
97 ldc1 $f23, THREAD_FPR23(\thread)
98 ldc1 $f25, THREAD_FPR25(\thread)
99 ldc1 $f27, THREAD_FPR27(\thread)
100 ldc1 $f29, THREAD_FPR29(\thread)
101 ldc1 $f31, THREAD_FPR31(\thread)
102 .endm
103
104 .macro fpu_restore_double thread status tmp
105 sll \tmp, \status, 5
106 bgez \tmp, 1f # 16 register mode?
107
108 fpu_restore_16odd \thread
1091: fpu_restore_16even \thread \tmp
110 .endm
111
112 .macro cpu_save_nonscratch thread 16 .macro cpu_save_nonscratch thread
113 LONG_S s0, THREAD_REG16(\thread) 17 LONG_S s0, THREAD_REG16(\thread)
114 LONG_S s1, THREAD_REG17(\thread) 18 LONG_S s1, THREAD_REG17(\thread)
diff --git a/arch/mips/include/asm/asmmacro.h b/arch/mips/include/asm/asmmacro.h
index 6c8342ae74db..3220c93ea981 100644
--- a/arch/mips/include/asm/asmmacro.h
+++ b/arch/mips/include/asm/asmmacro.h
@@ -62,6 +62,113 @@
62 .endm 62 .endm
63#endif /* CONFIG_MIPS_MT_SMTC */ 63#endif /* CONFIG_MIPS_MT_SMTC */
64 64
65 .macro fpu_save_16even thread tmp=t0
66 cfc1 \tmp, fcr31
67 sdc1 $f0, THREAD_FPR0(\thread)
68 sdc1 $f2, THREAD_FPR2(\thread)
69 sdc1 $f4, THREAD_FPR4(\thread)
70 sdc1 $f6, THREAD_FPR6(\thread)
71 sdc1 $f8, THREAD_FPR8(\thread)
72 sdc1 $f10, THREAD_FPR10(\thread)
73 sdc1 $f12, THREAD_FPR12(\thread)
74 sdc1 $f14, THREAD_FPR14(\thread)
75 sdc1 $f16, THREAD_FPR16(\thread)
76 sdc1 $f18, THREAD_FPR18(\thread)
77 sdc1 $f20, THREAD_FPR20(\thread)
78 sdc1 $f22, THREAD_FPR22(\thread)
79 sdc1 $f24, THREAD_FPR24(\thread)
80 sdc1 $f26, THREAD_FPR26(\thread)
81 sdc1 $f28, THREAD_FPR28(\thread)
82 sdc1 $f30, THREAD_FPR30(\thread)
83 sw \tmp, THREAD_FCR31(\thread)
84 .endm
85
86 .macro fpu_save_16odd thread
87 .set push
88 .set mips64r2
89 sdc1 $f1, THREAD_FPR1(\thread)
90 sdc1 $f3, THREAD_FPR3(\thread)
91 sdc1 $f5, THREAD_FPR5(\thread)
92 sdc1 $f7, THREAD_FPR7(\thread)
93 sdc1 $f9, THREAD_FPR9(\thread)
94 sdc1 $f11, THREAD_FPR11(\thread)
95 sdc1 $f13, THREAD_FPR13(\thread)
96 sdc1 $f15, THREAD_FPR15(\thread)
97 sdc1 $f17, THREAD_FPR17(\thread)
98 sdc1 $f19, THREAD_FPR19(\thread)
99 sdc1 $f21, THREAD_FPR21(\thread)
100 sdc1 $f23, THREAD_FPR23(\thread)
101 sdc1 $f25, THREAD_FPR25(\thread)
102 sdc1 $f27, THREAD_FPR27(\thread)
103 sdc1 $f29, THREAD_FPR29(\thread)
104 sdc1 $f31, THREAD_FPR31(\thread)
105 .set pop
106 .endm
107
108 .macro fpu_save_double thread status tmp
109#if defined(CONFIG_MIPS64) || defined(CONFIG_CPU_MIPS32_R2)
110 sll \tmp, \status, 5
111 bgez \tmp, 10f
112 fpu_save_16odd \thread
11310:
114#endif
115 fpu_save_16even \thread \tmp
116 .endm
117
118 .macro fpu_restore_16even thread tmp=t0
119 lw \tmp, THREAD_FCR31(\thread)
120 ldc1 $f0, THREAD_FPR0(\thread)
121 ldc1 $f2, THREAD_FPR2(\thread)
122 ldc1 $f4, THREAD_FPR4(\thread)
123 ldc1 $f6, THREAD_FPR6(\thread)
124 ldc1 $f8, THREAD_FPR8(\thread)
125 ldc1 $f10, THREAD_FPR10(\thread)
126 ldc1 $f12, THREAD_FPR12(\thread)
127 ldc1 $f14, THREAD_FPR14(\thread)
128 ldc1 $f16, THREAD_FPR16(\thread)
129 ldc1 $f18, THREAD_FPR18(\thread)
130 ldc1 $f20, THREAD_FPR20(\thread)
131 ldc1 $f22, THREAD_FPR22(\thread)
132 ldc1 $f24, THREAD_FPR24(\thread)
133 ldc1 $f26, THREAD_FPR26(\thread)
134 ldc1 $f28, THREAD_FPR28(\thread)
135 ldc1 $f30, THREAD_FPR30(\thread)
136 ctc1 \tmp, fcr31
137 .endm
138
139 .macro fpu_restore_16odd thread
140 .set push
141 .set mips64r2
142 ldc1 $f1, THREAD_FPR1(\thread)
143 ldc1 $f3, THREAD_FPR3(\thread)
144 ldc1 $f5, THREAD_FPR5(\thread)
145 ldc1 $f7, THREAD_FPR7(\thread)
146 ldc1 $f9, THREAD_FPR9(\thread)
147 ldc1 $f11, THREAD_FPR11(\thread)
148 ldc1 $f13, THREAD_FPR13(\thread)
149 ldc1 $f15, THREAD_FPR15(\thread)
150 ldc1 $f17, THREAD_FPR17(\thread)
151 ldc1 $f19, THREAD_FPR19(\thread)
152 ldc1 $f21, THREAD_FPR21(\thread)
153 ldc1 $f23, THREAD_FPR23(\thread)
154 ldc1 $f25, THREAD_FPR25(\thread)
155 ldc1 $f27, THREAD_FPR27(\thread)
156 ldc1 $f29, THREAD_FPR29(\thread)
157 ldc1 $f31, THREAD_FPR31(\thread)
158 .set pop
159 .endm
160
161 .macro fpu_restore_double thread status tmp
162#if defined(CONFIG_MIPS64) || defined(CONFIG_CPU_MIPS32_R2)
163 sll \tmp, \status, 5
164 bgez \tmp, 10f # 16 register mode?
165
166 fpu_restore_16odd \thread
16710:
168#endif
169 fpu_restore_16even \thread \tmp
170 .endm
171
65/* 172/*
66 * Temporary until all gas have MT ASE support 173 * Temporary until all gas have MT ASE support
67 */ 174 */
diff --git a/arch/mips/include/asm/bmips.h b/arch/mips/include/asm/bmips.h
index 27bd060d716e..cbaccebf5065 100644
--- a/arch/mips/include/asm/bmips.h
+++ b/arch/mips/include/asm/bmips.h
@@ -46,8 +46,35 @@
46 46
47#include <linux/cpumask.h> 47#include <linux/cpumask.h>
48#include <asm/r4kcache.h> 48#include <asm/r4kcache.h>
49#include <asm/smp-ops.h>
50
51extern struct plat_smp_ops bmips43xx_smp_ops;
52extern struct plat_smp_ops bmips5000_smp_ops;
53
54static inline int register_bmips_smp_ops(void)
55{
56#if IS_ENABLED(CONFIG_CPU_BMIPS) && IS_ENABLED(CONFIG_SMP)
57 switch (current_cpu_type()) {
58 case CPU_BMIPS32:
59 case CPU_BMIPS3300:
60 return register_up_smp_ops();
61 case CPU_BMIPS4350:
62 case CPU_BMIPS4380:
63 register_smp_ops(&bmips43xx_smp_ops);
64 break;
65 case CPU_BMIPS5000:
66 register_smp_ops(&bmips5000_smp_ops);
67 break;
68 default:
69 return -ENODEV;
70 }
71
72 return 0;
73#else
74 return -ENODEV;
75#endif
76}
49 77
50extern struct plat_smp_ops bmips_smp_ops;
51extern char bmips_reset_nmi_vec; 78extern char bmips_reset_nmi_vec;
52extern char bmips_reset_nmi_vec_end; 79extern char bmips_reset_nmi_vec_end;
53extern char bmips_smp_movevec; 80extern char bmips_smp_movevec;
diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h
index d445d060e346..6e70b03b6aab 100644
--- a/arch/mips/include/asm/cpu-features.h
+++ b/arch/mips/include/asm/cpu-features.h
@@ -20,6 +20,13 @@
20#ifndef cpu_has_tlb 20#ifndef cpu_has_tlb
21#define cpu_has_tlb (cpu_data[0].options & MIPS_CPU_TLB) 21#define cpu_has_tlb (cpu_data[0].options & MIPS_CPU_TLB)
22#endif 22#endif
23#ifndef cpu_has_tlbinv
24#define cpu_has_tlbinv (cpu_data[0].options & MIPS_CPU_TLBINV)
25#endif
26#ifndef cpu_has_segments
27#define cpu_has_segments (cpu_data[0].options & MIPS_CPU_SEGMENTS)
28#endif
29
23 30
24/* 31/*
25 * For the moment we don't consider R6000 and R8000 so we can assume that 32 * For the moment we don't consider R6000 and R8000 so we can assume that
diff --git a/arch/mips/include/asm/cpu-info.h b/arch/mips/include/asm/cpu-info.h
index 21c8e29c8f91..8f7adf0ac1e3 100644
--- a/arch/mips/include/asm/cpu-info.h
+++ b/arch/mips/include/asm/cpu-info.h
@@ -52,6 +52,9 @@ struct cpuinfo_mips {
52 unsigned int cputype; 52 unsigned int cputype;
53 int isa_level; 53 int isa_level;
54 int tlbsize; 54 int tlbsize;
55 int tlbsizevtlb;
56 int tlbsizeftlbsets;
57 int tlbsizeftlbways;
55 struct cache_desc icache; /* Primary I-cache */ 58 struct cache_desc icache; /* Primary I-cache */
56 struct cache_desc dcache; /* Primary D or combined I/D cache */ 59 struct cache_desc dcache; /* Primary D or combined I/D cache */
57 struct cache_desc scache; /* Secondary cache */ 60 struct cache_desc scache; /* Secondary cache */
diff --git a/arch/mips/include/asm/cpu-type.h b/arch/mips/include/asm/cpu-type.h
index 4a402cc60c03..02f591bd95ca 100644
--- a/arch/mips/include/asm/cpu-type.h
+++ b/arch/mips/include/asm/cpu-type.h
@@ -27,10 +27,7 @@ static inline int __pure __get_cpu_type(const int cpu_type)
27#ifdef CONFIG_SYS_HAS_CPU_MIPS32_R1 27#ifdef CONFIG_SYS_HAS_CPU_MIPS32_R1
28 case CPU_4KC: 28 case CPU_4KC:
29 case CPU_ALCHEMY: 29 case CPU_ALCHEMY:
30 case CPU_BMIPS3300:
31 case CPU_BMIPS4350:
32 case CPU_PR4450: 30 case CPU_PR4450:
33 case CPU_BMIPS32:
34 case CPU_JZRISC: 31 case CPU_JZRISC:
35#endif 32#endif
36 33
@@ -47,6 +44,8 @@ static inline int __pure __get_cpu_type(const int cpu_type)
47 case CPU_74K: 44 case CPU_74K:
48 case CPU_M14KC: 45 case CPU_M14KC:
49 case CPU_M14KEC: 46 case CPU_M14KEC:
47 case CPU_INTERAPTIV:
48 case CPU_PROAPTIV:
50#endif 49#endif
51 50
52#ifdef CONFIG_SYS_HAS_CPU_MIPS64_R1 51#ifdef CONFIG_SYS_HAS_CPU_MIPS64_R1
@@ -163,6 +162,16 @@ static inline int __pure __get_cpu_type(const int cpu_type)
163 case CPU_CAVIUM_OCTEON2: 162 case CPU_CAVIUM_OCTEON2:
164#endif 163#endif
165 164
165#if defined(CONFIG_SYS_HAS_CPU_BMIPS32_3300) || \
166 defined (CONFIG_SYS_HAS_CPU_MIPS32_R1)
167 case CPU_BMIPS32:
168 case CPU_BMIPS3300:
169#endif
170
171#ifdef CONFIG_SYS_HAS_CPU_BMIPS4350
172 case CPU_BMIPS4350:
173#endif
174
166#ifdef CONFIG_SYS_HAS_CPU_BMIPS4380 175#ifdef CONFIG_SYS_HAS_CPU_BMIPS4380
167 case CPU_BMIPS4380: 176 case CPU_BMIPS4380:
168#endif 177#endif
diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
index d2035e16502a..76411df3d971 100644
--- a/arch/mips/include/asm/cpu.h
+++ b/arch/mips/include/asm/cpu.h
@@ -111,6 +111,10 @@
111#define PRID_IMP_1074K 0x9a00 111#define PRID_IMP_1074K 0x9a00
112#define PRID_IMP_M14KC 0x9c00 112#define PRID_IMP_M14KC 0x9c00
113#define PRID_IMP_M14KEC 0x9e00 113#define PRID_IMP_M14KEC 0x9e00
114#define PRID_IMP_INTERAPTIV_UP 0xa000
115#define PRID_IMP_INTERAPTIV_MP 0xa100
116#define PRID_IMP_PROAPTIV_UP 0xa200
117#define PRID_IMP_PROAPTIV_MP 0xa300
114 118
115/* 119/*
116 * These are the PRID's for when 23:16 == PRID_COMP_SIBYTE 120 * These are the PRID's for when 23:16 == PRID_COMP_SIBYTE
@@ -194,6 +198,7 @@
194#define PRID_IMP_NETLOGIC_XLP8XX 0x1000 198#define PRID_IMP_NETLOGIC_XLP8XX 0x1000
195#define PRID_IMP_NETLOGIC_XLP3XX 0x1100 199#define PRID_IMP_NETLOGIC_XLP3XX 0x1100
196#define PRID_IMP_NETLOGIC_XLP2XX 0x1200 200#define PRID_IMP_NETLOGIC_XLP2XX 0x1200
201#define PRID_IMP_NETLOGIC_XLP9XX 0x1500
197 202
198/* 203/*
199 * Particular Revision values for bits 7:0 of the PRId register. 204 * Particular Revision values for bits 7:0 of the PRId register.
@@ -249,6 +254,8 @@
249 254
250#define FPIR_IMP_NONE 0x0000 255#define FPIR_IMP_NONE 0x0000
251 256
257#if !defined(__ASSEMBLY__)
258
252enum cpu_type_enum { 259enum cpu_type_enum {
253 CPU_UNKNOWN, 260 CPU_UNKNOWN,
254 261
@@ -289,7 +296,7 @@ enum cpu_type_enum {
289 CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_1004K, CPU_74K, 296 CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_1004K, CPU_74K,
290 CPU_ALCHEMY, CPU_PR4450, CPU_BMIPS32, CPU_BMIPS3300, CPU_BMIPS4350, 297 CPU_ALCHEMY, CPU_PR4450, CPU_BMIPS32, CPU_BMIPS3300, CPU_BMIPS4350,
291 CPU_BMIPS4380, CPU_BMIPS5000, CPU_JZRISC, CPU_LOONGSON1, CPU_M14KC, 298 CPU_BMIPS4380, CPU_BMIPS5000, CPU_JZRISC, CPU_LOONGSON1, CPU_M14KC,
292 CPU_M14KEC, 299 CPU_M14KEC, CPU_INTERAPTIV, CPU_PROAPTIV,
293 300
294 /* 301 /*
295 * MIPS64 class processors 302 * MIPS64 class processors
@@ -301,6 +308,7 @@ enum cpu_type_enum {
301 CPU_LAST 308 CPU_LAST
302}; 309};
303 310
311#endif /* !__ASSEMBLY */
304 312
305/* 313/*
306 * ISA Level encodings 314 * ISA Level encodings
@@ -348,6 +356,8 @@ enum cpu_type_enum {
348#define MIPS_CPU_PCI 0x00400000 /* CPU has Perf Ctr Int indicator */ 356#define MIPS_CPU_PCI 0x00400000 /* CPU has Perf Ctr Int indicator */
349#define MIPS_CPU_RIXI 0x00800000 /* CPU has TLB Read/eXec Inhibit */ 357#define MIPS_CPU_RIXI 0x00800000 /* CPU has TLB Read/eXec Inhibit */
350#define MIPS_CPU_MICROMIPS 0x01000000 /* CPU has microMIPS capability */ 358#define MIPS_CPU_MICROMIPS 0x01000000 /* CPU has microMIPS capability */
359#define MIPS_CPU_TLBINV 0x02000000 /* CPU supports TLBINV/F */
360#define MIPS_CPU_SEGMENTS 0x04000000 /* CPU supports Segmentation Control registers */
351 361
352/* 362/*
353 * CPU ASE encodings 363 * CPU ASE encodings
diff --git a/arch/mips/include/asm/dma-coherence.h b/arch/mips/include/asm/dma-coherence.h
index 242cbb3ca582..bc5e85d579e6 100644
--- a/arch/mips/include/asm/dma-coherence.h
+++ b/arch/mips/include/asm/dma-coherence.h
@@ -9,7 +9,16 @@
9#ifndef __ASM_DMA_COHERENCE_H 9#ifndef __ASM_DMA_COHERENCE_H
10#define __ASM_DMA_COHERENCE_H 10#define __ASM_DMA_COHERENCE_H
11 11
12#ifdef CONFIG_DMA_MAYBE_COHERENT
12extern int coherentio; 13extern int coherentio;
13extern int hw_coherentio; 14extern int hw_coherentio;
15#else
16#ifdef CONFIG_DMA_COHERENT
17#define coherentio 1
18#else
19#define coherentio 0
20#endif
21#define hw_coherentio 0
22#endif /* CONFIG_DMA_MAYBE_COHERENT */
14 23
15#endif 24#endif
diff --git a/arch/mips/include/asm/elf.h b/arch/mips/include/asm/elf.h
index a66359ef4ece..d4144056e928 100644
--- a/arch/mips/include/asm/elf.h
+++ b/arch/mips/include/asm/elf.h
@@ -36,6 +36,7 @@
36#define EF_MIPS_ABI2 0x00000020 36#define EF_MIPS_ABI2 0x00000020
37#define EF_MIPS_OPTIONS_FIRST 0x00000080 37#define EF_MIPS_OPTIONS_FIRST 0x00000080
38#define EF_MIPS_32BITMODE 0x00000100 38#define EF_MIPS_32BITMODE 0x00000100
39#define EF_MIPS_FP64 0x00000200
39#define EF_MIPS_ABI 0x0000f000 40#define EF_MIPS_ABI 0x0000f000
40#define EF_MIPS_ARCH 0xf0000000 41#define EF_MIPS_ARCH 0xf0000000
41 42
@@ -176,6 +177,18 @@ typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG];
176#ifdef CONFIG_32BIT 177#ifdef CONFIG_32BIT
177 178
178/* 179/*
180 * In order to be sure that we don't attempt to execute an O32 binary which
181 * requires 64 bit FP (FR=1) on a system which does not support it we refuse
182 * to execute any binary which has bits specified by the following macro set
183 * in its ELF header flags.
184 */
185#ifdef CONFIG_MIPS_O32_FP64_SUPPORT
186# define __MIPS_O32_FP64_MUST_BE_ZERO 0
187#else
188# define __MIPS_O32_FP64_MUST_BE_ZERO EF_MIPS_FP64
189#endif
190
191/*
179 * This is used to ensure we don't load something for the wrong architecture. 192 * This is used to ensure we don't load something for the wrong architecture.
180 */ 193 */
181#define elf_check_arch(hdr) \ 194#define elf_check_arch(hdr) \
@@ -192,6 +205,8 @@ typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG];
192 if (((__h->e_flags & EF_MIPS_ABI) != 0) && \ 205 if (((__h->e_flags & EF_MIPS_ABI) != 0) && \
193 ((__h->e_flags & EF_MIPS_ABI) != EF_MIPS_ABI_O32)) \ 206 ((__h->e_flags & EF_MIPS_ABI) != EF_MIPS_ABI_O32)) \
194 __res = 0; \ 207 __res = 0; \
208 if (__h->e_flags & __MIPS_O32_FP64_MUST_BE_ZERO) \
209 __res = 0; \
195 \ 210 \
196 __res; \ 211 __res; \
197}) 212})
@@ -249,6 +264,11 @@ extern struct mips_abi mips_abi_n32;
249 264
250#define SET_PERSONALITY(ex) \ 265#define SET_PERSONALITY(ex) \
251do { \ 266do { \
267 if ((ex).e_flags & EF_MIPS_FP64) \
268 clear_thread_flag(TIF_32BIT_FPREGS); \
269 else \
270 set_thread_flag(TIF_32BIT_FPREGS); \
271 \
252 if (personality(current->personality) != PER_LINUX) \ 272 if (personality(current->personality) != PER_LINUX) \
253 set_personality(PER_LINUX); \ 273 set_personality(PER_LINUX); \
254 \ 274 \
@@ -271,14 +291,18 @@ do { \
271#endif 291#endif
272 292
273#ifdef CONFIG_MIPS32_O32 293#ifdef CONFIG_MIPS32_O32
274#define __SET_PERSONALITY32_O32() \ 294#define __SET_PERSONALITY32_O32(ex) \
275 do { \ 295 do { \
276 set_thread_flag(TIF_32BIT_REGS); \ 296 set_thread_flag(TIF_32BIT_REGS); \
277 set_thread_flag(TIF_32BIT_ADDR); \ 297 set_thread_flag(TIF_32BIT_ADDR); \
298 \
299 if (!((ex).e_flags & EF_MIPS_FP64)) \
300 set_thread_flag(TIF_32BIT_FPREGS); \
301 \
278 current->thread.abi = &mips_abi_32; \ 302 current->thread.abi = &mips_abi_32; \
279 } while (0) 303 } while (0)
280#else 304#else
281#define __SET_PERSONALITY32_O32() \ 305#define __SET_PERSONALITY32_O32(ex) \
282 do { } while (0) 306 do { } while (0)
283#endif 307#endif
284 308
@@ -289,7 +313,7 @@ do { \
289 ((ex).e_flags & EF_MIPS_ABI) == 0) \ 313 ((ex).e_flags & EF_MIPS_ABI) == 0) \
290 __SET_PERSONALITY32_N32(); \ 314 __SET_PERSONALITY32_N32(); \
291 else \ 315 else \
292 __SET_PERSONALITY32_O32(); \ 316 __SET_PERSONALITY32_O32(ex); \
293} while (0) 317} while (0)
294#else 318#else
295#define __SET_PERSONALITY32(ex) do { } while (0) 319#define __SET_PERSONALITY32(ex) do { } while (0)
@@ -300,6 +324,7 @@ do { \
300 unsigned int p; \ 324 unsigned int p; \
301 \ 325 \
302 clear_thread_flag(TIF_32BIT_REGS); \ 326 clear_thread_flag(TIF_32BIT_REGS); \
327 clear_thread_flag(TIF_32BIT_FPREGS); \
303 clear_thread_flag(TIF_32BIT_ADDR); \ 328 clear_thread_flag(TIF_32BIT_ADDR); \
304 \ 329 \
305 if ((ex).e_ident[EI_CLASS] == ELFCLASS32) \ 330 if ((ex).e_ident[EI_CLASS] == ELFCLASS32) \
diff --git a/arch/mips/include/asm/fpu.h b/arch/mips/include/asm/fpu.h
index d088e5db4903..cfe092fc720d 100644
--- a/arch/mips/include/asm/fpu.h
+++ b/arch/mips/include/asm/fpu.h
@@ -33,11 +33,48 @@ extern void _init_fpu(void);
33extern void _save_fp(struct task_struct *); 33extern void _save_fp(struct task_struct *);
34extern void _restore_fp(struct task_struct *); 34extern void _restore_fp(struct task_struct *);
35 35
36#define __enable_fpu() \ 36/*
37do { \ 37 * This enum specifies a mode in which we want the FPU to operate, for cores
38 set_c0_status(ST0_CU1); \ 38 * which implement the Status.FR bit. Note that FPU_32BIT & FPU_64BIT
39 enable_fpu_hazard(); \ 39 * purposefully have the values 0 & 1 respectively, so that an integer value
40} while (0) 40 * of Status.FR can be trivially casted to the corresponding enum fpu_mode.
41 */
42enum fpu_mode {
43 FPU_32BIT = 0, /* FR = 0 */
44 FPU_64BIT, /* FR = 1 */
45 FPU_AS_IS,
46};
47
48static inline int __enable_fpu(enum fpu_mode mode)
49{
50 int fr;
51
52 switch (mode) {
53 case FPU_AS_IS:
54 /* just enable the FPU in its current mode */
55 set_c0_status(ST0_CU1);
56 enable_fpu_hazard();
57 return 0;
58
59 case FPU_64BIT:
60#if !(defined(CONFIG_CPU_MIPS32_R2) || defined(CONFIG_MIPS64))
61 /* we only have a 32-bit FPU */
62 return SIGFPE;
63#endif
64 /* fall through */
65 case FPU_32BIT:
66 /* set CU1 & change FR appropriately */
67 fr = (int)mode;
68 change_c0_status(ST0_CU1 | ST0_FR, ST0_CU1 | (fr ? ST0_FR : 0));
69 enable_fpu_hazard();
70
71 /* check FR has the desired value */
72 return (!!(read_c0_status() & ST0_FR) == !!fr) ? 0 : SIGFPE;
73
74 default:
75 BUG();
76 }
77}
41 78
42#define __disable_fpu() \ 79#define __disable_fpu() \
43do { \ 80do { \
@@ -45,19 +82,6 @@ do { \
45 disable_fpu_hazard(); \ 82 disable_fpu_hazard(); \
46} while (0) 83} while (0)
47 84
48#define enable_fpu() \
49do { \
50 if (cpu_has_fpu) \
51 __enable_fpu(); \
52} while (0)
53
54#define disable_fpu() \
55do { \
56 if (cpu_has_fpu) \
57 __disable_fpu(); \
58} while (0)
59
60
61#define clear_fpu_owner() clear_thread_flag(TIF_USEDFPU) 85#define clear_fpu_owner() clear_thread_flag(TIF_USEDFPU)
62 86
63static inline int __is_fpu_owner(void) 87static inline int __is_fpu_owner(void)
@@ -70,27 +94,46 @@ static inline int is_fpu_owner(void)
70 return cpu_has_fpu && __is_fpu_owner(); 94 return cpu_has_fpu && __is_fpu_owner();
71} 95}
72 96
73static inline void __own_fpu(void) 97static inline int __own_fpu(void)
74{ 98{
75 __enable_fpu(); 99 enum fpu_mode mode;
100 int ret;
101
102 mode = !test_thread_flag(TIF_32BIT_FPREGS);
103 ret = __enable_fpu(mode);
104 if (ret)
105 return ret;
106
76 KSTK_STATUS(current) |= ST0_CU1; 107 KSTK_STATUS(current) |= ST0_CU1;
108 if (mode == FPU_64BIT)
109 KSTK_STATUS(current) |= ST0_FR;
110 else /* mode == FPU_32BIT */
111 KSTK_STATUS(current) &= ~ST0_FR;
112
77 set_thread_flag(TIF_USEDFPU); 113 set_thread_flag(TIF_USEDFPU);
114 return 0;
78} 115}
79 116
80static inline void own_fpu_inatomic(int restore) 117static inline int own_fpu_inatomic(int restore)
81{ 118{
119 int ret = 0;
120
82 if (cpu_has_fpu && !__is_fpu_owner()) { 121 if (cpu_has_fpu && !__is_fpu_owner()) {
83 __own_fpu(); 122 ret = __own_fpu();
84 if (restore) 123 if (restore && !ret)
85 _restore_fp(current); 124 _restore_fp(current);
86 } 125 }
126 return ret;
87} 127}
88 128
89static inline void own_fpu(int restore) 129static inline int own_fpu(int restore)
90{ 130{
131 int ret;
132
91 preempt_disable(); 133 preempt_disable();
92 own_fpu_inatomic(restore); 134 ret = own_fpu_inatomic(restore);
93 preempt_enable(); 135 preempt_enable();
136 return ret;
94} 137}
95 138
96static inline void lose_fpu(int save) 139static inline void lose_fpu(int save)
@@ -106,16 +149,21 @@ static inline void lose_fpu(int save)
106 preempt_enable(); 149 preempt_enable();
107} 150}
108 151
109static inline void init_fpu(void) 152static inline int init_fpu(void)
110{ 153{
154 int ret = 0;
155
111 preempt_disable(); 156 preempt_disable();
112 if (cpu_has_fpu) { 157 if (cpu_has_fpu) {
113 __own_fpu(); 158 ret = __own_fpu();
114 _init_fpu(); 159 if (!ret)
160 _init_fpu();
115 } else { 161 } else {
116 fpu_emulator_init_fpu(); 162 fpu_emulator_init_fpu();
117 } 163 }
164
118 preempt_enable(); 165 preempt_enable();
166 return ret;
119} 167}
120 168
121static inline void save_fp(struct task_struct *tsk) 169static inline void save_fp(struct task_struct *tsk)
diff --git a/arch/mips/include/asm/highmem.h b/arch/mips/include/asm/highmem.h
index b0dd0c84df70..572e63ec2a38 100644
--- a/arch/mips/include/asm/highmem.h
+++ b/arch/mips/include/asm/highmem.h
@@ -19,7 +19,6 @@
19 19
20#ifdef __KERNEL__ 20#ifdef __KERNEL__
21 21
22#include <linux/init.h>
23#include <linux/interrupt.h> 22#include <linux/interrupt.h>
24#include <linux/uaccess.h> 23#include <linux/uaccess.h>
25#include <asm/kmap_types.h> 24#include <asm/kmap_types.h>
diff --git a/arch/mips/include/asm/kvm_host.h b/arch/mips/include/asm/kvm_host.h
index 32966969f2f9..a995fce87791 100644
--- a/arch/mips/include/asm/kvm_host.h
+++ b/arch/mips/include/asm/kvm_host.h
@@ -391,9 +391,6 @@ struct kvm_vcpu_arch {
391 uint32_t guest_kernel_asid[NR_CPUS]; 391 uint32_t guest_kernel_asid[NR_CPUS];
392 struct mm_struct guest_kernel_mm, guest_user_mm; 392 struct mm_struct guest_kernel_mm, guest_user_mm;
393 393
394 struct kvm_mips_tlb shadow_tlb[NR_CPUS][KVM_MIPS_GUEST_TLB_SIZE];
395
396
397 struct hrtimer comparecount_timer; 394 struct hrtimer comparecount_timer;
398 395
399 int last_sched_cpu; 396 int last_sched_cpu;
@@ -529,7 +526,6 @@ extern enum emulation_result kvm_mips_handle_tlbmod(unsigned long cause,
529 526
530extern void kvm_mips_dump_host_tlbs(void); 527extern void kvm_mips_dump_host_tlbs(void);
531extern void kvm_mips_dump_guest_tlbs(struct kvm_vcpu *vcpu); 528extern void kvm_mips_dump_guest_tlbs(struct kvm_vcpu *vcpu);
532extern void kvm_mips_dump_shadow_tlbs(struct kvm_vcpu *vcpu);
533extern void kvm_mips_flush_host_tlb(int skip_kseg0); 529extern void kvm_mips_flush_host_tlb(int skip_kseg0);
534extern int kvm_mips_host_tlb_inv(struct kvm_vcpu *vcpu, unsigned long entryhi); 530extern int kvm_mips_host_tlb_inv(struct kvm_vcpu *vcpu, unsigned long entryhi);
535extern int kvm_mips_host_tlb_inv_index(struct kvm_vcpu *vcpu, int index); 531extern int kvm_mips_host_tlb_inv_index(struct kvm_vcpu *vcpu, int index);
@@ -541,10 +537,7 @@ extern unsigned long kvm_mips_translate_guest_kseg0_to_hpa(struct kvm_vcpu *vcpu
541 unsigned long gva); 537 unsigned long gva);
542extern void kvm_get_new_mmu_context(struct mm_struct *mm, unsigned long cpu, 538extern void kvm_get_new_mmu_context(struct mm_struct *mm, unsigned long cpu,
543 struct kvm_vcpu *vcpu); 539 struct kvm_vcpu *vcpu);
544extern void kvm_shadow_tlb_put(struct kvm_vcpu *vcpu);
545extern void kvm_shadow_tlb_load(struct kvm_vcpu *vcpu);
546extern void kvm_local_flush_tlb_all(void); 540extern void kvm_local_flush_tlb_all(void);
547extern void kvm_mips_init_shadow_tlb(struct kvm_vcpu *vcpu);
548extern void kvm_mips_alloc_new_mmu_context(struct kvm_vcpu *vcpu); 541extern void kvm_mips_alloc_new_mmu_context(struct kvm_vcpu *vcpu);
549extern void kvm_mips_vcpu_load(struct kvm_vcpu *vcpu, int cpu); 542extern void kvm_mips_vcpu_load(struct kvm_vcpu *vcpu, int cpu);
550extern void kvm_mips_vcpu_put(struct kvm_vcpu *vcpu); 543extern void kvm_mips_vcpu_put(struct kvm_vcpu *vcpu);
diff --git a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
index b86a1253a5bf..cd41e93bc1d8 100644
--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
@@ -16,7 +16,6 @@
16#define __ASM_MACH_AR71XX_REGS_H 16#define __ASM_MACH_AR71XX_REGS_H
17 17
18#include <linux/types.h> 18#include <linux/types.h>
19#include <linux/init.h>
20#include <linux/io.h> 19#include <linux/io.h>
21#include <linux/bitops.h> 20#include <linux/bitops.h>
22 21
diff --git a/arch/mips/include/asm/mach-bcm47xx/bcm47xx.h b/arch/mips/include/asm/mach-bcm47xx/bcm47xx.h
index cc7563ba1cbf..7527c1d33d02 100644
--- a/arch/mips/include/asm/mach-bcm47xx/bcm47xx.h
+++ b/arch/mips/include/asm/mach-bcm47xx/bcm47xx.h
@@ -56,4 +56,6 @@ void bcm47xx_fill_bcma_boardinfo(struct bcma_boardinfo *boardinfo,
56 const char *prefix); 56 const char *prefix);
57#endif 57#endif
58 58
59void bcm47xx_set_system_type(u16 chip_id);
60
59#endif /* __ASM_BCM47XX_H */ 61#endif /* __ASM_BCM47XX_H */
diff --git a/arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h b/arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h
index 00867dd05a69..40005fb39618 100644
--- a/arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h
+++ b/arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h
@@ -66,6 +66,7 @@ enum bcm47xx_board {
66 BCM47XX_BOARD_LINKSYS_WRT310NV1, 66 BCM47XX_BOARD_LINKSYS_WRT310NV1,
67 BCM47XX_BOARD_LINKSYS_WRT310NV2, 67 BCM47XX_BOARD_LINKSYS_WRT310NV2,
68 BCM47XX_BOARD_LINKSYS_WRT54G3GV2, 68 BCM47XX_BOARD_LINKSYS_WRT54G3GV2,
69 BCM47XX_BOARD_LINKSYS_WRT54GSV1,
69 BCM47XX_BOARD_LINKSYS_WRT610NV1, 70 BCM47XX_BOARD_LINKSYS_WRT610NV1,
70 BCM47XX_BOARD_LINKSYS_WRT610NV2, 71 BCM47XX_BOARD_LINKSYS_WRT610NV2,
71 BCM47XX_BOARD_LINKSYS_WRTSL54GS, 72 BCM47XX_BOARD_LINKSYS_WRTSL54GS,
diff --git a/arch/mips/include/asm/mach-bcm47xx/cpu-feature-overrides.h b/arch/mips/include/asm/mach-bcm47xx/cpu-feature-overrides.h
new file mode 100644
index 000000000000..b7992cd4aaf9
--- /dev/null
+++ b/arch/mips/include/asm/mach-bcm47xx/cpu-feature-overrides.h
@@ -0,0 +1,82 @@
1#ifndef __ASM_MACH_BCM47XX_CPU_FEATURE_OVERRIDES_H
2#define __ASM_MACH_BCM47XX_CPU_FEATURE_OVERRIDES_H
3
4#define cpu_has_tlb 1
5#define cpu_has_4kex 1
6#define cpu_has_3k_cache 0
7#define cpu_has_4k_cache 1
8#define cpu_has_tx39_cache 0
9#define cpu_has_fpu 0
10#define cpu_has_32fpr 0
11#define cpu_has_counter 1
12#if defined(CONFIG_BCM47XX_BCMA) && !defined(CONFIG_BCM47XX_SSB)
13#define cpu_has_watch 1
14#elif defined(CONFIG_BCM47XX_SSB) && !defined(CONFIG_BCM47XX_BCMA)
15#define cpu_has_watch 0
16#endif
17#define cpu_has_divec 1
18#define cpu_has_vce 0
19#define cpu_has_cache_cdex_p 0
20#define cpu_has_cache_cdex_s 0
21#define cpu_has_prefetch 1
22#define cpu_has_mcheck 1
23#define cpu_has_ejtag 1
24#define cpu_has_llsc 1
25
26/* cpu_has_mips16 */
27#define cpu_has_mdmx 0
28#define cpu_has_mips3d 0
29#define cpu_has_rixi 0
30#define cpu_has_mmips 0
31#define cpu_has_smartmips 0
32#define cpu_has_vtag_icache 0
33/* cpu_has_dc_aliases */
34#define cpu_has_ic_fills_f_dc 0
35#define cpu_has_pindexed_dcache 0
36#define cpu_icache_snoops_remote_store 0
37
38#define cpu_has_mips_2 1
39#define cpu_has_mips_3 0
40#define cpu_has_mips32r1 1
41#if defined(CONFIG_BCM47XX_BCMA) && !defined(CONFIG_BCM47XX_SSB)
42#define cpu_has_mips32r2 1
43#elif defined(CONFIG_BCM47XX_SSB) && !defined(CONFIG_BCM47XX_BCMA)
44#define cpu_has_mips32r2 0
45#endif
46#define cpu_has_mips64r1 0
47#define cpu_has_mips64r2 0
48
49#if defined(CONFIG_BCM47XX_BCMA) && !defined(CONFIG_BCM47XX_SSB)
50#define cpu_has_dsp 1
51#define cpu_has_dsp2 1
52#elif defined(CONFIG_BCM47XX_SSB) && !defined(CONFIG_BCM47XX_BCMA)
53#define cpu_has_dsp 0
54#define cpu_has_dsp2 0
55#endif
56#define cpu_has_mipsmt 0
57/* cpu_has_userlocal */
58
59#define cpu_has_nofpuex 0
60#define cpu_has_64bits 0
61#define cpu_has_64bit_zero_reg 0
62#if defined(CONFIG_BCM47XX_BCMA) && !defined(CONFIG_BCM47XX_SSB)
63#define cpu_has_vint 1
64#elif defined(CONFIG_BCM47XX_SSB) && !defined(CONFIG_BCM47XX_BCMA)
65#define cpu_has_vint 0
66#endif
67#define cpu_has_veic 0
68#define cpu_has_inclusive_pcaches 0
69
70#if defined(CONFIG_BCM47XX_BCMA) && !defined(CONFIG_BCM47XX_SSB)
71#define cpu_dcache_line_size() 32
72#define cpu_icache_line_size() 32
73#define cpu_has_perf_cntr_intr_bit 1
74#elif defined(CONFIG_BCM47XX_SSB) && !defined(CONFIG_BCM47XX_BCMA)
75#define cpu_dcache_line_size() 16
76#define cpu_icache_line_size() 16
77#define cpu_has_perf_cntr_intr_bit 0
78#endif
79#define cpu_scache_line_size() 0
80#define cpu_has_vz 0
81
82#endif /* __ASM_MACH_BCM47XX_CPU_FEATURE_OVERRIDES_H */
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
index 19f9134bfe2f..3112f08f0c72 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
@@ -145,6 +145,7 @@ enum bcm63xx_regs_set {
145 RSET_UART1, 145 RSET_UART1,
146 RSET_GPIO, 146 RSET_GPIO,
147 RSET_SPI, 147 RSET_SPI,
148 RSET_HSSPI,
148 RSET_UDC0, 149 RSET_UDC0,
149 RSET_OHCI0, 150 RSET_OHCI0,
150 RSET_OHCI_PRIV, 151 RSET_OHCI_PRIV,
@@ -193,6 +194,7 @@ enum bcm63xx_regs_set {
193#define RSET_ENETDMAS_SIZE(chans) (16 * (chans)) 194#define RSET_ENETDMAS_SIZE(chans) (16 * (chans))
194#define RSET_ENETSW_SIZE 65536 195#define RSET_ENETSW_SIZE 65536
195#define RSET_UART_SIZE 24 196#define RSET_UART_SIZE 24
197#define RSET_HSSPI_SIZE 1536
196#define RSET_UDC_SIZE 256 198#define RSET_UDC_SIZE 256
197#define RSET_OHCI_SIZE 256 199#define RSET_OHCI_SIZE 256
198#define RSET_EHCI_SIZE 256 200#define RSET_EHCI_SIZE 256
@@ -265,6 +267,7 @@ enum bcm63xx_regs_set {
265#define BCM_6328_UART1_BASE (0xb0000120) 267#define BCM_6328_UART1_BASE (0xb0000120)
266#define BCM_6328_GPIO_BASE (0xb0000080) 268#define BCM_6328_GPIO_BASE (0xb0000080)
267#define BCM_6328_SPI_BASE (0xdeadbeef) 269#define BCM_6328_SPI_BASE (0xdeadbeef)
270#define BCM_6328_HSSPI_BASE (0xb0001000)
268#define BCM_6328_UDC0_BASE (0xdeadbeef) 271#define BCM_6328_UDC0_BASE (0xdeadbeef)
269#define BCM_6328_USBDMA_BASE (0xb000c000) 272#define BCM_6328_USBDMA_BASE (0xb000c000)
270#define BCM_6328_OHCI0_BASE (0xb0002600) 273#define BCM_6328_OHCI0_BASE (0xb0002600)
@@ -313,6 +316,7 @@ enum bcm63xx_regs_set {
313#define BCM_6338_UART1_BASE (0xdeadbeef) 316#define BCM_6338_UART1_BASE (0xdeadbeef)
314#define BCM_6338_GPIO_BASE (0xfffe0400) 317#define BCM_6338_GPIO_BASE (0xfffe0400)
315#define BCM_6338_SPI_BASE (0xfffe0c00) 318#define BCM_6338_SPI_BASE (0xfffe0c00)
319#define BCM_6338_HSSPI_BASE (0xdeadbeef)
316#define BCM_6338_UDC0_BASE (0xdeadbeef) 320#define BCM_6338_UDC0_BASE (0xdeadbeef)
317#define BCM_6338_USBDMA_BASE (0xfffe2400) 321#define BCM_6338_USBDMA_BASE (0xfffe2400)
318#define BCM_6338_OHCI0_BASE (0xdeadbeef) 322#define BCM_6338_OHCI0_BASE (0xdeadbeef)
@@ -360,6 +364,7 @@ enum bcm63xx_regs_set {
360#define BCM_6345_UART1_BASE (0xdeadbeef) 364#define BCM_6345_UART1_BASE (0xdeadbeef)
361#define BCM_6345_GPIO_BASE (0xfffe0400) 365#define BCM_6345_GPIO_BASE (0xfffe0400)
362#define BCM_6345_SPI_BASE (0xdeadbeef) 366#define BCM_6345_SPI_BASE (0xdeadbeef)
367#define BCM_6345_HSSPI_BASE (0xdeadbeef)
363#define BCM_6345_UDC0_BASE (0xdeadbeef) 368#define BCM_6345_UDC0_BASE (0xdeadbeef)
364#define BCM_6345_USBDMA_BASE (0xfffe2800) 369#define BCM_6345_USBDMA_BASE (0xfffe2800)
365#define BCM_6345_ENET0_BASE (0xfffe1800) 370#define BCM_6345_ENET0_BASE (0xfffe1800)
@@ -406,6 +411,7 @@ enum bcm63xx_regs_set {
406#define BCM_6348_UART1_BASE (0xdeadbeef) 411#define BCM_6348_UART1_BASE (0xdeadbeef)
407#define BCM_6348_GPIO_BASE (0xfffe0400) 412#define BCM_6348_GPIO_BASE (0xfffe0400)
408#define BCM_6348_SPI_BASE (0xfffe0c00) 413#define BCM_6348_SPI_BASE (0xfffe0c00)
414#define BCM_6348_HSSPI_BASE (0xdeadbeef)
409#define BCM_6348_UDC0_BASE (0xfffe1000) 415#define BCM_6348_UDC0_BASE (0xfffe1000)
410#define BCM_6348_USBDMA_BASE (0xdeadbeef) 416#define BCM_6348_USBDMA_BASE (0xdeadbeef)
411#define BCM_6348_OHCI0_BASE (0xfffe1b00) 417#define BCM_6348_OHCI0_BASE (0xfffe1b00)
@@ -451,6 +457,7 @@ enum bcm63xx_regs_set {
451#define BCM_6358_UART1_BASE (0xfffe0120) 457#define BCM_6358_UART1_BASE (0xfffe0120)
452#define BCM_6358_GPIO_BASE (0xfffe0080) 458#define BCM_6358_GPIO_BASE (0xfffe0080)
453#define BCM_6358_SPI_BASE (0xfffe0800) 459#define BCM_6358_SPI_BASE (0xfffe0800)
460#define BCM_6358_HSSPI_BASE (0xdeadbeef)
454#define BCM_6358_UDC0_BASE (0xfffe0800) 461#define BCM_6358_UDC0_BASE (0xfffe0800)
455#define BCM_6358_USBDMA_BASE (0xdeadbeef) 462#define BCM_6358_USBDMA_BASE (0xdeadbeef)
456#define BCM_6358_OHCI0_BASE (0xfffe1400) 463#define BCM_6358_OHCI0_BASE (0xfffe1400)
@@ -553,6 +560,7 @@ enum bcm63xx_regs_set {
553#define BCM_6368_UART1_BASE (0xb0000120) 560#define BCM_6368_UART1_BASE (0xb0000120)
554#define BCM_6368_GPIO_BASE (0xb0000080) 561#define BCM_6368_GPIO_BASE (0xb0000080)
555#define BCM_6368_SPI_BASE (0xb0000800) 562#define BCM_6368_SPI_BASE (0xb0000800)
563#define BCM_6368_HSSPI_BASE (0xdeadbeef)
556#define BCM_6368_UDC0_BASE (0xdeadbeef) 564#define BCM_6368_UDC0_BASE (0xdeadbeef)
557#define BCM_6368_USBDMA_BASE (0xb0004800) 565#define BCM_6368_USBDMA_BASE (0xb0004800)
558#define BCM_6368_OHCI0_BASE (0xb0001600) 566#define BCM_6368_OHCI0_BASE (0xb0001600)
@@ -604,6 +612,7 @@ extern const unsigned long *bcm63xx_regs_base;
604 __GEN_RSET_BASE(__cpu, UART1) \ 612 __GEN_RSET_BASE(__cpu, UART1) \
605 __GEN_RSET_BASE(__cpu, GPIO) \ 613 __GEN_RSET_BASE(__cpu, GPIO) \
606 __GEN_RSET_BASE(__cpu, SPI) \ 614 __GEN_RSET_BASE(__cpu, SPI) \
615 __GEN_RSET_BASE(__cpu, HSSPI) \
607 __GEN_RSET_BASE(__cpu, UDC0) \ 616 __GEN_RSET_BASE(__cpu, UDC0) \
608 __GEN_RSET_BASE(__cpu, OHCI0) \ 617 __GEN_RSET_BASE(__cpu, OHCI0) \
609 __GEN_RSET_BASE(__cpu, OHCI_PRIV) \ 618 __GEN_RSET_BASE(__cpu, OHCI_PRIV) \
@@ -647,6 +656,7 @@ extern const unsigned long *bcm63xx_regs_base;
647 [RSET_UART1] = BCM_## __cpu ##_UART1_BASE, \ 656 [RSET_UART1] = BCM_## __cpu ##_UART1_BASE, \
648 [RSET_GPIO] = BCM_## __cpu ##_GPIO_BASE, \ 657 [RSET_GPIO] = BCM_## __cpu ##_GPIO_BASE, \
649 [RSET_SPI] = BCM_## __cpu ##_SPI_BASE, \ 658 [RSET_SPI] = BCM_## __cpu ##_SPI_BASE, \
659 [RSET_HSSPI] = BCM_## __cpu ##_HSSPI_BASE, \
650 [RSET_UDC0] = BCM_## __cpu ##_UDC0_BASE, \ 660 [RSET_UDC0] = BCM_## __cpu ##_UDC0_BASE, \
651 [RSET_OHCI0] = BCM_## __cpu ##_OHCI0_BASE, \ 661 [RSET_OHCI0] = BCM_## __cpu ##_OHCI0_BASE, \
652 [RSET_OHCI_PRIV] = BCM_## __cpu ##_OHCI_PRIV_BASE, \ 662 [RSET_OHCI_PRIV] = BCM_## __cpu ##_OHCI_PRIV_BASE, \
@@ -727,6 +737,7 @@ enum bcm63xx_irq {
727 IRQ_ENET0, 737 IRQ_ENET0,
728 IRQ_ENET1, 738 IRQ_ENET1,
729 IRQ_ENET_PHY, 739 IRQ_ENET_PHY,
740 IRQ_HSSPI,
730 IRQ_OHCI0, 741 IRQ_OHCI0,
731 IRQ_EHCI0, 742 IRQ_EHCI0,
732 IRQ_USBD, 743 IRQ_USBD,
@@ -815,6 +826,7 @@ enum bcm63xx_irq {
815#define BCM_6328_ENET0_IRQ 0 826#define BCM_6328_ENET0_IRQ 0
816#define BCM_6328_ENET1_IRQ 0 827#define BCM_6328_ENET1_IRQ 0
817#define BCM_6328_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 12) 828#define BCM_6328_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 12)
829#define BCM_6328_HSSPI_IRQ (IRQ_INTERNAL_BASE + 29)
818#define BCM_6328_OHCI0_IRQ (BCM_6328_HIGH_IRQ_BASE + 9) 830#define BCM_6328_OHCI0_IRQ (BCM_6328_HIGH_IRQ_BASE + 9)
819#define BCM_6328_EHCI0_IRQ (BCM_6328_HIGH_IRQ_BASE + 10) 831#define BCM_6328_EHCI0_IRQ (BCM_6328_HIGH_IRQ_BASE + 10)
820#define BCM_6328_USBD_IRQ (IRQ_INTERNAL_BASE + 4) 832#define BCM_6328_USBD_IRQ (IRQ_INTERNAL_BASE + 4)
@@ -860,6 +872,7 @@ enum bcm63xx_irq {
860#define BCM_6338_ENET0_IRQ (IRQ_INTERNAL_BASE + 8) 872#define BCM_6338_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
861#define BCM_6338_ENET1_IRQ 0 873#define BCM_6338_ENET1_IRQ 0
862#define BCM_6338_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9) 874#define BCM_6338_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9)
875#define BCM_6338_HSSPI_IRQ 0
863#define BCM_6338_OHCI0_IRQ 0 876#define BCM_6338_OHCI0_IRQ 0
864#define BCM_6338_EHCI0_IRQ 0 877#define BCM_6338_EHCI0_IRQ 0
865#define BCM_6338_USBD_IRQ 0 878#define BCM_6338_USBD_IRQ 0
@@ -898,6 +911,7 @@ enum bcm63xx_irq {
898#define BCM_6345_ENET0_IRQ (IRQ_INTERNAL_BASE + 8) 911#define BCM_6345_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
899#define BCM_6345_ENET1_IRQ 0 912#define BCM_6345_ENET1_IRQ 0
900#define BCM_6345_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 12) 913#define BCM_6345_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 12)
914#define BCM_6345_HSSPI_IRQ 0
901#define BCM_6345_OHCI0_IRQ 0 915#define BCM_6345_OHCI0_IRQ 0
902#define BCM_6345_EHCI0_IRQ 0 916#define BCM_6345_EHCI0_IRQ 0
903#define BCM_6345_USBD_IRQ 0 917#define BCM_6345_USBD_IRQ 0
@@ -936,6 +950,7 @@ enum bcm63xx_irq {
936#define BCM_6348_ENET0_IRQ (IRQ_INTERNAL_BASE + 8) 950#define BCM_6348_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
937#define BCM_6348_ENET1_IRQ (IRQ_INTERNAL_BASE + 7) 951#define BCM_6348_ENET1_IRQ (IRQ_INTERNAL_BASE + 7)
938#define BCM_6348_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9) 952#define BCM_6348_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9)
953#define BCM_6348_HSSPI_IRQ 0
939#define BCM_6348_OHCI0_IRQ (IRQ_INTERNAL_BASE + 12) 954#define BCM_6348_OHCI0_IRQ (IRQ_INTERNAL_BASE + 12)
940#define BCM_6348_EHCI0_IRQ 0 955#define BCM_6348_EHCI0_IRQ 0
941#define BCM_6348_USBD_IRQ 0 956#define BCM_6348_USBD_IRQ 0
@@ -974,6 +989,7 @@ enum bcm63xx_irq {
974#define BCM_6358_ENET0_IRQ (IRQ_INTERNAL_BASE + 8) 989#define BCM_6358_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
975#define BCM_6358_ENET1_IRQ (IRQ_INTERNAL_BASE + 6) 990#define BCM_6358_ENET1_IRQ (IRQ_INTERNAL_BASE + 6)
976#define BCM_6358_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9) 991#define BCM_6358_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9)
992#define BCM_6358_HSSPI_IRQ 0
977#define BCM_6358_OHCI0_IRQ (IRQ_INTERNAL_BASE + 5) 993#define BCM_6358_OHCI0_IRQ (IRQ_INTERNAL_BASE + 5)
978#define BCM_6358_EHCI0_IRQ (IRQ_INTERNAL_BASE + 10) 994#define BCM_6358_EHCI0_IRQ (IRQ_INTERNAL_BASE + 10)
979#define BCM_6358_USBD_IRQ 0 995#define BCM_6358_USBD_IRQ 0
@@ -1086,6 +1102,7 @@ enum bcm63xx_irq {
1086#define BCM_6368_ENET0_IRQ 0 1102#define BCM_6368_ENET0_IRQ 0
1087#define BCM_6368_ENET1_IRQ 0 1103#define BCM_6368_ENET1_IRQ 0
1088#define BCM_6368_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 15) 1104#define BCM_6368_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 15)
1105#define BCM_6368_HSSPI_IRQ 0
1089#define BCM_6368_OHCI0_IRQ (IRQ_INTERNAL_BASE + 5) 1106#define BCM_6368_OHCI0_IRQ (IRQ_INTERNAL_BASE + 5)
1090#define BCM_6368_EHCI0_IRQ (IRQ_INTERNAL_BASE + 7) 1107#define BCM_6368_EHCI0_IRQ (IRQ_INTERNAL_BASE + 7)
1091#define BCM_6368_USBD_IRQ (IRQ_INTERNAL_BASE + 8) 1108#define BCM_6368_USBD_IRQ (IRQ_INTERNAL_BASE + 8)
@@ -1133,6 +1150,7 @@ extern const int *bcm63xx_irqs;
1133 [IRQ_ENET0] = BCM_## __cpu ##_ENET0_IRQ, \ 1150 [IRQ_ENET0] = BCM_## __cpu ##_ENET0_IRQ, \
1134 [IRQ_ENET1] = BCM_## __cpu ##_ENET1_IRQ, \ 1151 [IRQ_ENET1] = BCM_## __cpu ##_ENET1_IRQ, \
1135 [IRQ_ENET_PHY] = BCM_## __cpu ##_ENET_PHY_IRQ, \ 1152 [IRQ_ENET_PHY] = BCM_## __cpu ##_ENET_PHY_IRQ, \
1153 [IRQ_HSSPI] = BCM_## __cpu ##_HSSPI_IRQ, \
1136 [IRQ_OHCI0] = BCM_## __cpu ##_OHCI0_IRQ, \ 1154 [IRQ_OHCI0] = BCM_## __cpu ##_OHCI0_IRQ, \
1137 [IRQ_EHCI0] = BCM_## __cpu ##_EHCI0_IRQ, \ 1155 [IRQ_EHCI0] = BCM_## __cpu ##_EHCI0_IRQ, \
1138 [IRQ_USBD] = BCM_## __cpu ##_USBD_IRQ, \ 1156 [IRQ_USBD] = BCM_## __cpu ##_USBD_IRQ, \
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_hsspi.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_hsspi.h
new file mode 100644
index 000000000000..1b1acafb3d79
--- /dev/null
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_hsspi.h
@@ -0,0 +1,8 @@
1#ifndef BCM63XX_DEV_HSSPI_H
2#define BCM63XX_DEV_HSSPI_H
3
4#include <linux/types.h>
5
6int bcm63xx_hsspi_register(void);
7
8#endif /* BCM63XX_DEV_HSSPI_H */
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
index 9875db31d883..ab427f8814e6 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
@@ -463,126 +463,6 @@
463#define WDT_SOFTRESET_REG 0xc 463#define WDT_SOFTRESET_REG 0xc
464 464
465/************************************************************************* 465/*************************************************************************
466 * _REG relative to RSET_UARTx
467 *************************************************************************/
468
469/* UART Control Register */
470#define UART_CTL_REG 0x0
471#define UART_CTL_RXTMOUTCNT_SHIFT 0
472#define UART_CTL_RXTMOUTCNT_MASK (0x1f << UART_CTL_RXTMOUTCNT_SHIFT)
473#define UART_CTL_RSTTXDN_SHIFT 5
474#define UART_CTL_RSTTXDN_MASK (1 << UART_CTL_RSTTXDN_SHIFT)
475#define UART_CTL_RSTRXFIFO_SHIFT 6
476#define UART_CTL_RSTRXFIFO_MASK (1 << UART_CTL_RSTRXFIFO_SHIFT)
477#define UART_CTL_RSTTXFIFO_SHIFT 7
478#define UART_CTL_RSTTXFIFO_MASK (1 << UART_CTL_RSTTXFIFO_SHIFT)
479#define UART_CTL_STOPBITS_SHIFT 8
480#define UART_CTL_STOPBITS_MASK (0xf << UART_CTL_STOPBITS_SHIFT)
481#define UART_CTL_STOPBITS_1 (0x7 << UART_CTL_STOPBITS_SHIFT)
482#define UART_CTL_STOPBITS_2 (0xf << UART_CTL_STOPBITS_SHIFT)
483#define UART_CTL_BITSPERSYM_SHIFT 12
484#define UART_CTL_BITSPERSYM_MASK (0x3 << UART_CTL_BITSPERSYM_SHIFT)
485#define UART_CTL_XMITBRK_SHIFT 14
486#define UART_CTL_XMITBRK_MASK (1 << UART_CTL_XMITBRK_SHIFT)
487#define UART_CTL_RSVD_SHIFT 15
488#define UART_CTL_RSVD_MASK (1 << UART_CTL_RSVD_SHIFT)
489#define UART_CTL_RXPAREVEN_SHIFT 16
490#define UART_CTL_RXPAREVEN_MASK (1 << UART_CTL_RXPAREVEN_SHIFT)
491#define UART_CTL_RXPAREN_SHIFT 17
492#define UART_CTL_RXPAREN_MASK (1 << UART_CTL_RXPAREN_SHIFT)
493#define UART_CTL_TXPAREVEN_SHIFT 18
494#define UART_CTL_TXPAREVEN_MASK (1 << UART_CTL_TXPAREVEN_SHIFT)
495#define UART_CTL_TXPAREN_SHIFT 18
496#define UART_CTL_TXPAREN_MASK (1 << UART_CTL_TXPAREN_SHIFT)
497#define UART_CTL_LOOPBACK_SHIFT 20
498#define UART_CTL_LOOPBACK_MASK (1 << UART_CTL_LOOPBACK_SHIFT)
499#define UART_CTL_RXEN_SHIFT 21
500#define UART_CTL_RXEN_MASK (1 << UART_CTL_RXEN_SHIFT)
501#define UART_CTL_TXEN_SHIFT 22
502#define UART_CTL_TXEN_MASK (1 << UART_CTL_TXEN_SHIFT)
503#define UART_CTL_BRGEN_SHIFT 23
504#define UART_CTL_BRGEN_MASK (1 << UART_CTL_BRGEN_SHIFT)
505
506/* UART Baudword register */
507#define UART_BAUD_REG 0x4
508
509/* UART Misc Control register */
510#define UART_MCTL_REG 0x8
511#define UART_MCTL_DTR_SHIFT 0
512#define UART_MCTL_DTR_MASK (1 << UART_MCTL_DTR_SHIFT)
513#define UART_MCTL_RTS_SHIFT 1
514#define UART_MCTL_RTS_MASK (1 << UART_MCTL_RTS_SHIFT)
515#define UART_MCTL_RXFIFOTHRESH_SHIFT 8
516#define UART_MCTL_RXFIFOTHRESH_MASK (0xf << UART_MCTL_RXFIFOTHRESH_SHIFT)
517#define UART_MCTL_TXFIFOTHRESH_SHIFT 12
518#define UART_MCTL_TXFIFOTHRESH_MASK (0xf << UART_MCTL_TXFIFOTHRESH_SHIFT)
519#define UART_MCTL_RXFIFOFILL_SHIFT 16
520#define UART_MCTL_RXFIFOFILL_MASK (0x1f << UART_MCTL_RXFIFOFILL_SHIFT)
521#define UART_MCTL_TXFIFOFILL_SHIFT 24
522#define UART_MCTL_TXFIFOFILL_MASK (0x1f << UART_MCTL_TXFIFOFILL_SHIFT)
523
524/* UART External Input Configuration register */
525#define UART_EXTINP_REG 0xc
526#define UART_EXTINP_RI_SHIFT 0
527#define UART_EXTINP_RI_MASK (1 << UART_EXTINP_RI_SHIFT)
528#define UART_EXTINP_CTS_SHIFT 1
529#define UART_EXTINP_CTS_MASK (1 << UART_EXTINP_CTS_SHIFT)
530#define UART_EXTINP_DCD_SHIFT 2
531#define UART_EXTINP_DCD_MASK (1 << UART_EXTINP_DCD_SHIFT)
532#define UART_EXTINP_DSR_SHIFT 3
533#define UART_EXTINP_DSR_MASK (1 << UART_EXTINP_DSR_SHIFT)
534#define UART_EXTINP_IRSTAT(x) (1 << (x + 4))
535#define UART_EXTINP_IRMASK(x) (1 << (x + 8))
536#define UART_EXTINP_IR_RI 0
537#define UART_EXTINP_IR_CTS 1
538#define UART_EXTINP_IR_DCD 2
539#define UART_EXTINP_IR_DSR 3
540#define UART_EXTINP_RI_NOSENSE_SHIFT 16
541#define UART_EXTINP_RI_NOSENSE_MASK (1 << UART_EXTINP_RI_NOSENSE_SHIFT)
542#define UART_EXTINP_CTS_NOSENSE_SHIFT 17
543#define UART_EXTINP_CTS_NOSENSE_MASK (1 << UART_EXTINP_CTS_NOSENSE_SHIFT)
544#define UART_EXTINP_DCD_NOSENSE_SHIFT 18
545#define UART_EXTINP_DCD_NOSENSE_MASK (1 << UART_EXTINP_DCD_NOSENSE_SHIFT)
546#define UART_EXTINP_DSR_NOSENSE_SHIFT 19
547#define UART_EXTINP_DSR_NOSENSE_MASK (1 << UART_EXTINP_DSR_NOSENSE_SHIFT)
548
549/* UART Interrupt register */
550#define UART_IR_REG 0x10
551#define UART_IR_MASK(x) (1 << (x + 16))
552#define UART_IR_STAT(x) (1 << (x))
553#define UART_IR_EXTIP 0
554#define UART_IR_TXUNDER 1
555#define UART_IR_TXOVER 2
556#define UART_IR_TXTRESH 3
557#define UART_IR_TXRDLATCH 4
558#define UART_IR_TXEMPTY 5
559#define UART_IR_RXUNDER 6
560#define UART_IR_RXOVER 7
561#define UART_IR_RXTIMEOUT 8
562#define UART_IR_RXFULL 9
563#define UART_IR_RXTHRESH 10
564#define UART_IR_RXNOTEMPTY 11
565#define UART_IR_RXFRAMEERR 12
566#define UART_IR_RXPARERR 13
567#define UART_IR_RXBRK 14
568#define UART_IR_TXDONE 15
569
570/* UART Fifo register */
571#define UART_FIFO_REG 0x14
572#define UART_FIFO_VALID_SHIFT 0
573#define UART_FIFO_VALID_MASK 0xff
574#define UART_FIFO_FRAMEERR_SHIFT 8
575#define UART_FIFO_FRAMEERR_MASK (1 << UART_FIFO_FRAMEERR_SHIFT)
576#define UART_FIFO_PARERR_SHIFT 9
577#define UART_FIFO_PARERR_MASK (1 << UART_FIFO_PARERR_SHIFT)
578#define UART_FIFO_BRKDET_SHIFT 10
579#define UART_FIFO_BRKDET_MASK (1 << UART_FIFO_BRKDET_SHIFT)
580#define UART_FIFO_ANYERR_MASK (UART_FIFO_FRAMEERR_MASK | \
581 UART_FIFO_PARERR_MASK | \
582 UART_FIFO_BRKDET_MASK)
583
584
585/*************************************************************************
586 * _REG relative to RSET_GPIO 466 * _REG relative to RSET_GPIO
587 *************************************************************************/ 467 *************************************************************************/
588 468
diff --git a/arch/mips/include/asm/mach-generic/dma-coherence.h b/arch/mips/include/asm/mach-generic/dma-coherence.h
index a9e8f6b62b0b..7629c35986f7 100644
--- a/arch/mips/include/asm/mach-generic/dma-coherence.h
+++ b/arch/mips/include/asm/mach-generic/dma-coherence.h
@@ -49,11 +49,7 @@ static inline int plat_dma_supported(struct device *dev, u64 mask)
49 49
50static inline int plat_device_is_coherent(struct device *dev) 50static inline int plat_device_is_coherent(struct device *dev)
51{ 51{
52#ifdef CONFIG_DMA_COHERENT
53 return 1;
54#else
55 return coherentio; 52 return coherentio;
56#endif
57} 53}
58 54
59#ifdef CONFIG_SWIOTLB 55#ifdef CONFIG_SWIOTLB
diff --git a/arch/mips/include/asm/mach-generic/floppy.h b/arch/mips/include/asm/mach-generic/floppy.h
index 5b5cd689a2f7..e2561d99a3fe 100644
--- a/arch/mips/include/asm/mach-generic/floppy.h
+++ b/arch/mips/include/asm/mach-generic/floppy.h
@@ -9,7 +9,6 @@
9#define __ASM_MACH_GENERIC_FLOPPY_H 9#define __ASM_MACH_GENERIC_FLOPPY_H
10 10
11#include <linux/delay.h> 11#include <linux/delay.h>
12#include <linux/init.h>
13#include <linux/ioport.h> 12#include <linux/ioport.h>
14#include <linux/sched.h> 13#include <linux/sched.h>
15#include <linux/linkage.h> 14#include <linux/linkage.h>
diff --git a/arch/mips/include/asm/mach-generic/ide.h b/arch/mips/include/asm/mach-generic/ide.h
index affa66f5c2da..4ae5fbcb15a5 100644
--- a/arch/mips/include/asm/mach-generic/ide.h
+++ b/arch/mips/include/asm/mach-generic/ide.h
@@ -23,7 +23,7 @@
23static inline void __ide_flush_prologue(void) 23static inline void __ide_flush_prologue(void)
24{ 24{
25#ifdef CONFIG_SMP 25#ifdef CONFIG_SMP
26 if (cpu_has_dc_aliases) 26 if (cpu_has_dc_aliases || !cpu_has_ic_fills_f_dc)
27 preempt_disable(); 27 preempt_disable();
28#endif 28#endif
29} 29}
@@ -31,14 +31,14 @@ static inline void __ide_flush_prologue(void)
31static inline void __ide_flush_epilogue(void) 31static inline void __ide_flush_epilogue(void)
32{ 32{
33#ifdef CONFIG_SMP 33#ifdef CONFIG_SMP
34 if (cpu_has_dc_aliases) 34 if (cpu_has_dc_aliases || !cpu_has_ic_fills_f_dc)
35 preempt_enable(); 35 preempt_enable();
36#endif 36#endif
37} 37}
38 38
39static inline void __ide_flush_dcache_range(unsigned long addr, unsigned long size) 39static inline void __ide_flush_dcache_range(unsigned long addr, unsigned long size)
40{ 40{
41 if (cpu_has_dc_aliases) { 41 if (cpu_has_dc_aliases || !cpu_has_ic_fills_f_dc) {
42 unsigned long end = addr + size; 42 unsigned long end = addr + size;
43 43
44 while (addr < end) { 44 while (addr < end) {
diff --git a/arch/mips/include/asm/mach-jazz/floppy.h b/arch/mips/include/asm/mach-jazz/floppy.h
index 62aa1e287fba..4b86c88a03b7 100644
--- a/arch/mips/include/asm/mach-jazz/floppy.h
+++ b/arch/mips/include/asm/mach-jazz/floppy.h
@@ -9,7 +9,6 @@
9#define __ASM_MACH_JAZZ_FLOPPY_H 9#define __ASM_MACH_JAZZ_FLOPPY_H
10 10
11#include <linux/delay.h> 11#include <linux/delay.h>
12#include <linux/init.h>
13#include <linux/linkage.h> 12#include <linux/linkage.h>
14#include <linux/types.h> 13#include <linux/types.h>
15#include <linux/mm.h> 14#include <linux/mm.h>
diff --git a/arch/mips/include/asm/mach-jz4740/platform.h b/arch/mips/include/asm/mach-jz4740/platform.h
index 05988c2d6565..069b43a9da6f 100644
--- a/arch/mips/include/asm/mach-jz4740/platform.h
+++ b/arch/mips/include/asm/mach-jz4740/platform.h
@@ -21,6 +21,7 @@
21 21
22extern struct platform_device jz4740_usb_ohci_device; 22extern struct platform_device jz4740_usb_ohci_device;
23extern struct platform_device jz4740_udc_device; 23extern struct platform_device jz4740_udc_device;
24extern struct platform_device jz4740_udc_xceiv_device;
24extern struct platform_device jz4740_mmc_device; 25extern struct platform_device jz4740_mmc_device;
25extern struct platform_device jz4740_rtc_device; 26extern struct platform_device jz4740_rtc_device;
26extern struct platform_device jz4740_i2c_device; 27extern struct platform_device jz4740_i2c_device;
diff --git a/arch/mips/include/asm/mach-netlogic/irq.h b/arch/mips/include/asm/mach-netlogic/irq.h
index 868ed8a2ed5c..c0dbd530cca6 100644
--- a/arch/mips/include/asm/mach-netlogic/irq.h
+++ b/arch/mips/include/asm/mach-netlogic/irq.h
@@ -9,7 +9,8 @@
9#define __ASM_NETLOGIC_IRQ_H 9#define __ASM_NETLOGIC_IRQ_H
10 10
11#include <asm/mach-netlogic/multi-node.h> 11#include <asm/mach-netlogic/multi-node.h>
12#define NR_IRQS (64 * NLM_NR_NODES) 12#define NLM_IRQS_PER_NODE 1024
13#define NR_IRQS (NLM_IRQS_PER_NODE * NLM_NR_NODES)
13 14
14#define MIPS_CPU_IRQ_BASE 0 15#define MIPS_CPU_IRQ_BASE 0
15 16
diff --git a/arch/mips/include/asm/mach-netlogic/multi-node.h b/arch/mips/include/asm/mach-netlogic/multi-node.h
index d62fc773f4d7..9ed8dacdc37c 100644
--- a/arch/mips/include/asm/mach-netlogic/multi-node.h
+++ b/arch/mips/include/asm/mach-netlogic/multi-node.h
@@ -47,8 +47,37 @@
47#endif 47#endif
48#endif 48#endif
49 49
50#define NLM_CORES_PER_NODE 8
51#define NLM_THREADS_PER_CORE 4 50#define NLM_THREADS_PER_CORE 4
52#define NLM_CPUS_PER_NODE (NLM_CORES_PER_NODE * NLM_THREADS_PER_CORE) 51#ifdef CONFIG_CPU_XLR
52#define nlm_cores_per_node() 8
53#else
54extern unsigned int xlp_cores_per_node;
55#define nlm_cores_per_node() xlp_cores_per_node
56#endif
57
58#define nlm_threads_per_node() (nlm_cores_per_node() * NLM_THREADS_PER_CORE)
59#define nlm_cpuid_to_node(c) ((c) / nlm_threads_per_node())
60
61struct nlm_soc_info {
62 unsigned long coremask; /* cores enabled on the soc */
63 unsigned long ebase; /* not used now */
64 uint64_t irqmask; /* EIMR for the node */
65 uint64_t sysbase; /* only for XLP - sys block base */
66 uint64_t picbase; /* PIC block base */
67 spinlock_t piclock; /* lock for PIC access */
68 cpumask_t cpumask; /* logical cpu mask for node */
69 unsigned int socbus;
70};
71
72extern struct nlm_soc_info nlm_nodes[NLM_NR_NODES];
73#define nlm_get_node(i) (&nlm_nodes[i])
74#define nlm_node_present(n) ((n) >= 0 && (n) < NLM_NR_NODES && \
75 nlm_get_node(n)->coremask != 0)
76#ifdef CONFIG_CPU_XLR
77#define nlm_current_node() (&nlm_nodes[0])
78#else
79#define nlm_current_node() (&nlm_nodes[nlm_nodeid()])
80#endif
81void nlm_node_init(int node);
53 82
54#endif 83#endif
diff --git a/arch/mips/include/asm/mach-netlogic/topology.h b/arch/mips/include/asm/mach-netlogic/topology.h
new file mode 100644
index 000000000000..0da99fa11c38
--- /dev/null
+++ b/arch/mips/include/asm/mach-netlogic/topology.h
@@ -0,0 +1,20 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2013 Broadcom Corporation
7 */
8#ifndef _ASM_MACH_NETLOGIC_TOPOLOGY_H
9#define _ASM_MACH_NETLOGIC_TOPOLOGY_H
10
11#include <asm/mach-netlogic/multi-node.h>
12
13#define topology_physical_package_id(cpu) cpu_to_node(cpu)
14#define topology_core_id(cpu) (cpu_logical_map(cpu) / NLM_THREADS_PER_CORE)
15#define topology_thread_cpumask(cpu) (&cpu_sibling_map[cpu])
16#define topology_core_cpumask(cpu) cpumask_of_node(cpu_to_node(cpu))
17
18#include <asm-generic/topology.h>
19
20#endif /* _ASM_MACH_NETLOGIC_TOPOLOGY_H */
diff --git a/arch/mips/include/asm/mips-boards/piix4.h b/arch/mips/include/asm/mips-boards/piix4.h
index e33227998713..836e2ede24de 100644
--- a/arch/mips/include/asm/mips-boards/piix4.h
+++ b/arch/mips/include/asm/mips-boards/piix4.h
@@ -26,6 +26,10 @@
26#define PIIX4_FUNC0_PIRQRC_IRQ_ROUTING_DISABLE (1 << 7) 26#define PIIX4_FUNC0_PIRQRC_IRQ_ROUTING_DISABLE (1 << 7)
27#define PIIX4_FUNC0_PIRQRC_IRQ_ROUTING_MASK 0xf 27#define PIIX4_FUNC0_PIRQRC_IRQ_ROUTING_MASK 0xf
28#define PIIX4_FUNC0_PIRQRC_IRQ_ROUTING_MAX 16 28#define PIIX4_FUNC0_PIRQRC_IRQ_ROUTING_MAX 16
29/* SERIRQ Control */
30#define PIIX4_FUNC0_SERIRQC 0x64
31#define PIIX4_FUNC0_SERIRQC_EN (1 << 7)
32#define PIIX4_FUNC0_SERIRQC_CONT (1 << 6)
29/* Top Of Memory */ 33/* Top Of Memory */
30#define PIIX4_FUNC0_TOM 0x69 34#define PIIX4_FUNC0_TOM 0x69
31#define PIIX4_FUNC0_TOM_TOP_OF_MEMORY_MASK 0xf0 35#define PIIX4_FUNC0_TOM_TOP_OF_MEMORY_MASK 0xf0
@@ -34,6 +38,9 @@
34#define PIIX4_FUNC0_DLC_USBPR_EN (1 << 2) 38#define PIIX4_FUNC0_DLC_USBPR_EN (1 << 2)
35#define PIIX4_FUNC0_DLC_PASSIVE_RELEASE_EN (1 << 1) 39#define PIIX4_FUNC0_DLC_PASSIVE_RELEASE_EN (1 << 1)
36#define PIIX4_FUNC0_DLC_DELAYED_TRANSACTION_EN (1 << 0) 40#define PIIX4_FUNC0_DLC_DELAYED_TRANSACTION_EN (1 << 0)
41/* General Configuration */
42#define PIIX4_FUNC0_GENCFG 0xb0
43#define PIIX4_FUNC0_GENCFG_SERIRQ (1 << 16)
37 44
38/* IDE Timing */ 45/* IDE Timing */
39#define PIIX4_FUNC1_IDETIM_PRIMARY_LO 0x40 46#define PIIX4_FUNC1_IDETIM_PRIMARY_LO 0x40
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index e0331414c7d6..bbc3dd4294bc 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -14,6 +14,7 @@
14#define _ASM_MIPSREGS_H 14#define _ASM_MIPSREGS_H
15 15
16#include <linux/linkage.h> 16#include <linux/linkage.h>
17#include <linux/types.h>
17#include <asm/hazards.h> 18#include <asm/hazards.h>
18#include <asm/war.h> 19#include <asm/war.h>
19 20
@@ -573,7 +574,9 @@
573#define MIPS_CONF1_IA (_ULCAST_(7) << 16) 574#define MIPS_CONF1_IA (_ULCAST_(7) << 16)
574#define MIPS_CONF1_IL (_ULCAST_(7) << 19) 575#define MIPS_CONF1_IL (_ULCAST_(7) << 19)
575#define MIPS_CONF1_IS (_ULCAST_(7) << 22) 576#define MIPS_CONF1_IS (_ULCAST_(7) << 22)
576#define MIPS_CONF1_TLBS (_ULCAST_(63)<< 25) 577#define MIPS_CONF1_TLBS_SHIFT (25)
578#define MIPS_CONF1_TLBS_SIZE (6)
579#define MIPS_CONF1_TLBS (_ULCAST_(63) << MIPS_CONF1_TLBS_SHIFT)
577 580
578#define MIPS_CONF2_SA (_ULCAST_(15)<< 0) 581#define MIPS_CONF2_SA (_ULCAST_(15)<< 0)
579#define MIPS_CONF2_SL (_ULCAST_(15)<< 4) 582#define MIPS_CONF2_SL (_ULCAST_(15)<< 4)
@@ -587,21 +590,53 @@
587#define MIPS_CONF3_TL (_ULCAST_(1) << 0) 590#define MIPS_CONF3_TL (_ULCAST_(1) << 0)
588#define MIPS_CONF3_SM (_ULCAST_(1) << 1) 591#define MIPS_CONF3_SM (_ULCAST_(1) << 1)
589#define MIPS_CONF3_MT (_ULCAST_(1) << 2) 592#define MIPS_CONF3_MT (_ULCAST_(1) << 2)
593#define MIPS_CONF3_CDMM (_ULCAST_(1) << 3)
590#define MIPS_CONF3_SP (_ULCAST_(1) << 4) 594#define MIPS_CONF3_SP (_ULCAST_(1) << 4)
591#define MIPS_CONF3_VINT (_ULCAST_(1) << 5) 595#define MIPS_CONF3_VINT (_ULCAST_(1) << 5)
592#define MIPS_CONF3_VEIC (_ULCAST_(1) << 6) 596#define MIPS_CONF3_VEIC (_ULCAST_(1) << 6)
593#define MIPS_CONF3_LPA (_ULCAST_(1) << 7) 597#define MIPS_CONF3_LPA (_ULCAST_(1) << 7)
598#define MIPS_CONF3_ITL (_ULCAST_(1) << 8)
599#define MIPS_CONF3_CTXTC (_ULCAST_(1) << 9)
594#define MIPS_CONF3_DSP (_ULCAST_(1) << 10) 600#define MIPS_CONF3_DSP (_ULCAST_(1) << 10)
595#define MIPS_CONF3_DSP2P (_ULCAST_(1) << 11) 601#define MIPS_CONF3_DSP2P (_ULCAST_(1) << 11)
596#define MIPS_CONF3_RXI (_ULCAST_(1) << 12) 602#define MIPS_CONF3_RXI (_ULCAST_(1) << 12)
597#define MIPS_CONF3_ULRI (_ULCAST_(1) << 13) 603#define MIPS_CONF3_ULRI (_ULCAST_(1) << 13)
598#define MIPS_CONF3_ISA (_ULCAST_(3) << 14) 604#define MIPS_CONF3_ISA (_ULCAST_(3) << 14)
599#define MIPS_CONF3_ISA_OE (_ULCAST_(1) << 16) 605#define MIPS_CONF3_ISA_OE (_ULCAST_(1) << 16)
606#define MIPS_CONF3_MCU (_ULCAST_(1) << 17)
607#define MIPS_CONF3_MMAR (_ULCAST_(7) << 18)
608#define MIPS_CONF3_IPLW (_ULCAST_(3) << 21)
600#define MIPS_CONF3_VZ (_ULCAST_(1) << 23) 609#define MIPS_CONF3_VZ (_ULCAST_(1) << 23)
601 610#define MIPS_CONF3_PW (_ULCAST_(1) << 24)
611#define MIPS_CONF3_SC (_ULCAST_(1) << 25)
612#define MIPS_CONF3_BI (_ULCAST_(1) << 26)
613#define MIPS_CONF3_BP (_ULCAST_(1) << 27)
614#define MIPS_CONF3_MSA (_ULCAST_(1) << 28)
615#define MIPS_CONF3_CMGCR (_ULCAST_(1) << 29)
616#define MIPS_CONF3_BPG (_ULCAST_(1) << 30)
617
618#define MIPS_CONF4_MMUSIZEEXT_SHIFT (0)
602#define MIPS_CONF4_MMUSIZEEXT (_ULCAST_(255) << 0) 619#define MIPS_CONF4_MMUSIZEEXT (_ULCAST_(255) << 0)
620#define MIPS_CONF4_FTLBSETS_SHIFT (0)
621#define MIPS_CONF4_FTLBSETS_SHIFT (0)
622#define MIPS_CONF4_FTLBSETS (_ULCAST_(15) << MIPS_CONF4_FTLBSETS_SHIFT)
623#define MIPS_CONF4_FTLBWAYS_SHIFT (4)
624#define MIPS_CONF4_FTLBWAYS (_ULCAST_(15) << MIPS_CONF4_FTLBWAYS_SHIFT)
625#define MIPS_CONF4_FTLBPAGESIZE_SHIFT (8)
626/* bits 10:8 in FTLB-only configurations */
627#define MIPS_CONF4_FTLBPAGESIZE (_ULCAST_(7) << MIPS_CONF4_FTLBPAGESIZE_SHIFT)
628/* bits 12:8 in VTLB-FTLB only configurations */
629#define MIPS_CONF4_VFTLBPAGESIZE (_ULCAST_(31) << MIPS_CONF4_FTLBPAGESIZE_SHIFT)
603#define MIPS_CONF4_MMUEXTDEF (_ULCAST_(3) << 14) 630#define MIPS_CONF4_MMUEXTDEF (_ULCAST_(3) << 14)
604#define MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT (_ULCAST_(1) << 14) 631#define MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT (_ULCAST_(1) << 14)
632#define MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT (_ULCAST_(2) << 14)
633#define MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT (_ULCAST_(3) << 14)
634#define MIPS_CONF4_KSCREXIST (_ULCAST_(255) << 16)
635#define MIPS_CONF4_VTLBSIZEEXT_SHIFT (24)
636#define MIPS_CONF4_VTLBSIZEEXT (_ULCAST_(15) << MIPS_CONF4_VTLBSIZEEXT_SHIFT)
637#define MIPS_CONF4_AE (_ULCAST_(1) << 28)
638#define MIPS_CONF4_IE (_ULCAST_(3) << 29)
639#define MIPS_CONF4_TLBINV (_ULCAST_(2) << 29)
605 640
606#define MIPS_CONF5_NF (_ULCAST_(1) << 0) 641#define MIPS_CONF5_NF (_ULCAST_(1) << 0)
607#define MIPS_CONF5_UFR (_ULCAST_(1) << 2) 642#define MIPS_CONF5_UFR (_ULCAST_(1) << 2)
@@ -611,11 +646,15 @@
611#define MIPS_CONF5_K (_ULCAST_(1) << 30) 646#define MIPS_CONF5_K (_ULCAST_(1) << 30)
612 647
613#define MIPS_CONF6_SYND (_ULCAST_(1) << 13) 648#define MIPS_CONF6_SYND (_ULCAST_(1) << 13)
649/* proAptiv FTLB on/off bit */
650#define MIPS_CONF6_FTLBEN (_ULCAST_(1) << 15)
614 651
615#define MIPS_CONF7_WII (_ULCAST_(1) << 31) 652#define MIPS_CONF7_WII (_ULCAST_(1) << 31)
616 653
617#define MIPS_CONF7_RPS (_ULCAST_(1) << 2) 654#define MIPS_CONF7_RPS (_ULCAST_(1) << 2)
618 655
656/* EntryHI bit definition */
657#define MIPS_ENTRYHI_EHINV (_ULCAST_(1) << 10)
619 658
620/* 659/*
621 * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register. 660 * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register.
@@ -628,6 +667,26 @@
628#define MIPS_FPIR_L (_ULCAST_(1) << 21) 667#define MIPS_FPIR_L (_ULCAST_(1) << 21)
629#define MIPS_FPIR_F64 (_ULCAST_(1) << 22) 668#define MIPS_FPIR_F64 (_ULCAST_(1) << 22)
630 669
670/*
671 * Bits in the MIPS32 Memory Segmentation registers.
672 */
673#define MIPS_SEGCFG_PA_SHIFT 9
674#define MIPS_SEGCFG_PA (_ULCAST_(127) << MIPS_SEGCFG_PA_SHIFT)
675#define MIPS_SEGCFG_AM_SHIFT 4
676#define MIPS_SEGCFG_AM (_ULCAST_(7) << MIPS_SEGCFG_AM_SHIFT)
677#define MIPS_SEGCFG_EU_SHIFT 3
678#define MIPS_SEGCFG_EU (_ULCAST_(1) << MIPS_SEGCFG_EU_SHIFT)
679#define MIPS_SEGCFG_C_SHIFT 0
680#define MIPS_SEGCFG_C (_ULCAST_(7) << MIPS_SEGCFG_C_SHIFT)
681
682#define MIPS_SEGCFG_UUSK _ULCAST_(7)
683#define MIPS_SEGCFG_USK _ULCAST_(5)
684#define MIPS_SEGCFG_MUSUK _ULCAST_(4)
685#define MIPS_SEGCFG_MUSK _ULCAST_(3)
686#define MIPS_SEGCFG_MSK _ULCAST_(2)
687#define MIPS_SEGCFG_MK _ULCAST_(1)
688#define MIPS_SEGCFG_UK _ULCAST_(0)
689
631#ifndef __ASSEMBLY__ 690#ifndef __ASSEMBLY__
632 691
633/* 692/*
@@ -649,6 +708,19 @@ static inline int mm_insn_16bit(u16 insn)
649} 708}
650 709
651/* 710/*
711 * TLB Invalidate Flush
712 */
713static inline void tlbinvf(void)
714{
715 __asm__ __volatile__(
716 ".set push\n\t"
717 ".set noreorder\n\t"
718 ".word 0x42000004\n\t" /* tlbinvf */
719 ".set pop");
720}
721
722
723/*
652 * Functions to access the R10000 performance counters. These are basically 724 * Functions to access the R10000 performance counters. These are basically
653 * mfc0 and mtc0 instructions from and to coprocessor register with a 5-bit 725 * mfc0 and mtc0 instructions from and to coprocessor register with a 5-bit
654 * performance counter number encoded into bits 1 ... 5 of the instruction. 726 * performance counter number encoded into bits 1 ... 5 of the instruction.
@@ -1102,6 +1174,15 @@ do { \
1102#define read_c0_ebase() __read_32bit_c0_register($15, 1) 1174#define read_c0_ebase() __read_32bit_c0_register($15, 1)
1103#define write_c0_ebase(val) __write_32bit_c0_register($15, 1, val) 1175#define write_c0_ebase(val) __write_32bit_c0_register($15, 1, val)
1104 1176
1177/* MIPSR3 */
1178#define read_c0_segctl0() __read_32bit_c0_register($5, 2)
1179#define write_c0_segctl0(val) __write_32bit_c0_register($5, 2, val)
1180
1181#define read_c0_segctl1() __read_32bit_c0_register($5, 3)
1182#define write_c0_segctl1(val) __write_32bit_c0_register($5, 3, val)
1183
1184#define read_c0_segctl2() __read_32bit_c0_register($5, 4)
1185#define write_c0_segctl2(val) __write_32bit_c0_register($5, 4, val)
1105 1186
1106/* Cavium OCTEON (cnMIPS) */ 1187/* Cavium OCTEON (cnMIPS) */
1107#define read_c0_cvmcount() __read_ulong_c0_register($9, 6) 1188#define read_c0_cvmcount() __read_ulong_c0_register($9, 6)
diff --git a/arch/mips/include/asm/netlogic/common.h b/arch/mips/include/asm/netlogic/common.h
index bb68c3398c80..c281f03eb312 100644
--- a/arch/mips/include/asm/netlogic/common.h
+++ b/arch/mips/include/asm/netlogic/common.h
@@ -84,7 +84,6 @@ nlm_set_nmi_handler(void *handler)
84 */ 84 */
85void nlm_init_boot_cpu(void); 85void nlm_init_boot_cpu(void);
86unsigned int nlm_get_cpu_frequency(void); 86unsigned int nlm_get_cpu_frequency(void);
87void nlm_node_init(int node);
88extern struct plat_smp_ops nlm_smp_ops; 87extern struct plat_smp_ops nlm_smp_ops;
89extern char nlm_reset_entry[], nlm_reset_entry_end[]; 88extern char nlm_reset_entry[], nlm_reset_entry_end[];
90 89
@@ -94,26 +93,16 @@ extern struct dma_map_ops nlm_swiotlb_dma_ops;
94extern unsigned int nlm_threads_per_core; 93extern unsigned int nlm_threads_per_core;
95extern cpumask_t nlm_cpumask; 94extern cpumask_t nlm_cpumask;
96 95
97struct nlm_soc_info {
98 unsigned long coremask; /* cores enabled on the soc */
99 unsigned long ebase;
100 uint64_t irqmask;
101 uint64_t sysbase; /* only for XLP */
102 uint64_t picbase;
103 spinlock_t piclock;
104};
105
106#define nlm_get_node(i) (&nlm_nodes[i])
107#ifdef CONFIG_CPU_XLR
108#define nlm_current_node() (&nlm_nodes[0])
109#else
110#define nlm_current_node() (&nlm_nodes[nlm_nodeid()])
111#endif
112
113struct irq_data; 96struct irq_data;
114uint64_t nlm_pci_irqmask(int node); 97uint64_t nlm_pci_irqmask(int node);
98void nlm_setup_pic_irq(int node, int picirq, int irq, int irt);
115void nlm_set_pic_extra_ack(int node, int irq, void (*xack)(struct irq_data *)); 99void nlm_set_pic_extra_ack(int node, int irq, void (*xack)(struct irq_data *));
116 100
101#ifdef CONFIG_PCI_MSI
102void nlm_dispatch_msi(int node, int lirq);
103void nlm_dispatch_msix(int node, int msixirq);
104#endif
105
117/* 106/*
118 * The NR_IRQs is divided between nodes, each of them has a separate irq space 107 * The NR_IRQs is divided between nodes, each of them has a separate irq space
119 */ 108 */
@@ -122,7 +111,6 @@ static inline int nlm_irq_to_xirq(int node, int irq)
122 return node * NR_IRQS / NLM_NR_NODES + irq; 111 return node * NR_IRQS / NLM_NR_NODES + irq;
123} 112}
124 113
125extern struct nlm_soc_info nlm_nodes[NLM_NR_NODES];
126extern int nlm_cpu_ready[]; 114extern int nlm_cpu_ready[];
127#endif 115#endif
128#endif /* _NETLOGIC_COMMON_H_ */ 116#endif /* _NETLOGIC_COMMON_H_ */
diff --git a/arch/mips/include/asm/netlogic/mips-extns.h b/arch/mips/include/asm/netlogic/mips-extns.h
index f299d31d7c1a..de9aada6f4c1 100644
--- a/arch/mips/include/asm/netlogic/mips-extns.h
+++ b/arch/mips/include/asm/netlogic/mips-extns.h
@@ -146,7 +146,12 @@ static inline int hard_smp_processor_id(void)
146 146
147static inline int nlm_nodeid(void) 147static inline int nlm_nodeid(void)
148{ 148{
149 return (__read_32bit_c0_register($15, 1) >> 5) & 0x3; 149 uint32_t prid = read_c0_prid();
150
151 if ((prid & 0xff00) == PRID_IMP_NETLOGIC_XLP9XX)
152 return (__read_32bit_c0_register($15, 1) >> 7) & 0x7;
153 else
154 return (__read_32bit_c0_register($15, 1) >> 5) & 0x3;
150} 155}
151 156
152static inline unsigned int nlm_core_id(void) 157static inline unsigned int nlm_core_id(void)
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/bridge.h b/arch/mips/include/asm/netlogic/xlp-hal/bridge.h
index 4e8eacb9588a..3067f983495d 100644
--- a/arch/mips/include/asm/netlogic/xlp-hal/bridge.h
+++ b/arch/mips/include/asm/netlogic/xlp-hal/bridge.h
@@ -69,44 +69,9 @@
69#define BRIDGE_FLASH_LIMIT3 0x13 69#define BRIDGE_FLASH_LIMIT3 0x13
70 70
71#define BRIDGE_DRAM_BAR(i) (0x14 + (i)) 71#define BRIDGE_DRAM_BAR(i) (0x14 + (i))
72#define BRIDGE_DRAM_BAR0 0x14
73#define BRIDGE_DRAM_BAR1 0x15
74#define BRIDGE_DRAM_BAR2 0x16
75#define BRIDGE_DRAM_BAR3 0x17
76#define BRIDGE_DRAM_BAR4 0x18
77#define BRIDGE_DRAM_BAR5 0x19
78#define BRIDGE_DRAM_BAR6 0x1a
79#define BRIDGE_DRAM_BAR7 0x1b
80
81#define BRIDGE_DRAM_LIMIT(i) (0x1c + (i)) 72#define BRIDGE_DRAM_LIMIT(i) (0x1c + (i))
82#define BRIDGE_DRAM_LIMIT0 0x1c
83#define BRIDGE_DRAM_LIMIT1 0x1d
84#define BRIDGE_DRAM_LIMIT2 0x1e
85#define BRIDGE_DRAM_LIMIT3 0x1f
86#define BRIDGE_DRAM_LIMIT4 0x20
87#define BRIDGE_DRAM_LIMIT5 0x21
88#define BRIDGE_DRAM_LIMIT6 0x22
89#define BRIDGE_DRAM_LIMIT7 0x23
90
91#define BRIDGE_DRAM_NODE_TRANSLN(i) (0x24 + (i)) 73#define BRIDGE_DRAM_NODE_TRANSLN(i) (0x24 + (i))
92#define BRIDGE_DRAM_NODE_TRANSLN0 0x24
93#define BRIDGE_DRAM_NODE_TRANSLN1 0x25
94#define BRIDGE_DRAM_NODE_TRANSLN2 0x26
95#define BRIDGE_DRAM_NODE_TRANSLN3 0x27
96#define BRIDGE_DRAM_NODE_TRANSLN4 0x28
97#define BRIDGE_DRAM_NODE_TRANSLN5 0x29
98#define BRIDGE_DRAM_NODE_TRANSLN6 0x2a
99#define BRIDGE_DRAM_NODE_TRANSLN7 0x2b
100
101#define BRIDGE_DRAM_CHNL_TRANSLN(i) (0x2c + (i)) 74#define BRIDGE_DRAM_CHNL_TRANSLN(i) (0x2c + (i))
102#define BRIDGE_DRAM_CHNL_TRANSLN0 0x2c
103#define BRIDGE_DRAM_CHNL_TRANSLN1 0x2d
104#define BRIDGE_DRAM_CHNL_TRANSLN2 0x2e
105#define BRIDGE_DRAM_CHNL_TRANSLN3 0x2f
106#define BRIDGE_DRAM_CHNL_TRANSLN4 0x30
107#define BRIDGE_DRAM_CHNL_TRANSLN5 0x31
108#define BRIDGE_DRAM_CHNL_TRANSLN6 0x32
109#define BRIDGE_DRAM_CHNL_TRANSLN7 0x33
110 75
111#define BRIDGE_PCIEMEM_BASE0 0x34 76#define BRIDGE_PCIEMEM_BASE0 0x34
112#define BRIDGE_PCIEMEM_BASE1 0x35 77#define BRIDGE_PCIEMEM_BASE1 0x35
@@ -178,12 +143,42 @@
178#define BRIDGE_GIO_WEIGHT 0x2cb 143#define BRIDGE_GIO_WEIGHT 0x2cb
179#define BRIDGE_FLASH_WEIGHT 0x2cc 144#define BRIDGE_FLASH_WEIGHT 0x2cc
180 145
146/* FIXME verify */
147#define BRIDGE_9XX_FLASH_BAR(i) (0x11 + (i))
148#define BRIDGE_9XX_FLASH_BAR_LIMIT(i) (0x15 + (i))
149
150#define BRIDGE_9XX_DRAM_BAR(i) (0x19 + (i))
151#define BRIDGE_9XX_DRAM_LIMIT(i) (0x29 + (i))
152#define BRIDGE_9XX_DRAM_NODE_TRANSLN(i) (0x39 + (i))
153#define BRIDGE_9XX_DRAM_CHNL_TRANSLN(i) (0x49 + (i))
154
155#define BRIDGE_9XX_ADDRESS_ERROR0 0x9d
156#define BRIDGE_9XX_ADDRESS_ERROR1 0x9e
157#define BRIDGE_9XX_ADDRESS_ERROR2 0x9f
158
159#define BRIDGE_9XX_PCIEMEM_BASE0 0x59
160#define BRIDGE_9XX_PCIEMEM_BASE1 0x5a
161#define BRIDGE_9XX_PCIEMEM_BASE2 0x5b
162#define BRIDGE_9XX_PCIEMEM_BASE3 0x5c
163#define BRIDGE_9XX_PCIEMEM_LIMIT0 0x5d
164#define BRIDGE_9XX_PCIEMEM_LIMIT1 0x5e
165#define BRIDGE_9XX_PCIEMEM_LIMIT2 0x5f
166#define BRIDGE_9XX_PCIEMEM_LIMIT3 0x60
167#define BRIDGE_9XX_PCIEIO_BASE0 0x61
168#define BRIDGE_9XX_PCIEIO_BASE1 0x62
169#define BRIDGE_9XX_PCIEIO_BASE2 0x63
170#define BRIDGE_9XX_PCIEIO_BASE3 0x64
171#define BRIDGE_9XX_PCIEIO_LIMIT0 0x65
172#define BRIDGE_9XX_PCIEIO_LIMIT1 0x66
173#define BRIDGE_9XX_PCIEIO_LIMIT2 0x67
174#define BRIDGE_9XX_PCIEIO_LIMIT3 0x68
175
181#ifndef __ASSEMBLY__ 176#ifndef __ASSEMBLY__
182 177
183#define nlm_read_bridge_reg(b, r) nlm_read_reg(b, r) 178#define nlm_read_bridge_reg(b, r) nlm_read_reg(b, r)
184#define nlm_write_bridge_reg(b, r, v) nlm_write_reg(b, r, v) 179#define nlm_write_bridge_reg(b, r, v) nlm_write_reg(b, r, v)
185#define nlm_get_bridge_pcibase(node) \ 180#define nlm_get_bridge_pcibase(node) nlm_pcicfg_base(cpu_is_xlp9xx() ? \
186 nlm_pcicfg_base(XLP_IO_BRIDGE_OFFSET(node)) 181 XLP9XX_IO_BRIDGE_OFFSET(node) : XLP_IO_BRIDGE_OFFSET(node))
187#define nlm_get_bridge_regbase(node) \ 182#define nlm_get_bridge_regbase(node) \
188 (nlm_get_bridge_pcibase(node) + XLP_IO_PCI_HDRSZ) 183 (nlm_get_bridge_pcibase(node) + XLP_IO_PCI_HDRSZ)
189 184
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/iomap.h b/arch/mips/include/asm/netlogic/xlp-hal/iomap.h
index 55eee77adaca..1f23dfaa7167 100644
--- a/arch/mips/include/asm/netlogic/xlp-hal/iomap.h
+++ b/arch/mips/include/asm/netlogic/xlp-hal/iomap.h
@@ -48,8 +48,10 @@
48#define XLP_IO_SIZE (64 << 20) /* ECFG space size */ 48#define XLP_IO_SIZE (64 << 20) /* ECFG space size */
49#define XLP_IO_PCI_HDRSZ 0x100 49#define XLP_IO_PCI_HDRSZ 0x100
50#define XLP_IO_DEV(node, dev) ((dev) + (node) * 8) 50#define XLP_IO_DEV(node, dev) ((dev) + (node) * 8)
51#define XLP_HDR_OFFSET(node, bus, dev, fn) (((bus) << 20) | \ 51#define XLP_IO_PCI_OFFSET(b, d, f) (((b) << 20) | ((d) << 15) | ((f) << 12))
52 ((XLP_IO_DEV(node, dev)) << 15) | ((fn) << 12)) 52
53#define XLP_HDR_OFFSET(node, bus, dev, fn) \
54 XLP_IO_PCI_OFFSET(bus, XLP_IO_DEV(node, dev), fn)
53 55
54#define XLP_IO_BRIDGE_OFFSET(node) XLP_HDR_OFFSET(node, 0, 0, 0) 56#define XLP_IO_BRIDGE_OFFSET(node) XLP_HDR_OFFSET(node, 0, 0, 0)
55/* coherent inter chip */ 57/* coherent inter chip */
@@ -109,6 +111,36 @@
109#define XLP_IO_MMC_OFFSET(node, slot) \ 111#define XLP_IO_MMC_OFFSET(node, slot) \
110 ((XLP_IO_SD_OFFSET(node))+(slot*0x100)+XLP_IO_PCI_HDRSZ) 112 ((XLP_IO_SD_OFFSET(node))+(slot*0x100)+XLP_IO_PCI_HDRSZ)
111 113
114/* Things have changed drastically in XLP 9XX */
115#define XLP9XX_HDR_OFFSET(n, d, f) \
116 XLP_IO_PCI_OFFSET(xlp9xx_get_socbus(n), d, f)
117
118#define XLP9XX_IO_BRIDGE_OFFSET(node) XLP_IO_PCI_OFFSET(0, 0, node)
119#define XLP9XX_IO_PIC_OFFSET(node) XLP9XX_HDR_OFFSET(node, 2, 0)
120#define XLP9XX_IO_UART_OFFSET(node) XLP9XX_HDR_OFFSET(node, 2, 2)
121#define XLP9XX_IO_SYS_OFFSET(node) XLP9XX_HDR_OFFSET(node, 6, 0)
122#define XLP9XX_IO_FUSE_OFFSET(node) XLP9XX_HDR_OFFSET(node, 6, 1)
123#define XLP9XX_IO_JTAG_OFFSET(node) XLP9XX_HDR_OFFSET(node, 6, 4)
124
125#define XLP9XX_IO_PCIE_OFFSET(node, i) XLP9XX_HDR_OFFSET(node, 1, i)
126#define XLP9XX_IO_PCIE0_OFFSET(node) XLP9XX_HDR_OFFSET(node, 1, 0)
127#define XLP9XX_IO_PCIE2_OFFSET(node) XLP9XX_HDR_OFFSET(node, 1, 2)
128#define XLP9XX_IO_PCIE3_OFFSET(node) XLP9XX_HDR_OFFSET(node, 1, 3)
129
130/* XLP9xx USB block */
131#define XLP9XX_IO_USB_OFFSET(node, i) XLP9XX_HDR_OFFSET(node, 4, i)
132#define XLP9XX_IO_USB_XHCI0_OFFSET(node) XLP9XX_HDR_OFFSET(node, 4, 1)
133#define XLP9XX_IO_USB_XHCI1_OFFSET(node) XLP9XX_HDR_OFFSET(node, 4, 2)
134
135/* XLP9XX on-chip SATA controller */
136#define XLP9XX_IO_SATA_OFFSET(node) XLP9XX_HDR_OFFSET(node, 3, 2)
137
138#define XLP9XX_IO_NOR_OFFSET(node) XLP9XX_HDR_OFFSET(node, 7, 0)
139#define XLP9XX_IO_NAND_OFFSET(node) XLP9XX_HDR_OFFSET(node, 7, 1)
140#define XLP9XX_IO_SPI_OFFSET(node) XLP9XX_HDR_OFFSET(node, 7, 2)
141/* SD flash */
142#define XLP9XX_IO_MMCSD_OFFSET(node) XLP9XX_HDR_OFFSET(node, 7, 3)
143
112/* PCI config header register id's */ 144/* PCI config header register id's */
113#define XLP_PCI_CFGREG0 0x00 145#define XLP_PCI_CFGREG0 0x00
114#define XLP_PCI_CFGREG1 0x01 146#define XLP_PCI_CFGREG1 0x01
@@ -156,11 +188,23 @@
156#define PCI_DEVICE_ID_NLM_MMC 0x1018 188#define PCI_DEVICE_ID_NLM_MMC 0x1018
157#define PCI_DEVICE_ID_NLM_XHCI 0x101d 189#define PCI_DEVICE_ID_NLM_XHCI 0x101d
158 190
191#define PCI_DEVICE_ID_XLP9XX_SATA 0x901A
192#define PCI_DEVICE_ID_XLP9XX_XHCI 0x901D
193
159#ifndef __ASSEMBLY__ 194#ifndef __ASSEMBLY__
160 195
161#define nlm_read_pci_reg(b, r) nlm_read_reg(b, r) 196#define nlm_read_pci_reg(b, r) nlm_read_reg(b, r)
162#define nlm_write_pci_reg(b, r, v) nlm_write_reg(b, r, v) 197#define nlm_write_pci_reg(b, r, v) nlm_write_reg(b, r, v)
163 198
199static inline int xlp9xx_get_socbus(int node)
200{
201 uint64_t socbridge;
202
203 if (node == 0)
204 return 1;
205 socbridge = nlm_pcicfg_base(XLP9XX_IO_BRIDGE_OFFSET(node));
206 return (nlm_read_pci_reg(socbridge, 0x6) >> 8) & 0xff;
207}
164#endif /* !__ASSEMBLY */ 208#endif /* !__ASSEMBLY */
165 209
166#endif /* __NLM_HAL_IOMAP_H__ */ 210#endif /* __NLM_HAL_IOMAP_H__ */
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/pcibus.h b/arch/mips/include/asm/netlogic/xlp-hal/pcibus.h
index b559cb9f56ea..d4deb87ad069 100644
--- a/arch/mips/include/asm/netlogic/xlp-hal/pcibus.h
+++ b/arch/mips/include/asm/netlogic/xlp-hal/pcibus.h
@@ -52,25 +52,48 @@
52#define PCIE_BYTE_SWAP_MEM_LIM 0x248 52#define PCIE_BYTE_SWAP_MEM_LIM 0x248
53#define PCIE_BYTE_SWAP_IO_BASE 0x249 53#define PCIE_BYTE_SWAP_IO_BASE 0x249
54#define PCIE_BYTE_SWAP_IO_LIM 0x24A 54#define PCIE_BYTE_SWAP_IO_LIM 0x24A
55
56#define PCIE_BRIDGE_MSIX_ADDR_BASE 0x24F
57#define PCIE_BRIDGE_MSIX_ADDR_LIMIT 0x250
55#define PCIE_MSI_STATUS 0x25A 58#define PCIE_MSI_STATUS 0x25A
56#define PCIE_MSI_EN 0x25B 59#define PCIE_MSI_EN 0x25B
60#define PCIE_MSIX_STATUS 0x25D
61#define PCIE_INT_STATUS0 0x25F
62#define PCIE_INT_STATUS1 0x260
57#define PCIE_INT_EN0 0x261 63#define PCIE_INT_EN0 0x261
64#define PCIE_INT_EN1 0x262
58 65
59/* PCIE_MSI_EN */ 66/* XLP9XX has basic changes */
60#define PCIE_MSI_VECTOR_INT_EN 0xFFFFFFFF 67#define PCIE_9XX_BYTE_SWAP_MEM_BASE 0x25c
68#define PCIE_9XX_BYTE_SWAP_MEM_LIM 0x25d
69#define PCIE_9XX_BYTE_SWAP_IO_BASE 0x25e
70#define PCIE_9XX_BYTE_SWAP_IO_LIM 0x25f
61 71
62/* PCIE_INT_EN0 */ 72/* other */
63#define PCIE_MSI_INT_EN (1 << 9) 73#define PCIE_NLINKS 4
64 74
75/* MSI addresses */
76#define MSI_ADDR_BASE 0xfffee00000ULL
77#define MSI_ADDR_SZ 0x10000
78#define MSI_LINK_ADDR(n, l) (MSI_ADDR_BASE + \
79 (PCIE_NLINKS * (n) + (l)) * MSI_ADDR_SZ)
80#define MSIX_ADDR_BASE 0xfffef00000ULL
81#define MSIX_LINK_ADDR(n, l) (MSIX_ADDR_BASE + \
82 (PCIE_NLINKS * (n) + (l)) * MSI_ADDR_SZ)
65#ifndef __ASSEMBLY__ 83#ifndef __ASSEMBLY__
66 84
67#define nlm_read_pcie_reg(b, r) nlm_read_reg(b, r) 85#define nlm_read_pcie_reg(b, r) nlm_read_reg(b, r)
68#define nlm_write_pcie_reg(b, r, v) nlm_write_reg(b, r, v) 86#define nlm_write_pcie_reg(b, r, v) nlm_write_reg(b, r, v)
69#define nlm_get_pcie_base(node, inst) \ 87#define nlm_get_pcie_base(node, inst) nlm_pcicfg_base(cpu_is_xlp9xx() ? \
70 nlm_pcicfg_base(XLP_IO_PCIE_OFFSET(node, inst)) 88 XLP9XX_IO_PCIE_OFFSET(node, inst) : XLP_IO_PCIE_OFFSET(node, inst))
71#define nlm_get_pcie_regbase(node, inst) \ 89
72 (nlm_get_pcie_base(node, inst) + XLP_IO_PCI_HDRSZ) 90#ifdef CONFIG_PCI_MSI
91void xlp_init_node_msi_irqs(int node, int link);
92#else
93static inline void xlp_init_node_msi_irqs(int node, int link) {}
94#endif
95
96struct pci_dev *xlp_get_pcie_link(const struct pci_dev *dev);
73 97
74int xlp_pcie_link_irt(int link);
75#endif 98#endif
76#endif /* __NLM_HAL_PCIBUS_H__ */ 99#endif /* __NLM_HAL_PCIBUS_H__ */
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/pic.h b/arch/mips/include/asm/netlogic/xlp-hal/pic.h
index 105389b79f09..f10bf3bba58f 100644
--- a/arch/mips/include/asm/netlogic/xlp-hal/pic.h
+++ b/arch/mips/include/asm/netlogic/xlp-hal/pic.h
@@ -150,12 +150,19 @@
150#define PIC_IRT0 0x74 150#define PIC_IRT0 0x74
151#define PIC_IRT(i) (PIC_IRT0 + ((i) * 2)) 151#define PIC_IRT(i) (PIC_IRT0 + ((i) * 2))
152 152
153#define TIMER_CYCLES_MAXVAL 0xffffffffffffffffULL 153#define PIC_9XX_PENDING_0 0x6
154#define PIC_9XX_PENDING_1 0x8
155#define PIC_9XX_PENDING_2 0xa
156#define PIC_9XX_PENDING_3 0xc
157
158#define PIC_9XX_IRT0 0x1c0
159#define PIC_9XX_IRT(i) (PIC_9XX_IRT0 + ((i) * 2))
154 160
155/* 161/*
156 * IRT Map 162 * IRT Map
157 */ 163 */
158#define PIC_NUM_IRTS 160 164#define PIC_NUM_IRTS 160
165#define PIC_9XX_NUM_IRTS 256
159 166
160#define PIC_IRT_WD_0_INDEX 0 167#define PIC_IRT_WD_0_INDEX 0
161#define PIC_IRT_WD_1_INDEX 1 168#define PIC_IRT_WD_1_INDEX 1
@@ -193,14 +200,9 @@
193#define PIC_IRT_PCIE_LINK_INDEX(num) ((num) + PIC_IRT_PCIE_LINK_0_INDEX) 200#define PIC_IRT_PCIE_LINK_INDEX(num) ((num) + PIC_IRT_PCIE_LINK_0_INDEX)
194 201
195#define PIC_CLOCK_TIMER 7 202#define PIC_CLOCK_TIMER 7
196#define PIC_IRQ_BASE 8
197 203
198#if !defined(LOCORE) && !defined(__ASSEMBLY__) 204#if !defined(LOCORE) && !defined(__ASSEMBLY__)
199 205
200#define PIC_IRT_FIRST_IRQ (PIC_IRQ_BASE)
201#define PIC_IRT_LAST_IRQ 63
202#define PIC_IRQ_IS_IRT(irq) ((irq) >= PIC_IRT_FIRST_IRQ)
203
204/* 206/*
205 * Misc 207 * Misc
206 */ 208 */
@@ -210,30 +212,26 @@
210 212
211#define nlm_read_pic_reg(b, r) nlm_read_reg64(b, r) 213#define nlm_read_pic_reg(b, r) nlm_read_reg64(b, r)
212#define nlm_write_pic_reg(b, r, v) nlm_write_reg64(b, r, v) 214#define nlm_write_pic_reg(b, r, v) nlm_write_reg64(b, r, v)
213#define nlm_get_pic_pcibase(node) nlm_pcicfg_base(XLP_IO_PIC_OFFSET(node)) 215#define nlm_get_pic_pcibase(node) nlm_pcicfg_base(cpu_is_xlp9xx() ? \
216 XLP9XX_IO_PIC_OFFSET(node) : XLP_IO_PIC_OFFSET(node))
214#define nlm_get_pic_regbase(node) (nlm_get_pic_pcibase(node) + XLP_IO_PCI_HDRSZ) 217#define nlm_get_pic_regbase(node) (nlm_get_pic_pcibase(node) + XLP_IO_PCI_HDRSZ)
215 218
216/* We use PIC on node 0 as a timer */ 219/* We use PIC on node 0 as a timer */
217#define pic_timer_freq() nlm_get_pic_frequency(0) 220#define pic_timer_freq() nlm_get_pic_frequency(0)
218 221
219/* IRT and h/w interrupt routines */ 222/* IRT and h/w interrupt routines */
220static inline int
221nlm_pic_read_irt(uint64_t base, int irt_index)
222{
223 return nlm_read_pic_reg(base, PIC_IRT(irt_index));
224}
225
226static inline void 223static inline void
227nlm_set_irt_to_cpu(uint64_t base, int irt, int cpu) 224nlm_9xx_pic_write_irt(uint64_t base, int irt_num, int en, int nmi,
225 int sch, int vec, int dt, int db, int cpu)
228{ 226{
229 uint64_t val; 227 uint64_t val;
230 228
231 val = nlm_read_pic_reg(base, PIC_IRT(irt)); 229 val = (((uint64_t)en & 0x1) << 22) | ((nmi & 0x1) << 23) |
232 /* clear cpuset and mask */ 230 ((0 /*mc*/) << 20) | ((vec & 0x3f) << 24) |
233 val &= ~((0x7ull << 16) | 0xffff); 231 ((dt & 0x1) << 21) | (0 /*ptr*/ << 16) |
234 /* set DB, cpuset and cpumask */ 232 (cpu & 0x3ff);
235 val |= (1 << 19) | ((cpu >> 4) << 16) | (1 << (cpu & 0xf)); 233
236 nlm_write_pic_reg(base, PIC_IRT(irt), val); 234 nlm_write_pic_reg(base, PIC_9XX_IRT(irt_num), val);
237} 235}
238 236
239static inline void 237static inline void
@@ -254,9 +252,13 @@ static inline void
254nlm_pic_write_irt_direct(uint64_t base, int irt_num, int en, int nmi, 252nlm_pic_write_irt_direct(uint64_t base, int irt_num, int en, int nmi,
255 int sch, int vec, int cpu) 253 int sch, int vec, int cpu)
256{ 254{
257 nlm_pic_write_irt(base, irt_num, en, nmi, sch, vec, 1, 255 if (cpu_is_xlp9xx())
258 (cpu >> 4), /* thread group */ 256 nlm_9xx_pic_write_irt(base, irt_num, en, nmi, sch, vec,
259 1 << (cpu & 0xf)); /* thread mask */ 257 1, 0, cpu);
258 else
259 nlm_pic_write_irt(base, irt_num, en, nmi, sch, vec, 1,
260 (cpu >> 4), /* thread group */
261 1 << (cpu & 0xf)); /* thread mask */
260} 262}
261 263
262static inline uint64_t 264static inline uint64_t
@@ -298,8 +300,13 @@ nlm_pic_enable_irt(uint64_t base, int irt)
298{ 300{
299 uint64_t reg; 301 uint64_t reg;
300 302
301 reg = nlm_read_pic_reg(base, PIC_IRT(irt)); 303 if (cpu_is_xlp9xx()) {
302 nlm_write_pic_reg(base, PIC_IRT(irt), reg | (1u << 31)); 304 reg = nlm_read_pic_reg(base, PIC_9XX_IRT(irt));
305 nlm_write_pic_reg(base, PIC_9XX_IRT(irt), reg | (1 << 22));
306 } else {
307 reg = nlm_read_pic_reg(base, PIC_IRT(irt));
308 nlm_write_pic_reg(base, PIC_IRT(irt), reg | (1u << 31));
309 }
303} 310}
304 311
305static inline void 312static inline void
@@ -307,8 +314,15 @@ nlm_pic_disable_irt(uint64_t base, int irt)
307{ 314{
308 uint64_t reg; 315 uint64_t reg;
309 316
310 reg = nlm_read_pic_reg(base, PIC_IRT(irt)); 317 if (cpu_is_xlp9xx()) {
311 nlm_write_pic_reg(base, PIC_IRT(irt), reg & ~((uint64_t)1 << 31)); 318 reg = nlm_read_pic_reg(base, PIC_9XX_IRT(irt));
319 reg &= ~((uint64_t)1 << 22);
320 nlm_write_pic_reg(base, PIC_9XX_IRT(irt), reg);
321 } else {
322 reg = nlm_read_pic_reg(base, PIC_IRT(irt));
323 reg &= ~((uint64_t)1 << 31);
324 nlm_write_pic_reg(base, PIC_IRT(irt), reg);
325 }
312} 326}
313 327
314static inline void 328static inline void
@@ -316,8 +330,13 @@ nlm_pic_send_ipi(uint64_t base, int hwt, int irq, int nmi)
316{ 330{
317 uint64_t ipi; 331 uint64_t ipi;
318 332
319 ipi = ((uint64_t)nmi << 31) | (irq << 20); 333 if (cpu_is_xlp9xx())
320 ipi |= ((hwt >> 4) << 16) | (1 << (hwt & 0xf)); /* cpuset and mask */ 334 ipi = (nmi << 23) | (irq << 24) |
335 (0/*mcm*/ << 20) | (0/*ptr*/ << 16) | hwt;
336 else
337 ipi = ((uint64_t)nmi << 31) | (irq << 20) |
338 ((hwt >> 4) << 16) | (1 << (hwt & 0xf));
339
321 nlm_write_pic_reg(base, PIC_IPI_CTL, ipi); 340 nlm_write_pic_reg(base, PIC_IPI_CTL, ipi);
322} 341}
323 342
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/sys.h b/arch/mips/include/asm/netlogic/xlp-hal/sys.h
index fcf2833c16ca..d9b107ffca93 100644
--- a/arch/mips/include/asm/netlogic/xlp-hal/sys.h
+++ b/arch/mips/include/asm/netlogic/xlp-hal/sys.h
@@ -147,13 +147,29 @@
147#define SYS_SYS_PLL_MEM_REQ 0x2a3 147#define SYS_SYS_PLL_MEM_REQ 0x2a3
148#define SYS_PLL_MEM_STAT 0x2a4 148#define SYS_PLL_MEM_STAT 0x2a4
149 149
150/* Registers changed on 9XX */
151#define SYS_9XX_POWER_ON_RESET_CFG 0x00
152#define SYS_9XX_CHIP_RESET 0x01
153#define SYS_9XX_CPU_RESET 0x02
154#define SYS_9XX_CPU_NONCOHERENT_MODE 0x03
155
156/* XLP 9XX fuse block registers */
157#define FUSE_9XX_DEVCFG6 0xc6
158
150#ifndef __ASSEMBLY__ 159#ifndef __ASSEMBLY__
151 160
152#define nlm_read_sys_reg(b, r) nlm_read_reg(b, r) 161#define nlm_read_sys_reg(b, r) nlm_read_reg(b, r)
153#define nlm_write_sys_reg(b, r, v) nlm_write_reg(b, r, v) 162#define nlm_write_sys_reg(b, r, v) nlm_write_reg(b, r, v)
154#define nlm_get_sys_pcibase(node) nlm_pcicfg_base(XLP_IO_SYS_OFFSET(node)) 163#define nlm_get_sys_pcibase(node) nlm_pcicfg_base(cpu_is_xlp9xx() ? \
164 XLP9XX_IO_SYS_OFFSET(node) : XLP_IO_SYS_OFFSET(node))
155#define nlm_get_sys_regbase(node) (nlm_get_sys_pcibase(node) + XLP_IO_PCI_HDRSZ) 165#define nlm_get_sys_regbase(node) (nlm_get_sys_pcibase(node) + XLP_IO_PCI_HDRSZ)
156 166
167/* XLP9XX fuse block */
168#define nlm_get_fuse_pcibase(node) \
169 nlm_pcicfg_base(XLP9XX_IO_FUSE_OFFSET(node))
170#define nlm_get_fuse_regbase(node) \
171 (nlm_get_fuse_pcibase(node) + XLP_IO_PCI_HDRSZ)
172
157unsigned int nlm_get_pic_frequency(int node); 173unsigned int nlm_get_pic_frequency(int node);
158#endif 174#endif
159#endif 175#endif
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/uart.h b/arch/mips/include/asm/netlogic/xlp-hal/uart.h
index 86d16e1e6072..a6c54424dd95 100644
--- a/arch/mips/include/asm/netlogic/xlp-hal/uart.h
+++ b/arch/mips/include/asm/netlogic/xlp-hal/uart.h
@@ -94,7 +94,8 @@
94#define nlm_read_uart_reg(b, r) nlm_read_reg(b, r) 94#define nlm_read_uart_reg(b, r) nlm_read_reg(b, r)
95#define nlm_write_uart_reg(b, r, v) nlm_write_reg(b, r, v) 95#define nlm_write_uart_reg(b, r, v) nlm_write_reg(b, r, v)
96#define nlm_get_uart_pcibase(node, inst) \ 96#define nlm_get_uart_pcibase(node, inst) \
97 nlm_pcicfg_base(XLP_IO_UART_OFFSET(node, inst)) 97 nlm_pcicfg_base(cpu_is_xlp9xx() ? XLP9XX_IO_UART_OFFSET(node) : \
98 XLP_IO_UART_OFFSET(node, inst))
98#define nlm_get_uart_regbase(node, inst) \ 99#define nlm_get_uart_regbase(node, inst) \
99 (nlm_get_uart_pcibase(node, inst) + XLP_IO_PCI_HDRSZ) 100 (nlm_get_uart_pcibase(node, inst) + XLP_IO_PCI_HDRSZ)
100 101
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/xlp.h b/arch/mips/include/asm/netlogic/xlp-hal/xlp.h
index 470f2095b346..2b0c9599ebe5 100644
--- a/arch/mips/include/asm/netlogic/xlp-hal/xlp.h
+++ b/arch/mips/include/asm/netlogic/xlp-hal/xlp.h
@@ -37,10 +37,9 @@
37 37
38#define PIC_UART_0_IRQ 17 38#define PIC_UART_0_IRQ 17
39#define PIC_UART_1_IRQ 18 39#define PIC_UART_1_IRQ 18
40#define PIC_PCIE_LINK_0_IRQ 19 40
41#define PIC_PCIE_LINK_1_IRQ 20 41#define PIC_PCIE_LINK_LEGACY_IRQ_BASE 19
42#define PIC_PCIE_LINK_2_IRQ 21 42#define PIC_PCIE_LINK_LEGACY_IRQ(i) (19 + (i))
43#define PIC_PCIE_LINK_3_IRQ 22
44 43
45#define PIC_EHCI_0_IRQ 23 44#define PIC_EHCI_0_IRQ 23
46#define PIC_EHCI_1_IRQ 24 45#define PIC_EHCI_1_IRQ 24
@@ -51,6 +50,8 @@
51#define PIC_2XX_XHCI_0_IRQ 23 50#define PIC_2XX_XHCI_0_IRQ 23
52#define PIC_2XX_XHCI_1_IRQ 24 51#define PIC_2XX_XHCI_1_IRQ 24
53#define PIC_2XX_XHCI_2_IRQ 25 52#define PIC_2XX_XHCI_2_IRQ 25
53#define PIC_9XX_XHCI_0_IRQ 23
54#define PIC_9XX_XHCI_1_IRQ 24
54 55
55#define PIC_MMC_IRQ 29 56#define PIC_MMC_IRQ 29
56#define PIC_I2C_0_IRQ 30 57#define PIC_I2C_0_IRQ 30
@@ -58,6 +59,23 @@
58#define PIC_I2C_2_IRQ 32 59#define PIC_I2C_2_IRQ 32
59#define PIC_I2C_3_IRQ 33 60#define PIC_I2C_3_IRQ 33
60 61
62#define PIC_PCIE_LINK_MSI_IRQ_BASE 44 /* 44 - 47 MSI IRQ */
63#define PIC_PCIE_LINK_MSI_IRQ(i) (44 + (i))
64
65/* MSI-X with second link-level dispatch */
66#define PIC_PCIE_MSIX_IRQ_BASE 48 /* 48 - 51 MSI-X IRQ */
67#define PIC_PCIE_MSIX_IRQ(i) (48 + (i))
68
69#define NLM_MSIX_VEC_BASE 96 /* 96 - 127 - MSIX mapped */
70#define NLM_MSI_VEC_BASE 128 /* 128 -255 - MSI mapped */
71
72#define NLM_PIC_INDIRECT_VEC_BASE 512
73#define NLM_GPIO_VEC_BASE 768
74
75#define PIC_IRQ_BASE 8
76#define PIC_IRT_FIRST_IRQ PIC_IRQ_BASE
77#define PIC_IRT_LAST_IRQ 63
78
61#ifndef __ASSEMBLY__ 79#ifndef __ASSEMBLY__
62 80
63/* SMP support functions */ 81/* SMP support functions */
@@ -68,6 +86,9 @@ void xlp_mmu_init(void);
68void nlm_hal_init(void); 86void nlm_hal_init(void);
69int xlp_get_dram_map(int n, uint64_t *dram_map); 87int xlp_get_dram_map(int n, uint64_t *dram_map);
70 88
89struct pci_dev;
90int xlp_socdev_to_node(const struct pci_dev *dev);
91
71/* Device tree related */ 92/* Device tree related */
72void xlp_early_init_devtree(void); 93void xlp_early_init_devtree(void);
73void *xlp_dt_init(void *fdtp); 94void *xlp_dt_init(void *fdtp);
@@ -76,8 +97,15 @@ static inline int cpu_is_xlpii(void)
76{ 97{
77 int chip = read_c0_prid() & 0xff00; 98 int chip = read_c0_prid() & 0xff00;
78 99
79 return chip == PRID_IMP_NETLOGIC_XLP2XX; 100 return chip == PRID_IMP_NETLOGIC_XLP2XX ||
101 chip == PRID_IMP_NETLOGIC_XLP9XX;
80} 102}
81 103
104static inline int cpu_is_xlp9xx(void)
105{
106 int chip = read_c0_prid() & 0xff00;
107
108 return chip == PRID_IMP_NETLOGIC_XLP9XX;
109}
82#endif /* !__ASSEMBLY__ */ 110#endif /* !__ASSEMBLY__ */
83#endif /* _ASM_NLM_XLP_H */ 111#endif /* _ASM_NLM_XLP_H */
diff --git a/arch/mips/include/asm/netlogic/xlr/xlr.h b/arch/mips/include/asm/netlogic/xlr/xlr.h
index c1667e0c272a..ceb991ca8436 100644
--- a/arch/mips/include/asm/netlogic/xlr/xlr.h
+++ b/arch/mips/include/asm/netlogic/xlr/xlr.h
@@ -35,11 +35,6 @@
35#ifndef _ASM_NLM_XLR_H 35#ifndef _ASM_NLM_XLR_H
36#define _ASM_NLM_XLR_H 36#define _ASM_NLM_XLR_H
37 37
38/* Platform UART functions */
39struct uart_port;
40unsigned int nlm_xlr_uart_in(struct uart_port *, int);
41void nlm_xlr_uart_out(struct uart_port *, int, int);
42
43/* SMP helpers */ 38/* SMP helpers */
44void xlr_wakeup_secondary_cpus(void); 39void xlr_wakeup_secondary_cpus(void);
45 40
diff --git a/arch/mips/include/asm/octeon/cvmx-helper-board.h b/arch/mips/include/asm/octeon/cvmx-helper-board.h
index 41785dd0ddd0..893320375aef 100644
--- a/arch/mips/include/asm/octeon/cvmx-helper-board.h
+++ b/arch/mips/include/asm/octeon/cvmx-helper-board.h
@@ -36,6 +36,13 @@
36 36
37#include <asm/octeon/cvmx-helper.h> 37#include <asm/octeon/cvmx-helper.h>
38 38
39enum cvmx_helper_board_usb_clock_types {
40 USB_CLOCK_TYPE_REF_12,
41 USB_CLOCK_TYPE_REF_24,
42 USB_CLOCK_TYPE_REF_48,
43 USB_CLOCK_TYPE_CRYSTAL_12,
44};
45
39typedef enum { 46typedef enum {
40 set_phy_link_flags_autoneg = 0x1, 47 set_phy_link_flags_autoneg = 0x1,
41 set_phy_link_flags_flow_control_dont_touch = 0x0 << 1, 48 set_phy_link_flags_flow_control_dont_touch = 0x0 << 1,
@@ -154,4 +161,6 @@ extern int __cvmx_helper_board_interface_probe(int interface,
154 */ 161 */
155extern int __cvmx_helper_board_hardware_enable(int interface); 162extern int __cvmx_helper_board_hardware_enable(int interface);
156 163
164enum cvmx_helper_board_usb_clock_types __cvmx_helper_board_usb_get_clock_type(void);
165
157#endif /* __CVMX_HELPER_BOARD_H__ */ 166#endif /* __CVMX_HELPER_BOARD_H__ */
diff --git a/arch/mips/include/asm/page.h b/arch/mips/include/asm/page.h
index f6be4741f7e8..5e08bcc74897 100644
--- a/arch/mips/include/asm/page.h
+++ b/arch/mips/include/asm/page.h
@@ -11,6 +11,8 @@
11 11
12#include <spaces.h> 12#include <spaces.h>
13#include <linux/const.h> 13#include <linux/const.h>
14#include <linux/kernel.h>
15#include <asm/mipsregs.h>
14 16
15/* 17/*
16 * PAGE_SHIFT determines the page size 18 * PAGE_SHIFT determines the page size
@@ -33,6 +35,29 @@
33#define PAGE_SIZE (_AC(1,UL) << PAGE_SHIFT) 35#define PAGE_SIZE (_AC(1,UL) << PAGE_SHIFT)
34#define PAGE_MASK (~((1 << PAGE_SHIFT) - 1)) 36#define PAGE_MASK (~((1 << PAGE_SHIFT) - 1))
35 37
38/*
39 * This is used for calculating the real page sizes
40 * for FTLB or VTLB + FTLB confugrations.
41 */
42static inline unsigned int page_size_ftlb(unsigned int mmuextdef)
43{
44 switch (mmuextdef) {
45 case MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT:
46 if (PAGE_SIZE == (1 << 30))
47 return 5;
48 if (PAGE_SIZE == (1llu << 32))
49 return 6;
50 if (PAGE_SIZE > (256 << 10))
51 return 7; /* reserved */
52 /* fall through */
53 case MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT:
54 return (PAGE_SHIFT - 10) / 2;
55 default:
56 panic("Invalid FTLB configuration with Conf4_mmuextdef=%d value\n",
57 mmuextdef >> 14);
58 }
59}
60
36#ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT 61#ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
37#define HPAGE_SHIFT (PAGE_SHIFT + PAGE_SHIFT - 3) 62#define HPAGE_SHIFT (PAGE_SHIFT + PAGE_SHIFT - 3)
38#define HPAGE_SIZE (_AC(1,UL) << HPAGE_SHIFT) 63#define HPAGE_SIZE (_AC(1,UL) << HPAGE_SHIFT)
diff --git a/arch/mips/include/asm/rtlx.h b/arch/mips/include/asm/rtlx.h
index 90985b61dbd9..c1020654876e 100644
--- a/arch/mips/include/asm/rtlx.h
+++ b/arch/mips/include/asm/rtlx.h
@@ -1,13 +1,18 @@
1/* 1/*
2 * Copyright (C) 2004, 2005 MIPS Technologies, Inc. All rights reserved. 2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
3 * 5 *
6 * Copyright (C) 2004, 2005 MIPS Technologies, Inc. All rights reserved.
7 * Copyright (C) 2013 Imagination Technologies Ltd.
4 */ 8 */
5
6#ifndef __ASM_RTLX_H_ 9#ifndef __ASM_RTLX_H_
7#define __ASM_RTLX_H_ 10#define __ASM_RTLX_H_
8 11
9#include <irq.h> 12#include <irq.h>
10 13
14#define RTLX_MODULE_NAME "rtlx"
15
11#define LX_NODE_BASE 10 16#define LX_NODE_BASE 10
12 17
13#define MIPS_CPU_RTLX_IRQ 0 18#define MIPS_CPU_RTLX_IRQ 0
@@ -15,18 +20,31 @@
15#define RTLX_VERSION 2 20#define RTLX_VERSION 2
16#define RTLX_xID 0x12345600 21#define RTLX_xID 0x12345600
17#define RTLX_ID (RTLX_xID | RTLX_VERSION) 22#define RTLX_ID (RTLX_xID | RTLX_VERSION)
23#define RTLX_BUFFER_SIZE 2048
18#define RTLX_CHANNELS 8 24#define RTLX_CHANNELS 8
19 25
20#define RTLX_CHANNEL_STDIO 0 26#define RTLX_CHANNEL_STDIO 0
21#define RTLX_CHANNEL_DBG 1 27#define RTLX_CHANNEL_DBG 1
22#define RTLX_CHANNEL_SYSIO 2 28#define RTLX_CHANNEL_SYSIO 2
23 29
24extern int rtlx_open(int index, int can_sleep); 30void rtlx_starting(int vpe);
25extern int rtlx_release(int index); 31void rtlx_stopping(int vpe);
26extern ssize_t rtlx_read(int index, void __user *buff, size_t count); 32
27extern ssize_t rtlx_write(int index, const void __user *buffer, size_t count); 33int rtlx_open(int index, int can_sleep);
28extern unsigned int rtlx_read_poll(int index, int can_sleep); 34int rtlx_release(int index);
29extern unsigned int rtlx_write_poll(int index); 35ssize_t rtlx_read(int index, void __user *buff, size_t count);
36ssize_t rtlx_write(int index, const void __user *buffer, size_t count);
37unsigned int rtlx_read_poll(int index, int can_sleep);
38unsigned int rtlx_write_poll(int index);
39
40int __init rtlx_module_init(void);
41void __exit rtlx_module_exit(void);
42
43void _interrupt_sp(void);
44
45extern struct vpe_notifications rtlx_notify;
46extern const struct file_operations rtlx_fops;
47extern void (*aprp_hook)(void);
30 48
31enum rtlx_state { 49enum rtlx_state {
32 RTLX_STATE_UNUSED = 0, 50 RTLX_STATE_UNUSED = 0,
@@ -35,10 +53,15 @@ enum rtlx_state {
35 RTLX_STATE_OPENED 53 RTLX_STATE_OPENED
36}; 54};
37 55
38#define RTLX_BUFFER_SIZE 2048 56extern struct chan_waitqueues {
57 wait_queue_head_t rt_queue;
58 wait_queue_head_t lx_queue;
59 atomic_t in_open;
60 struct mutex mutex;
61} channel_wqs[RTLX_CHANNELS];
39 62
40/* each channel supports read and write. 63/* each channel supports read and write.
41 linux (vpe0) reads lx_buffer and writes rt_buffer 64 linux (vpe0) reads lx_buffer and writes rt_buffer
42 SP (vpe1) reads rt_buffer and writes lx_buffer 65 SP (vpe1) reads rt_buffer and writes lx_buffer
43*/ 66*/
44struct rtlx_channel { 67struct rtlx_channel {
@@ -55,11 +78,11 @@ struct rtlx_channel {
55 char *lx_buffer; 78 char *lx_buffer;
56}; 79};
57 80
58struct rtlx_info { 81extern struct rtlx_info {
59 unsigned long id; 82 unsigned long id;
60 enum rtlx_state state; 83 enum rtlx_state state;
84 int ap_int_pending; /* Status of 0 or 1 for CONFIG_MIPS_CMP only */
61 85
62 struct rtlx_channel channel[RTLX_CHANNELS]; 86 struct rtlx_channel channel[RTLX_CHANNELS];
63}; 87} *rtlx;
64
65#endif /* __ASM_RTLX_H_ */ 88#endif /* __ASM_RTLX_H_ */
diff --git a/arch/mips/include/asm/switch_to.h b/arch/mips/include/asm/switch_to.h
index eb0af15ac656..278d45a09728 100644
--- a/arch/mips/include/asm/switch_to.h
+++ b/arch/mips/include/asm/switch_to.h
@@ -19,11 +19,19 @@
19 19
20struct task_struct; 20struct task_struct;
21 21
22/* 22/**
23 * switch_to(n) should switch tasks to task nr n, first 23 * resume - resume execution of a task
24 * checking that n isn't the current task, in which case it does nothing. 24 * @prev: The task previously executed.
25 * @next: The task to begin executing.
26 * @next_ti: task_thread_info(next).
27 * @usedfpu: Non-zero if prev's FP context should be saved.
28 *
29 * This function is used whilst scheduling to save the context of prev & load
30 * the context of next. Returns prev.
25 */ 31 */
26extern asmlinkage void *resume(void *last, void *next, void *next_ti, u32 __usedfpu); 32extern asmlinkage struct task_struct *resume(struct task_struct *prev,
33 struct task_struct *next, struct thread_info *next_ti,
34 u32 usedfpu);
27 35
28extern unsigned int ll_bit; 36extern unsigned int ll_bit;
29extern struct task_struct *ll_task; 37extern struct task_struct *ll_task;
diff --git a/arch/mips/include/asm/syscall.h b/arch/mips/include/asm/syscall.h
index 81c89132c59d..33e8dbfc1b63 100644
--- a/arch/mips/include/asm/syscall.h
+++ b/arch/mips/include/asm/syscall.h
@@ -29,7 +29,7 @@ static inline long syscall_get_nr(struct task_struct *task,
29static inline unsigned long mips_get_syscall_arg(unsigned long *arg, 29static inline unsigned long mips_get_syscall_arg(unsigned long *arg,
30 struct task_struct *task, struct pt_regs *regs, unsigned int n) 30 struct task_struct *task, struct pt_regs *regs, unsigned int n)
31{ 31{
32 unsigned long usp = regs->regs[29]; 32 unsigned long usp __maybe_unused = regs->regs[29];
33 33
34 switch (n) { 34 switch (n) {
35 case 0: case 1: case 2: case 3: 35 case 0: case 1: case 2: case 3:
diff --git a/arch/mips/include/asm/thread_info.h b/arch/mips/include/asm/thread_info.h
index 4f58ef6d0eed..24846f9053fe 100644
--- a/arch/mips/include/asm/thread_info.h
+++ b/arch/mips/include/asm/thread_info.h
@@ -110,11 +110,12 @@ static inline struct thread_info *current_thread_info(void)
110#define TIF_NOHZ 19 /* in adaptive nohz mode */ 110#define TIF_NOHZ 19 /* in adaptive nohz mode */
111#define TIF_FIXADE 20 /* Fix address errors in software */ 111#define TIF_FIXADE 20 /* Fix address errors in software */
112#define TIF_LOGADE 21 /* Log address errors to syslog */ 112#define TIF_LOGADE 21 /* Log address errors to syslog */
113#define TIF_32BIT_REGS 22 /* also implies 16/32 fprs */ 113#define TIF_32BIT_REGS 22 /* 32-bit general purpose registers */
114#define TIF_32BIT_ADDR 23 /* 32-bit address space (o32/n32) */ 114#define TIF_32BIT_ADDR 23 /* 32-bit address space (o32/n32) */
115#define TIF_FPUBOUND 24 /* thread bound to FPU-full CPU set */ 115#define TIF_FPUBOUND 24 /* thread bound to FPU-full CPU set */
116#define TIF_LOAD_WATCH 25 /* If set, load watch registers */ 116#define TIF_LOAD_WATCH 25 /* If set, load watch registers */
117#define TIF_SYSCALL_TRACEPOINT 26 /* syscall tracepoint instrumentation */ 117#define TIF_SYSCALL_TRACEPOINT 26 /* syscall tracepoint instrumentation */
118#define TIF_32BIT_FPREGS 27 /* 32-bit floating point registers */
118#define TIF_SYSCALL_TRACE 31 /* syscall trace active */ 119#define TIF_SYSCALL_TRACE 31 /* syscall trace active */
119 120
120#define _TIF_SYSCALL_TRACE (1<<TIF_SYSCALL_TRACE) 121#define _TIF_SYSCALL_TRACE (1<<TIF_SYSCALL_TRACE)
@@ -131,6 +132,7 @@ static inline struct thread_info *current_thread_info(void)
131#define _TIF_32BIT_ADDR (1<<TIF_32BIT_ADDR) 132#define _TIF_32BIT_ADDR (1<<TIF_32BIT_ADDR)
132#define _TIF_FPUBOUND (1<<TIF_FPUBOUND) 133#define _TIF_FPUBOUND (1<<TIF_FPUBOUND)
133#define _TIF_LOAD_WATCH (1<<TIF_LOAD_WATCH) 134#define _TIF_LOAD_WATCH (1<<TIF_LOAD_WATCH)
135#define _TIF_32BIT_FPREGS (1<<TIF_32BIT_FPREGS)
134#define _TIF_SYSCALL_TRACEPOINT (1<<TIF_SYSCALL_TRACEPOINT) 136#define _TIF_SYSCALL_TRACEPOINT (1<<TIF_SYSCALL_TRACEPOINT)
135 137
136#define _TIF_WORK_SYSCALL_ENTRY (_TIF_NOHZ | _TIF_SYSCALL_TRACE | \ 138#define _TIF_WORK_SYSCALL_ENTRY (_TIF_NOHZ | _TIF_SYSCALL_TRACE | \
diff --git a/arch/mips/include/asm/tlb.h b/arch/mips/include/asm/tlb.h
index c67842bc8ef3..4a2349302b55 100644
--- a/arch/mips/include/asm/tlb.h
+++ b/arch/mips/include/asm/tlb.h
@@ -18,6 +18,10 @@
18 */ 18 */
19#define tlb_flush(tlb) flush_tlb_mm((tlb)->mm) 19#define tlb_flush(tlb) flush_tlb_mm((tlb)->mm)
20 20
21#define UNIQUE_ENTRYHI(idx) \
22 ((CKSEG0 + ((idx) << (PAGE_SHIFT + 1))) | \
23 (cpu_has_tlbinv ? MIPS_ENTRYHI_EHINV : 0))
24
21#include <asm-generic/tlb.h> 25#include <asm-generic/tlb.h>
22 26
23#endif /* __ASM_TLB_H */ 27#endif /* __ASM_TLB_H */
diff --git a/arch/mips/include/asm/vpe.h b/arch/mips/include/asm/vpe.h
index 0880fe8809b1..7849f3978fea 100644
--- a/arch/mips/include/asm/vpe.h
+++ b/arch/mips/include/asm/vpe.h
@@ -1,24 +1,95 @@
1/* 1/*
2 * Copyright (C) 2005 MIPS Technologies, Inc. All rights reserved. 2 * This file is subject to the terms and conditions of the GNU General Public
3 * 3 * License. See the file "COPYING" in the main directory of this archive
4 * This program is free software; you can distribute it and/or modify it 4 * for more details.
5 * under the terms of the GNU General Public License (Version 2) as
6 * published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
11 * for more details.
12 *
13 * You should have received a copy of the GNU General Public License along
14 * with this program; if not, write to the Free Software Foundation, Inc.,
15 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
16 * 5 *
6 * Copyright (C) 2005 MIPS Technologies, Inc. All rights reserved.
7 * Copyright (C) 2013 Imagination Technologies Ltd.
17 */ 8 */
18
19#ifndef _ASM_VPE_H 9#ifndef _ASM_VPE_H
20#define _ASM_VPE_H 10#define _ASM_VPE_H
21 11
12#include <linux/init.h>
13#include <linux/list.h>
14#include <linux/smp.h>
15#include <linux/spinlock.h>
16
17#define VPE_MODULE_NAME "vpe"
18#define VPE_MODULE_MINOR 1
19
20/* grab the likely amount of memory we will need. */
21#ifdef CONFIG_MIPS_VPE_LOADER_TOM
22#define P_SIZE (2 * 1024 * 1024)
23#else
24/* add an overhead to the max kmalloc size for non-striped symbols/etc */
25#define P_SIZE (256 * 1024)
26#endif
27
28#define MAX_VPES 16
29#define VPE_PATH_MAX 256
30
31static inline int aprp_cpu_index(void)
32{
33#ifdef CONFIG_MIPS_CMP
34 return setup_max_cpus;
35#else
36 extern int tclimit;
37 return tclimit;
38#endif
39}
40
41enum vpe_state {
42 VPE_STATE_UNUSED = 0,
43 VPE_STATE_INUSE,
44 VPE_STATE_RUNNING
45};
46
47enum tc_state {
48 TC_STATE_UNUSED = 0,
49 TC_STATE_INUSE,
50 TC_STATE_RUNNING,
51 TC_STATE_DYNAMIC
52};
53
54struct vpe {
55 enum vpe_state state;
56
57 /* (device) minor associated with this vpe */
58 int minor;
59
60 /* elfloader stuff */
61 void *load_addr;
62 unsigned long len;
63 char *pbuffer;
64 unsigned long plen;
65 char cwd[VPE_PATH_MAX];
66
67 unsigned long __start;
68
69 /* tc's associated with this vpe */
70 struct list_head tc;
71
72 /* The list of vpe's */
73 struct list_head list;
74
75 /* shared symbol address */
76 void *shared_ptr;
77
78 /* the list of who wants to know when something major happens */
79 struct list_head notify;
80
81 unsigned int ntcs;
82};
83
84struct tc {
85 enum tc_state state;
86 int index;
87
88 struct vpe *pvpe; /* parent VPE */
89 struct list_head tc; /* The list of TC's with this VPE */
90 struct list_head list; /* The global list of tc's */
91};
92
22struct vpe_notifications { 93struct vpe_notifications {
23 void (*start)(int vpe); 94 void (*start)(int vpe);
24 void (*stop)(int vpe); 95 void (*stop)(int vpe);
@@ -26,10 +97,34 @@ struct vpe_notifications {
26 struct list_head list; 97 struct list_head list;
27}; 98};
28 99
100struct vpe_control {
101 spinlock_t vpe_list_lock;
102 struct list_head vpe_list; /* Virtual processing elements */
103 spinlock_t tc_list_lock;
104 struct list_head tc_list; /* Thread contexts */
105};
106
107extern unsigned long physical_memsize;
108extern struct vpe_control vpecontrol;
109extern const struct file_operations vpe_fops;
110
111int vpe_notify(int index, struct vpe_notifications *notify);
112
113void *vpe_get_shared(int index);
114char *vpe_getcwd(int index);
115
116struct vpe *get_vpe(int minor);
117struct tc *get_tc(int index);
118struct vpe *alloc_vpe(int minor);
119struct tc *alloc_tc(int index);
120void release_vpe(struct vpe *v);
29 121
30extern int vpe_notify(int index, struct vpe_notifications *notify); 122void *alloc_progmem(unsigned long len);
123void release_progmem(void *ptr);
31 124
32extern void *vpe_get_shared(int index); 125int __weak vpe_run(struct vpe *v);
33extern char *vpe_getcwd(int index); 126void cleanup_tc(struct tc *tc);
34 127
128int __init vpe_module_init(void);
129void __exit vpe_module_exit(void);
35#endif /* _ASM_VPE_H */ 130#endif /* _ASM_VPE_H */
diff --git a/arch/mips/include/uapi/asm/inst.h b/arch/mips/include/uapi/asm/inst.h
index e5a676e3d3c0..b39ba25b41cc 100644
--- a/arch/mips/include/uapi/asm/inst.h
+++ b/arch/mips/include/uapi/asm/inst.h
@@ -98,8 +98,9 @@ enum rt_op {
98 */ 98 */
99enum cop_op { 99enum cop_op {
100 mfc_op = 0x00, dmfc_op = 0x01, 100 mfc_op = 0x00, dmfc_op = 0x01,
101 cfc_op = 0x02, mtc_op = 0x04, 101 cfc_op = 0x02, mfhc_op = 0x03,
102 dmtc_op = 0x05, ctc_op = 0x06, 102 mtc_op = 0x04, dmtc_op = 0x05,
103 ctc_op = 0x06, mthc_op = 0x07,
103 bc_op = 0x08, cop_op = 0x10, 104 bc_op = 0x08, cop_op = 0x10,
104 copm_op = 0x18 105 copm_op = 0x18
105}; 106};
@@ -397,8 +398,10 @@ enum mm_32f_73_minor_op {
397 mm_movt1_op = 0xa5, 398 mm_movt1_op = 0xa5,
398 mm_ftruncw_op = 0xac, 399 mm_ftruncw_op = 0xac,
399 mm_fneg1_op = 0xad, 400 mm_fneg1_op = 0xad,
401 mm_mfhc1_op = 0xc0,
400 mm_froundl_op = 0xcc, 402 mm_froundl_op = 0xcc,
401 mm_fcvtd1_op = 0xcd, 403 mm_fcvtd1_op = 0xcd,
404 mm_mthc1_op = 0xe0,
402 mm_froundw_op = 0xec, 405 mm_froundw_op = 0xec,
403 mm_fcvts1_op = 0xed, 406 mm_fcvts1_op = 0xed,
404}; 407};
diff --git a/arch/mips/jz4740/board-qi_lb60.c b/arch/mips/jz4740/board-qi_lb60.c
index 8a5ec0eedeb0..c01900e5d078 100644
--- a/arch/mips/jz4740/board-qi_lb60.c
+++ b/arch/mips/jz4740/board-qi_lb60.c
@@ -427,6 +427,7 @@ static struct platform_device qi_lb60_audio_device = {
427 427
428static struct platform_device *jz_platform_devices[] __initdata = { 428static struct platform_device *jz_platform_devices[] __initdata = {
429 &jz4740_udc_device, 429 &jz4740_udc_device,
430 &jz4740_udc_xceiv_device,
430 &jz4740_mmc_device, 431 &jz4740_mmc_device,
431 &jz4740_nand_device, 432 &jz4740_nand_device,
432 &qi_lb60_keypad, 433 &qi_lb60_keypad,
diff --git a/arch/mips/jz4740/platform.c b/arch/mips/jz4740/platform.c
index df65677f3d0b..a447101cf9f1 100644
--- a/arch/mips/jz4740/platform.c
+++ b/arch/mips/jz4740/platform.c
@@ -14,13 +14,14 @@
14 */ 14 */
15 15
16#include <linux/device.h> 16#include <linux/device.h>
17#include <linux/init.h>
18#include <linux/kernel.h> 17#include <linux/kernel.h>
19#include <linux/platform_device.h> 18#include <linux/platform_device.h>
20#include <linux/resource.h> 19#include <linux/resource.h>
21 20
22#include <linux/dma-mapping.h> 21#include <linux/dma-mapping.h>
23 22
23#include <linux/usb/musb.h>
24
24#include <asm/mach-jz4740/platform.h> 25#include <asm/mach-jz4740/platform.h>
25#include <asm/mach-jz4740/base.h> 26#include <asm/mach-jz4740/base.h>
26#include <asm/mach-jz4740/irq.h> 27#include <asm/mach-jz4740/irq.h>
@@ -56,29 +57,35 @@ struct platform_device jz4740_usb_ohci_device = {
56 .resource = jz4740_usb_ohci_resources, 57 .resource = jz4740_usb_ohci_resources,
57}; 58};
58 59
59/* UDC (USB gadget controller) */ 60/* USB Device Controller */
60static struct resource jz4740_usb_gdt_resources[] = { 61struct platform_device jz4740_udc_xceiv_device = {
61 { 62 .name = "usb_phy_gen_xceiv",
62 .start = JZ4740_UDC_BASE_ADDR, 63 .id = 0,
63 .end = JZ4740_UDC_BASE_ADDR + 0x1000 - 1, 64};
64 .flags = IORESOURCE_MEM, 65
66static struct resource jz4740_udc_resources[] = {
67 [0] = {
68 .start = JZ4740_UDC_BASE_ADDR,
69 .end = JZ4740_UDC_BASE_ADDR + 0x10000 - 1,
70 .flags = IORESOURCE_MEM,
65 }, 71 },
66 { 72 [1] = {
67 .start = JZ4740_IRQ_UDC, 73 .start = JZ4740_IRQ_UDC,
68 .end = JZ4740_IRQ_UDC, 74 .end = JZ4740_IRQ_UDC,
69 .flags = IORESOURCE_IRQ, 75 .flags = IORESOURCE_IRQ,
76 .name = "mc",
70 }, 77 },
71}; 78};
72 79
73struct platform_device jz4740_udc_device = { 80struct platform_device jz4740_udc_device = {
74 .name = "jz-udc", 81 .name = "musb-jz4740",
75 .id = -1, 82 .id = -1,
76 .dev = { 83 .dev = {
77 .dma_mask = &jz4740_udc_device.dev.coherent_dma_mask, 84 .dma_mask = &jz4740_udc_device.dev.coherent_dma_mask,
78 .coherent_dma_mask = DMA_BIT_MASK(32), 85 .coherent_dma_mask = DMA_BIT_MASK(32),
79 }, 86 },
80 .num_resources = ARRAY_SIZE(jz4740_usb_gdt_resources), 87 .num_resources = ARRAY_SIZE(jz4740_udc_resources),
81 .resource = jz4740_usb_gdt_resources, 88 .resource = jz4740_udc_resources,
82}; 89};
83 90
84/* MMC/SD controller */ 91/* MMC/SD controller */
diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile
index 1c1b71752c84..26c6175e1379 100644
--- a/arch/mips/kernel/Makefile
+++ b/arch/mips/kernel/Makefile
@@ -30,6 +30,7 @@ obj-$(CONFIG_CSRC_R4K) += csrc-r4k.o
30obj-$(CONFIG_CSRC_SB1250) += csrc-sb1250.o 30obj-$(CONFIG_CSRC_SB1250) += csrc-sb1250.o
31obj-$(CONFIG_SYNC_R4K) += sync-r4k.o 31obj-$(CONFIG_SYNC_R4K) += sync-r4k.o
32 32
33obj-$(CONFIG_DEBUG_FS) += segment.o
33obj-$(CONFIG_STACKTRACE) += stacktrace.o 34obj-$(CONFIG_STACKTRACE) += stacktrace.o
34obj-$(CONFIG_MODULES) += mips_ksyms.o module.o 35obj-$(CONFIG_MODULES) += mips_ksyms.o module.o
35obj-$(CONFIG_MODULES_USE_ELF_RELA) += module-rela.o 36obj-$(CONFIG_MODULES_USE_ELF_RELA) += module-rela.o
@@ -55,7 +56,11 @@ obj-$(CONFIG_MIPS_CMP) += smp-cmp.o
55obj-$(CONFIG_CPU_MIPSR2) += spram.o 56obj-$(CONFIG_CPU_MIPSR2) += spram.o
56 57
57obj-$(CONFIG_MIPS_VPE_LOADER) += vpe.o 58obj-$(CONFIG_MIPS_VPE_LOADER) += vpe.o
59obj-$(CONFIG_MIPS_VPE_LOADER_CMP) += vpe-cmp.o
60obj-$(CONFIG_MIPS_VPE_LOADER_MT) += vpe-mt.o
58obj-$(CONFIG_MIPS_VPE_APSP_API) += rtlx.o 61obj-$(CONFIG_MIPS_VPE_APSP_API) += rtlx.o
62obj-$(CONFIG_MIPS_VPE_APSP_API_CMP) += rtlx-cmp.o
63obj-$(CONFIG_MIPS_VPE_APSP_API_MT) += rtlx-mt.o
59 64
60obj-$(CONFIG_I8259) += i8259.o 65obj-$(CONFIG_I8259) += i8259.o
61obj-$(CONFIG_IRQ_CPU) += irq_cpu.o 66obj-$(CONFIG_IRQ_CPU) += irq_cpu.o
diff --git a/arch/mips/kernel/binfmt_elfo32.c b/arch/mips/kernel/binfmt_elfo32.c
index 202e581e6096..7faf5f2bee25 100644
--- a/arch/mips/kernel/binfmt_elfo32.c
+++ b/arch/mips/kernel/binfmt_elfo32.c
@@ -28,6 +28,18 @@ typedef double elf_fpreg_t;
28typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG]; 28typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG];
29 29
30/* 30/*
31 * In order to be sure that we don't attempt to execute an O32 binary which
32 * requires 64 bit FP (FR=1) on a system which does not support it we refuse
33 * to execute any binary which has bits specified by the following macro set
34 * in its ELF header flags.
35 */
36#ifdef CONFIG_MIPS_O32_FP64_SUPPORT
37# define __MIPS_O32_FP64_MUST_BE_ZERO 0
38#else
39# define __MIPS_O32_FP64_MUST_BE_ZERO EF_MIPS_FP64
40#endif
41
42/*
31 * This is used to ensure we don't load something for the wrong architecture. 43 * This is used to ensure we don't load something for the wrong architecture.
32 */ 44 */
33#define elf_check_arch(hdr) \ 45#define elf_check_arch(hdr) \
@@ -44,6 +56,8 @@ typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG];
44 if (((__h->e_flags & EF_MIPS_ABI) != 0) && \ 56 if (((__h->e_flags & EF_MIPS_ABI) != 0) && \
45 ((__h->e_flags & EF_MIPS_ABI) != EF_MIPS_ABI_O32)) \ 57 ((__h->e_flags & EF_MIPS_ABI) != EF_MIPS_ABI_O32)) \
46 __res = 0; \ 58 __res = 0; \
59 if (__h->e_flags & __MIPS_O32_FP64_MUST_BE_ZERO) \
60 __res = 0; \
47 \ 61 \
48 __res; \ 62 __res; \
49}) 63})
diff --git a/arch/mips/kernel/bmips_vec.S b/arch/mips/kernel/bmips_vec.S
index bd79c4f9bff4..a5bf73d22fcc 100644
--- a/arch/mips/kernel/bmips_vec.S
+++ b/arch/mips/kernel/bmips_vec.S
@@ -8,11 +8,11 @@
8 * Reset/NMI/re-entry vectors for BMIPS processors 8 * Reset/NMI/re-entry vectors for BMIPS processors
9 */ 9 */
10 10
11#include <linux/init.h>
12 11
13#include <asm/asm.h> 12#include <asm/asm.h>
14#include <asm/asmmacro.h> 13#include <asm/asmmacro.h>
15#include <asm/cacheops.h> 14#include <asm/cacheops.h>
15#include <asm/cpu.h>
16#include <asm/regdef.h> 16#include <asm/regdef.h>
17#include <asm/mipsregs.h> 17#include <asm/mipsregs.h>
18#include <asm/stackframe.h> 18#include <asm/stackframe.h>
@@ -91,12 +91,18 @@ NESTED(bmips_reset_nmi_vec, PT_SIZE, sp)
91 beqz k0, bmips_smp_entry 91 beqz k0, bmips_smp_entry
92 92
93#if defined(CONFIG_CPU_BMIPS5000) 93#if defined(CONFIG_CPU_BMIPS5000)
94 mfc0 k0, CP0_PRID
95 li k1, PRID_IMP_BMIPS5000
96 andi k0, 0xff00
97 bne k0, k1, 1f
98
94 /* if we're not on core 0, this must be the SMP boot signal */ 99 /* if we're not on core 0, this must be the SMP boot signal */
95 li k1, (3 << 25) 100 li k1, (3 << 25)
96 mfc0 k0, $22 101 mfc0 k0, $22
97 and k0, k1 102 and k0, k1
98 bnez k0, bmips_smp_entry 103 bnez k0, bmips_smp_entry
99#endif 1041:
105#endif /* CONFIG_CPU_BMIPS5000 */
100#endif /* CONFIG_SMP */ 106#endif /* CONFIG_SMP */
101 107
102 /* nope, it's just a regular NMI */ 108 /* nope, it's just a regular NMI */
@@ -139,7 +145,12 @@ bmips_smp_entry:
139 xori k0, 0x04 145 xori k0, 0x04
140 mtc0 k0, CP0_CONFIG 146 mtc0 k0, CP0_CONFIG
141 147
148 mfc0 k0, CP0_PRID
149 andi k0, 0xff00
142#if defined(CONFIG_CPU_BMIPS4350) || defined(CONFIG_CPU_BMIPS4380) 150#if defined(CONFIG_CPU_BMIPS4350) || defined(CONFIG_CPU_BMIPS4380)
151 li k1, PRID_IMP_BMIPS43XX
152 bne k0, k1, 2f
153
143 /* initialize CPU1's local I-cache */ 154 /* initialize CPU1's local I-cache */
144 li k0, 0x80000000 155 li k0, 0x80000000
145 li k1, 0x80010000 156 li k1, 0x80010000
@@ -150,14 +161,21 @@ bmips_smp_entry:
1501: cache Index_Store_Tag_I, 0(k0) 1611: cache Index_Store_Tag_I, 0(k0)
151 addiu k0, 16 162 addiu k0, 16
152 bne k0, k1, 1b 163 bne k0, k1, 1b
153#elif defined(CONFIG_CPU_BMIPS5000) 164
165 b 3f
1662:
167#endif /* CONFIG_CPU_BMIPS4350 || CONFIG_CPU_BMIPS4380 */
168#if defined(CONFIG_CPU_BMIPS5000)
154 /* set exception vector base */ 169 /* set exception vector base */
170 li k1, PRID_IMP_BMIPS5000
171 bne k0, k1, 3f
172
155 la k0, ebase 173 la k0, ebase
156 lw k0, 0(k0) 174 lw k0, 0(k0)
157 mtc0 k0, $15, 1 175 mtc0 k0, $15, 1
158 BARRIER 176 BARRIER
159#endif 177#endif /* CONFIG_CPU_BMIPS5000 */
160 1783:
161 /* jump back to kseg0 in case we need to remap the kseg1 area */ 179 /* jump back to kseg0 in case we need to remap the kseg1 area */
162 la k0, 1f 180 la k0, 1f
163 jr k0 181 jr k0
@@ -221,8 +239,18 @@ END(bmips_smp_int_vec)
221LEAF(bmips_enable_xks01) 239LEAF(bmips_enable_xks01)
222 240
223#if defined(CONFIG_XKS01) 241#if defined(CONFIG_XKS01)
224 242 mfc0 t0, CP0_PRID
243 andi t2, t0, 0xff00
225#if defined(CONFIG_CPU_BMIPS4380) 244#if defined(CONFIG_CPU_BMIPS4380)
245 li t1, PRID_IMP_BMIPS43XX
246 bne t2, t1, 1f
247
248 andi t0, 0xff
249 addiu t1, t0, -PRID_REV_BMIPS4380_HI
250 bgtz t1, 2f
251 addiu t0, -PRID_REV_BMIPS4380_LO
252 bltz t0, 2f
253
226 mfc0 t0, $22, 3 254 mfc0 t0, $22, 3
227 li t1, 0x1ff0 255 li t1, 0x1ff0
228 li t2, (1 << 12) | (1 << 9) 256 li t2, (1 << 12) | (1 << 9)
@@ -231,7 +259,13 @@ LEAF(bmips_enable_xks01)
231 or t0, t2 259 or t0, t2
232 mtc0 t0, $22, 3 260 mtc0 t0, $22, 3
233 BARRIER 261 BARRIER
234#elif defined(CONFIG_CPU_BMIPS5000) 262 b 2f
2631:
264#endif /* CONFIG_CPU_BMIPS4380 */
265#if defined(CONFIG_CPU_BMIPS5000)
266 li t1, PRID_IMP_BMIPS5000
267 bne t2, t1, 2f
268
235 mfc0 t0, $22, 5 269 mfc0 t0, $22, 5
236 li t1, 0x01ff 270 li t1, 0x01ff
237 li t2, (1 << 8) | (1 << 5) 271 li t2, (1 << 8) | (1 << 5)
@@ -240,12 +274,8 @@ LEAF(bmips_enable_xks01)
240 or t0, t2 274 or t0, t2
241 mtc0 t0, $22, 5 275 mtc0 t0, $22, 5
242 BARRIER 276 BARRIER
243#else 277#endif /* CONFIG_CPU_BMIPS5000 */
244 2782:
245#error Missing XKS01 setup
246
247#endif
248
249#endif /* defined(CONFIG_XKS01) */ 279#endif /* defined(CONFIG_XKS01) */
250 280
251 jr ra 281 jr ra
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index c814287bdf5d..530f832de02c 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -112,7 +112,7 @@ static inline unsigned long cpu_get_fpu_id(void)
112 unsigned long tmp, fpu_id; 112 unsigned long tmp, fpu_id;
113 113
114 tmp = read_c0_status(); 114 tmp = read_c0_status();
115 __enable_fpu(); 115 __enable_fpu(FPU_AS_IS);
116 fpu_id = read_32bit_cp1_register(CP1_REVISION); 116 fpu_id = read_32bit_cp1_register(CP1_REVISION);
117 write_c0_status(tmp); 117 write_c0_status(tmp);
118 return fpu_id; 118 return fpu_id;
@@ -163,6 +163,25 @@ static void set_isa(struct cpuinfo_mips *c, unsigned int isa)
163static char unknown_isa[] = KERN_ERR \ 163static char unknown_isa[] = KERN_ERR \
164 "Unsupported ISA type, c0.config0: %d."; 164 "Unsupported ISA type, c0.config0: %d.";
165 165
166static void set_ftlb_enable(struct cpuinfo_mips *c, int enable)
167{
168 unsigned int config6;
169 /*
170 * Config6 is implementation dependent and it's currently only
171 * used by proAptiv
172 */
173 if (c->cputype == CPU_PROAPTIV) {
174 config6 = read_c0_config6();
175 if (enable)
176 /* Enable FTLB */
177 write_c0_config6(config6 | MIPS_CONF6_FTLBEN);
178 else
179 /* Disable FTLB */
180 write_c0_config6(config6 & ~MIPS_CONF6_FTLBEN);
181 back_to_back_c0_hazard();
182 }
183}
184
166static inline unsigned int decode_config0(struct cpuinfo_mips *c) 185static inline unsigned int decode_config0(struct cpuinfo_mips *c)
167{ 186{
168 unsigned int config0; 187 unsigned int config0;
@@ -170,8 +189,13 @@ static inline unsigned int decode_config0(struct cpuinfo_mips *c)
170 189
171 config0 = read_c0_config(); 190 config0 = read_c0_config();
172 191
173 if (((config0 & MIPS_CONF_MT) >> 7) == 1) 192 /*
193 * Look for Standard TLB or Dual VTLB and FTLB
194 */
195 if ((((config0 & MIPS_CONF_MT) >> 7) == 1) ||
196 (((config0 & MIPS_CONF_MT) >> 7) == 4))
174 c->options |= MIPS_CPU_TLB; 197 c->options |= MIPS_CPU_TLB;
198
175 isa = (config0 & MIPS_CONF_AT) >> 13; 199 isa = (config0 & MIPS_CONF_AT) >> 13;
176 switch (isa) { 200 switch (isa) {
177 case 0: 201 case 0:
@@ -226,8 +250,11 @@ static inline unsigned int decode_config1(struct cpuinfo_mips *c)
226 c->options |= MIPS_CPU_FPU; 250 c->options |= MIPS_CPU_FPU;
227 c->options |= MIPS_CPU_32FPR; 251 c->options |= MIPS_CPU_32FPR;
228 } 252 }
229 if (cpu_has_tlb) 253 if (cpu_has_tlb) {
230 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1; 254 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
255 c->tlbsizevtlb = c->tlbsize;
256 c->tlbsizeftlbsets = 0;
257 }
231 258
232 return config1 & MIPS_CONF_M; 259 return config1 & MIPS_CONF_M;
233} 260}
@@ -272,6 +299,8 @@ static inline unsigned int decode_config3(struct cpuinfo_mips *c)
272 c->options |= MIPS_CPU_MICROMIPS; 299 c->options |= MIPS_CPU_MICROMIPS;
273 if (config3 & MIPS_CONF3_VZ) 300 if (config3 & MIPS_CONF3_VZ)
274 c->ases |= MIPS_ASE_VZ; 301 c->ases |= MIPS_ASE_VZ;
302 if (config3 & MIPS_CONF3_SC)
303 c->options |= MIPS_CPU_SEGMENTS;
275 304
276 return config3 & MIPS_CONF_M; 305 return config3 & MIPS_CONF_M;
277} 306}
@@ -279,12 +308,51 @@ static inline unsigned int decode_config3(struct cpuinfo_mips *c)
279static inline unsigned int decode_config4(struct cpuinfo_mips *c) 308static inline unsigned int decode_config4(struct cpuinfo_mips *c)
280{ 309{
281 unsigned int config4; 310 unsigned int config4;
311 unsigned int newcf4;
312 unsigned int mmuextdef;
313 unsigned int ftlb_page = MIPS_CONF4_FTLBPAGESIZE;
282 314
283 config4 = read_c0_config4(); 315 config4 = read_c0_config4();
284 316
285 if ((config4 & MIPS_CONF4_MMUEXTDEF) == MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT 317 if (cpu_has_tlb) {
286 && cpu_has_tlb) 318 if (((config4 & MIPS_CONF4_IE) >> 29) == 2)
287 c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40; 319 c->options |= MIPS_CPU_TLBINV;
320 mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF;
321 switch (mmuextdef) {
322 case MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT:
323 c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40;
324 c->tlbsizevtlb = c->tlbsize;
325 break;
326 case MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT:
327 c->tlbsizevtlb +=
328 ((config4 & MIPS_CONF4_VTLBSIZEEXT) >>
329 MIPS_CONF4_VTLBSIZEEXT_SHIFT) * 0x40;
330 c->tlbsize = c->tlbsizevtlb;
331 ftlb_page = MIPS_CONF4_VFTLBPAGESIZE;
332 /* fall through */
333 case MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT:
334 newcf4 = (config4 & ~ftlb_page) |
335 (page_size_ftlb(mmuextdef) <<
336 MIPS_CONF4_FTLBPAGESIZE_SHIFT);
337 write_c0_config4(newcf4);
338 back_to_back_c0_hazard();
339 config4 = read_c0_config4();
340 if (config4 != newcf4) {
341 pr_err("PAGE_SIZE 0x%lx is not supported by FTLB (config4=0x%x)\n",
342 PAGE_SIZE, config4);
343 /* Switch FTLB off */
344 set_ftlb_enable(c, 0);
345 break;
346 }
347 c->tlbsizeftlbsets = 1 <<
348 ((config4 & MIPS_CONF4_FTLBSETS) >>
349 MIPS_CONF4_FTLBSETS_SHIFT);
350 c->tlbsizeftlbways = ((config4 & MIPS_CONF4_FTLBWAYS) >>
351 MIPS_CONF4_FTLBWAYS_SHIFT) + 2;
352 c->tlbsize += c->tlbsizeftlbways * c->tlbsizeftlbsets;
353 break;
354 }
355 }
288 356
289 c->kscratch_mask = (config4 >> 16) & 0xff; 357 c->kscratch_mask = (config4 >> 16) & 0xff;
290 358
@@ -312,6 +380,9 @@ static void decode_configs(struct cpuinfo_mips *c)
312 380
313 c->scache.flags = MIPS_CACHE_NOT_PRESENT; 381 c->scache.flags = MIPS_CACHE_NOT_PRESENT;
314 382
383 /* Enable FTLB if present */
384 set_ftlb_enable(c, 1);
385
315 ok = decode_config0(c); /* Read Config registers. */ 386 ok = decode_config0(c); /* Read Config registers. */
316 BUG_ON(!ok); /* Arch spec violation! */ 387 BUG_ON(!ok); /* Arch spec violation! */
317 if (ok) 388 if (ok)
@@ -675,7 +746,6 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
675 746
676static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu) 747static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
677{ 748{
678 decode_configs(c);
679 switch (c->processor_id & PRID_IMP_MASK) { 749 switch (c->processor_id & PRID_IMP_MASK) {
680 case PRID_IMP_4KC: 750 case PRID_IMP_4KC:
681 c->cputype = CPU_4KC; 751 c->cputype = CPU_4KC;
@@ -739,8 +809,26 @@ static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
739 c->cputype = CPU_74K; 809 c->cputype = CPU_74K;
740 __cpu_name[cpu] = "MIPS 1074Kc"; 810 __cpu_name[cpu] = "MIPS 1074Kc";
741 break; 811 break;
812 case PRID_IMP_INTERAPTIV_UP:
813 c->cputype = CPU_INTERAPTIV;
814 __cpu_name[cpu] = "MIPS interAptiv";
815 break;
816 case PRID_IMP_INTERAPTIV_MP:
817 c->cputype = CPU_INTERAPTIV;
818 __cpu_name[cpu] = "MIPS interAptiv (multi)";
819 break;
820 case PRID_IMP_PROAPTIV_UP:
821 c->cputype = CPU_PROAPTIV;
822 __cpu_name[cpu] = "MIPS proAptiv";
823 break;
824 case PRID_IMP_PROAPTIV_MP:
825 c->cputype = CPU_PROAPTIV;
826 __cpu_name[cpu] = "MIPS proAptiv (multi)";
827 break;
742 } 828 }
743 829
830 decode_configs(c);
831
744 spram_config(); 832 spram_config();
745} 833}
746 834
@@ -943,6 +1031,7 @@ static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu)
943 1031
944 switch (c->processor_id & PRID_IMP_MASK) { 1032 switch (c->processor_id & PRID_IMP_MASK) {
945 case PRID_IMP_NETLOGIC_XLP2XX: 1033 case PRID_IMP_NETLOGIC_XLP2XX:
1034 case PRID_IMP_NETLOGIC_XLP9XX:
946 c->cputype = CPU_XLP; 1035 c->cputype = CPU_XLP;
947 __cpu_name[cpu] = "Broadcom XLPII"; 1036 __cpu_name[cpu] = "Broadcom XLPII";
948 break; 1037 break;
diff --git a/arch/mips/kernel/crash.c b/arch/mips/kernel/crash.c
index 93aa302948d7..d21264681e97 100644
--- a/arch/mips/kernel/crash.c
+++ b/arch/mips/kernel/crash.c
@@ -5,7 +5,6 @@
5#include <linux/bootmem.h> 5#include <linux/bootmem.h>
6#include <linux/crash_dump.h> 6#include <linux/crash_dump.h>
7#include <linux/delay.h> 7#include <linux/delay.h>
8#include <linux/init.h>
9#include <linux/irq.h> 8#include <linux/irq.h>
10#include <linux/types.h> 9#include <linux/types.h>
11#include <linux/sched.h> 10#include <linux/sched.h>
diff --git a/arch/mips/kernel/genex.S b/arch/mips/kernel/genex.S
index 47d7583cd67f..d84f6a509502 100644
--- a/arch/mips/kernel/genex.S
+++ b/arch/mips/kernel/genex.S
@@ -476,6 +476,7 @@ NESTED(nmi_handler, PT_SIZE, sp)
476 BUILD_HANDLER ov ov sti silent /* #12 */ 476 BUILD_HANDLER ov ov sti silent /* #12 */
477 BUILD_HANDLER tr tr sti silent /* #13 */ 477 BUILD_HANDLER tr tr sti silent /* #13 */
478 BUILD_HANDLER fpe fpe fpe silent /* #15 */ 478 BUILD_HANDLER fpe fpe fpe silent /* #15 */
479 BUILD_HANDLER ftlb ftlb none silent /* #16 */
479 BUILD_HANDLER mdmx mdmx sti silent /* #22 */ 480 BUILD_HANDLER mdmx mdmx sti silent /* #22 */
480#ifdef CONFIG_HARDWARE_WATCHPOINTS 481#ifdef CONFIG_HARDWARE_WATCHPOINTS
481 /* 482 /*
diff --git a/arch/mips/kernel/idle.c b/arch/mips/kernel/idle.c
index f7991d95bff9..3553243bf9d6 100644
--- a/arch/mips/kernel/idle.c
+++ b/arch/mips/kernel/idle.c
@@ -184,6 +184,8 @@ void __init check_wait(void)
184 case CPU_24K: 184 case CPU_24K:
185 case CPU_34K: 185 case CPU_34K:
186 case CPU_1004K: 186 case CPU_1004K:
187 case CPU_INTERAPTIV:
188 case CPU_PROAPTIV:
187 cpu_wait = r4k_wait; 189 cpu_wait = r4k_wait;
188 if (read_c0_config7() & MIPS_CONF7_WII) 190 if (read_c0_config7() & MIPS_CONF7_WII)
189 cpu_wait = r4k_wait_irqoff; 191 cpu_wait = r4k_wait_irqoff;
diff --git a/arch/mips/kernel/proc.c b/arch/mips/kernel/proc.c
index 8c58d8a84bf3..00d20974b3e7 100644
--- a/arch/mips/kernel/proc.c
+++ b/arch/mips/kernel/proc.c
@@ -65,26 +65,25 @@ static int show_cpuinfo(struct seq_file *m, void *v)
65 cpu_data[n].watch_reg_masks[i]); 65 cpu_data[n].watch_reg_masks[i]);
66 seq_printf(m, "]\n"); 66 seq_printf(m, "]\n");
67 } 67 }
68 if (cpu_has_mips_r) { 68
69 seq_printf(m, "isa\t\t\t: mips1"); 69 seq_printf(m, "isa\t\t\t: mips1");
70 if (cpu_has_mips_2) 70 if (cpu_has_mips_2)
71 seq_printf(m, "%s", " mips2"); 71 seq_printf(m, "%s", " mips2");
72 if (cpu_has_mips_3) 72 if (cpu_has_mips_3)
73 seq_printf(m, "%s", " mips3"); 73 seq_printf(m, "%s", " mips3");
74 if (cpu_has_mips_4) 74 if (cpu_has_mips_4)
75 seq_printf(m, "%s", " mips4"); 75 seq_printf(m, "%s", " mips4");
76 if (cpu_has_mips_5) 76 if (cpu_has_mips_5)
77 seq_printf(m, "%s", " mips5"); 77 seq_printf(m, "%s", " mips5");
78 if (cpu_has_mips32r1) 78 if (cpu_has_mips32r1)
79 seq_printf(m, "%s", " mips32r1"); 79 seq_printf(m, "%s", " mips32r1");
80 if (cpu_has_mips32r2) 80 if (cpu_has_mips32r2)
81 seq_printf(m, "%s", " mips32r2"); 81 seq_printf(m, "%s", " mips32r2");
82 if (cpu_has_mips64r1) 82 if (cpu_has_mips64r1)
83 seq_printf(m, "%s", " mips64r1"); 83 seq_printf(m, "%s", " mips64r1");
84 if (cpu_has_mips64r2) 84 if (cpu_has_mips64r2)
85 seq_printf(m, "%s", " mips64r2"); 85 seq_printf(m, "%s", " mips64r2");
86 seq_printf(m, "\n"); 86 seq_printf(m, "\n");
87 }
88 87
89 seq_printf(m, "ASEs implemented\t:"); 88 seq_printf(m, "ASEs implemented\t:");
90 if (cpu_has_mips16) seq_printf(m, "%s", " mips16"); 89 if (cpu_has_mips16) seq_printf(m, "%s", " mips16");
@@ -107,7 +106,14 @@ static int show_cpuinfo(struct seq_file *m, void *v)
107 seq_printf(m, "kscratch registers\t: %d\n", 106 seq_printf(m, "kscratch registers\t: %d\n",
108 hweight8(cpu_data[n].kscratch_mask)); 107 hweight8(cpu_data[n].kscratch_mask));
109 seq_printf(m, "core\t\t\t: %d\n", cpu_data[n].core); 108 seq_printf(m, "core\t\t\t: %d\n", cpu_data[n].core);
110 109#if defined(CONFIG_MIPS_MT_SMP) || defined(CONFIG_MIPS_MT_SMTC)
110 if (cpu_has_mipsmt) {
111 seq_printf(m, "VPE\t\t\t: %d\n", cpu_data[n].vpe_id);
112#if defined(CONFIG_MIPS_MT_SMTC)
113 seq_printf(m, "TC\t\t\t: %d\n", cpu_data[n].tc_id);
114#endif
115 }
116#endif
111 sprintf(fmt, "VCE%%c exceptions\t\t: %s\n", 117 sprintf(fmt, "VCE%%c exceptions\t\t: %s\n",
112 cpu_has_vce ? "%u" : "not available"); 118 cpu_has_vce ? "%u" : "not available");
113 seq_printf(m, fmt, 'D', vced_count); 119 seq_printf(m, fmt, 'D', vced_count);
diff --git a/arch/mips/kernel/process.c b/arch/mips/kernel/process.c
index ddc76103e78c..6ae540e133b2 100644
--- a/arch/mips/kernel/process.c
+++ b/arch/mips/kernel/process.c
@@ -60,15 +60,11 @@ void start_thread(struct pt_regs * regs, unsigned long pc, unsigned long sp)
60 60
61 /* New thread loses kernel privileges. */ 61 /* New thread loses kernel privileges. */
62 status = regs->cp0_status & ~(ST0_CU0|ST0_CU1|ST0_FR|KU_MASK); 62 status = regs->cp0_status & ~(ST0_CU0|ST0_CU1|ST0_FR|KU_MASK);
63#ifdef CONFIG_64BIT
64 status |= test_thread_flag(TIF_32BIT_REGS) ? 0 : ST0_FR;
65#endif
66 status |= KU_USER; 63 status |= KU_USER;
67 regs->cp0_status = status; 64 regs->cp0_status = status;
68 clear_used_math(); 65 clear_used_math();
69 clear_fpu_owner(); 66 clear_fpu_owner();
70 if (cpu_has_dsp) 67 init_dsp();
71 __init_dsp();
72 regs->cp0_epc = pc; 68 regs->cp0_epc = pc;
73 regs->regs[29] = sp; 69 regs->regs[29] = sp;
74} 70}
diff --git a/arch/mips/kernel/ptrace.c b/arch/mips/kernel/ptrace.c
index b52e1d2b33e0..7da9b76db4d9 100644
--- a/arch/mips/kernel/ptrace.c
+++ b/arch/mips/kernel/ptrace.c
@@ -137,13 +137,13 @@ int ptrace_getfpregs(struct task_struct *child, __u32 __user *data)
137 if (cpu_has_mipsmt) { 137 if (cpu_has_mipsmt) {
138 unsigned int vpflags = dvpe(); 138 unsigned int vpflags = dvpe();
139 flags = read_c0_status(); 139 flags = read_c0_status();
140 __enable_fpu(); 140 __enable_fpu(FPU_AS_IS);
141 __asm__ __volatile__("cfc1\t%0,$0" : "=r" (tmp)); 141 __asm__ __volatile__("cfc1\t%0,$0" : "=r" (tmp));
142 write_c0_status(flags); 142 write_c0_status(flags);
143 evpe(vpflags); 143 evpe(vpflags);
144 } else { 144 } else {
145 flags = read_c0_status(); 145 flags = read_c0_status();
146 __enable_fpu(); 146 __enable_fpu(FPU_AS_IS);
147 __asm__ __volatile__("cfc1\t%0,$0" : "=r" (tmp)); 147 __asm__ __volatile__("cfc1\t%0,$0" : "=r" (tmp));
148 write_c0_status(flags); 148 write_c0_status(flags);
149 } 149 }
@@ -408,6 +408,7 @@ long arch_ptrace(struct task_struct *child, long request,
408 /* Read the word at location addr in the USER area. */ 408 /* Read the word at location addr in the USER area. */
409 case PTRACE_PEEKUSR: { 409 case PTRACE_PEEKUSR: {
410 struct pt_regs *regs; 410 struct pt_regs *regs;
411 fpureg_t *fregs;
411 unsigned long tmp = 0; 412 unsigned long tmp = 0;
412 413
413 regs = task_pt_regs(child); 414 regs = task_pt_regs(child);
@@ -418,26 +419,28 @@ long arch_ptrace(struct task_struct *child, long request,
418 tmp = regs->regs[addr]; 419 tmp = regs->regs[addr];
419 break; 420 break;
420 case FPR_BASE ... FPR_BASE + 31: 421 case FPR_BASE ... FPR_BASE + 31:
421 if (tsk_used_math(child)) { 422 if (!tsk_used_math(child)) {
422 fpureg_t *fregs = get_fpu_regs(child); 423 /* FP not yet used */
424 tmp = -1;
425 break;
426 }
427 fregs = get_fpu_regs(child);
423 428
424#ifdef CONFIG_32BIT 429#ifdef CONFIG_32BIT
430 if (test_thread_flag(TIF_32BIT_FPREGS)) {
425 /* 431 /*
426 * The odd registers are actually the high 432 * The odd registers are actually the high
427 * order bits of the values stored in the even 433 * order bits of the values stored in the even
428 * registers - unless we're using r2k_switch.S. 434 * registers - unless we're using r2k_switch.S.
429 */ 435 */
430 if (addr & 1) 436 if (addr & 1)
431 tmp = (unsigned long) (fregs[((addr & ~1) - 32)] >> 32); 437 tmp = fregs[(addr & ~1) - 32] >> 32;
432 else 438 else
433 tmp = (unsigned long) (fregs[(addr - 32)] & 0xffffffff); 439 tmp = fregs[addr - 32];
434#endif 440 break;
435#ifdef CONFIG_64BIT
436 tmp = fregs[addr - FPR_BASE];
437#endif
438 } else {
439 tmp = -1; /* FP not yet used */
440 } 441 }
442#endif
443 tmp = fregs[addr - FPR_BASE];
441 break; 444 break;
442 case PC: 445 case PC:
443 tmp = regs->cp0_epc; 446 tmp = regs->cp0_epc;
@@ -483,13 +486,13 @@ long arch_ptrace(struct task_struct *child, long request,
483 if (cpu_has_mipsmt) { 486 if (cpu_has_mipsmt) {
484 unsigned int vpflags = dvpe(); 487 unsigned int vpflags = dvpe();
485 flags = read_c0_status(); 488 flags = read_c0_status();
486 __enable_fpu(); 489 __enable_fpu(FPU_AS_IS);
487 __asm__ __volatile__("cfc1\t%0,$0": "=r" (tmp)); 490 __asm__ __volatile__("cfc1\t%0,$0": "=r" (tmp));
488 write_c0_status(flags); 491 write_c0_status(flags);
489 evpe(vpflags); 492 evpe(vpflags);
490 } else { 493 } else {
491 flags = read_c0_status(); 494 flags = read_c0_status();
492 __enable_fpu(); 495 __enable_fpu(FPU_AS_IS);
493 __asm__ __volatile__("cfc1\t%0,$0": "=r" (tmp)); 496 __asm__ __volatile__("cfc1\t%0,$0": "=r" (tmp));
494 write_c0_status(flags); 497 write_c0_status(flags);
495 } 498 }
@@ -554,22 +557,25 @@ long arch_ptrace(struct task_struct *child, long request,
554 child->thread.fpu.fcr31 = 0; 557 child->thread.fpu.fcr31 = 0;
555 } 558 }
556#ifdef CONFIG_32BIT 559#ifdef CONFIG_32BIT
557 /* 560 if (test_thread_flag(TIF_32BIT_FPREGS)) {
558 * The odd registers are actually the high order bits 561 /*
559 * of the values stored in the even registers - unless 562 * The odd registers are actually the high
560 * we're using r2k_switch.S. 563 * order bits of the values stored in the even
561 */ 564 * registers - unless we're using r2k_switch.S.
562 if (addr & 1) { 565 */
563 fregs[(addr & ~1) - FPR_BASE] &= 0xffffffff; 566 if (addr & 1) {
564 fregs[(addr & ~1) - FPR_BASE] |= ((unsigned long long) data) << 32; 567 fregs[(addr & ~1) - FPR_BASE] &=
565 } else { 568 0xffffffff;
566 fregs[addr - FPR_BASE] &= ~0xffffffffLL; 569 fregs[(addr & ~1) - FPR_BASE] |=
567 fregs[addr - FPR_BASE] |= data; 570 ((u64)data) << 32;
571 } else {
572 fregs[addr - FPR_BASE] &= ~0xffffffffLL;
573 fregs[addr - FPR_BASE] |= data;
574 }
575 break;
568 } 576 }
569#endif 577#endif
570#ifdef CONFIG_64BIT
571 fregs[addr - FPR_BASE] = data; 578 fregs[addr - FPR_BASE] = data;
572#endif
573 break; 579 break;
574 } 580 }
575 case PC: 581 case PC:
diff --git a/arch/mips/kernel/ptrace32.c b/arch/mips/kernel/ptrace32.c
index 9486055ba660..b8aa2dd5b00b 100644
--- a/arch/mips/kernel/ptrace32.c
+++ b/arch/mips/kernel/ptrace32.c
@@ -80,6 +80,7 @@ long compat_arch_ptrace(struct task_struct *child, compat_long_t request,
80 /* Read the word at location addr in the USER area. */ 80 /* Read the word at location addr in the USER area. */
81 case PTRACE_PEEKUSR: { 81 case PTRACE_PEEKUSR: {
82 struct pt_regs *regs; 82 struct pt_regs *regs;
83 fpureg_t *fregs;
83 unsigned int tmp; 84 unsigned int tmp;
84 85
85 regs = task_pt_regs(child); 86 regs = task_pt_regs(child);
@@ -90,21 +91,25 @@ long compat_arch_ptrace(struct task_struct *child, compat_long_t request,
90 tmp = regs->regs[addr]; 91 tmp = regs->regs[addr];
91 break; 92 break;
92 case FPR_BASE ... FPR_BASE + 31: 93 case FPR_BASE ... FPR_BASE + 31:
93 if (tsk_used_math(child)) { 94 if (!tsk_used_math(child)) {
94 fpureg_t *fregs = get_fpu_regs(child); 95 /* FP not yet used */
95 96 tmp = -1;
97 break;
98 }
99 fregs = get_fpu_regs(child);
100 if (test_thread_flag(TIF_32BIT_FPREGS)) {
96 /* 101 /*
97 * The odd registers are actually the high 102 * The odd registers are actually the high
98 * order bits of the values stored in the even 103 * order bits of the values stored in the even
99 * registers - unless we're using r2k_switch.S. 104 * registers - unless we're using r2k_switch.S.
100 */ 105 */
101 if (addr & 1) 106 if (addr & 1)
102 tmp = (unsigned long) (fregs[((addr & ~1) - 32)] >> 32); 107 tmp = fregs[(addr & ~1) - 32] >> 32;
103 else 108 else
104 tmp = (unsigned long) (fregs[(addr - 32)] & 0xffffffff); 109 tmp = fregs[addr - 32];
105 } else { 110 break;
106 tmp = -1; /* FP not yet used */
107 } 111 }
112 tmp = fregs[addr - FPR_BASE];
108 break; 113 break;
109 case PC: 114 case PC:
110 tmp = regs->cp0_epc; 115 tmp = regs->cp0_epc;
@@ -147,13 +152,13 @@ long compat_arch_ptrace(struct task_struct *child, compat_long_t request,
147 if (cpu_has_mipsmt) { 152 if (cpu_has_mipsmt) {
148 unsigned int vpflags = dvpe(); 153 unsigned int vpflags = dvpe();
149 flags = read_c0_status(); 154 flags = read_c0_status();
150 __enable_fpu(); 155 __enable_fpu(FPU_AS_IS);
151 __asm__ __volatile__("cfc1\t%0,$0": "=r" (tmp)); 156 __asm__ __volatile__("cfc1\t%0,$0": "=r" (tmp));
152 write_c0_status(flags); 157 write_c0_status(flags);
153 evpe(vpflags); 158 evpe(vpflags);
154 } else { 159 } else {
155 flags = read_c0_status(); 160 flags = read_c0_status();
156 __enable_fpu(); 161 __enable_fpu(FPU_AS_IS);
157 __asm__ __volatile__("cfc1\t%0,$0": "=r" (tmp)); 162 __asm__ __volatile__("cfc1\t%0,$0": "=r" (tmp));
158 write_c0_status(flags); 163 write_c0_status(flags);
159 } 164 }
@@ -236,20 +241,24 @@ long compat_arch_ptrace(struct task_struct *child, compat_long_t request,
236 sizeof(child->thread.fpu)); 241 sizeof(child->thread.fpu));
237 child->thread.fpu.fcr31 = 0; 242 child->thread.fpu.fcr31 = 0;
238 } 243 }
239 /* 244 if (test_thread_flag(TIF_32BIT_FPREGS)) {
240 * The odd registers are actually the high order bits 245 /*
241 * of the values stored in the even registers - unless 246 * The odd registers are actually the high
242 * we're using r2k_switch.S. 247 * order bits of the values stored in the even
243 */ 248 * registers - unless we're using r2k_switch.S.
244 if (addr & 1) { 249 */
245 fregs[(addr & ~1) - FPR_BASE] &= 0xffffffff; 250 if (addr & 1) {
246 fregs[(addr & ~1) - FPR_BASE] |= ((unsigned long long) data) << 32; 251 fregs[(addr & ~1) - FPR_BASE] &=
247 } else { 252 0xffffffff;
248 fregs[addr - FPR_BASE] &= ~0xffffffffLL; 253 fregs[(addr & ~1) - FPR_BASE] |=
249 /* Must cast, lest sign extension fill upper 254 ((u64)data) << 32;
250 bits! */ 255 } else {
251 fregs[addr - FPR_BASE] |= (unsigned int)data; 256 fregs[addr - FPR_BASE] &= ~0xffffffffLL;
257 fregs[addr - FPR_BASE] |= data;
258 }
259 break;
252 } 260 }
261 fregs[addr - FPR_BASE] = data;
253 break; 262 break;
254 } 263 }
255 case PC: 264 case PC:
diff --git a/arch/mips/kernel/r4k_fpu.S b/arch/mips/kernel/r4k_fpu.S
index 55ffe149dae9..253b2fb52026 100644
--- a/arch/mips/kernel/r4k_fpu.S
+++ b/arch/mips/kernel/r4k_fpu.S
@@ -35,7 +35,15 @@
35LEAF(_save_fp_context) 35LEAF(_save_fp_context)
36 cfc1 t1, fcr31 36 cfc1 t1, fcr31
37 37
38#ifdef CONFIG_64BIT 38#if defined(CONFIG_64BIT) || defined(CONFIG_MIPS32_R2)
39 .set push
40#ifdef CONFIG_MIPS32_R2
41 .set mips64r2
42 mfc0 t0, CP0_STATUS
43 sll t0, t0, 5
44 bgez t0, 1f # skip storing odd if FR=0
45 nop
46#endif
39 /* Store the 16 odd double precision registers */ 47 /* Store the 16 odd double precision registers */
40 EX sdc1 $f1, SC_FPREGS+8(a0) 48 EX sdc1 $f1, SC_FPREGS+8(a0)
41 EX sdc1 $f3, SC_FPREGS+24(a0) 49 EX sdc1 $f3, SC_FPREGS+24(a0)
@@ -53,6 +61,7 @@ LEAF(_save_fp_context)
53 EX sdc1 $f27, SC_FPREGS+216(a0) 61 EX sdc1 $f27, SC_FPREGS+216(a0)
54 EX sdc1 $f29, SC_FPREGS+232(a0) 62 EX sdc1 $f29, SC_FPREGS+232(a0)
55 EX sdc1 $f31, SC_FPREGS+248(a0) 63 EX sdc1 $f31, SC_FPREGS+248(a0)
641: .set pop
56#endif 65#endif
57 66
58 /* Store the 16 even double precision registers */ 67 /* Store the 16 even double precision registers */
@@ -82,7 +91,31 @@ LEAF(_save_fp_context)
82LEAF(_save_fp_context32) 91LEAF(_save_fp_context32)
83 cfc1 t1, fcr31 92 cfc1 t1, fcr31
84 93
85 EX sdc1 $f0, SC32_FPREGS+0(a0) 94 mfc0 t0, CP0_STATUS
95 sll t0, t0, 5
96 bgez t0, 1f # skip storing odd if FR=0
97 nop
98
99 /* Store the 16 odd double precision registers */
100 EX sdc1 $f1, SC32_FPREGS+8(a0)
101 EX sdc1 $f3, SC32_FPREGS+24(a0)
102 EX sdc1 $f5, SC32_FPREGS+40(a0)
103 EX sdc1 $f7, SC32_FPREGS+56(a0)
104 EX sdc1 $f9, SC32_FPREGS+72(a0)
105 EX sdc1 $f11, SC32_FPREGS+88(a0)
106 EX sdc1 $f13, SC32_FPREGS+104(a0)
107 EX sdc1 $f15, SC32_FPREGS+120(a0)
108 EX sdc1 $f17, SC32_FPREGS+136(a0)
109 EX sdc1 $f19, SC32_FPREGS+152(a0)
110 EX sdc1 $f21, SC32_FPREGS+168(a0)
111 EX sdc1 $f23, SC32_FPREGS+184(a0)
112 EX sdc1 $f25, SC32_FPREGS+200(a0)
113 EX sdc1 $f27, SC32_FPREGS+216(a0)
114 EX sdc1 $f29, SC32_FPREGS+232(a0)
115 EX sdc1 $f31, SC32_FPREGS+248(a0)
116
117 /* Store the 16 even double precision registers */
1181: EX sdc1 $f0, SC32_FPREGS+0(a0)
86 EX sdc1 $f2, SC32_FPREGS+16(a0) 119 EX sdc1 $f2, SC32_FPREGS+16(a0)
87 EX sdc1 $f4, SC32_FPREGS+32(a0) 120 EX sdc1 $f4, SC32_FPREGS+32(a0)
88 EX sdc1 $f6, SC32_FPREGS+48(a0) 121 EX sdc1 $f6, SC32_FPREGS+48(a0)
@@ -114,7 +147,16 @@ LEAF(_save_fp_context32)
114 */ 147 */
115LEAF(_restore_fp_context) 148LEAF(_restore_fp_context)
116 EX lw t0, SC_FPC_CSR(a0) 149 EX lw t0, SC_FPC_CSR(a0)
117#ifdef CONFIG_64BIT 150
151#if defined(CONFIG_64BIT) || defined(CONFIG_MIPS32_R2)
152 .set push
153#ifdef CONFIG_MIPS32_R2
154 .set mips64r2
155 mfc0 t0, CP0_STATUS
156 sll t0, t0, 5
157 bgez t0, 1f # skip loading odd if FR=0
158 nop
159#endif
118 EX ldc1 $f1, SC_FPREGS+8(a0) 160 EX ldc1 $f1, SC_FPREGS+8(a0)
119 EX ldc1 $f3, SC_FPREGS+24(a0) 161 EX ldc1 $f3, SC_FPREGS+24(a0)
120 EX ldc1 $f5, SC_FPREGS+40(a0) 162 EX ldc1 $f5, SC_FPREGS+40(a0)
@@ -131,6 +173,7 @@ LEAF(_restore_fp_context)
131 EX ldc1 $f27, SC_FPREGS+216(a0) 173 EX ldc1 $f27, SC_FPREGS+216(a0)
132 EX ldc1 $f29, SC_FPREGS+232(a0) 174 EX ldc1 $f29, SC_FPREGS+232(a0)
133 EX ldc1 $f31, SC_FPREGS+248(a0) 175 EX ldc1 $f31, SC_FPREGS+248(a0)
1761: .set pop
134#endif 177#endif
135 EX ldc1 $f0, SC_FPREGS+0(a0) 178 EX ldc1 $f0, SC_FPREGS+0(a0)
136 EX ldc1 $f2, SC_FPREGS+16(a0) 179 EX ldc1 $f2, SC_FPREGS+16(a0)
@@ -157,7 +200,30 @@ LEAF(_restore_fp_context)
157LEAF(_restore_fp_context32) 200LEAF(_restore_fp_context32)
158 /* Restore an o32 sigcontext. */ 201 /* Restore an o32 sigcontext. */
159 EX lw t0, SC32_FPC_CSR(a0) 202 EX lw t0, SC32_FPC_CSR(a0)
160 EX ldc1 $f0, SC32_FPREGS+0(a0) 203
204 mfc0 t0, CP0_STATUS
205 sll t0, t0, 5
206 bgez t0, 1f # skip loading odd if FR=0
207 nop
208
209 EX ldc1 $f1, SC32_FPREGS+8(a0)
210 EX ldc1 $f3, SC32_FPREGS+24(a0)
211 EX ldc1 $f5, SC32_FPREGS+40(a0)
212 EX ldc1 $f7, SC32_FPREGS+56(a0)
213 EX ldc1 $f9, SC32_FPREGS+72(a0)
214 EX ldc1 $f11, SC32_FPREGS+88(a0)
215 EX ldc1 $f13, SC32_FPREGS+104(a0)
216 EX ldc1 $f15, SC32_FPREGS+120(a0)
217 EX ldc1 $f17, SC32_FPREGS+136(a0)
218 EX ldc1 $f19, SC32_FPREGS+152(a0)
219 EX ldc1 $f21, SC32_FPREGS+168(a0)
220 EX ldc1 $f23, SC32_FPREGS+184(a0)
221 EX ldc1 $f25, SC32_FPREGS+200(a0)
222 EX ldc1 $f27, SC32_FPREGS+216(a0)
223 EX ldc1 $f29, SC32_FPREGS+232(a0)
224 EX ldc1 $f31, SC32_FPREGS+248(a0)
225
2261: EX ldc1 $f0, SC32_FPREGS+0(a0)
161 EX ldc1 $f2, SC32_FPREGS+16(a0) 227 EX ldc1 $f2, SC32_FPREGS+16(a0)
162 EX ldc1 $f4, SC32_FPREGS+32(a0) 228 EX ldc1 $f4, SC32_FPREGS+32(a0)
163 EX ldc1 $f6, SC32_FPREGS+48(a0) 229 EX ldc1 $f6, SC32_FPREGS+48(a0)
diff --git a/arch/mips/kernel/r4k_switch.S b/arch/mips/kernel/r4k_switch.S
index 078de5eaca8f..cc78dd9a17c7 100644
--- a/arch/mips/kernel/r4k_switch.S
+++ b/arch/mips/kernel/r4k_switch.S
@@ -123,7 +123,7 @@
123 * Save a thread's fp context. 123 * Save a thread's fp context.
124 */ 124 */
125LEAF(_save_fp) 125LEAF(_save_fp)
126#ifdef CONFIG_64BIT 126#if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2)
127 mfc0 t0, CP0_STATUS 127 mfc0 t0, CP0_STATUS
128#endif 128#endif
129 fpu_save_double a0 t0 t1 # clobbers t1 129 fpu_save_double a0 t0 t1 # clobbers t1
@@ -134,7 +134,7 @@ LEAF(_save_fp)
134 * Restore a thread's fp context. 134 * Restore a thread's fp context.
135 */ 135 */
136LEAF(_restore_fp) 136LEAF(_restore_fp)
137#ifdef CONFIG_64BIT 137#if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2)
138 mfc0 t0, CP0_STATUS 138 mfc0 t0, CP0_STATUS
139#endif 139#endif
140 fpu_restore_double a0 t0 t1 # clobbers t1 140 fpu_restore_double a0 t0 t1 # clobbers t1
@@ -228,6 +228,47 @@ LEAF(_init_fpu)
228 mtc1 t1, $f29 228 mtc1 t1, $f29
229 mtc1 t1, $f30 229 mtc1 t1, $f30
230 mtc1 t1, $f31 230 mtc1 t1, $f31
231
232#ifdef CONFIG_CPU_MIPS32_R2
233 .set push
234 .set mips64r2
235 sll t0, t0, 5 # is Status.FR set?
236 bgez t0, 1f # no: skip setting upper 32b
237
238 mthc1 t1, $f0
239 mthc1 t1, $f1
240 mthc1 t1, $f2
241 mthc1 t1, $f3
242 mthc1 t1, $f4
243 mthc1 t1, $f5
244 mthc1 t1, $f6
245 mthc1 t1, $f7
246 mthc1 t1, $f8
247 mthc1 t1, $f9
248 mthc1 t1, $f10
249 mthc1 t1, $f11
250 mthc1 t1, $f12
251 mthc1 t1, $f13
252 mthc1 t1, $f14
253 mthc1 t1, $f15
254 mthc1 t1, $f16
255 mthc1 t1, $f17
256 mthc1 t1, $f18
257 mthc1 t1, $f19
258 mthc1 t1, $f20
259 mthc1 t1, $f21
260 mthc1 t1, $f22
261 mthc1 t1, $f23
262 mthc1 t1, $f24
263 mthc1 t1, $f25
264 mthc1 t1, $f26
265 mthc1 t1, $f27
266 mthc1 t1, $f28
267 mthc1 t1, $f29
268 mthc1 t1, $f30
269 mthc1 t1, $f31
2701: .set pop
271#endif /* CONFIG_CPU_MIPS32_R2 */
231#else 272#else
232 .set mips3 273 .set mips3
233 dmtc1 t1, $f0 274 dmtc1 t1, $f0
diff --git a/arch/mips/kernel/rtlx-cmp.c b/arch/mips/kernel/rtlx-cmp.c
new file mode 100644
index 000000000000..56dc69635153
--- /dev/null
+++ b/arch/mips/kernel/rtlx-cmp.c
@@ -0,0 +1,116 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2005 MIPS Technologies, Inc. All rights reserved.
7 * Copyright (C) 2013 Imagination Technologies Ltd.
8 */
9#include <linux/device.h>
10#include <linux/fs.h>
11#include <linux/err.h>
12#include <linux/wait.h>
13#include <linux/sched.h>
14#include <linux/smp.h>
15
16#include <asm/mips_mt.h>
17#include <asm/vpe.h>
18#include <asm/rtlx.h>
19
20static int major;
21
22static void rtlx_interrupt(void)
23{
24 int i;
25 struct rtlx_info *info;
26 struct rtlx_info **p = vpe_get_shared(aprp_cpu_index());
27
28 if (p == NULL || *p == NULL)
29 return;
30
31 info = *p;
32
33 if (info->ap_int_pending == 1 && smp_processor_id() == 0) {
34 for (i = 0; i < RTLX_CHANNELS; i++) {
35 wake_up(&channel_wqs[i].lx_queue);
36 wake_up(&channel_wqs[i].rt_queue);
37 }
38 info->ap_int_pending = 0;
39 }
40}
41
42void _interrupt_sp(void)
43{
44 smp_send_reschedule(aprp_cpu_index());
45}
46
47int __init rtlx_module_init(void)
48{
49 struct device *dev;
50 int i, err;
51
52 if (!cpu_has_mipsmt) {
53 pr_warn("VPE loader: not a MIPS MT capable processor\n");
54 return -ENODEV;
55 }
56
57 if (num_possible_cpus() - aprp_cpu_index() < 1) {
58 pr_warn("No TCs reserved for AP/SP, not initializing RTLX.\n"
59 "Pass maxcpus=<n> argument as kernel argument\n");
60
61 return -ENODEV;
62 }
63
64 major = register_chrdev(0, RTLX_MODULE_NAME, &rtlx_fops);
65 if (major < 0) {
66 pr_err("rtlx_module_init: unable to register device\n");
67 return major;
68 }
69
70 /* initialise the wait queues */
71 for (i = 0; i < RTLX_CHANNELS; i++) {
72 init_waitqueue_head(&channel_wqs[i].rt_queue);
73 init_waitqueue_head(&channel_wqs[i].lx_queue);
74 atomic_set(&channel_wqs[i].in_open, 0);
75 mutex_init(&channel_wqs[i].mutex);
76
77 dev = device_create(mt_class, NULL, MKDEV(major, i), NULL,
78 "%s%d", RTLX_MODULE_NAME, i);
79 if (IS_ERR(dev)) {
80 err = PTR_ERR(dev);
81 goto out_chrdev;
82 }
83 }
84
85 /* set up notifiers */
86 rtlx_notify.start = rtlx_starting;
87 rtlx_notify.stop = rtlx_stopping;
88 vpe_notify(aprp_cpu_index(), &rtlx_notify);
89
90 if (cpu_has_vint) {
91 aprp_hook = rtlx_interrupt;
92 } else {
93 pr_err("APRP RTLX init on non-vectored-interrupt processor\n");
94 err = -ENODEV;
95 goto out_class;
96 }
97
98 return 0;
99
100out_class:
101 for (i = 0; i < RTLX_CHANNELS; i++)
102 device_destroy(mt_class, MKDEV(major, i));
103out_chrdev:
104 unregister_chrdev(major, RTLX_MODULE_NAME);
105
106 return err;
107}
108
109void __exit rtlx_module_exit(void)
110{
111 int i;
112
113 for (i = 0; i < RTLX_CHANNELS; i++)
114 device_destroy(mt_class, MKDEV(major, i));
115 unregister_chrdev(major, RTLX_MODULE_NAME);
116}
diff --git a/arch/mips/kernel/rtlx-mt.c b/arch/mips/kernel/rtlx-mt.c
new file mode 100644
index 000000000000..91d61ba422b4
--- /dev/null
+++ b/arch/mips/kernel/rtlx-mt.c
@@ -0,0 +1,148 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2005 MIPS Technologies, Inc. All rights reserved.
7 * Copyright (C) 2013 Imagination Technologies Ltd.
8 */
9#include <linux/device.h>
10#include <linux/fs.h>
11#include <linux/err.h>
12#include <linux/wait.h>
13#include <linux/sched.h>
14#include <linux/interrupt.h>
15#include <linux/irq.h>
16
17#include <asm/mips_mt.h>
18#include <asm/vpe.h>
19#include <asm/rtlx.h>
20
21static int major;
22
23static void rtlx_dispatch(void)
24{
25 if (read_c0_cause() & read_c0_status() & C_SW0)
26 do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_RTLX_IRQ);
27}
28
29/*
30 * Interrupt handler may be called before rtlx_init has otherwise had
31 * a chance to run.
32 */
33static irqreturn_t rtlx_interrupt(int irq, void *dev_id)
34{
35 unsigned int vpeflags;
36 unsigned long flags;
37 int i;
38
39 /* Ought not to be strictly necessary for SMTC builds */
40 local_irq_save(flags);
41 vpeflags = dvpe();
42 set_c0_status(0x100 << MIPS_CPU_RTLX_IRQ);
43 irq_enable_hazard();
44 evpe(vpeflags);
45 local_irq_restore(flags);
46
47 for (i = 0; i < RTLX_CHANNELS; i++) {
48 wake_up(&channel_wqs[i].lx_queue);
49 wake_up(&channel_wqs[i].rt_queue);
50 }
51
52 return IRQ_HANDLED;
53}
54
55static struct irqaction rtlx_irq = {
56 .handler = rtlx_interrupt,
57 .name = "RTLX",
58};
59
60static int rtlx_irq_num = MIPS_CPU_IRQ_BASE + MIPS_CPU_RTLX_IRQ;
61
62void _interrupt_sp(void)
63{
64 unsigned long flags;
65
66 local_irq_save(flags);
67 dvpe();
68 settc(1);
69 write_vpe_c0_cause(read_vpe_c0_cause() | C_SW0);
70 evpe(EVPE_ENABLE);
71 local_irq_restore(flags);
72}
73
74int __init rtlx_module_init(void)
75{
76 struct device *dev;
77 int i, err;
78
79 if (!cpu_has_mipsmt) {
80 pr_warn("VPE loader: not a MIPS MT capable processor\n");
81 return -ENODEV;
82 }
83
84 if (aprp_cpu_index() == 0) {
85 pr_warn("No TCs reserved for AP/SP, not initializing RTLX.\n"
86 "Pass maxtcs=<n> argument as kernel argument\n");
87
88 return -ENODEV;
89 }
90
91 major = register_chrdev(0, RTLX_MODULE_NAME, &rtlx_fops);
92 if (major < 0) {
93 pr_err("rtlx_module_init: unable to register device\n");
94 return major;
95 }
96
97 /* initialise the wait queues */
98 for (i = 0; i < RTLX_CHANNELS; i++) {
99 init_waitqueue_head(&channel_wqs[i].rt_queue);
100 init_waitqueue_head(&channel_wqs[i].lx_queue);
101 atomic_set(&channel_wqs[i].in_open, 0);
102 mutex_init(&channel_wqs[i].mutex);
103
104 dev = device_create(mt_class, NULL, MKDEV(major, i), NULL,
105 "%s%d", RTLX_MODULE_NAME, i);
106 if (IS_ERR(dev)) {
107 err = PTR_ERR(dev);
108 goto out_chrdev;
109 }
110 }
111
112 /* set up notifiers */
113 rtlx_notify.start = rtlx_starting;
114 rtlx_notify.stop = rtlx_stopping;
115 vpe_notify(aprp_cpu_index(), &rtlx_notify);
116
117 if (cpu_has_vint) {
118 aprp_hook = rtlx_dispatch;
119 } else {
120 pr_err("APRP RTLX init on non-vectored-interrupt processor\n");
121 err = -ENODEV;
122 goto out_class;
123 }
124
125 rtlx_irq.dev_id = rtlx;
126 err = setup_irq(rtlx_irq_num, &rtlx_irq);
127 if (err)
128 goto out_class;
129
130 return 0;
131
132out_class:
133 for (i = 0; i < RTLX_CHANNELS; i++)
134 device_destroy(mt_class, MKDEV(major, i));
135out_chrdev:
136 unregister_chrdev(major, RTLX_MODULE_NAME);
137
138 return err;
139}
140
141void __exit rtlx_module_exit(void)
142{
143 int i;
144
145 for (i = 0; i < RTLX_CHANNELS; i++)
146 device_destroy(mt_class, MKDEV(major, i));
147 unregister_chrdev(major, RTLX_MODULE_NAME);
148}
diff --git a/arch/mips/kernel/rtlx.c b/arch/mips/kernel/rtlx.c
index 2c12ea1668d1..31b1b763cb29 100644
--- a/arch/mips/kernel/rtlx.c
+++ b/arch/mips/kernel/rtlx.c
@@ -1,114 +1,51 @@
1/* 1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
2 * Copyright (C) 2005 MIPS Technologies, Inc. All rights reserved. 6 * Copyright (C) 2005 MIPS Technologies, Inc. All rights reserved.
3 * Copyright (C) 2005, 06 Ralf Baechle (ralf@linux-mips.org) 7 * Copyright (C) 2005, 06 Ralf Baechle (ralf@linux-mips.org)
4 * 8 * Copyright (C) 2013 Imagination Technologies Ltd.
5 * This program is free software; you can distribute it and/or modify it
6 * under the terms of the GNU General Public License (Version 2) as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * for more details.
13 *
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
17 *
18 */ 9 */
19
20#include <linux/device.h>
21#include <linux/kernel.h> 10#include <linux/kernel.h>
22#include <linux/fs.h> 11#include <linux/fs.h>
23#include <linux/init.h>
24#include <asm/uaccess.h>
25#include <linux/list.h>
26#include <linux/vmalloc.h>
27#include <linux/elf.h>
28#include <linux/seq_file.h>
29#include <linux/syscalls.h> 12#include <linux/syscalls.h>
30#include <linux/moduleloader.h> 13#include <linux/moduleloader.h>
31#include <linux/interrupt.h> 14#include <linux/atomic.h>
32#include <linux/poll.h>
33#include <linux/sched.h>
34#include <linux/wait.h>
35#include <asm/mipsmtregs.h> 15#include <asm/mipsmtregs.h>
36#include <asm/mips_mt.h> 16#include <asm/mips_mt.h>
37#include <asm/cacheflush.h>
38#include <linux/atomic.h>
39#include <asm/cpu.h>
40#include <asm/processor.h> 17#include <asm/processor.h>
41#include <asm/vpe.h>
42#include <asm/rtlx.h> 18#include <asm/rtlx.h>
43#include <asm/setup.h> 19#include <asm/setup.h>
20#include <asm/vpe.h>
44 21
45static struct rtlx_info *rtlx;
46static int major;
47static char module_name[] = "rtlx";
48
49static struct chan_waitqueues {
50 wait_queue_head_t rt_queue;
51 wait_queue_head_t lx_queue;
52 atomic_t in_open;
53 struct mutex mutex;
54} channel_wqs[RTLX_CHANNELS];
55
56static struct vpe_notifications notify;
57static int sp_stopping; 22static int sp_stopping;
58 23struct rtlx_info *rtlx;
59extern void *vpe_get_shared(int index); 24struct chan_waitqueues channel_wqs[RTLX_CHANNELS];
60 25struct vpe_notifications rtlx_notify;
61static void rtlx_dispatch(void) 26void (*aprp_hook)(void) = NULL;
62{ 27EXPORT_SYMBOL(aprp_hook);
63 do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_RTLX_IRQ);
64}
65
66
67/* Interrupt handler may be called before rtlx_init has otherwise had
68 a chance to run.
69*/
70static irqreturn_t rtlx_interrupt(int irq, void *dev_id)
71{
72 unsigned int vpeflags;
73 unsigned long flags;
74 int i;
75
76 /* Ought not to be strictly necessary for SMTC builds */
77 local_irq_save(flags);
78 vpeflags = dvpe();
79 set_c0_status(0x100 << MIPS_CPU_RTLX_IRQ);
80 irq_enable_hazard();
81 evpe(vpeflags);
82 local_irq_restore(flags);
83
84 for (i = 0; i < RTLX_CHANNELS; i++) {
85 wake_up(&channel_wqs[i].lx_queue);
86 wake_up(&channel_wqs[i].rt_queue);
87 }
88
89 return IRQ_HANDLED;
90}
91 28
92static void __used dump_rtlx(void) 29static void __used dump_rtlx(void)
93{ 30{
94 int i; 31 int i;
95 32
96 printk("id 0x%lx state %d\n", rtlx->id, rtlx->state); 33 pr_info("id 0x%lx state %d\n", rtlx->id, rtlx->state);
97 34
98 for (i = 0; i < RTLX_CHANNELS; i++) { 35 for (i = 0; i < RTLX_CHANNELS; i++) {
99 struct rtlx_channel *chan = &rtlx->channel[i]; 36 struct rtlx_channel *chan = &rtlx->channel[i];
100 37
101 printk(" rt_state %d lx_state %d buffer_size %d\n", 38 pr_info(" rt_state %d lx_state %d buffer_size %d\n",
102 chan->rt_state, chan->lx_state, chan->buffer_size); 39 chan->rt_state, chan->lx_state, chan->buffer_size);
103 40
104 printk(" rt_read %d rt_write %d\n", 41 pr_info(" rt_read %d rt_write %d\n",
105 chan->rt_read, chan->rt_write); 42 chan->rt_read, chan->rt_write);
106 43
107 printk(" lx_read %d lx_write %d\n", 44 pr_info(" lx_read %d lx_write %d\n",
108 chan->lx_read, chan->lx_write); 45 chan->lx_read, chan->lx_write);
109 46
110 printk(" rt_buffer <%s>\n", chan->rt_buffer); 47 pr_info(" rt_buffer <%s>\n", chan->rt_buffer);
111 printk(" lx_buffer <%s>\n", chan->lx_buffer); 48 pr_info(" lx_buffer <%s>\n", chan->lx_buffer);
112 } 49 }
113} 50}
114 51
@@ -116,8 +53,7 @@ static void __used dump_rtlx(void)
116static int rtlx_init(struct rtlx_info *rtlxi) 53static int rtlx_init(struct rtlx_info *rtlxi)
117{ 54{
118 if (rtlxi->id != RTLX_ID) { 55 if (rtlxi->id != RTLX_ID) {
119 printk(KERN_ERR "no valid RTLX id at 0x%p 0x%lx\n", 56 pr_err("no valid RTLX id at 0x%p 0x%lx\n", rtlxi, rtlxi->id);
120 rtlxi, rtlxi->id);
121 return -ENOEXEC; 57 return -ENOEXEC;
122 } 58 }
123 59
@@ -127,20 +63,20 @@ static int rtlx_init(struct rtlx_info *rtlxi)
127} 63}
128 64
129/* notifications */ 65/* notifications */
130static void starting(int vpe) 66void rtlx_starting(int vpe)
131{ 67{
132 int i; 68 int i;
133 sp_stopping = 0; 69 sp_stopping = 0;
134 70
135 /* force a reload of rtlx */ 71 /* force a reload of rtlx */
136 rtlx=NULL; 72 rtlx = NULL;
137 73
138 /* wake up any sleeping rtlx_open's */ 74 /* wake up any sleeping rtlx_open's */
139 for (i = 0; i < RTLX_CHANNELS; i++) 75 for (i = 0; i < RTLX_CHANNELS; i++)
140 wake_up_interruptible(&channel_wqs[i].lx_queue); 76 wake_up_interruptible(&channel_wqs[i].lx_queue);
141} 77}
142 78
143static void stopping(int vpe) 79void rtlx_stopping(int vpe)
144{ 80{
145 int i; 81 int i;
146 82
@@ -158,31 +94,30 @@ int rtlx_open(int index, int can_sleep)
158 int ret = 0; 94 int ret = 0;
159 95
160 if (index >= RTLX_CHANNELS) { 96 if (index >= RTLX_CHANNELS) {
161 printk(KERN_DEBUG "rtlx_open index out of range\n"); 97 pr_debug(KERN_DEBUG "rtlx_open index out of range\n");
162 return -ENOSYS; 98 return -ENOSYS;
163 } 99 }
164 100
165 if (atomic_inc_return(&channel_wqs[index].in_open) > 1) { 101 if (atomic_inc_return(&channel_wqs[index].in_open) > 1) {
166 printk(KERN_DEBUG "rtlx_open channel %d already opened\n", 102 pr_debug(KERN_DEBUG "rtlx_open channel %d already opened\n", index);
167 index);
168 ret = -EBUSY; 103 ret = -EBUSY;
169 goto out_fail; 104 goto out_fail;
170 } 105 }
171 106
172 if (rtlx == NULL) { 107 if (rtlx == NULL) {
173 if( (p = vpe_get_shared(tclimit)) == NULL) { 108 p = vpe_get_shared(aprp_cpu_index());
174 if (can_sleep) { 109 if (p == NULL) {
175 ret = __wait_event_interruptible( 110 if (can_sleep) {
111 ret = __wait_event_interruptible(
176 channel_wqs[index].lx_queue, 112 channel_wqs[index].lx_queue,
177 (p = vpe_get_shared(tclimit))); 113 (p = vpe_get_shared(aprp_cpu_index())));
178 if (ret) 114 if (ret)
115 goto out_fail;
116 } else {
117 pr_debug("No SP program loaded, and device opened with O_NONBLOCK\n");
118 ret = -ENOSYS;
179 goto out_fail; 119 goto out_fail;
180 } else { 120 }
181 printk(KERN_DEBUG "No SP program loaded, and device "
182 "opened with O_NONBLOCK\n");
183 ret = -ENOSYS;
184 goto out_fail;
185 }
186 } 121 }
187 122
188 smp_rmb(); 123 smp_rmb();
@@ -204,24 +139,24 @@ int rtlx_open(int index, int can_sleep)
204 ret = -ERESTARTSYS; 139 ret = -ERESTARTSYS;
205 goto out_fail; 140 goto out_fail;
206 } 141 }
207 finish_wait(&channel_wqs[index].lx_queue, &wait); 142 finish_wait(&channel_wqs[index].lx_queue,
143 &wait);
208 } else { 144 } else {
209 pr_err(" *vpe_get_shared is NULL. " 145 pr_err(" *vpe_get_shared is NULL. Has an SP program been loaded?\n");
210 "Has an SP program been loaded?\n");
211 ret = -ENOSYS; 146 ret = -ENOSYS;
212 goto out_fail; 147 goto out_fail;
213 } 148 }
214 } 149 }
215 150
216 if ((unsigned int)*p < KSEG0) { 151 if ((unsigned int)*p < KSEG0) {
217 printk(KERN_WARNING "vpe_get_shared returned an " 152 pr_warn("vpe_get_shared returned an invalid pointer maybe an error code %d\n",
218 "invalid pointer maybe an error code %d\n", 153 (int)*p);
219 (int)*p);
220 ret = -ENOSYS; 154 ret = -ENOSYS;
221 goto out_fail; 155 goto out_fail;
222 } 156 }
223 157
224 if ((ret = rtlx_init(*p)) < 0) 158 ret = rtlx_init(*p);
159 if (ret < 0)
225 goto out_ret; 160 goto out_ret;
226 } 161 }
227 162
@@ -352,7 +287,7 @@ ssize_t rtlx_write(int index, const void __user *buffer, size_t count)
352 size_t fl; 287 size_t fl;
353 288
354 if (rtlx == NULL) 289 if (rtlx == NULL)
355 return(-ENOSYS); 290 return -ENOSYS;
356 291
357 rt = &rtlx->channel[index]; 292 rt = &rtlx->channel[index];
358 293
@@ -361,8 +296,8 @@ ssize_t rtlx_write(int index, const void __user *buffer, size_t count)
361 rt_read = rt->rt_read; 296 rt_read = rt->rt_read;
362 297
363 /* total number of bytes to copy */ 298 /* total number of bytes to copy */
364 count = min(count, (size_t)write_spacefree(rt_read, rt->rt_write, 299 count = min_t(size_t, count, write_spacefree(rt_read, rt->rt_write,
365 rt->buffer_size)); 300 rt->buffer_size));
366 301
367 /* first bit from write pointer to the end of the buffer, or count */ 302 /* first bit from write pointer to the end of the buffer, or count */
368 fl = min(count, (size_t) rt->buffer_size - rt->rt_write); 303 fl = min(count, (size_t) rt->buffer_size - rt->rt_write);
@@ -372,9 +307,8 @@ ssize_t rtlx_write(int index, const void __user *buffer, size_t count)
372 goto out; 307 goto out;
373 308
374 /* if there's any left copy to the beginning of the buffer */ 309 /* if there's any left copy to the beginning of the buffer */
375 if (count - fl) { 310 if (count - fl)
376 failed = copy_from_user(rt->rt_buffer, buffer + fl, count - fl); 311 failed = copy_from_user(rt->rt_buffer, buffer + fl, count - fl);
377 }
378 312
379out: 313out:
380 count -= failed; 314 count -= failed;
@@ -384,6 +318,8 @@ out:
384 smp_wmb(); 318 smp_wmb();
385 mutex_unlock(&channel_wqs[index].mutex); 319 mutex_unlock(&channel_wqs[index].mutex);
386 320
321 _interrupt_sp();
322
387 return count; 323 return count;
388} 324}
389 325
@@ -398,7 +334,7 @@ static int file_release(struct inode *inode, struct file *filp)
398 return rtlx_release(iminor(inode)); 334 return rtlx_release(iminor(inode));
399} 335}
400 336
401static unsigned int file_poll(struct file *file, poll_table * wait) 337static unsigned int file_poll(struct file *file, poll_table *wait)
402{ 338{
403 int minor = iminor(file_inode(file)); 339 int minor = iminor(file_inode(file));
404 unsigned int mask = 0; 340 unsigned int mask = 0;
@@ -420,21 +356,20 @@ static unsigned int file_poll(struct file *file, poll_table * wait)
420 return mask; 356 return mask;
421} 357}
422 358
423static ssize_t file_read(struct file *file, char __user * buffer, size_t count, 359static ssize_t file_read(struct file *file, char __user *buffer, size_t count,
424 loff_t * ppos) 360 loff_t *ppos)
425{ 361{
426 int minor = iminor(file_inode(file)); 362 int minor = iminor(file_inode(file));
427 363
428 /* data available? */ 364 /* data available? */
429 if (!rtlx_read_poll(minor, (file->f_flags & O_NONBLOCK) ? 0 : 1)) { 365 if (!rtlx_read_poll(minor, (file->f_flags & O_NONBLOCK) ? 0 : 1))
430 return 0; // -EAGAIN makes cat whinge 366 return 0; /* -EAGAIN makes 'cat' whine */
431 }
432 367
433 return rtlx_read(minor, buffer, count); 368 return rtlx_read(minor, buffer, count);
434} 369}
435 370
436static ssize_t file_write(struct file *file, const char __user * buffer, 371static ssize_t file_write(struct file *file, const char __user *buffer,
437 size_t count, loff_t * ppos) 372 size_t count, loff_t *ppos)
438{ 373{
439 int minor = iminor(file_inode(file)); 374 int minor = iminor(file_inode(file));
440 375
@@ -454,100 +389,16 @@ static ssize_t file_write(struct file *file, const char __user * buffer,
454 return rtlx_write(minor, buffer, count); 389 return rtlx_write(minor, buffer, count);
455} 390}
456 391
457static const struct file_operations rtlx_fops = { 392const struct file_operations rtlx_fops = {
458 .owner = THIS_MODULE, 393 .owner = THIS_MODULE,
459 .open = file_open, 394 .open = file_open,
460 .release = file_release, 395 .release = file_release,
461 .write = file_write, 396 .write = file_write,
462 .read = file_read, 397 .read = file_read,
463 .poll = file_poll, 398 .poll = file_poll,
464 .llseek = noop_llseek, 399 .llseek = noop_llseek,
465}; 400};
466 401
467static struct irqaction rtlx_irq = {
468 .handler = rtlx_interrupt,
469 .name = "RTLX",
470};
471
472static int rtlx_irq_num = MIPS_CPU_IRQ_BASE + MIPS_CPU_RTLX_IRQ;
473
474static char register_chrdev_failed[] __initdata =
475 KERN_ERR "rtlx_module_init: unable to register device\n";
476
477static int __init rtlx_module_init(void)
478{
479 struct device *dev;
480 int i, err;
481
482 if (!cpu_has_mipsmt) {
483 printk("VPE loader: not a MIPS MT capable processor\n");
484 return -ENODEV;
485 }
486
487 if (tclimit == 0) {
488 printk(KERN_WARNING "No TCs reserved for AP/SP, not "
489 "initializing RTLX.\nPass maxtcs=<n> argument as kernel "
490 "argument\n");
491
492 return -ENODEV;
493 }
494
495 major = register_chrdev(0, module_name, &rtlx_fops);
496 if (major < 0) {
497 printk(register_chrdev_failed);
498 return major;
499 }
500
501 /* initialise the wait queues */
502 for (i = 0; i < RTLX_CHANNELS; i++) {
503 init_waitqueue_head(&channel_wqs[i].rt_queue);
504 init_waitqueue_head(&channel_wqs[i].lx_queue);
505 atomic_set(&channel_wqs[i].in_open, 0);
506 mutex_init(&channel_wqs[i].mutex);
507
508 dev = device_create(mt_class, NULL, MKDEV(major, i), NULL,
509 "%s%d", module_name, i);
510 if (IS_ERR(dev)) {
511 err = PTR_ERR(dev);
512 goto out_chrdev;
513 }
514 }
515
516 /* set up notifiers */
517 notify.start = starting;
518 notify.stop = stopping;
519 vpe_notify(tclimit, &notify);
520
521 if (cpu_has_vint)
522 set_vi_handler(MIPS_CPU_RTLX_IRQ, rtlx_dispatch);
523 else {
524 pr_err("APRP RTLX init on non-vectored-interrupt processor\n");
525 err = -ENODEV;
526 goto out_chrdev;
527 }
528
529 rtlx_irq.dev_id = rtlx;
530 setup_irq(rtlx_irq_num, &rtlx_irq);
531
532 return 0;
533
534out_chrdev:
535 for (i = 0; i < RTLX_CHANNELS; i++)
536 device_destroy(mt_class, MKDEV(major, i));
537
538 return err;
539}
540
541static void __exit rtlx_module_exit(void)
542{
543 int i;
544
545 for (i = 0; i < RTLX_CHANNELS; i++)
546 device_destroy(mt_class, MKDEV(major, i));
547
548 unregister_chrdev(major, module_name);
549}
550
551module_init(rtlx_module_init); 402module_init(rtlx_module_init);
552module_exit(rtlx_module_exit); 403module_exit(rtlx_module_exit);
553 404
diff --git a/arch/mips/kernel/segment.c b/arch/mips/kernel/segment.c
new file mode 100644
index 000000000000..076ead2a9859
--- /dev/null
+++ b/arch/mips/kernel/segment.c
@@ -0,0 +1,110 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2013 Imagination Technologies Ltd.
7 */
8
9#include <linux/kernel.h>
10#include <linux/debugfs.h>
11#include <linux/seq_file.h>
12#include <asm/cpu.h>
13#include <asm/mipsregs.h>
14
15static void build_segment_config(char *str, unsigned int cfg)
16{
17 unsigned int am;
18 static const char * const am_str[] = {
19 "UK", "MK", "MSK", "MUSK", "MUSUK", "USK",
20 "RSRVD", "UUSK"};
21
22 /* Segment access mode. */
23 am = (cfg & MIPS_SEGCFG_AM) >> MIPS_SEGCFG_AM_SHIFT;
24 str += sprintf(str, "%-5s", am_str[am]);
25
26 /*
27 * Access modes MK, MSK and MUSK are mapped segments. Therefore
28 * there is no direct physical address mapping.
29 */
30 if ((am == 0) || (am > 3)) {
31 str += sprintf(str, " %03lx",
32 ((cfg & MIPS_SEGCFG_PA) >> MIPS_SEGCFG_PA_SHIFT));
33 str += sprintf(str, " %01ld",
34 ((cfg & MIPS_SEGCFG_C) >> MIPS_SEGCFG_C_SHIFT));
35 } else {
36 str += sprintf(str, " UND");
37 str += sprintf(str, " U");
38 }
39
40 /* Exception configuration. */
41 str += sprintf(str, " %01ld\n",
42 ((cfg & MIPS_SEGCFG_EU) >> MIPS_SEGCFG_EU_SHIFT));
43}
44
45static int show_segments(struct seq_file *m, void *v)
46{
47 unsigned int segcfg;
48 char str[42];
49
50 seq_puts(m, "Segment Virtual Size Access Mode Physical Caching EU\n");
51 seq_puts(m, "------- ------- ---- ----------- -------- ------- --\n");
52
53 segcfg = read_c0_segctl0();
54 build_segment_config(str, segcfg);
55 seq_printf(m, " 0 e0000000 512M %s", str);
56
57 segcfg >>= 16;
58 build_segment_config(str, segcfg);
59 seq_printf(m, " 1 c0000000 512M %s", str);
60
61 segcfg = read_c0_segctl1();
62 build_segment_config(str, segcfg);
63 seq_printf(m, " 2 a0000000 512M %s", str);
64
65 segcfg >>= 16;
66 build_segment_config(str, segcfg);
67 seq_printf(m, " 3 80000000 512M %s", str);
68
69 segcfg = read_c0_segctl2();
70 build_segment_config(str, segcfg);
71 seq_printf(m, " 4 40000000 1G %s", str);
72
73 segcfg >>= 16;
74 build_segment_config(str, segcfg);
75 seq_printf(m, " 5 00000000 1G %s\n", str);
76
77 return 0;
78}
79
80static int segments_open(struct inode *inode, struct file *file)
81{
82 return single_open(file, show_segments, NULL);
83}
84
85static const struct file_operations segments_fops = {
86 .open = segments_open,
87 .read = seq_read,
88 .llseek = seq_lseek,
89 .release = single_release,
90};
91
92static int __init segments_info(void)
93{
94 extern struct dentry *mips_debugfs_dir;
95 struct dentry *segments;
96
97 if (cpu_has_segments) {
98 if (!mips_debugfs_dir)
99 return -ENODEV;
100
101 segments = debugfs_create_file("segments", S_IRUGO,
102 mips_debugfs_dir, NULL,
103 &segments_fops);
104 if (!segments)
105 return -ENOMEM;
106 }
107 return 0;
108}
109
110device_initcall(segments_info);
diff --git a/arch/mips/kernel/signal.c b/arch/mips/kernel/signal.c
index 2f285abc76d5..5199563c4403 100644
--- a/arch/mips/kernel/signal.c
+++ b/arch/mips/kernel/signal.c
@@ -71,8 +71,9 @@ static int protected_save_fp_context(struct sigcontext __user *sc)
71 int err; 71 int err;
72 while (1) { 72 while (1) {
73 lock_fpu_owner(); 73 lock_fpu_owner();
74 own_fpu_inatomic(1); 74 err = own_fpu_inatomic(1);
75 err = save_fp_context(sc); /* this might fail */ 75 if (!err)
76 err = save_fp_context(sc); /* this might fail */
76 unlock_fpu_owner(); 77 unlock_fpu_owner();
77 if (likely(!err)) 78 if (likely(!err))
78 break; 79 break;
@@ -91,8 +92,9 @@ static int protected_restore_fp_context(struct sigcontext __user *sc)
91 int err, tmp __maybe_unused; 92 int err, tmp __maybe_unused;
92 while (1) { 93 while (1) {
93 lock_fpu_owner(); 94 lock_fpu_owner();
94 own_fpu_inatomic(0); 95 err = own_fpu_inatomic(0);
95 err = restore_fp_context(sc); /* this might fail */ 96 if (!err)
97 err = restore_fp_context(sc); /* this might fail */
96 unlock_fpu_owner(); 98 unlock_fpu_owner();
97 if (likely(!err)) 99 if (likely(!err))
98 break; 100 break;
diff --git a/arch/mips/kernel/signal32.c b/arch/mips/kernel/signal32.c
index 1905a419aa46..3d60f7750fa8 100644
--- a/arch/mips/kernel/signal32.c
+++ b/arch/mips/kernel/signal32.c
@@ -85,8 +85,9 @@ static int protected_save_fp_context32(struct sigcontext32 __user *sc)
85 int err; 85 int err;
86 while (1) { 86 while (1) {
87 lock_fpu_owner(); 87 lock_fpu_owner();
88 own_fpu_inatomic(1); 88 err = own_fpu_inatomic(1);
89 err = save_fp_context32(sc); /* this might fail */ 89 if (!err)
90 err = save_fp_context32(sc); /* this might fail */
90 unlock_fpu_owner(); 91 unlock_fpu_owner();
91 if (likely(!err)) 92 if (likely(!err))
92 break; 93 break;
@@ -105,8 +106,9 @@ static int protected_restore_fp_context32(struct sigcontext32 __user *sc)
105 int err, tmp __maybe_unused; 106 int err, tmp __maybe_unused;
106 while (1) { 107 while (1) {
107 lock_fpu_owner(); 108 lock_fpu_owner();
108 own_fpu_inatomic(0); 109 err = own_fpu_inatomic(0);
109 err = restore_fp_context32(sc); /* this might fail */ 110 if (!err)
111 err = restore_fp_context32(sc); /* this might fail */
110 unlock_fpu_owner(); 112 unlock_fpu_owner();
111 if (likely(!err)) 113 if (likely(!err))
112 break; 114 break;
diff --git a/arch/mips/kernel/smp-bmips.c b/arch/mips/kernel/smp-bmips.c
index 2362665ba496..ea4c2dc31692 100644
--- a/arch/mips/kernel/smp-bmips.c
+++ b/arch/mips/kernel/smp-bmips.c
@@ -49,8 +49,10 @@ cpumask_t bmips_booted_mask;
49unsigned long bmips_smp_boot_sp; 49unsigned long bmips_smp_boot_sp;
50unsigned long bmips_smp_boot_gp; 50unsigned long bmips_smp_boot_gp;
51 51
52static void bmips_send_ipi_single(int cpu, unsigned int action); 52static void bmips43xx_send_ipi_single(int cpu, unsigned int action);
53static irqreturn_t bmips_ipi_interrupt(int irq, void *dev_id); 53static void bmips5000_send_ipi_single(int cpu, unsigned int action);
54static irqreturn_t bmips43xx_ipi_interrupt(int irq, void *dev_id);
55static irqreturn_t bmips5000_ipi_interrupt(int irq, void *dev_id);
54 56
55/* SW interrupts 0,1 are used for interprocessor signaling */ 57/* SW interrupts 0,1 are used for interprocessor signaling */
56#define IPI0_IRQ (MIPS_CPU_IRQ_BASE + 0) 58#define IPI0_IRQ (MIPS_CPU_IRQ_BASE + 0)
@@ -64,49 +66,58 @@ static irqreturn_t bmips_ipi_interrupt(int irq, void *dev_id);
64static void __init bmips_smp_setup(void) 66static void __init bmips_smp_setup(void)
65{ 67{
66 int i, cpu = 1, boot_cpu = 0; 68 int i, cpu = 1, boot_cpu = 0;
67
68#if defined(CONFIG_CPU_BMIPS4350) || defined(CONFIG_CPU_BMIPS4380)
69 int cpu_hw_intr; 69 int cpu_hw_intr;
70 70
71 /* arbitration priority */ 71 switch (current_cpu_type()) {
72 clear_c0_brcm_cmt_ctrl(0x30); 72 case CPU_BMIPS4350:
73 73 case CPU_BMIPS4380:
74 /* NBK and weak order flags */ 74 /* arbitration priority */
75 set_c0_brcm_config_0(0x30000); 75 clear_c0_brcm_cmt_ctrl(0x30);
76 76
77 /* Find out if we are running on TP0 or TP1 */ 77 /* NBK and weak order flags */
78 boot_cpu = !!(read_c0_brcm_cmt_local() & (1 << 31)); 78 set_c0_brcm_config_0(0x30000);
79 79
80 /* 80 /* Find out if we are running on TP0 or TP1 */
81 * MIPS interrupts 0,1 (SW INT 0,1) cross over to the other thread 81 boot_cpu = !!(read_c0_brcm_cmt_local() & (1 << 31));
82 * MIPS interrupt 2 (HW INT 0) is the CPU0 L1 controller output 82
83 * MIPS interrupt 3 (HW INT 1) is the CPU1 L1 controller output 83 /*
84 */ 84 * MIPS interrupts 0,1 (SW INT 0,1) cross over to the other
85 if (boot_cpu == 0) 85 * thread
86 cpu_hw_intr = 0x02; 86 * MIPS interrupt 2 (HW INT 0) is the CPU0 L1 controller output
87 else 87 * MIPS interrupt 3 (HW INT 1) is the CPU1 L1 controller output
88 cpu_hw_intr = 0x1d; 88 */
89 89 if (boot_cpu == 0)
90 change_c0_brcm_cmt_intr(0xf8018000, (cpu_hw_intr << 27) | (0x03 << 15)); 90 cpu_hw_intr = 0x02;
91 91 else
92 /* single core, 2 threads (2 pipelines) */ 92 cpu_hw_intr = 0x1d;
93 max_cpus = 2; 93
94#elif defined(CONFIG_CPU_BMIPS5000) 94 change_c0_brcm_cmt_intr(0xf8018000,
95 /* enable raceless SW interrupts */ 95 (cpu_hw_intr << 27) | (0x03 << 15));
96 set_c0_brcm_config(0x03 << 22); 96
97 97 /* single core, 2 threads (2 pipelines) */
98 /* route HW interrupt 0 to CPU0, HW interrupt 1 to CPU1 */ 98 max_cpus = 2;
99 change_c0_brcm_mode(0x1f << 27, 0x02 << 27); 99
100 100 break;
101 /* N cores, 2 threads per core */ 101 case CPU_BMIPS5000:
102 max_cpus = (((read_c0_brcm_config() >> 6) & 0x03) + 1) << 1; 102 /* enable raceless SW interrupts */
103 set_c0_brcm_config(0x03 << 22);
104
105 /* route HW interrupt 0 to CPU0, HW interrupt 1 to CPU1 */
106 change_c0_brcm_mode(0x1f << 27, 0x02 << 27);
107
108 /* N cores, 2 threads per core */
109 max_cpus = (((read_c0_brcm_config() >> 6) & 0x03) + 1) << 1;
110
111 /* clear any pending SW interrupts */
112 for (i = 0; i < max_cpus; i++) {
113 write_c0_brcm_action(ACTION_CLR_IPI(i, 0));
114 write_c0_brcm_action(ACTION_CLR_IPI(i, 1));
115 }
103 116
104 /* clear any pending SW interrupts */ 117 break;
105 for (i = 0; i < max_cpus; i++) { 118 default:
106 write_c0_brcm_action(ACTION_CLR_IPI(i, 0)); 119 max_cpus = 1;
107 write_c0_brcm_action(ACTION_CLR_IPI(i, 1));
108 } 120 }
109#endif
110 121
111 if (!bmips_smp_enabled) 122 if (!bmips_smp_enabled)
112 max_cpus = 1; 123 max_cpus = 1;
@@ -134,6 +145,20 @@ static void __init bmips_smp_setup(void)
134 */ 145 */
135static void bmips_prepare_cpus(unsigned int max_cpus) 146static void bmips_prepare_cpus(unsigned int max_cpus)
136{ 147{
148 irqreturn_t (*bmips_ipi_interrupt)(int irq, void *dev_id);
149
150 switch (current_cpu_type()) {
151 case CPU_BMIPS4350:
152 case CPU_BMIPS4380:
153 bmips_ipi_interrupt = bmips43xx_ipi_interrupt;
154 break;
155 case CPU_BMIPS5000:
156 bmips_ipi_interrupt = bmips5000_ipi_interrupt;
157 break;
158 default:
159 return;
160 }
161
137 if (request_irq(IPI0_IRQ, bmips_ipi_interrupt, IRQF_PERCPU, 162 if (request_irq(IPI0_IRQ, bmips_ipi_interrupt, IRQF_PERCPU,
138 "smp_ipi0", NULL)) 163 "smp_ipi0", NULL))
139 panic("Can't request IPI0 interrupt"); 164 panic("Can't request IPI0 interrupt");
@@ -168,26 +193,39 @@ static void bmips_boot_secondary(int cpu, struct task_struct *idle)
168 193
169 pr_info("SMP: Booting CPU%d...\n", cpu); 194 pr_info("SMP: Booting CPU%d...\n", cpu);
170 195
171 if (cpumask_test_cpu(cpu, &bmips_booted_mask)) 196 if (cpumask_test_cpu(cpu, &bmips_booted_mask)) {
172 bmips_send_ipi_single(cpu, 0); 197 switch (current_cpu_type()) {
198 case CPU_BMIPS4350:
199 case CPU_BMIPS4380:
200 bmips43xx_send_ipi_single(cpu, 0);
201 break;
202 case CPU_BMIPS5000:
203 bmips5000_send_ipi_single(cpu, 0);
204 break;
205 }
206 }
173 else { 207 else {
174#if defined(CONFIG_CPU_BMIPS4350) || defined(CONFIG_CPU_BMIPS4380) 208 switch (current_cpu_type()) {
175 /* Reset slave TP1 if booting from TP0 */ 209 case CPU_BMIPS4350:
176 if (cpu_logical_map(cpu) == 1) 210 case CPU_BMIPS4380:
177 set_c0_brcm_cmt_ctrl(0x01); 211 /* Reset slave TP1 if booting from TP0 */
178#elif defined(CONFIG_CPU_BMIPS5000) 212 if (cpu_logical_map(cpu) == 1)
179 if (cpu & 0x01) 213 set_c0_brcm_cmt_ctrl(0x01);
180 write_c0_brcm_action(ACTION_BOOT_THREAD(cpu)); 214 break;
181 else { 215 case CPU_BMIPS5000:
182 /* 216 if (cpu & 0x01)
183 * core N thread 0 was already booted; just 217 write_c0_brcm_action(ACTION_BOOT_THREAD(cpu));
184 * pulse the NMI line 218 else {
185 */ 219 /*
186 bmips_write_zscm_reg(0x210, 0xc0000000); 220 * core N thread 0 was already booted; just
187 udelay(10); 221 * pulse the NMI line
188 bmips_write_zscm_reg(0x210, 0x00); 222 */
223 bmips_write_zscm_reg(0x210, 0xc0000000);
224 udelay(10);
225 bmips_write_zscm_reg(0x210, 0x00);
226 }
227 break;
189 } 228 }
190#endif
191 cpumask_set_cpu(cpu, &bmips_booted_mask); 229 cpumask_set_cpu(cpu, &bmips_booted_mask);
192 } 230 }
193} 231}
@@ -199,26 +237,32 @@ static void bmips_init_secondary(void)
199{ 237{
200 /* move NMI vector to kseg0, in case XKS01 is enabled */ 238 /* move NMI vector to kseg0, in case XKS01 is enabled */
201 239
202#if defined(CONFIG_CPU_BMIPS4350) || defined(CONFIG_CPU_BMIPS4380) 240 void __iomem *cbr;
203 void __iomem *cbr = BMIPS_GET_CBR();
204 unsigned long old_vec; 241 unsigned long old_vec;
205 unsigned long relo_vector; 242 unsigned long relo_vector;
206 int boot_cpu; 243 int boot_cpu;
207 244
208 boot_cpu = !!(read_c0_brcm_cmt_local() & (1 << 31)); 245 switch (current_cpu_type()) {
209 relo_vector = boot_cpu ? BMIPS_RELO_VECTOR_CONTROL_0 : 246 case CPU_BMIPS4350:
210 BMIPS_RELO_VECTOR_CONTROL_1; 247 case CPU_BMIPS4380:
248 cbr = BMIPS_GET_CBR();
211 249
212 old_vec = __raw_readl(cbr + relo_vector); 250 boot_cpu = !!(read_c0_brcm_cmt_local() & (1 << 31));
213 __raw_writel(old_vec & ~0x20000000, cbr + relo_vector); 251 relo_vector = boot_cpu ? BMIPS_RELO_VECTOR_CONTROL_0 :
252 BMIPS_RELO_VECTOR_CONTROL_1;
214 253
215 clear_c0_cause(smp_processor_id() ? C_SW1 : C_SW0); 254 old_vec = __raw_readl(cbr + relo_vector);
216#elif defined(CONFIG_CPU_BMIPS5000) 255 __raw_writel(old_vec & ~0x20000000, cbr + relo_vector);
217 write_c0_brcm_bootvec(read_c0_brcm_bootvec() &
218 (smp_processor_id() & 0x01 ? ~0x20000000 : ~0x2000));
219 256
220 write_c0_brcm_action(ACTION_CLR_IPI(smp_processor_id(), 0)); 257 clear_c0_cause(smp_processor_id() ? C_SW1 : C_SW0);
221#endif 258 break;
259 case CPU_BMIPS5000:
260 write_c0_brcm_bootvec(read_c0_brcm_bootvec() &
261 (smp_processor_id() & 0x01 ? ~0x20000000 : ~0x2000));
262
263 write_c0_brcm_action(ACTION_CLR_IPI(smp_processor_id(), 0));
264 break;
265 }
222} 266}
223 267
224/* 268/*
@@ -243,8 +287,6 @@ static void bmips_cpus_done(void)
243{ 287{
244} 288}
245 289
246#if defined(CONFIG_CPU_BMIPS5000)
247
248/* 290/*
249 * BMIPS5000 raceless IPIs 291 * BMIPS5000 raceless IPIs
250 * 292 *
@@ -253,12 +295,12 @@ static void bmips_cpus_done(void)
253 * IPI1 is used for SMP_CALL_FUNCTION 295 * IPI1 is used for SMP_CALL_FUNCTION
254 */ 296 */
255 297
256static void bmips_send_ipi_single(int cpu, unsigned int action) 298static void bmips5000_send_ipi_single(int cpu, unsigned int action)
257{ 299{
258 write_c0_brcm_action(ACTION_SET_IPI(cpu, action == SMP_CALL_FUNCTION)); 300 write_c0_brcm_action(ACTION_SET_IPI(cpu, action == SMP_CALL_FUNCTION));
259} 301}
260 302
261static irqreturn_t bmips_ipi_interrupt(int irq, void *dev_id) 303static irqreturn_t bmips5000_ipi_interrupt(int irq, void *dev_id)
262{ 304{
263 int action = irq - IPI0_IRQ; 305 int action = irq - IPI0_IRQ;
264 306
@@ -272,7 +314,14 @@ static irqreturn_t bmips_ipi_interrupt(int irq, void *dev_id)
272 return IRQ_HANDLED; 314 return IRQ_HANDLED;
273} 315}
274 316
275#else 317static void bmips5000_send_ipi_mask(const struct cpumask *mask,
318 unsigned int action)
319{
320 unsigned int i;
321
322 for_each_cpu(i, mask)
323 bmips5000_send_ipi_single(i, action);
324}
276 325
277/* 326/*
278 * BMIPS43xx racey IPIs 327 * BMIPS43xx racey IPIs
@@ -287,7 +336,7 @@ static irqreturn_t bmips_ipi_interrupt(int irq, void *dev_id)
287static DEFINE_SPINLOCK(ipi_lock); 336static DEFINE_SPINLOCK(ipi_lock);
288static DEFINE_PER_CPU(int, ipi_action_mask); 337static DEFINE_PER_CPU(int, ipi_action_mask);
289 338
290static void bmips_send_ipi_single(int cpu, unsigned int action) 339static void bmips43xx_send_ipi_single(int cpu, unsigned int action)
291{ 340{
292 unsigned long flags; 341 unsigned long flags;
293 342
@@ -298,7 +347,7 @@ static void bmips_send_ipi_single(int cpu, unsigned int action)
298 spin_unlock_irqrestore(&ipi_lock, flags); 347 spin_unlock_irqrestore(&ipi_lock, flags);
299} 348}
300 349
301static irqreturn_t bmips_ipi_interrupt(int irq, void *dev_id) 350static irqreturn_t bmips43xx_ipi_interrupt(int irq, void *dev_id)
302{ 351{
303 unsigned long flags; 352 unsigned long flags;
304 int action, cpu = irq - IPI0_IRQ; 353 int action, cpu = irq - IPI0_IRQ;
@@ -317,15 +366,13 @@ static irqreturn_t bmips_ipi_interrupt(int irq, void *dev_id)
317 return IRQ_HANDLED; 366 return IRQ_HANDLED;
318} 367}
319 368
320#endif /* BMIPS type */ 369static void bmips43xx_send_ipi_mask(const struct cpumask *mask,
321
322static void bmips_send_ipi_mask(const struct cpumask *mask,
323 unsigned int action) 370 unsigned int action)
324{ 371{
325 unsigned int i; 372 unsigned int i;
326 373
327 for_each_cpu(i, mask) 374 for_each_cpu(i, mask)
328 bmips_send_ipi_single(i, action); 375 bmips43xx_send_ipi_single(i, action);
329} 376}
330 377
331#ifdef CONFIG_HOTPLUG_CPU 378#ifdef CONFIG_HOTPLUG_CPU
@@ -381,15 +428,30 @@ void __ref play_dead(void)
381 428
382#endif /* CONFIG_HOTPLUG_CPU */ 429#endif /* CONFIG_HOTPLUG_CPU */
383 430
384struct plat_smp_ops bmips_smp_ops = { 431struct plat_smp_ops bmips43xx_smp_ops = {
432 .smp_setup = bmips_smp_setup,
433 .prepare_cpus = bmips_prepare_cpus,
434 .boot_secondary = bmips_boot_secondary,
435 .smp_finish = bmips_smp_finish,
436 .init_secondary = bmips_init_secondary,
437 .cpus_done = bmips_cpus_done,
438 .send_ipi_single = bmips43xx_send_ipi_single,
439 .send_ipi_mask = bmips43xx_send_ipi_mask,
440#ifdef CONFIG_HOTPLUG_CPU
441 .cpu_disable = bmips_cpu_disable,
442 .cpu_die = bmips_cpu_die,
443#endif
444};
445
446struct plat_smp_ops bmips5000_smp_ops = {
385 .smp_setup = bmips_smp_setup, 447 .smp_setup = bmips_smp_setup,
386 .prepare_cpus = bmips_prepare_cpus, 448 .prepare_cpus = bmips_prepare_cpus,
387 .boot_secondary = bmips_boot_secondary, 449 .boot_secondary = bmips_boot_secondary,
388 .smp_finish = bmips_smp_finish, 450 .smp_finish = bmips_smp_finish,
389 .init_secondary = bmips_init_secondary, 451 .init_secondary = bmips_init_secondary,
390 .cpus_done = bmips_cpus_done, 452 .cpus_done = bmips_cpus_done,
391 .send_ipi_single = bmips_send_ipi_single, 453 .send_ipi_single = bmips5000_send_ipi_single,
392 .send_ipi_mask = bmips_send_ipi_mask, 454 .send_ipi_mask = bmips5000_send_ipi_mask,
393#ifdef CONFIG_HOTPLUG_CPU 455#ifdef CONFIG_HOTPLUG_CPU
394 .cpu_disable = bmips_cpu_disable, 456 .cpu_disable = bmips_cpu_disable,
395 .cpu_die = bmips_cpu_die, 457 .cpu_die = bmips_cpu_die,
@@ -427,43 +489,47 @@ void bmips_ebase_setup(void)
427 489
428 BUG_ON(ebase != CKSEG0); 490 BUG_ON(ebase != CKSEG0);
429 491
430#if defined(CONFIG_CPU_BMIPS4350) 492 switch (current_cpu_type()) {
431 /* 493 case CPU_BMIPS4350:
432 * BMIPS4350 cannot relocate the normal vectors, but it 494 /*
433 * can relocate the BEV=1 vectors. So CPU1 starts up at 495 * BMIPS4350 cannot relocate the normal vectors, but it
434 * the relocated BEV=1, IV=0 general exception vector @ 496 * can relocate the BEV=1 vectors. So CPU1 starts up at
435 * 0xa000_0380. 497 * the relocated BEV=1, IV=0 general exception vector @
436 * 498 * 0xa000_0380.
437 * set_uncached_handler() is used here because: 499 *
438 * - CPU1 will run this from uncached space 500 * set_uncached_handler() is used here because:
439 * - None of the cacheflush functions are set up yet 501 * - CPU1 will run this from uncached space
440 */ 502 * - None of the cacheflush functions are set up yet
441 set_uncached_handler(BMIPS_WARM_RESTART_VEC - CKSEG0, 503 */
442 &bmips_smp_int_vec, 0x80); 504 set_uncached_handler(BMIPS_WARM_RESTART_VEC - CKSEG0,
443 __sync(); 505 &bmips_smp_int_vec, 0x80);
444 return; 506 __sync();
445#elif defined(CONFIG_CPU_BMIPS4380) 507 return;
446 /* 508 case CPU_BMIPS4380:
447 * 0x8000_0000: reset/NMI (initially in kseg1) 509 /*
448 * 0x8000_0400: normal vectors 510 * 0x8000_0000: reset/NMI (initially in kseg1)
449 */ 511 * 0x8000_0400: normal vectors
450 new_ebase = 0x80000400; 512 */
451 cbr = BMIPS_GET_CBR(); 513 new_ebase = 0x80000400;
452 __raw_writel(0x80080800, cbr + BMIPS_RELO_VECTOR_CONTROL_0); 514 cbr = BMIPS_GET_CBR();
453 __raw_writel(0xa0080800, cbr + BMIPS_RELO_VECTOR_CONTROL_1); 515 __raw_writel(0x80080800, cbr + BMIPS_RELO_VECTOR_CONTROL_0);
454#elif defined(CONFIG_CPU_BMIPS5000) 516 __raw_writel(0xa0080800, cbr + BMIPS_RELO_VECTOR_CONTROL_1);
455 /* 517 break;
456 * 0x8000_0000: reset/NMI (initially in kseg1) 518 case CPU_BMIPS5000:
457 * 0x8000_1000: normal vectors 519 /*
458 */ 520 * 0x8000_0000: reset/NMI (initially in kseg1)
459 new_ebase = 0x80001000; 521 * 0x8000_1000: normal vectors
460 write_c0_brcm_bootvec(0xa0088008); 522 */
461 write_c0_ebase(new_ebase); 523 new_ebase = 0x80001000;
462 if (max_cpus > 2) 524 write_c0_brcm_bootvec(0xa0088008);
463 bmips_write_zscm_reg(0xa0, 0xa008a008); 525 write_c0_ebase(new_ebase);
464#else 526 if (max_cpus > 2)
465 return; 527 bmips_write_zscm_reg(0xa0, 0xa008a008);
466#endif 528 break;
529 default:
530 return;
531 }
532
467 board_nmi_handler_setup = &bmips_nmi_handler_setup; 533 board_nmi_handler_setup = &bmips_nmi_handler_setup;
468 ebase = new_ebase; 534 ebase = new_ebase;
469} 535}
diff --git a/arch/mips/kernel/smp-cmp.c b/arch/mips/kernel/smp-cmp.c
index 5969f1e9b62a..1b925d8a610c 100644
--- a/arch/mips/kernel/smp-cmp.c
+++ b/arch/mips/kernel/smp-cmp.c
@@ -199,11 +199,14 @@ void __init cmp_prepare_cpus(unsigned int max_cpus)
199 pr_debug("SMPCMP: CPU%d: %s max_cpus=%d\n", 199 pr_debug("SMPCMP: CPU%d: %s max_cpus=%d\n",
200 smp_processor_id(), __func__, max_cpus); 200 smp_processor_id(), __func__, max_cpus);
201 201
202#ifdef CONFIG_MIPS_MT
202 /* 203 /*
203 * FIXME: some of these options are per-system, some per-core and 204 * FIXME: some of these options are per-system, some per-core and
204 * some per-cpu 205 * some per-cpu
205 */ 206 */
206 mips_mt_set_cpuoptions(); 207 mips_mt_set_cpuoptions();
208#endif
209
207} 210}
208 211
209struct plat_smp_ops cmp_smp_ops = { 212struct plat_smp_ops cmp_smp_ops = {
diff --git a/arch/mips/kernel/smp-mt.c b/arch/mips/kernel/smp-mt.c
index 57a3f7a2b370..0fb8cefc9114 100644
--- a/arch/mips/kernel/smp-mt.c
+++ b/arch/mips/kernel/smp-mt.c
@@ -71,6 +71,7 @@ static unsigned int __init smvp_vpe_init(unsigned int tc, unsigned int mvpconf0,
71 71
72 /* Record this as available CPU */ 72 /* Record this as available CPU */
73 set_cpu_possible(tc, true); 73 set_cpu_possible(tc, true);
74 set_cpu_present(tc, true);
74 __cpu_number_map[tc] = ++ncpu; 75 __cpu_number_map[tc] = ++ncpu;
75 __cpu_logical_map[ncpu] = tc; 76 __cpu_logical_map[ncpu] = tc;
76 } 77 }
@@ -112,12 +113,39 @@ static void __init smvp_tc_init(unsigned int tc, unsigned int mvpconf0)
112 write_tc_c0_tchalt(TCHALT_H); 113 write_tc_c0_tchalt(TCHALT_H);
113} 114}
114 115
116#ifdef CONFIG_IRQ_GIC
117static void mp_send_ipi_single(int cpu, unsigned int action)
118{
119 unsigned long flags;
120
121 local_irq_save(flags);
122
123 switch (action) {
124 case SMP_CALL_FUNCTION:
125 gic_send_ipi(plat_ipi_call_int_xlate(cpu));
126 break;
127
128 case SMP_RESCHEDULE_YOURSELF:
129 gic_send_ipi(plat_ipi_resched_int_xlate(cpu));
130 break;
131 }
132
133 local_irq_restore(flags);
134}
135#endif
136
115static void vsmp_send_ipi_single(int cpu, unsigned int action) 137static void vsmp_send_ipi_single(int cpu, unsigned int action)
116{ 138{
117 int i; 139 int i;
118 unsigned long flags; 140 unsigned long flags;
119 int vpflags; 141 int vpflags;
120 142
143#ifdef CONFIG_IRQ_GIC
144 if (gic_present) {
145 mp_send_ipi_single(cpu, action);
146 return;
147 }
148#endif
121 local_irq_save(flags); 149 local_irq_save(flags);
122 150
123 vpflags = dvpe(); /* can't access the other CPU's registers whilst MVPE enabled */ 151 vpflags = dvpe(); /* can't access the other CPU's registers whilst MVPE enabled */
diff --git a/arch/mips/kernel/spram.c b/arch/mips/kernel/spram.c
index 93f86817f20a..b242e2c10ea0 100644
--- a/arch/mips/kernel/spram.c
+++ b/arch/mips/kernel/spram.c
@@ -8,7 +8,6 @@
8 * 8 *
9 * Copyright (C) 2007, 2008 MIPS Technologies, Inc. 9 * Copyright (C) 2007, 2008 MIPS Technologies, Inc.
10 */ 10 */
11#include <linux/init.h>
12#include <linux/kernel.h> 11#include <linux/kernel.h>
13#include <linux/ptrace.h> 12#include <linux/ptrace.h>
14#include <linux/stddef.h> 13#include <linux/stddef.h>
@@ -206,6 +205,8 @@ void spram_config(void)
206 case CPU_34K: 205 case CPU_34K:
207 case CPU_74K: 206 case CPU_74K:
208 case CPU_1004K: 207 case CPU_1004K:
208 case CPU_INTERAPTIV:
209 case CPU_PROAPTIV:
209 config0 = read_c0_config(); 210 config0 = read_c0_config();
210 /* FIXME: addresses are Malta specific */ 211 /* FIXME: addresses are Malta specific */
211 if (config0 & (1<<24)) { 212 if (config0 & (1<<24)) {
diff --git a/arch/mips/kernel/sync-r4k.c b/arch/mips/kernel/sync-r4k.c
index 84536bf4a154..c24ad5f4b324 100644
--- a/arch/mips/kernel/sync-r4k.c
+++ b/arch/mips/kernel/sync-r4k.c
@@ -11,7 +11,6 @@
11 */ 11 */
12 12
13#include <linux/kernel.h> 13#include <linux/kernel.h>
14#include <linux/init.h>
15#include <linux/irqflags.h> 14#include <linux/irqflags.h>
16#include <linux/cpumask.h> 15#include <linux/cpumask.h>
17 16
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index f9c8746be8d6..e0b499694d18 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -78,6 +78,7 @@ extern asmlinkage void handle_cpu(void);
78extern asmlinkage void handle_ov(void); 78extern asmlinkage void handle_ov(void);
79extern asmlinkage void handle_tr(void); 79extern asmlinkage void handle_tr(void);
80extern asmlinkage void handle_fpe(void); 80extern asmlinkage void handle_fpe(void);
81extern asmlinkage void handle_ftlb(void);
81extern asmlinkage void handle_mdmx(void); 82extern asmlinkage void handle_mdmx(void);
82extern asmlinkage void handle_watch(void); 83extern asmlinkage void handle_watch(void);
83extern asmlinkage void handle_mt(void); 84extern asmlinkage void handle_mt(void);
@@ -1080,7 +1081,7 @@ asmlinkage void do_cpu(struct pt_regs *regs)
1080 unsigned long old_epc, old31; 1081 unsigned long old_epc, old31;
1081 unsigned int opcode; 1082 unsigned int opcode;
1082 unsigned int cpid; 1083 unsigned int cpid;
1083 int status; 1084 int status, err;
1084 unsigned long __maybe_unused flags; 1085 unsigned long __maybe_unused flags;
1085 1086
1086 prev_state = exception_enter(); 1087 prev_state = exception_enter();
@@ -1153,19 +1154,19 @@ asmlinkage void do_cpu(struct pt_regs *regs)
1153 1154
1154 case 1: 1155 case 1:
1155 if (used_math()) /* Using the FPU again. */ 1156 if (used_math()) /* Using the FPU again. */
1156 own_fpu(1); 1157 err = own_fpu(1);
1157 else { /* First time FPU user. */ 1158 else { /* First time FPU user. */
1158 init_fpu(); 1159 err = init_fpu();
1159 set_used_math(); 1160 set_used_math();
1160 } 1161 }
1161 1162
1162 if (!raw_cpu_has_fpu) { 1163 if (!raw_cpu_has_fpu || err) {
1163 int sig; 1164 int sig;
1164 void __user *fault_addr = NULL; 1165 void __user *fault_addr = NULL;
1165 sig = fpu_emulator_cop1Handler(regs, 1166 sig = fpu_emulator_cop1Handler(regs,
1166 &current->thread.fpu, 1167 &current->thread.fpu,
1167 0, &fault_addr); 1168 0, &fault_addr);
1168 if (!process_fpemu_return(sig, fault_addr)) 1169 if (!process_fpemu_return(sig, fault_addr) && !err)
1169 mt_ase_fp_affinity(); 1170 mt_ase_fp_affinity();
1170 } 1171 }
1171 1172
@@ -1336,6 +1337,8 @@ static inline void parity_protection_init(void)
1336 case CPU_34K: 1337 case CPU_34K:
1337 case CPU_74K: 1338 case CPU_74K:
1338 case CPU_1004K: 1339 case CPU_1004K:
1340 case CPU_INTERAPTIV:
1341 case CPU_PROAPTIV:
1339 { 1342 {
1340#define ERRCTL_PE 0x80000000 1343#define ERRCTL_PE 0x80000000
1341#define ERRCTL_L2P 0x00800000 1344#define ERRCTL_L2P 0x00800000
@@ -1425,14 +1428,27 @@ asmlinkage void cache_parity_error(void)
1425 printk("Decoded c0_cacheerr: %s cache fault in %s reference.\n", 1428 printk("Decoded c0_cacheerr: %s cache fault in %s reference.\n",
1426 reg_val & (1<<30) ? "secondary" : "primary", 1429 reg_val & (1<<30) ? "secondary" : "primary",
1427 reg_val & (1<<31) ? "data" : "insn"); 1430 reg_val & (1<<31) ? "data" : "insn");
1428 printk("Error bits: %s%s%s%s%s%s%s\n", 1431 if (cpu_has_mips_r2 &&
1429 reg_val & (1<<29) ? "ED " : "", 1432 ((current_cpu_data.processor_id && 0xff0000) == PRID_COMP_MIPS)) {
1430 reg_val & (1<<28) ? "ET " : "", 1433 pr_err("Error bits: %s%s%s%s%s%s%s%s\n",
1431 reg_val & (1<<26) ? "EE " : "", 1434 reg_val & (1<<29) ? "ED " : "",
1432 reg_val & (1<<25) ? "EB " : "", 1435 reg_val & (1<<28) ? "ET " : "",
1433 reg_val & (1<<24) ? "EI " : "", 1436 reg_val & (1<<27) ? "ES " : "",
1434 reg_val & (1<<23) ? "E1 " : "", 1437 reg_val & (1<<26) ? "EE " : "",
1435 reg_val & (1<<22) ? "E0 " : ""); 1438 reg_val & (1<<25) ? "EB " : "",
1439 reg_val & (1<<24) ? "EI " : "",
1440 reg_val & (1<<23) ? "E1 " : "",
1441 reg_val & (1<<22) ? "E0 " : "");
1442 } else {
1443 pr_err("Error bits: %s%s%s%s%s%s%s\n",
1444 reg_val & (1<<29) ? "ED " : "",
1445 reg_val & (1<<28) ? "ET " : "",
1446 reg_val & (1<<26) ? "EE " : "",
1447 reg_val & (1<<25) ? "EB " : "",
1448 reg_val & (1<<24) ? "EI " : "",
1449 reg_val & (1<<23) ? "E1 " : "",
1450 reg_val & (1<<22) ? "E0 " : "");
1451 }
1436 printk("IDX: 0x%08x\n", reg_val & ((1<<22)-1)); 1452 printk("IDX: 0x%08x\n", reg_val & ((1<<22)-1));
1437 1453
1438#if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64) 1454#if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
@@ -1446,6 +1462,34 @@ asmlinkage void cache_parity_error(void)
1446 panic("Can't handle the cache error!"); 1462 panic("Can't handle the cache error!");
1447} 1463}
1448 1464
1465asmlinkage void do_ftlb(void)
1466{
1467 const int field = 2 * sizeof(unsigned long);
1468 unsigned int reg_val;
1469
1470 /* For the moment, report the problem and hang. */
1471 if (cpu_has_mips_r2 &&
1472 ((current_cpu_data.processor_id && 0xff0000) == PRID_COMP_MIPS)) {
1473 pr_err("FTLB error exception, cp0_ecc=0x%08x:\n",
1474 read_c0_ecc());
1475 pr_err("cp0_errorepc == %0*lx\n", field, read_c0_errorepc());
1476 reg_val = read_c0_cacheerr();
1477 pr_err("c0_cacheerr == %08x\n", reg_val);
1478
1479 if ((reg_val & 0xc0000000) == 0xc0000000) {
1480 pr_err("Decoded c0_cacheerr: FTLB parity error\n");
1481 } else {
1482 pr_err("Decoded c0_cacheerr: %s cache fault in %s reference.\n",
1483 reg_val & (1<<30) ? "secondary" : "primary",
1484 reg_val & (1<<31) ? "data" : "insn");
1485 }
1486 } else {
1487 pr_err("FTLB error exception\n");
1488 }
1489 /* Just print the cacheerr bits for now */
1490 cache_parity_error();
1491}
1492
1449/* 1493/*
1450 * SDBBP EJTAG debug exception handler. 1494 * SDBBP EJTAG debug exception handler.
1451 * We skip the instruction and return to the next instruction. 1495 * We skip the instruction and return to the next instruction.
@@ -1995,6 +2039,7 @@ void __init trap_init(void)
1995 if (cpu_has_fpu && !cpu_has_nofpuex) 2039 if (cpu_has_fpu && !cpu_has_nofpuex)
1996 set_except_vector(15, handle_fpe); 2040 set_except_vector(15, handle_fpe);
1997 2041
2042 set_except_vector(16, handle_ftlb);
1998 set_except_vector(22, handle_mdmx); 2043 set_except_vector(22, handle_mdmx);
1999 2044
2000 if (cpu_has_mcheck) 2045 if (cpu_has_mcheck)
diff --git a/arch/mips/kernel/vpe-cmp.c b/arch/mips/kernel/vpe-cmp.c
new file mode 100644
index 000000000000..9268ebc0f61e
--- /dev/null
+++ b/arch/mips/kernel/vpe-cmp.c
@@ -0,0 +1,180 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2004, 2005 MIPS Technologies, Inc. All rights reserved.
7 * Copyright (C) 2013 Imagination Technologies Ltd.
8 */
9#include <linux/kernel.h>
10#include <linux/device.h>
11#include <linux/fs.h>
12#include <linux/slab.h>
13#include <linux/export.h>
14
15#include <asm/vpe.h>
16
17static int major;
18
19void cleanup_tc(struct tc *tc)
20{
21
22}
23
24static ssize_t store_kill(struct device *dev, struct device_attribute *attr,
25 const char *buf, size_t len)
26{
27 struct vpe *vpe = get_vpe(aprp_cpu_index());
28 struct vpe_notifications *notifier;
29
30 list_for_each_entry(notifier, &vpe->notify, list)
31 notifier->stop(aprp_cpu_index());
32
33 release_progmem(vpe->load_addr);
34 vpe->state = VPE_STATE_UNUSED;
35
36 return len;
37}
38static DEVICE_ATTR(kill, S_IWUSR, NULL, store_kill);
39
40static ssize_t ntcs_show(struct device *cd, struct device_attribute *attr,
41 char *buf)
42{
43 struct vpe *vpe = get_vpe(aprp_cpu_index());
44
45 return sprintf(buf, "%d\n", vpe->ntcs);
46}
47
48static ssize_t ntcs_store(struct device *dev, struct device_attribute *attr,
49 const char *buf, size_t len)
50{
51 struct vpe *vpe = get_vpe(aprp_cpu_index());
52 unsigned long new;
53 int ret;
54
55 ret = kstrtoul(buf, 0, &new);
56 if (ret < 0)
57 return ret;
58
59 /* APRP can only reserve one TC in a VPE and no more. */
60 if (new != 1)
61 return -EINVAL;
62
63 vpe->ntcs = new;
64
65 return len;
66}
67static DEVICE_ATTR_RW(ntcs);
68
69static struct attribute *vpe_attrs[] = {
70 &dev_attr_kill.attr,
71 &dev_attr_ntcs.attr,
72 NULL,
73};
74ATTRIBUTE_GROUPS(vpe);
75
76static void vpe_device_release(struct device *cd)
77{
78 kfree(cd);
79}
80
81static struct class vpe_class = {
82 .name = "vpe",
83 .owner = THIS_MODULE,
84 .dev_release = vpe_device_release,
85 .dev_groups = vpe_groups,
86};
87
88static struct device vpe_device;
89
90int __init vpe_module_init(void)
91{
92 struct vpe *v = NULL;
93 struct tc *t;
94 int err;
95
96 if (!cpu_has_mipsmt) {
97 pr_warn("VPE loader: not a MIPS MT capable processor\n");
98 return -ENODEV;
99 }
100
101 if (num_possible_cpus() - aprp_cpu_index() < 1) {
102 pr_warn("No VPEs reserved for AP/SP, not initialize VPE loader\n"
103 "Pass maxcpus=<n> argument as kernel argument\n");
104 return -ENODEV;
105 }
106
107 major = register_chrdev(0, VPE_MODULE_NAME, &vpe_fops);
108 if (major < 0) {
109 pr_warn("VPE loader: unable to register character device\n");
110 return major;
111 }
112
113 err = class_register(&vpe_class);
114 if (err) {
115 pr_err("vpe_class registration failed\n");
116 goto out_chrdev;
117 }
118
119 device_initialize(&vpe_device);
120 vpe_device.class = &vpe_class,
121 vpe_device.parent = NULL,
122 dev_set_name(&vpe_device, "vpe_sp");
123 vpe_device.devt = MKDEV(major, VPE_MODULE_MINOR);
124 err = device_add(&vpe_device);
125 if (err) {
126 pr_err("Adding vpe_device failed\n");
127 goto out_class;
128 }
129
130 t = alloc_tc(aprp_cpu_index());
131 if (!t) {
132 pr_warn("VPE: unable to allocate TC\n");
133 err = -ENOMEM;
134 goto out_dev;
135 }
136
137 /* VPE */
138 v = alloc_vpe(aprp_cpu_index());
139 if (v == NULL) {
140 pr_warn("VPE: unable to allocate VPE\n");
141 kfree(t);
142 err = -ENOMEM;
143 goto out_dev;
144 }
145
146 v->ntcs = 1;
147
148 /* add the tc to the list of this vpe's tc's. */
149 list_add(&t->tc, &v->tc);
150
151 /* TC */
152 t->pvpe = v; /* set the parent vpe */
153
154 return 0;
155
156out_dev:
157 device_del(&vpe_device);
158
159out_class:
160 class_unregister(&vpe_class);
161
162out_chrdev:
163 unregister_chrdev(major, VPE_MODULE_NAME);
164
165 return err;
166}
167
168void __exit vpe_module_exit(void)
169{
170 struct vpe *v, *n;
171
172 device_del(&vpe_device);
173 class_unregister(&vpe_class);
174 unregister_chrdev(major, VPE_MODULE_NAME);
175
176 /* No locking needed here */
177 list_for_each_entry_safe(v, n, &vpecontrol.vpe_list, list)
178 if (v->state != VPE_STATE_UNUSED)
179 release_vpe(v);
180}
diff --git a/arch/mips/kernel/vpe-mt.c b/arch/mips/kernel/vpe-mt.c
new file mode 100644
index 000000000000..949ae0e17018
--- /dev/null
+++ b/arch/mips/kernel/vpe-mt.c
@@ -0,0 +1,523 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2004, 2005 MIPS Technologies, Inc. All rights reserved.
7 * Copyright (C) 2013 Imagination Technologies Ltd.
8 */
9#include <linux/kernel.h>
10#include <linux/device.h>
11#include <linux/fs.h>
12#include <linux/slab.h>
13#include <linux/export.h>
14
15#include <asm/mipsregs.h>
16#include <asm/mipsmtregs.h>
17#include <asm/mips_mt.h>
18#include <asm/vpe.h>
19
20static int major;
21
22/* The number of TCs and VPEs physically available on the core */
23static int hw_tcs, hw_vpes;
24
25/* We are prepared so configure and start the VPE... */
26int vpe_run(struct vpe *v)
27{
28 unsigned long flags, val, dmt_flag;
29 struct vpe_notifications *notifier;
30 unsigned int vpeflags;
31 struct tc *t;
32
33 /* check we are the Master VPE */
34 local_irq_save(flags);
35 val = read_c0_vpeconf0();
36 if (!(val & VPECONF0_MVP)) {
37 pr_warn("VPE loader: only Master VPE's are able to config MT\n");
38 local_irq_restore(flags);
39
40 return -1;
41 }
42
43 dmt_flag = dmt();
44 vpeflags = dvpe();
45
46 if (list_empty(&v->tc)) {
47 evpe(vpeflags);
48 emt(dmt_flag);
49 local_irq_restore(flags);
50
51 pr_warn("VPE loader: No TC's associated with VPE %d\n",
52 v->minor);
53
54 return -ENOEXEC;
55 }
56
57 t = list_first_entry(&v->tc, struct tc, tc);
58
59 /* Put MVPE's into 'configuration state' */
60 set_c0_mvpcontrol(MVPCONTROL_VPC);
61
62 settc(t->index);
63
64 /* should check it is halted, and not activated */
65 if ((read_tc_c0_tcstatus() & TCSTATUS_A) ||
66 !(read_tc_c0_tchalt() & TCHALT_H)) {
67 evpe(vpeflags);
68 emt(dmt_flag);
69 local_irq_restore(flags);
70
71 pr_warn("VPE loader: TC %d is already active!\n",
72 t->index);
73
74 return -ENOEXEC;
75 }
76
77 /*
78 * Write the address we want it to start running from in the TCPC
79 * register.
80 */
81 write_tc_c0_tcrestart((unsigned long)v->__start);
82 write_tc_c0_tccontext((unsigned long)0);
83
84 /*
85 * Mark the TC as activated, not interrupt exempt and not dynamically
86 * allocatable
87 */
88 val = read_tc_c0_tcstatus();
89 val = (val & ~(TCSTATUS_DA | TCSTATUS_IXMT)) | TCSTATUS_A;
90 write_tc_c0_tcstatus(val);
91
92 write_tc_c0_tchalt(read_tc_c0_tchalt() & ~TCHALT_H);
93
94 /*
95 * The sde-kit passes 'memsize' to __start in $a3, so set something
96 * here... Or set $a3 to zero and define DFLT_STACK_SIZE and
97 * DFLT_HEAP_SIZE when you compile your program
98 */
99 mttgpr(6, v->ntcs);
100 mttgpr(7, physical_memsize);
101
102 /* set up VPE1 */
103 /*
104 * bind the TC to VPE 1 as late as possible so we only have the final
105 * VPE registers to set up, and so an EJTAG probe can trigger on it
106 */
107 write_tc_c0_tcbind((read_tc_c0_tcbind() & ~TCBIND_CURVPE) | 1);
108
109 write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() & ~(VPECONF0_VPA));
110
111 back_to_back_c0_hazard();
112
113 /* Set up the XTC bit in vpeconf0 to point at our tc */
114 write_vpe_c0_vpeconf0((read_vpe_c0_vpeconf0() & ~(VPECONF0_XTC))
115 | (t->index << VPECONF0_XTC_SHIFT));
116
117 back_to_back_c0_hazard();
118
119 /* enable this VPE */
120 write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() | VPECONF0_VPA);
121
122 /* clear out any left overs from a previous program */
123 write_vpe_c0_status(0);
124 write_vpe_c0_cause(0);
125
126 /* take system out of configuration state */
127 clear_c0_mvpcontrol(MVPCONTROL_VPC);
128
129 /*
130 * SMTC/SMVP kernels manage VPE enable independently,
131 * but uniprocessor kernels need to turn it on, even
132 * if that wasn't the pre-dvpe() state.
133 */
134#ifdef CONFIG_SMP
135 evpe(vpeflags);
136#else
137 evpe(EVPE_ENABLE);
138#endif
139 emt(dmt_flag);
140 local_irq_restore(flags);
141
142 list_for_each_entry(notifier, &v->notify, list)
143 notifier->start(VPE_MODULE_MINOR);
144
145 return 0;
146}
147
148void cleanup_tc(struct tc *tc)
149{
150 unsigned long flags;
151 unsigned int mtflags, vpflags;
152 int tmp;
153
154 local_irq_save(flags);
155 mtflags = dmt();
156 vpflags = dvpe();
157 /* Put MVPE's into 'configuration state' */
158 set_c0_mvpcontrol(MVPCONTROL_VPC);
159
160 settc(tc->index);
161 tmp = read_tc_c0_tcstatus();
162
163 /* mark not allocated and not dynamically allocatable */
164 tmp &= ~(TCSTATUS_A | TCSTATUS_DA);
165 tmp |= TCSTATUS_IXMT; /* interrupt exempt */
166 write_tc_c0_tcstatus(tmp);
167
168 write_tc_c0_tchalt(TCHALT_H);
169 mips_ihb();
170
171 clear_c0_mvpcontrol(MVPCONTROL_VPC);
172 evpe(vpflags);
173 emt(mtflags);
174 local_irq_restore(flags);
175}
176
177/* module wrapper entry points */
178/* give me a vpe */
179void *vpe_alloc(void)
180{
181 int i;
182 struct vpe *v;
183
184 /* find a vpe */
185 for (i = 1; i < MAX_VPES; i++) {
186 v = get_vpe(i);
187 if (v != NULL) {
188 v->state = VPE_STATE_INUSE;
189 return v;
190 }
191 }
192 return NULL;
193}
194EXPORT_SYMBOL(vpe_alloc);
195
196/* start running from here */
197int vpe_start(void *vpe, unsigned long start)
198{
199 struct vpe *v = vpe;
200
201 v->__start = start;
202 return vpe_run(v);
203}
204EXPORT_SYMBOL(vpe_start);
205
206/* halt it for now */
207int vpe_stop(void *vpe)
208{
209 struct vpe *v = vpe;
210 struct tc *t;
211 unsigned int evpe_flags;
212
213 evpe_flags = dvpe();
214
215 t = list_entry(v->tc.next, struct tc, tc);
216 if (t != NULL) {
217 settc(t->index);
218 write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() & ~VPECONF0_VPA);
219 }
220
221 evpe(evpe_flags);
222
223 return 0;
224}
225EXPORT_SYMBOL(vpe_stop);
226
227/* I've done with it thank you */
228int vpe_free(void *vpe)
229{
230 struct vpe *v = vpe;
231 struct tc *t;
232 unsigned int evpe_flags;
233
234 t = list_entry(v->tc.next, struct tc, tc);
235 if (t == NULL)
236 return -ENOEXEC;
237
238 evpe_flags = dvpe();
239
240 /* Put MVPE's into 'configuration state' */
241 set_c0_mvpcontrol(MVPCONTROL_VPC);
242
243 settc(t->index);
244 write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() & ~VPECONF0_VPA);
245
246 /* halt the TC */
247 write_tc_c0_tchalt(TCHALT_H);
248 mips_ihb();
249
250 /* mark the TC unallocated */
251 write_tc_c0_tcstatus(read_tc_c0_tcstatus() & ~TCSTATUS_A);
252
253 v->state = VPE_STATE_UNUSED;
254
255 clear_c0_mvpcontrol(MVPCONTROL_VPC);
256 evpe(evpe_flags);
257
258 return 0;
259}
260EXPORT_SYMBOL(vpe_free);
261
262static ssize_t store_kill(struct device *dev, struct device_attribute *attr,
263 const char *buf, size_t len)
264{
265 struct vpe *vpe = get_vpe(aprp_cpu_index());
266 struct vpe_notifications *notifier;
267
268 list_for_each_entry(notifier, &vpe->notify, list)
269 notifier->stop(aprp_cpu_index());
270
271 release_progmem(vpe->load_addr);
272 cleanup_tc(get_tc(aprp_cpu_index()));
273 vpe_stop(vpe);
274 vpe_free(vpe);
275
276 return len;
277}
278static DEVICE_ATTR(kill, S_IWUSR, NULL, store_kill);
279
280static ssize_t ntcs_show(struct device *cd, struct device_attribute *attr,
281 char *buf)
282{
283 struct vpe *vpe = get_vpe(aprp_cpu_index());
284
285 return sprintf(buf, "%d\n", vpe->ntcs);
286}
287
288static ssize_t ntcs_store(struct device *dev, struct device_attribute *attr,
289 const char *buf, size_t len)
290{
291 struct vpe *vpe = get_vpe(aprp_cpu_index());
292 unsigned long new;
293 int ret;
294
295 ret = kstrtoul(buf, 0, &new);
296 if (ret < 0)
297 return ret;
298
299 if (new == 0 || new > (hw_tcs - aprp_cpu_index()))
300 return -EINVAL;
301
302 vpe->ntcs = new;
303
304 return len;
305}
306static DEVICE_ATTR_RW(ntcs);
307
308static struct attribute *vpe_attrs[] = {
309 &dev_attr_kill.attr,
310 &dev_attr_ntcs.attr,
311 NULL,
312};
313ATTRIBUTE_GROUPS(vpe);
314
315static void vpe_device_release(struct device *cd)
316{
317 kfree(cd);
318}
319
320static struct class vpe_class = {
321 .name = "vpe",
322 .owner = THIS_MODULE,
323 .dev_release = vpe_device_release,
324 .dev_groups = vpe_groups,
325};
326
327static struct device vpe_device;
328
329int __init vpe_module_init(void)
330{
331 unsigned int mtflags, vpflags;
332 unsigned long flags, val;
333 struct vpe *v = NULL;
334 struct tc *t;
335 int tc, err;
336
337 if (!cpu_has_mipsmt) {
338 pr_warn("VPE loader: not a MIPS MT capable processor\n");
339 return -ENODEV;
340 }
341
342 if (vpelimit == 0) {
343 pr_warn("No VPEs reserved for AP/SP, not initialize VPE loader\n"
344 "Pass maxvpes=<n> argument as kernel argument\n");
345
346 return -ENODEV;
347 }
348
349 if (aprp_cpu_index() == 0) {
350 pr_warn("No TCs reserved for AP/SP, not initialize VPE loader\n"
351 "Pass maxtcs=<n> argument as kernel argument\n");
352
353 return -ENODEV;
354 }
355
356 major = register_chrdev(0, VPE_MODULE_NAME, &vpe_fops);
357 if (major < 0) {
358 pr_warn("VPE loader: unable to register character device\n");
359 return major;
360 }
361
362 err = class_register(&vpe_class);
363 if (err) {
364 pr_err("vpe_class registration failed\n");
365 goto out_chrdev;
366 }
367
368 device_initialize(&vpe_device);
369 vpe_device.class = &vpe_class,
370 vpe_device.parent = NULL,
371 dev_set_name(&vpe_device, "vpe1");
372 vpe_device.devt = MKDEV(major, VPE_MODULE_MINOR);
373 err = device_add(&vpe_device);
374 if (err) {
375 pr_err("Adding vpe_device failed\n");
376 goto out_class;
377 }
378
379 local_irq_save(flags);
380 mtflags = dmt();
381 vpflags = dvpe();
382
383 /* Put MVPE's into 'configuration state' */
384 set_c0_mvpcontrol(MVPCONTROL_VPC);
385
386 val = read_c0_mvpconf0();
387 hw_tcs = (val & MVPCONF0_PTC) + 1;
388 hw_vpes = ((val & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT) + 1;
389
390 for (tc = aprp_cpu_index(); tc < hw_tcs; tc++) {
391 /*
392 * Must re-enable multithreading temporarily or in case we
393 * reschedule send IPIs or similar we might hang.
394 */
395 clear_c0_mvpcontrol(MVPCONTROL_VPC);
396 evpe(vpflags);
397 emt(mtflags);
398 local_irq_restore(flags);
399 t = alloc_tc(tc);
400 if (!t) {
401 err = -ENOMEM;
402 goto out_dev;
403 }
404
405 local_irq_save(flags);
406 mtflags = dmt();
407 vpflags = dvpe();
408 set_c0_mvpcontrol(MVPCONTROL_VPC);
409
410 /* VPE's */
411 if (tc < hw_tcs) {
412 settc(tc);
413
414 v = alloc_vpe(tc);
415 if (v == NULL) {
416 pr_warn("VPE: unable to allocate VPE\n");
417 goto out_reenable;
418 }
419
420 v->ntcs = hw_tcs - aprp_cpu_index();
421
422 /* add the tc to the list of this vpe's tc's. */
423 list_add(&t->tc, &v->tc);
424
425 /* deactivate all but vpe0 */
426 if (tc >= aprp_cpu_index()) {
427 unsigned long tmp = read_vpe_c0_vpeconf0();
428
429 tmp &= ~VPECONF0_VPA;
430
431 /* master VPE */
432 tmp |= VPECONF0_MVP;
433 write_vpe_c0_vpeconf0(tmp);
434 }
435
436 /* disable multi-threading with TC's */
437 write_vpe_c0_vpecontrol(read_vpe_c0_vpecontrol() &
438 ~VPECONTROL_TE);
439
440 if (tc >= vpelimit) {
441 /*
442 * Set config to be the same as vpe0,
443 * particularly kseg0 coherency alg
444 */
445 write_vpe_c0_config(read_c0_config());
446 }
447 }
448
449 /* TC's */
450 t->pvpe = v; /* set the parent vpe */
451
452 if (tc >= aprp_cpu_index()) {
453 unsigned long tmp;
454
455 settc(tc);
456
457 /* Any TC that is bound to VPE0 gets left as is - in
458 * case we are running SMTC on VPE0. A TC that is bound
459 * to any other VPE gets bound to VPE0, ideally I'd like
460 * to make it homeless but it doesn't appear to let me
461 * bind a TC to a non-existent VPE. Which is perfectly
462 * reasonable.
463 *
464 * The (un)bound state is visible to an EJTAG probe so
465 * may notify GDB...
466 */
467 tmp = read_tc_c0_tcbind();
468 if (tmp & TCBIND_CURVPE) {
469 /* tc is bound >vpe0 */
470 write_tc_c0_tcbind(tmp & ~TCBIND_CURVPE);
471
472 t->pvpe = get_vpe(0); /* set the parent vpe */
473 }
474
475 /* halt the TC */
476 write_tc_c0_tchalt(TCHALT_H);
477 mips_ihb();
478
479 tmp = read_tc_c0_tcstatus();
480
481 /* mark not activated and not dynamically allocatable */
482 tmp &= ~(TCSTATUS_A | TCSTATUS_DA);
483 tmp |= TCSTATUS_IXMT; /* interrupt exempt */
484 write_tc_c0_tcstatus(tmp);
485 }
486 }
487
488out_reenable:
489 /* release config state */
490 clear_c0_mvpcontrol(MVPCONTROL_VPC);
491
492 evpe(vpflags);
493 emt(mtflags);
494 local_irq_restore(flags);
495
496 return 0;
497
498out_dev:
499 device_del(&vpe_device);
500
501out_class:
502 class_unregister(&vpe_class);
503
504out_chrdev:
505 unregister_chrdev(major, VPE_MODULE_NAME);
506
507 return err;
508}
509
510void __exit vpe_module_exit(void)
511{
512 struct vpe *v, *n;
513
514 device_del(&vpe_device);
515 class_unregister(&vpe_class);
516 unregister_chrdev(major, VPE_MODULE_NAME);
517
518 /* No locking needed here */
519 list_for_each_entry_safe(v, n, &vpecontrol.vpe_list, list) {
520 if (v->state != VPE_STATE_UNUSED)
521 release_vpe(v);
522 }
523}
diff --git a/arch/mips/kernel/vpe.c b/arch/mips/kernel/vpe.c
index 2d5c142bad67..11da314565cc 100644
--- a/arch/mips/kernel/vpe.c
+++ b/arch/mips/kernel/vpe.c
@@ -1,37 +1,22 @@
1/* 1/*
2 * Copyright (C) 2004, 2005 MIPS Technologies, Inc. All rights reserved. 2 * This file is subject to the terms and conditions of the GNU General Public
3 * 3 * License. See the file "COPYING" in the main directory of this archive
4 * This program is free software; you can distribute it and/or modify it 4 * for more details.
5 * under the terms of the GNU General Public License (Version 2) as
6 * published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
11 * for more details.
12 *
13 * You should have received a copy of the GNU General Public License along
14 * with this program; if not, write to the Free Software Foundation, Inc.,
15 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
16 */
17
18/*
19 * VPE support module
20 * 5 *
21 * Provides support for loading a MIPS SP program on VPE1. 6 * Copyright (C) 2004, 2005 MIPS Technologies, Inc. All rights reserved.
22 * The SP environment is rather simple, no tlb's. It needs to be relocatable 7 * Copyright (C) 2013 Imagination Technologies Ltd.
23 * (or partially linked). You should initialise your stack in the startup
24 * code. This loader looks for the symbol __start and sets up
25 * execution to resume from there. The MIPS SDE kit contains suitable examples.
26 * 8 *
27 * To load and run, simply cat a SP 'program file' to /dev/vpe1. 9 * VPE spport module for loading a MIPS SP program into VPE1. The SP
28 * i.e cat spapp >/dev/vpe1. 10 * environment is rather simple since there are no TLBs. It needs
11 * to be relocatable (or partiall linked). Initialize your stack in
12 * the startup-code. The loader looks for the symbol __start and sets
13 * up the execution to resume from there. To load and run, simply do
14 * a cat SP 'binary' to the /dev/vpe1 device.
29 */ 15 */
30#include <linux/kernel.h> 16#include <linux/kernel.h>
31#include <linux/device.h> 17#include <linux/device.h>
32#include <linux/fs.h> 18#include <linux/fs.h>
33#include <linux/init.h> 19#include <linux/init.h>
34#include <asm/uaccess.h>
35#include <linux/slab.h> 20#include <linux/slab.h>
36#include <linux/list.h> 21#include <linux/list.h>
37#include <linux/vmalloc.h> 22#include <linux/vmalloc.h>
@@ -46,13 +31,10 @@
46#include <asm/mipsmtregs.h> 31#include <asm/mipsmtregs.h>
47#include <asm/cacheflush.h> 32#include <asm/cacheflush.h>
48#include <linux/atomic.h> 33#include <linux/atomic.h>
49#include <asm/cpu.h>
50#include <asm/mips_mt.h> 34#include <asm/mips_mt.h>
51#include <asm/processor.h> 35#include <asm/processor.h>
52#include <asm/vpe.h> 36#include <asm/vpe.h>
53 37
54typedef void *vpe_handle;
55
56#ifndef ARCH_SHF_SMALL 38#ifndef ARCH_SHF_SMALL
57#define ARCH_SHF_SMALL 0 39#define ARCH_SHF_SMALL 0
58#endif 40#endif
@@ -60,95 +42,15 @@ typedef void *vpe_handle;
60/* If this is set, the section belongs in the init part of the module */ 42/* If this is set, the section belongs in the init part of the module */
61#define INIT_OFFSET_MASK (1UL << (BITS_PER_LONG-1)) 43#define INIT_OFFSET_MASK (1UL << (BITS_PER_LONG-1))
62 44
63/* 45struct vpe_control vpecontrol = {
64 * The number of TCs and VPEs physically available on the core
65 */
66static int hw_tcs, hw_vpes;
67static char module_name[] = "vpe";
68static int major;
69static const int minor = 1; /* fixed for now */
70
71/* grab the likely amount of memory we will need. */
72#ifdef CONFIG_MIPS_VPE_LOADER_TOM
73#define P_SIZE (2 * 1024 * 1024)
74#else
75/* add an overhead to the max kmalloc size for non-striped symbols/etc */
76#define P_SIZE (256 * 1024)
77#endif
78
79extern unsigned long physical_memsize;
80
81#define MAX_VPES 16
82#define VPE_PATH_MAX 256
83
84enum vpe_state {
85 VPE_STATE_UNUSED = 0,
86 VPE_STATE_INUSE,
87 VPE_STATE_RUNNING
88};
89
90enum tc_state {
91 TC_STATE_UNUSED = 0,
92 TC_STATE_INUSE,
93 TC_STATE_RUNNING,
94 TC_STATE_DYNAMIC
95};
96
97struct vpe {
98 enum vpe_state state;
99
100 /* (device) minor associated with this vpe */
101 int minor;
102
103 /* elfloader stuff */
104 void *load_addr;
105 unsigned long len;
106 char *pbuffer;
107 unsigned long plen;
108 char cwd[VPE_PATH_MAX];
109
110 unsigned long __start;
111
112 /* tc's associated with this vpe */
113 struct list_head tc;
114
115 /* The list of vpe's */
116 struct list_head list;
117
118 /* shared symbol address */
119 void *shared_ptr;
120
121 /* the list of who wants to know when something major happens */
122 struct list_head notify;
123
124 unsigned int ntcs;
125};
126
127struct tc {
128 enum tc_state state;
129 int index;
130
131 struct vpe *pvpe; /* parent VPE */
132 struct list_head tc; /* The list of TC's with this VPE */
133 struct list_head list; /* The global list of tc's */
134};
135
136struct {
137 spinlock_t vpe_list_lock;
138 struct list_head vpe_list; /* Virtual processing elements */
139 spinlock_t tc_list_lock;
140 struct list_head tc_list; /* Thread contexts */
141} vpecontrol = {
142 .vpe_list_lock = __SPIN_LOCK_UNLOCKED(vpe_list_lock), 46 .vpe_list_lock = __SPIN_LOCK_UNLOCKED(vpe_list_lock),
143 .vpe_list = LIST_HEAD_INIT(vpecontrol.vpe_list), 47 .vpe_list = LIST_HEAD_INIT(vpecontrol.vpe_list),
144 .tc_list_lock = __SPIN_LOCK_UNLOCKED(tc_list_lock), 48 .tc_list_lock = __SPIN_LOCK_UNLOCKED(tc_list_lock),
145 .tc_list = LIST_HEAD_INIT(vpecontrol.tc_list) 49 .tc_list = LIST_HEAD_INIT(vpecontrol.tc_list)
146}; 50};
147 51
148static void release_progmem(void *ptr);
149
150/* get the vpe associated with this minor */ 52/* get the vpe associated with this minor */
151static struct vpe *get_vpe(int minor) 53struct vpe *get_vpe(int minor)
152{ 54{
153 struct vpe *res, *v; 55 struct vpe *res, *v;
154 56
@@ -158,7 +60,7 @@ static struct vpe *get_vpe(int minor)
158 res = NULL; 60 res = NULL;
159 spin_lock(&vpecontrol.vpe_list_lock); 61 spin_lock(&vpecontrol.vpe_list_lock);
160 list_for_each_entry(v, &vpecontrol.vpe_list, list) { 62 list_for_each_entry(v, &vpecontrol.vpe_list, list) {
161 if (v->minor == minor) { 63 if (v->minor == VPE_MODULE_MINOR) {
162 res = v; 64 res = v;
163 break; 65 break;
164 } 66 }
@@ -169,7 +71,7 @@ static struct vpe *get_vpe(int minor)
169} 71}
170 72
171/* get the vpe associated with this minor */ 73/* get the vpe associated with this minor */
172static struct tc *get_tc(int index) 74struct tc *get_tc(int index)
173{ 75{
174 struct tc *res, *t; 76 struct tc *res, *t;
175 77
@@ -187,12 +89,13 @@ static struct tc *get_tc(int index)
187} 89}
188 90
189/* allocate a vpe and associate it with this minor (or index) */ 91/* allocate a vpe and associate it with this minor (or index) */
190static struct vpe *alloc_vpe(int minor) 92struct vpe *alloc_vpe(int minor)
191{ 93{
192 struct vpe *v; 94 struct vpe *v;
193 95
194 if ((v = kzalloc(sizeof(struct vpe), GFP_KERNEL)) == NULL) 96 v = kzalloc(sizeof(struct vpe), GFP_KERNEL);
195 return NULL; 97 if (v == NULL)
98 goto out;
196 99
197 INIT_LIST_HEAD(&v->tc); 100 INIT_LIST_HEAD(&v->tc);
198 spin_lock(&vpecontrol.vpe_list_lock); 101 spin_lock(&vpecontrol.vpe_list_lock);
@@ -200,17 +103,19 @@ static struct vpe *alloc_vpe(int minor)
200 spin_unlock(&vpecontrol.vpe_list_lock); 103 spin_unlock(&vpecontrol.vpe_list_lock);
201 104
202 INIT_LIST_HEAD(&v->notify); 105 INIT_LIST_HEAD(&v->notify);
203 v->minor = minor; 106 v->minor = VPE_MODULE_MINOR;
204 107
108out:
205 return v; 109 return v;
206} 110}
207 111
208/* allocate a tc. At startup only tc0 is running, all other can be halted. */ 112/* allocate a tc. At startup only tc0 is running, all other can be halted. */
209static struct tc *alloc_tc(int index) 113struct tc *alloc_tc(int index)
210{ 114{
211 struct tc *tc; 115 struct tc *tc;
212 116
213 if ((tc = kzalloc(sizeof(struct tc), GFP_KERNEL)) == NULL) 117 tc = kzalloc(sizeof(struct tc), GFP_KERNEL);
118 if (tc == NULL)
214 goto out; 119 goto out;
215 120
216 INIT_LIST_HEAD(&tc->tc); 121 INIT_LIST_HEAD(&tc->tc);
@@ -225,7 +130,7 @@ out:
225} 130}
226 131
227/* clean up and free everything */ 132/* clean up and free everything */
228static void release_vpe(struct vpe *v) 133void release_vpe(struct vpe *v)
229{ 134{
230 list_del(&v->list); 135 list_del(&v->list);
231 if (v->load_addr) 136 if (v->load_addr)
@@ -233,28 +138,8 @@ static void release_vpe(struct vpe *v)
233 kfree(v); 138 kfree(v);
234} 139}
235 140
236static void __maybe_unused dump_mtregs(void) 141/* Find some VPE program space */
237{ 142void *alloc_progmem(unsigned long len)
238 unsigned long val;
239
240 val = read_c0_config3();
241 printk("config3 0x%lx MT %ld\n", val,
242 (val & CONFIG3_MT) >> CONFIG3_MT_SHIFT);
243
244 val = read_c0_mvpcontrol();
245 printk("MVPControl 0x%lx, STLB %ld VPC %ld EVP %ld\n", val,
246 (val & MVPCONTROL_STLB) >> MVPCONTROL_STLB_SHIFT,
247 (val & MVPCONTROL_VPC) >> MVPCONTROL_VPC_SHIFT,
248 (val & MVPCONTROL_EVP));
249
250 val = read_c0_mvpconf0();
251 printk("mvpconf0 0x%lx, PVPE %ld PTC %ld M %ld\n", val,
252 (val & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT,
253 val & MVPCONF0_PTC, (val & MVPCONF0_M) >> MVPCONF0_M_SHIFT);
254}
255
256/* Find some VPE program space */
257static void *alloc_progmem(unsigned long len)
258{ 143{
259 void *addr; 144 void *addr;
260 145
@@ -273,7 +158,7 @@ static void *alloc_progmem(unsigned long len)
273 return addr; 158 return addr;
274} 159}
275 160
276static void release_progmem(void *ptr) 161void release_progmem(void *ptr)
277{ 162{
278#ifndef CONFIG_MIPS_VPE_LOADER_TOM 163#ifndef CONFIG_MIPS_VPE_LOADER_TOM
279 kfree(ptr); 164 kfree(ptr);
@@ -281,7 +166,7 @@ static void release_progmem(void *ptr)
281} 166}
282 167
283/* Update size with this section: return offset. */ 168/* Update size with this section: return offset. */
284static long get_offset(unsigned long *size, Elf_Shdr * sechdr) 169static long get_offset(unsigned long *size, Elf_Shdr *sechdr)
285{ 170{
286 long ret; 171 long ret;
287 172
@@ -294,8 +179,8 @@ static long get_offset(unsigned long *size, Elf_Shdr * sechdr)
294 might -- code, read-only data, read-write data, small data. Tally 179 might -- code, read-only data, read-write data, small data. Tally
295 sizes, and place the offsets into sh_entsize fields: high bit means it 180 sizes, and place the offsets into sh_entsize fields: high bit means it
296 belongs in init. */ 181 belongs in init. */
297static void layout_sections(struct module *mod, const Elf_Ehdr * hdr, 182static void layout_sections(struct module *mod, const Elf_Ehdr *hdr,
298 Elf_Shdr * sechdrs, const char *secstrings) 183 Elf_Shdr *sechdrs, const char *secstrings)
299{ 184{
300 static unsigned long const masks[][2] = { 185 static unsigned long const masks[][2] = {
301 /* NOTE: all executable code must be the first section 186 /* NOTE: all executable code must be the first section
@@ -315,7 +200,6 @@ static void layout_sections(struct module *mod, const Elf_Ehdr * hdr,
315 for (i = 0; i < hdr->e_shnum; ++i) { 200 for (i = 0; i < hdr->e_shnum; ++i) {
316 Elf_Shdr *s = &sechdrs[i]; 201 Elf_Shdr *s = &sechdrs[i];
317 202
318 // || strncmp(secstrings + s->sh_name, ".init", 5) == 0)
319 if ((s->sh_flags & masks[m][0]) != masks[m][0] 203 if ((s->sh_flags & masks[m][0]) != masks[m][0]
320 || (s->sh_flags & masks[m][1]) 204 || (s->sh_flags & masks[m][1])
321 || s->sh_entsize != ~0UL) 205 || s->sh_entsize != ~0UL)
@@ -330,7 +214,6 @@ static void layout_sections(struct module *mod, const Elf_Ehdr * hdr,
330 } 214 }
331} 215}
332 216
333
334/* from module-elf32.c, but subverted a little */ 217/* from module-elf32.c, but subverted a little */
335 218
336struct mips_hi16 { 219struct mips_hi16 {
@@ -353,20 +236,18 @@ static int apply_r_mips_gprel16(struct module *me, uint32_t *location,
353{ 236{
354 int rel; 237 int rel;
355 238
356 if( !(*location & 0xffff) ) { 239 if (!(*location & 0xffff)) {
357 rel = (int)v - gp_addr; 240 rel = (int)v - gp_addr;
358 } 241 } else {
359 else {
360 /* .sbss + gp(relative) + offset */ 242 /* .sbss + gp(relative) + offset */
361 /* kludge! */ 243 /* kludge! */
362 rel = (int)(short)((int)v + gp_offs + 244 rel = (int)(short)((int)v + gp_offs +
363 (int)(short)(*location & 0xffff) - gp_addr); 245 (int)(short)(*location & 0xffff) - gp_addr);
364 } 246 }
365 247
366 if( (rel > 32768) || (rel < -32768) ) { 248 if ((rel > 32768) || (rel < -32768)) {
367 printk(KERN_DEBUG "VPE loader: apply_r_mips_gprel16: " 249 pr_debug("VPE loader: apply_r_mips_gprel16: relative address 0x%x out of range of gp register\n",
368 "relative address 0x%x out of range of gp register\n", 250 rel);
369 rel);
370 return -ENOEXEC; 251 return -ENOEXEC;
371 } 252 }
372 253
@@ -380,12 +261,12 @@ static int apply_r_mips_pc16(struct module *me, uint32_t *location,
380{ 261{
381 int rel; 262 int rel;
382 rel = (((unsigned int)v - (unsigned int)location)); 263 rel = (((unsigned int)v - (unsigned int)location));
383 rel >>= 2; // because the offset is in _instructions_ not bytes. 264 rel >>= 2; /* because the offset is in _instructions_ not bytes. */
384 rel -= 1; // and one instruction less due to the branch delay slot. 265 rel -= 1; /* and one instruction less due to the branch delay slot. */
385 266
386 if( (rel > 32768) || (rel < -32768) ) { 267 if ((rel > 32768) || (rel < -32768)) {
387 printk(KERN_DEBUG "VPE loader: " 268 pr_debug("VPE loader: apply_r_mips_pc16: relative address out of range 0x%x\n",
388 "apply_r_mips_pc16: relative address out of range 0x%x\n", rel); 269 rel);
389 return -ENOEXEC; 270 return -ENOEXEC;
390 } 271 }
391 272
@@ -406,8 +287,7 @@ static int apply_r_mips_26(struct module *me, uint32_t *location,
406 Elf32_Addr v) 287 Elf32_Addr v)
407{ 288{
408 if (v % 4) { 289 if (v % 4) {
409 printk(KERN_DEBUG "VPE loader: apply_r_mips_26 " 290 pr_debug("VPE loader: apply_r_mips_26: unaligned relocation\n");
410 " unaligned relocation\n");
411 return -ENOEXEC; 291 return -ENOEXEC;
412 } 292 }
413 293
@@ -438,7 +318,7 @@ static int apply_r_mips_hi16(struct module *me, uint32_t *location,
438 * the carry we need to add. Save the information, and let LO16 do the 318 * the carry we need to add. Save the information, and let LO16 do the
439 * actual relocation. 319 * actual relocation.
440 */ 320 */
441 n = kmalloc(sizeof *n, GFP_KERNEL); 321 n = kmalloc(sizeof(*n), GFP_KERNEL);
442 if (!n) 322 if (!n)
443 return -ENOMEM; 323 return -ENOMEM;
444 324
@@ -470,9 +350,7 @@ static int apply_r_mips_lo16(struct module *me, uint32_t *location,
470 * The value for the HI16 had best be the same. 350 * The value for the HI16 had best be the same.
471 */ 351 */
472 if (v != l->value) { 352 if (v != l->value) {
473 printk(KERN_DEBUG "VPE loader: " 353 pr_debug("VPE loader: apply_r_mips_lo16/hi16: inconsistent value information\n");
474 "apply_r_mips_lo16/hi16: \t"
475 "inconsistent value information\n");
476 goto out_free; 354 goto out_free;
477 } 355 }
478 356
@@ -568,20 +446,19 @@ static int apply_relocations(Elf32_Shdr *sechdrs,
568 + ELF32_R_SYM(r_info); 446 + ELF32_R_SYM(r_info);
569 447
570 if (!sym->st_value) { 448 if (!sym->st_value) {
571 printk(KERN_DEBUG "%s: undefined weak symbol %s\n", 449 pr_debug("%s: undefined weak symbol %s\n",
572 me->name, strtab + sym->st_name); 450 me->name, strtab + sym->st_name);
573 /* just print the warning, dont barf */ 451 /* just print the warning, dont barf */
574 } 452 }
575 453
576 v = sym->st_value; 454 v = sym->st_value;
577 455
578 res = reloc_handlers[ELF32_R_TYPE(r_info)](me, location, v); 456 res = reloc_handlers[ELF32_R_TYPE(r_info)](me, location, v);
579 if( res ) { 457 if (res) {
580 char *r = rstrs[ELF32_R_TYPE(r_info)]; 458 char *r = rstrs[ELF32_R_TYPE(r_info)];
581 printk(KERN_WARNING "VPE loader: .text+0x%x " 459 pr_warn("VPE loader: .text+0x%x relocation type %s for symbol \"%s\" failed\n",
582 "relocation type %s for symbol \"%s\" failed\n", 460 rel[i].r_offset, r ? r : "UNKNOWN",
583 rel[i].r_offset, r ? r : "UNKNOWN", 461 strtab + sym->st_name);
584 strtab + sym->st_name);
585 return res; 462 return res;
586 } 463 }
587 } 464 }
@@ -596,10 +473,8 @@ static inline void save_gp_address(unsigned int secbase, unsigned int rel)
596} 473}
597/* end module-elf32.c */ 474/* end module-elf32.c */
598 475
599
600
601/* Change all symbols so that sh_value encodes the pointer directly. */ 476/* Change all symbols so that sh_value encodes the pointer directly. */
602static void simplify_symbols(Elf_Shdr * sechdrs, 477static void simplify_symbols(Elf_Shdr *sechdrs,
603 unsigned int symindex, 478 unsigned int symindex,
604 const char *strtab, 479 const char *strtab,
605 const char *secstrings, 480 const char *secstrings,
@@ -640,18 +515,16 @@ static void simplify_symbols(Elf_Shdr * sechdrs,
640 break; 515 break;
641 516
642 case SHN_MIPS_SCOMMON: 517 case SHN_MIPS_SCOMMON:
643 printk(KERN_DEBUG "simplify_symbols: ignoring SHN_MIPS_SCOMMON " 518 pr_debug("simplify_symbols: ignoring SHN_MIPS_SCOMMON symbol <%s> st_shndx %d\n",
644 "symbol <%s> st_shndx %d\n", strtab + sym[i].st_name, 519 strtab + sym[i].st_name, sym[i].st_shndx);
645 sym[i].st_shndx); 520 /* .sbss section */
646 // .sbss section
647 break; 521 break;
648 522
649 default: 523 default:
650 secbase = sechdrs[sym[i].st_shndx].sh_addr; 524 secbase = sechdrs[sym[i].st_shndx].sh_addr;
651 525
652 if (strncmp(strtab + sym[i].st_name, "_gp", 3) == 0) { 526 if (strncmp(strtab + sym[i].st_name, "_gp", 3) == 0)
653 save_gp_address(secbase, sym[i].st_value); 527 save_gp_address(secbase, sym[i].st_value);
654 }
655 528
656 sym[i].st_value += secbase; 529 sym[i].st_value += secbase;
657 break; 530 break;
@@ -660,142 +533,21 @@ static void simplify_symbols(Elf_Shdr * sechdrs,
660} 533}
661 534
662#ifdef DEBUG_ELFLOADER 535#ifdef DEBUG_ELFLOADER
663static void dump_elfsymbols(Elf_Shdr * sechdrs, unsigned int symindex, 536static void dump_elfsymbols(Elf_Shdr *sechdrs, unsigned int symindex,
664 const char *strtab, struct module *mod) 537 const char *strtab, struct module *mod)
665{ 538{
666 Elf_Sym *sym = (void *)sechdrs[symindex].sh_addr; 539 Elf_Sym *sym = (void *)sechdrs[symindex].sh_addr;
667 unsigned int i, n = sechdrs[symindex].sh_size / sizeof(Elf_Sym); 540 unsigned int i, n = sechdrs[symindex].sh_size / sizeof(Elf_Sym);
668 541
669 printk(KERN_DEBUG "dump_elfsymbols: n %d\n", n); 542 pr_debug("dump_elfsymbols: n %d\n", n);
670 for (i = 1; i < n; i++) { 543 for (i = 1; i < n; i++) {
671 printk(KERN_DEBUG " i %d name <%s> 0x%x\n", i, 544 pr_debug(" i %d name <%s> 0x%x\n", i, strtab + sym[i].st_name,
672 strtab + sym[i].st_name, sym[i].st_value); 545 sym[i].st_value);
673 } 546 }
674} 547}
675#endif 548#endif
676 549
677/* We are prepared so configure and start the VPE... */ 550static int find_vpe_symbols(struct vpe *v, Elf_Shdr *sechdrs,
678static int vpe_run(struct vpe * v)
679{
680 unsigned long flags, val, dmt_flag;
681 struct vpe_notifications *n;
682 unsigned int vpeflags;
683 struct tc *t;
684
685 /* check we are the Master VPE */
686 local_irq_save(flags);
687 val = read_c0_vpeconf0();
688 if (!(val & VPECONF0_MVP)) {
689 printk(KERN_WARNING
690 "VPE loader: only Master VPE's are allowed to configure MT\n");
691 local_irq_restore(flags);
692
693 return -1;
694 }
695
696 dmt_flag = dmt();
697 vpeflags = dvpe();
698
699 if (list_empty(&v->tc)) {
700 evpe(vpeflags);
701 emt(dmt_flag);
702 local_irq_restore(flags);
703
704 printk(KERN_WARNING
705 "VPE loader: No TC's associated with VPE %d\n",
706 v->minor);
707
708 return -ENOEXEC;
709 }
710
711 t = list_first_entry(&v->tc, struct tc, tc);
712
713 /* Put MVPE's into 'configuration state' */
714 set_c0_mvpcontrol(MVPCONTROL_VPC);
715
716 settc(t->index);
717
718 /* should check it is halted, and not activated */
719 if ((read_tc_c0_tcstatus() & TCSTATUS_A) || !(read_tc_c0_tchalt() & TCHALT_H)) {
720 evpe(vpeflags);
721 emt(dmt_flag);
722 local_irq_restore(flags);
723
724 printk(KERN_WARNING "VPE loader: TC %d is already active!\n",
725 t->index);
726
727 return -ENOEXEC;
728 }
729
730 /* Write the address we want it to start running from in the TCPC register. */
731 write_tc_c0_tcrestart((unsigned long)v->__start);
732 write_tc_c0_tccontext((unsigned long)0);
733
734 /*
735 * Mark the TC as activated, not interrupt exempt and not dynamically
736 * allocatable
737 */
738 val = read_tc_c0_tcstatus();
739 val = (val & ~(TCSTATUS_DA | TCSTATUS_IXMT)) | TCSTATUS_A;
740 write_tc_c0_tcstatus(val);
741
742 write_tc_c0_tchalt(read_tc_c0_tchalt() & ~TCHALT_H);
743
744 /*
745 * The sde-kit passes 'memsize' to __start in $a3, so set something
746 * here... Or set $a3 to zero and define DFLT_STACK_SIZE and
747 * DFLT_HEAP_SIZE when you compile your program
748 */
749 mttgpr(6, v->ntcs);
750 mttgpr(7, physical_memsize);
751
752 /* set up VPE1 */
753 /*
754 * bind the TC to VPE 1 as late as possible so we only have the final
755 * VPE registers to set up, and so an EJTAG probe can trigger on it
756 */
757 write_tc_c0_tcbind((read_tc_c0_tcbind() & ~TCBIND_CURVPE) | 1);
758
759 write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() & ~(VPECONF0_VPA));
760
761 back_to_back_c0_hazard();
762
763 /* Set up the XTC bit in vpeconf0 to point at our tc */
764 write_vpe_c0_vpeconf0( (read_vpe_c0_vpeconf0() & ~(VPECONF0_XTC))
765 | (t->index << VPECONF0_XTC_SHIFT));
766
767 back_to_back_c0_hazard();
768
769 /* enable this VPE */
770 write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() | VPECONF0_VPA);
771
772 /* clear out any left overs from a previous program */
773 write_vpe_c0_status(0);
774 write_vpe_c0_cause(0);
775
776 /* take system out of configuration state */
777 clear_c0_mvpcontrol(MVPCONTROL_VPC);
778
779 /*
780 * SMTC/SMVP kernels manage VPE enable independently,
781 * but uniprocessor kernels need to turn it on, even
782 * if that wasn't the pre-dvpe() state.
783 */
784#ifdef CONFIG_SMP
785 evpe(vpeflags);
786#else
787 evpe(EVPE_ENABLE);
788#endif
789 emt(dmt_flag);
790 local_irq_restore(flags);
791
792 list_for_each_entry(n, &v->notify, list)
793 n->start(minor);
794
795 return 0;
796}
797
798static int find_vpe_symbols(struct vpe * v, Elf_Shdr * sechdrs,
799 unsigned int symindex, const char *strtab, 551 unsigned int symindex, const char *strtab,
800 struct module *mod) 552 struct module *mod)
801{ 553{
@@ -803,16 +555,14 @@ static int find_vpe_symbols(struct vpe * v, Elf_Shdr * sechdrs,
803 unsigned int i, n = sechdrs[symindex].sh_size / sizeof(Elf_Sym); 555 unsigned int i, n = sechdrs[symindex].sh_size / sizeof(Elf_Sym);
804 556
805 for (i = 1; i < n; i++) { 557 for (i = 1; i < n; i++) {
806 if (strcmp(strtab + sym[i].st_name, "__start") == 0) { 558 if (strcmp(strtab + sym[i].st_name, "__start") == 0)
807 v->__start = sym[i].st_value; 559 v->__start = sym[i].st_value;
808 }
809 560
810 if (strcmp(strtab + sym[i].st_name, "vpe_shared") == 0) { 561 if (strcmp(strtab + sym[i].st_name, "vpe_shared") == 0)
811 v->shared_ptr = (void *)sym[i].st_value; 562 v->shared_ptr = (void *)sym[i].st_value;
812 }
813 } 563 }
814 564
815 if ( (v->__start == 0) || (v->shared_ptr == NULL)) 565 if ((v->__start == 0) || (v->shared_ptr == NULL))
816 return -1; 566 return -1;
817 567
818 return 0; 568 return 0;
@@ -823,14 +573,14 @@ static int find_vpe_symbols(struct vpe * v, Elf_Shdr * sechdrs,
823 * contents of the program (p)buffer performing relocatations/etc, free's it 573 * contents of the program (p)buffer performing relocatations/etc, free's it
824 * when finished. 574 * when finished.
825 */ 575 */
826static int vpe_elfload(struct vpe * v) 576static int vpe_elfload(struct vpe *v)
827{ 577{
828 Elf_Ehdr *hdr; 578 Elf_Ehdr *hdr;
829 Elf_Shdr *sechdrs; 579 Elf_Shdr *sechdrs;
830 long err = 0; 580 long err = 0;
831 char *secstrings, *strtab = NULL; 581 char *secstrings, *strtab = NULL;
832 unsigned int len, i, symindex = 0, strindex = 0, relocate = 0; 582 unsigned int len, i, symindex = 0, strindex = 0, relocate = 0;
833 struct module mod; // so we can re-use the relocations code 583 struct module mod; /* so we can re-use the relocations code */
834 584
835 memset(&mod, 0, sizeof(struct module)); 585 memset(&mod, 0, sizeof(struct module));
836 strcpy(mod.name, "VPE loader"); 586 strcpy(mod.name, "VPE loader");
@@ -844,8 +594,7 @@ static int vpe_elfload(struct vpe * v)
844 || (hdr->e_type != ET_REL && hdr->e_type != ET_EXEC) 594 || (hdr->e_type != ET_REL && hdr->e_type != ET_EXEC)
845 || !elf_check_arch(hdr) 595 || !elf_check_arch(hdr)
846 || hdr->e_shentsize != sizeof(*sechdrs)) { 596 || hdr->e_shentsize != sizeof(*sechdrs)) {
847 printk(KERN_WARNING 597 pr_warn("VPE loader: program wrong arch or weird elf version\n");
848 "VPE loader: program wrong arch or weird elf version\n");
849 598
850 return -ENOEXEC; 599 return -ENOEXEC;
851 } 600 }
@@ -854,8 +603,7 @@ static int vpe_elfload(struct vpe * v)
854 relocate = 1; 603 relocate = 1;
855 604
856 if (len < hdr->e_shoff + hdr->e_shnum * sizeof(Elf_Shdr)) { 605 if (len < hdr->e_shoff + hdr->e_shnum * sizeof(Elf_Shdr)) {
857 printk(KERN_ERR "VPE loader: program length %u truncated\n", 606 pr_err("VPE loader: program length %u truncated\n", len);
858 len);
859 607
860 return -ENOEXEC; 608 return -ENOEXEC;
861 } 609 }
@@ -870,22 +618,24 @@ static int vpe_elfload(struct vpe * v)
870 618
871 if (relocate) { 619 if (relocate) {
872 for (i = 1; i < hdr->e_shnum; i++) { 620 for (i = 1; i < hdr->e_shnum; i++) {
873 if (sechdrs[i].sh_type != SHT_NOBITS 621 if ((sechdrs[i].sh_type != SHT_NOBITS) &&
874 && len < sechdrs[i].sh_offset + sechdrs[i].sh_size) { 622 (len < sechdrs[i].sh_offset + sechdrs[i].sh_size)) {
875 printk(KERN_ERR "VPE program length %u truncated\n", 623 pr_err("VPE program length %u truncated\n",
876 len); 624 len);
877 return -ENOEXEC; 625 return -ENOEXEC;
878 } 626 }
879 627
880 /* Mark all sections sh_addr with their address in the 628 /* Mark all sections sh_addr with their address in the
881 temporary image. */ 629 temporary image. */
882 sechdrs[i].sh_addr = (size_t) hdr + sechdrs[i].sh_offset; 630 sechdrs[i].sh_addr = (size_t) hdr +
631 sechdrs[i].sh_offset;
883 632
884 /* Internal symbols and strings. */ 633 /* Internal symbols and strings. */
885 if (sechdrs[i].sh_type == SHT_SYMTAB) { 634 if (sechdrs[i].sh_type == SHT_SYMTAB) {
886 symindex = i; 635 symindex = i;
887 strindex = sechdrs[i].sh_link; 636 strindex = sechdrs[i].sh_link;
888 strtab = (char *)hdr + sechdrs[strindex].sh_offset; 637 strtab = (char *)hdr +
638 sechdrs[strindex].sh_offset;
889 } 639 }
890 } 640 }
891 layout_sections(&mod, hdr, sechdrs, secstrings); 641 layout_sections(&mod, hdr, sechdrs, secstrings);
@@ -912,8 +662,9 @@ static int vpe_elfload(struct vpe * v)
912 /* Update sh_addr to point to copy in image. */ 662 /* Update sh_addr to point to copy in image. */
913 sechdrs[i].sh_addr = (unsigned long)dest; 663 sechdrs[i].sh_addr = (unsigned long)dest;
914 664
915 printk(KERN_DEBUG " section sh_name %s sh_addr 0x%x\n", 665 pr_debug(" section sh_name %s sh_addr 0x%x\n",
916 secstrings + sechdrs[i].sh_name, sechdrs[i].sh_addr); 666 secstrings + sechdrs[i].sh_name,
667 sechdrs[i].sh_addr);
917 } 668 }
918 669
919 /* Fix up syms, so that st_value is a pointer to location. */ 670 /* Fix up syms, so that st_value is a pointer to location. */
@@ -934,17 +685,18 @@ static int vpe_elfload(struct vpe * v)
934 continue; 685 continue;
935 686
936 if (sechdrs[i].sh_type == SHT_REL) 687 if (sechdrs[i].sh_type == SHT_REL)
937 err = apply_relocations(sechdrs, strtab, symindex, i, 688 err = apply_relocations(sechdrs, strtab,
938 &mod); 689 symindex, i, &mod);
939 else if (sechdrs[i].sh_type == SHT_RELA) 690 else if (sechdrs[i].sh_type == SHT_RELA)
940 err = apply_relocate_add(sechdrs, strtab, symindex, i, 691 err = apply_relocate_add(sechdrs, strtab,
941 &mod); 692 symindex, i, &mod);
942 if (err < 0) 693 if (err < 0)
943 return err; 694 return err;
944 695
945 } 696 }
946 } else { 697 } else {
947 struct elf_phdr *phdr = (struct elf_phdr *) ((char *)hdr + hdr->e_phoff); 698 struct elf_phdr *phdr = (struct elf_phdr *)
699 ((char *)hdr + hdr->e_phoff);
948 700
949 for (i = 0; i < hdr->e_phnum; i++) { 701 for (i = 0; i < hdr->e_phnum; i++) {
950 if (phdr->p_type == PT_LOAD) { 702 if (phdr->p_type == PT_LOAD) {
@@ -962,11 +714,15 @@ static int vpe_elfload(struct vpe * v)
962 if (sechdrs[i].sh_type == SHT_SYMTAB) { 714 if (sechdrs[i].sh_type == SHT_SYMTAB) {
963 symindex = i; 715 symindex = i;
964 strindex = sechdrs[i].sh_link; 716 strindex = sechdrs[i].sh_link;
965 strtab = (char *)hdr + sechdrs[strindex].sh_offset; 717 strtab = (char *)hdr +
718 sechdrs[strindex].sh_offset;
966 719
967 /* mark the symtab's address for when we try to find the 720 /*
968 magic symbols */ 721 * mark symtab's address for when we try
969 sechdrs[i].sh_addr = (size_t) hdr + sechdrs[i].sh_offset; 722 * to find the magic symbols
723 */
724 sechdrs[i].sh_addr = (size_t) hdr +
725 sechdrs[i].sh_offset;
970 } 726 }
971 } 727 }
972 } 728 }
@@ -977,53 +733,19 @@ static int vpe_elfload(struct vpe * v)
977 733
978 if ((find_vpe_symbols(v, sechdrs, symindex, strtab, &mod)) < 0) { 734 if ((find_vpe_symbols(v, sechdrs, symindex, strtab, &mod)) < 0) {
979 if (v->__start == 0) { 735 if (v->__start == 0) {
980 printk(KERN_WARNING "VPE loader: program does not contain " 736 pr_warn("VPE loader: program does not contain a __start symbol\n");
981 "a __start symbol\n");
982 return -ENOEXEC; 737 return -ENOEXEC;
983 } 738 }
984 739
985 if (v->shared_ptr == NULL) 740 if (v->shared_ptr == NULL)
986 printk(KERN_WARNING "VPE loader: " 741 pr_warn("VPE loader: program does not contain vpe_shared symbol.\n"
987 "program does not contain vpe_shared symbol.\n" 742 " Unable to use AMVP (AP/SP) facilities.\n");
988 " Unable to use AMVP (AP/SP) facilities.\n");
989 } 743 }
990 744
991 printk(" elf loaded\n"); 745 pr_info(" elf loaded\n");
992 return 0; 746 return 0;
993} 747}
994 748
995static void cleanup_tc(struct tc *tc)
996{
997 unsigned long flags;
998 unsigned int mtflags, vpflags;
999 int tmp;
1000
1001 local_irq_save(flags);
1002 mtflags = dmt();
1003 vpflags = dvpe();
1004 /* Put MVPE's into 'configuration state' */
1005 set_c0_mvpcontrol(MVPCONTROL_VPC);
1006
1007 settc(tc->index);
1008 tmp = read_tc_c0_tcstatus();
1009
1010 /* mark not allocated and not dynamically allocatable */
1011 tmp &= ~(TCSTATUS_A | TCSTATUS_DA);
1012 tmp |= TCSTATUS_IXMT; /* interrupt exempt */
1013 write_tc_c0_tcstatus(tmp);
1014
1015 write_tc_c0_tchalt(TCHALT_H);
1016 mips_ihb();
1017
1018 /* bind it to anything other than VPE1 */
1019// write_tc_c0_tcbind(read_tc_c0_tcbind() & ~TCBIND_CURVPE); // | TCBIND_CURVPE
1020
1021 clear_c0_mvpcontrol(MVPCONTROL_VPC);
1022 evpe(vpflags);
1023 emt(mtflags);
1024 local_irq_restore(flags);
1025}
1026
1027static int getcwd(char *buff, int size) 749static int getcwd(char *buff, int size)
1028{ 750{
1029 mm_segment_t old_fs; 751 mm_segment_t old_fs;
@@ -1043,39 +765,39 @@ static int getcwd(char *buff, int size)
1043static int vpe_open(struct inode *inode, struct file *filp) 765static int vpe_open(struct inode *inode, struct file *filp)
1044{ 766{
1045 enum vpe_state state; 767 enum vpe_state state;
1046 struct vpe_notifications *not; 768 struct vpe_notifications *notifier;
1047 struct vpe *v; 769 struct vpe *v;
1048 int ret; 770 int ret;
1049 771
1050 if (minor != iminor(inode)) { 772 if (VPE_MODULE_MINOR != iminor(inode)) {
1051 /* assume only 1 device at the moment. */ 773 /* assume only 1 device at the moment. */
1052 pr_warning("VPE loader: only vpe1 is supported\n"); 774 pr_warn("VPE loader: only vpe1 is supported\n");
1053 775
1054 return -ENODEV; 776 return -ENODEV;
1055 } 777 }
1056 778
1057 if ((v = get_vpe(tclimit)) == NULL) { 779 v = get_vpe(aprp_cpu_index());
1058 pr_warning("VPE loader: unable to get vpe\n"); 780 if (v == NULL) {
781 pr_warn("VPE loader: unable to get vpe\n");
1059 782
1060 return -ENODEV; 783 return -ENODEV;
1061 } 784 }
1062 785
1063 state = xchg(&v->state, VPE_STATE_INUSE); 786 state = xchg(&v->state, VPE_STATE_INUSE);
1064 if (state != VPE_STATE_UNUSED) { 787 if (state != VPE_STATE_UNUSED) {
1065 printk(KERN_DEBUG "VPE loader: tc in use dumping regs\n"); 788 pr_debug("VPE loader: tc in use dumping regs\n");
1066 789
1067 list_for_each_entry(not, &v->notify, list) { 790 list_for_each_entry(notifier, &v->notify, list)
1068 not->stop(tclimit); 791 notifier->stop(aprp_cpu_index());
1069 }
1070 792
1071 release_progmem(v->load_addr); 793 release_progmem(v->load_addr);
1072 cleanup_tc(get_tc(tclimit)); 794 cleanup_tc(get_tc(aprp_cpu_index()));
1073 } 795 }
1074 796
1075 /* this of-course trashes what was there before... */ 797 /* this of-course trashes what was there before... */
1076 v->pbuffer = vmalloc(P_SIZE); 798 v->pbuffer = vmalloc(P_SIZE);
1077 if (!v->pbuffer) { 799 if (!v->pbuffer) {
1078 pr_warning("VPE loader: unable to allocate memory\n"); 800 pr_warn("VPE loader: unable to allocate memory\n");
1079 return -ENOMEM; 801 return -ENOMEM;
1080 } 802 }
1081 v->plen = P_SIZE; 803 v->plen = P_SIZE;
@@ -1085,7 +807,7 @@ static int vpe_open(struct inode *inode, struct file *filp)
1085 v->cwd[0] = 0; 807 v->cwd[0] = 0;
1086 ret = getcwd(v->cwd, VPE_PATH_MAX); 808 ret = getcwd(v->cwd, VPE_PATH_MAX);
1087 if (ret < 0) 809 if (ret < 0)
1088 printk(KERN_WARNING "VPE loader: open, getcwd returned %d\n", ret); 810 pr_warn("VPE loader: open, getcwd returned %d\n", ret);
1089 811
1090 v->shared_ptr = NULL; 812 v->shared_ptr = NULL;
1091 v->__start = 0; 813 v->__start = 0;
@@ -1099,20 +821,20 @@ static int vpe_release(struct inode *inode, struct file *filp)
1099 Elf_Ehdr *hdr; 821 Elf_Ehdr *hdr;
1100 int ret = 0; 822 int ret = 0;
1101 823
1102 v = get_vpe(tclimit); 824 v = get_vpe(aprp_cpu_index());
1103 if (v == NULL) 825 if (v == NULL)
1104 return -ENODEV; 826 return -ENODEV;
1105 827
1106 hdr = (Elf_Ehdr *) v->pbuffer; 828 hdr = (Elf_Ehdr *) v->pbuffer;
1107 if (memcmp(hdr->e_ident, ELFMAG, SELFMAG) == 0) { 829 if (memcmp(hdr->e_ident, ELFMAG, SELFMAG) == 0) {
1108 if (vpe_elfload(v) >= 0) { 830 if ((vpe_elfload(v) >= 0) && vpe_run) {
1109 vpe_run(v); 831 vpe_run(v);
1110 } else { 832 } else {
1111 printk(KERN_WARNING "VPE loader: ELF load failed.\n"); 833 pr_warn("VPE loader: ELF load failed.\n");
1112 ret = -ENOEXEC; 834 ret = -ENOEXEC;
1113 } 835 }
1114 } else { 836 } else {
1115 printk(KERN_WARNING "VPE loader: only elf files are supported\n"); 837 pr_warn("VPE loader: only elf files are supported\n");
1116 ret = -ENOEXEC; 838 ret = -ENOEXEC;
1117 } 839 }
1118 840
@@ -1130,22 +852,22 @@ static int vpe_release(struct inode *inode, struct file *filp)
1130 return ret; 852 return ret;
1131} 853}
1132 854
1133static ssize_t vpe_write(struct file *file, const char __user * buffer, 855static ssize_t vpe_write(struct file *file, const char __user *buffer,
1134 size_t count, loff_t * ppos) 856 size_t count, loff_t *ppos)
1135{ 857{
1136 size_t ret = count; 858 size_t ret = count;
1137 struct vpe *v; 859 struct vpe *v;
1138 860
1139 if (iminor(file_inode(file)) != minor) 861 if (iminor(file_inode(file)) != VPE_MODULE_MINOR)
1140 return -ENODEV; 862 return -ENODEV;
1141 863
1142 v = get_vpe(tclimit); 864 v = get_vpe(aprp_cpu_index());
865
1143 if (v == NULL) 866 if (v == NULL)
1144 return -ENODEV; 867 return -ENODEV;
1145 868
1146 if ((count + v->len) > v->plen) { 869 if ((count + v->len) > v->plen) {
1147 printk(KERN_WARNING 870 pr_warn("VPE loader: elf size too big. Perhaps strip uneeded symbols\n");
1148 "VPE loader: elf size too big. Perhaps strip uneeded symbols\n");
1149 return -ENOMEM; 871 return -ENOMEM;
1150 } 872 }
1151 873
@@ -1157,7 +879,7 @@ static ssize_t vpe_write(struct file *file, const char __user * buffer,
1157 return ret; 879 return ret;
1158} 880}
1159 881
1160static const struct file_operations vpe_fops = { 882const struct file_operations vpe_fops = {
1161 .owner = THIS_MODULE, 883 .owner = THIS_MODULE,
1162 .open = vpe_open, 884 .open = vpe_open,
1163 .release = vpe_release, 885 .release = vpe_release,
@@ -1165,396 +887,40 @@ static const struct file_operations vpe_fops = {
1165 .llseek = noop_llseek, 887 .llseek = noop_llseek,
1166}; 888};
1167 889
1168/* module wrapper entry points */
1169/* give me a vpe */
1170vpe_handle vpe_alloc(void)
1171{
1172 int i;
1173 struct vpe *v;
1174
1175 /* find a vpe */
1176 for (i = 1; i < MAX_VPES; i++) {
1177 if ((v = get_vpe(i)) != NULL) {
1178 v->state = VPE_STATE_INUSE;
1179 return v;
1180 }
1181 }
1182 return NULL;
1183}
1184
1185EXPORT_SYMBOL(vpe_alloc);
1186
1187/* start running from here */
1188int vpe_start(vpe_handle vpe, unsigned long start)
1189{
1190 struct vpe *v = vpe;
1191
1192 v->__start = start;
1193 return vpe_run(v);
1194}
1195
1196EXPORT_SYMBOL(vpe_start);
1197
1198/* halt it for now */
1199int vpe_stop(vpe_handle vpe)
1200{
1201 struct vpe *v = vpe;
1202 struct tc *t;
1203 unsigned int evpe_flags;
1204
1205 evpe_flags = dvpe();
1206
1207 if ((t = list_entry(v->tc.next, struct tc, tc)) != NULL) {
1208
1209 settc(t->index);
1210 write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() & ~VPECONF0_VPA);
1211 }
1212
1213 evpe(evpe_flags);
1214
1215 return 0;
1216}
1217
1218EXPORT_SYMBOL(vpe_stop);
1219
1220/* I've done with it thank you */
1221int vpe_free(vpe_handle vpe)
1222{
1223 struct vpe *v = vpe;
1224 struct tc *t;
1225 unsigned int evpe_flags;
1226
1227 if ((t = list_entry(v->tc.next, struct tc, tc)) == NULL) {
1228 return -ENOEXEC;
1229 }
1230
1231 evpe_flags = dvpe();
1232
1233 /* Put MVPE's into 'configuration state' */
1234 set_c0_mvpcontrol(MVPCONTROL_VPC);
1235
1236 settc(t->index);
1237 write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() & ~VPECONF0_VPA);
1238
1239 /* halt the TC */
1240 write_tc_c0_tchalt(TCHALT_H);
1241 mips_ihb();
1242
1243 /* mark the TC unallocated */
1244 write_tc_c0_tcstatus(read_tc_c0_tcstatus() & ~TCSTATUS_A);
1245
1246 v->state = VPE_STATE_UNUSED;
1247
1248 clear_c0_mvpcontrol(MVPCONTROL_VPC);
1249 evpe(evpe_flags);
1250
1251 return 0;
1252}
1253
1254EXPORT_SYMBOL(vpe_free);
1255
1256void *vpe_get_shared(int index) 890void *vpe_get_shared(int index)
1257{ 891{
1258 struct vpe *v; 892 struct vpe *v = get_vpe(index);
1259 893
1260 if ((v = get_vpe(index)) == NULL) 894 if (v == NULL)
1261 return NULL; 895 return NULL;
1262 896
1263 return v->shared_ptr; 897 return v->shared_ptr;
1264} 898}
1265
1266EXPORT_SYMBOL(vpe_get_shared); 899EXPORT_SYMBOL(vpe_get_shared);
1267 900
1268int vpe_notify(int index, struct vpe_notifications *notify) 901int vpe_notify(int index, struct vpe_notifications *notify)
1269{ 902{
1270 struct vpe *v; 903 struct vpe *v = get_vpe(index);
1271 904
1272 if ((v = get_vpe(index)) == NULL) 905 if (v == NULL)
1273 return -1; 906 return -1;
1274 907
1275 list_add(&notify->list, &v->notify); 908 list_add(&notify->list, &v->notify);
1276 return 0; 909 return 0;
1277} 910}
1278
1279EXPORT_SYMBOL(vpe_notify); 911EXPORT_SYMBOL(vpe_notify);
1280 912
1281char *vpe_getcwd(int index) 913char *vpe_getcwd(int index)
1282{ 914{
1283 struct vpe *v; 915 struct vpe *v = get_vpe(index);
1284 916
1285 if ((v = get_vpe(index)) == NULL) 917 if (v == NULL)
1286 return NULL; 918 return NULL;
1287 919
1288 return v->cwd; 920 return v->cwd;
1289} 921}
1290
1291EXPORT_SYMBOL(vpe_getcwd); 922EXPORT_SYMBOL(vpe_getcwd);
1292 923
1293static ssize_t store_kill(struct device *dev, struct device_attribute *attr,
1294 const char *buf, size_t len)
1295{
1296 struct vpe *vpe = get_vpe(tclimit);
1297 struct vpe_notifications *not;
1298
1299 list_for_each_entry(not, &vpe->notify, list) {
1300 not->stop(tclimit);
1301 }
1302
1303 release_progmem(vpe->load_addr);
1304 cleanup_tc(get_tc(tclimit));
1305 vpe_stop(vpe);
1306 vpe_free(vpe);
1307
1308 return len;
1309}
1310static DEVICE_ATTR(kill, S_IWUSR, NULL, store_kill);
1311
1312static ssize_t ntcs_show(struct device *cd, struct device_attribute *attr,
1313 char *buf)
1314{
1315 struct vpe *vpe = get_vpe(tclimit);
1316
1317 return sprintf(buf, "%d\n", vpe->ntcs);
1318}
1319
1320static ssize_t ntcs_store(struct device *dev, struct device_attribute *attr,
1321 const char *buf, size_t len)
1322{
1323 struct vpe *vpe = get_vpe(tclimit);
1324 unsigned long new;
1325 char *endp;
1326
1327 new = simple_strtoul(buf, &endp, 0);
1328 if (endp == buf)
1329 goto out_einval;
1330
1331 if (new == 0 || new > (hw_tcs - tclimit))
1332 goto out_einval;
1333
1334 vpe->ntcs = new;
1335
1336 return len;
1337
1338out_einval:
1339 return -EINVAL;
1340}
1341static DEVICE_ATTR_RW(ntcs);
1342
1343static struct attribute *vpe_attrs[] = {
1344 &dev_attr_kill.attr,
1345 &dev_attr_ntcs.attr,
1346 NULL,
1347};
1348ATTRIBUTE_GROUPS(vpe);
1349
1350static void vpe_device_release(struct device *cd)
1351{
1352 kfree(cd);
1353}
1354
1355struct class vpe_class = {
1356 .name = "vpe",
1357 .owner = THIS_MODULE,
1358 .dev_release = vpe_device_release,
1359 .dev_groups = vpe_groups,
1360};
1361
1362struct device vpe_device;
1363
1364static int __init vpe_module_init(void)
1365{
1366 unsigned int mtflags, vpflags;
1367 unsigned long flags, val;
1368 struct vpe *v = NULL;
1369 struct tc *t;
1370 int tc, err;
1371
1372 if (!cpu_has_mipsmt) {
1373 printk("VPE loader: not a MIPS MT capable processor\n");
1374 return -ENODEV;
1375 }
1376
1377 if (vpelimit == 0) {
1378 printk(KERN_WARNING "No VPEs reserved for AP/SP, not "
1379 "initializing VPE loader.\nPass maxvpes=<n> argument as "
1380 "kernel argument\n");
1381
1382 return -ENODEV;
1383 }
1384
1385 if (tclimit == 0) {
1386 printk(KERN_WARNING "No TCs reserved for AP/SP, not "
1387 "initializing VPE loader.\nPass maxtcs=<n> argument as "
1388 "kernel argument\n");
1389
1390 return -ENODEV;
1391 }
1392
1393 major = register_chrdev(0, module_name, &vpe_fops);
1394 if (major < 0) {
1395 printk("VPE loader: unable to register character device\n");
1396 return major;
1397 }
1398
1399 err = class_register(&vpe_class);
1400 if (err) {
1401 printk(KERN_ERR "vpe_class registration failed\n");
1402 goto out_chrdev;
1403 }
1404
1405 device_initialize(&vpe_device);
1406 vpe_device.class = &vpe_class,
1407 vpe_device.parent = NULL,
1408 dev_set_name(&vpe_device, "vpe1");
1409 vpe_device.devt = MKDEV(major, minor);
1410 err = device_add(&vpe_device);
1411 if (err) {
1412 printk(KERN_ERR "Adding vpe_device failed\n");
1413 goto out_class;
1414 }
1415
1416 local_irq_save(flags);
1417 mtflags = dmt();
1418 vpflags = dvpe();
1419
1420 /* Put MVPE's into 'configuration state' */
1421 set_c0_mvpcontrol(MVPCONTROL_VPC);
1422
1423 /* dump_mtregs(); */
1424
1425 val = read_c0_mvpconf0();
1426 hw_tcs = (val & MVPCONF0_PTC) + 1;
1427 hw_vpes = ((val & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT) + 1;
1428
1429 for (tc = tclimit; tc < hw_tcs; tc++) {
1430 /*
1431 * Must re-enable multithreading temporarily or in case we
1432 * reschedule send IPIs or similar we might hang.
1433 */
1434 clear_c0_mvpcontrol(MVPCONTROL_VPC);
1435 evpe(vpflags);
1436 emt(mtflags);
1437 local_irq_restore(flags);
1438 t = alloc_tc(tc);
1439 if (!t) {
1440 err = -ENOMEM;
1441 goto out;
1442 }
1443
1444 local_irq_save(flags);
1445 mtflags = dmt();
1446 vpflags = dvpe();
1447 set_c0_mvpcontrol(MVPCONTROL_VPC);
1448
1449 /* VPE's */
1450 if (tc < hw_tcs) {
1451 settc(tc);
1452
1453 if ((v = alloc_vpe(tc)) == NULL) {
1454 printk(KERN_WARNING "VPE: unable to allocate VPE\n");
1455
1456 goto out_reenable;
1457 }
1458
1459 v->ntcs = hw_tcs - tclimit;
1460
1461 /* add the tc to the list of this vpe's tc's. */
1462 list_add(&t->tc, &v->tc);
1463
1464 /* deactivate all but vpe0 */
1465 if (tc >= tclimit) {
1466 unsigned long tmp = read_vpe_c0_vpeconf0();
1467
1468 tmp &= ~VPECONF0_VPA;
1469
1470 /* master VPE */
1471 tmp |= VPECONF0_MVP;
1472 write_vpe_c0_vpeconf0(tmp);
1473 }
1474
1475 /* disable multi-threading with TC's */
1476 write_vpe_c0_vpecontrol(read_vpe_c0_vpecontrol() & ~VPECONTROL_TE);
1477
1478 if (tc >= vpelimit) {
1479 /*
1480 * Set config to be the same as vpe0,
1481 * particularly kseg0 coherency alg
1482 */
1483 write_vpe_c0_config(read_c0_config());
1484 }
1485 }
1486
1487 /* TC's */
1488 t->pvpe = v; /* set the parent vpe */
1489
1490 if (tc >= tclimit) {
1491 unsigned long tmp;
1492
1493 settc(tc);
1494
1495 /* Any TC that is bound to VPE0 gets left as is - in case
1496 we are running SMTC on VPE0. A TC that is bound to any
1497 other VPE gets bound to VPE0, ideally I'd like to make
1498 it homeless but it doesn't appear to let me bind a TC
1499 to a non-existent VPE. Which is perfectly reasonable.
1500
1501 The (un)bound state is visible to an EJTAG probe so may
1502 notify GDB...
1503 */
1504
1505 if (((tmp = read_tc_c0_tcbind()) & TCBIND_CURVPE)) {
1506 /* tc is bound >vpe0 */
1507 write_tc_c0_tcbind(tmp & ~TCBIND_CURVPE);
1508
1509 t->pvpe = get_vpe(0); /* set the parent vpe */
1510 }
1511
1512 /* halt the TC */
1513 write_tc_c0_tchalt(TCHALT_H);
1514 mips_ihb();
1515
1516 tmp = read_tc_c0_tcstatus();
1517
1518 /* mark not activated and not dynamically allocatable */
1519 tmp &= ~(TCSTATUS_A | TCSTATUS_DA);
1520 tmp |= TCSTATUS_IXMT; /* interrupt exempt */
1521 write_tc_c0_tcstatus(tmp);
1522 }
1523 }
1524
1525out_reenable:
1526 /* release config state */
1527 clear_c0_mvpcontrol(MVPCONTROL_VPC);
1528
1529 evpe(vpflags);
1530 emt(mtflags);
1531 local_irq_restore(flags);
1532
1533 return 0;
1534
1535out_class:
1536 class_unregister(&vpe_class);
1537out_chrdev:
1538 unregister_chrdev(major, module_name);
1539
1540out:
1541 return err;
1542}
1543
1544static void __exit vpe_module_exit(void)
1545{
1546 struct vpe *v, *n;
1547
1548 device_del(&vpe_device);
1549 unregister_chrdev(major, module_name);
1550
1551 /* No locking needed here */
1552 list_for_each_entry_safe(v, n, &vpecontrol.vpe_list, list) {
1553 if (v->state != VPE_STATE_UNUSED)
1554 release_vpe(v);
1555 }
1556}
1557
1558module_init(vpe_module_init); 924module_init(vpe_module_init);
1559module_exit(vpe_module_exit); 925module_exit(vpe_module_exit);
1560MODULE_DESCRIPTION("MIPS VPE Loader"); 926MODULE_DESCRIPTION("MIPS VPE Loader");
diff --git a/arch/mips/kvm/kvm_mips.c b/arch/mips/kvm/kvm_mips.c
index 73b34827826c..da5186fbd77a 100644
--- a/arch/mips/kvm/kvm_mips.c
+++ b/arch/mips/kvm/kvm_mips.c
@@ -1001,7 +1001,6 @@ int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
1001 hrtimer_init(&vcpu->arch.comparecount_timer, CLOCK_MONOTONIC, 1001 hrtimer_init(&vcpu->arch.comparecount_timer, CLOCK_MONOTONIC,
1002 HRTIMER_MODE_REL); 1002 HRTIMER_MODE_REL);
1003 vcpu->arch.comparecount_timer.function = kvm_mips_comparecount_wakeup; 1003 vcpu->arch.comparecount_timer.function = kvm_mips_comparecount_wakeup;
1004 kvm_mips_init_shadow_tlb(vcpu);
1005 return 0; 1004 return 0;
1006} 1005}
1007 1006
diff --git a/arch/mips/kvm/kvm_tlb.c b/arch/mips/kvm/kvm_tlb.c
index c777dd36d4a8..50ab9c4d4a5d 100644
--- a/arch/mips/kvm/kvm_tlb.c
+++ b/arch/mips/kvm/kvm_tlb.c
@@ -10,7 +10,6 @@
10* Authors: Sanjay Lal <sanjayl@kymasys.com> 10* Authors: Sanjay Lal <sanjayl@kymasys.com>
11*/ 11*/
12 12
13#include <linux/init.h>
14#include <linux/sched.h> 13#include <linux/sched.h>
15#include <linux/smp.h> 14#include <linux/smp.h>
16#include <linux/mm.h> 15#include <linux/mm.h>
@@ -25,6 +24,7 @@
25#include <asm/mmu_context.h> 24#include <asm/mmu_context.h>
26#include <asm/pgtable.h> 25#include <asm/pgtable.h>
27#include <asm/cacheflush.h> 26#include <asm/cacheflush.h>
27#include <asm/tlb.h>
28 28
29#undef CONFIG_MIPS_MT 29#undef CONFIG_MIPS_MT
30#include <asm/r4kcache.h> 30#include <asm/r4kcache.h>
@@ -35,9 +35,6 @@
35 35
36#define PRIx64 "llx" 36#define PRIx64 "llx"
37 37
38/* Use VZ EntryHi.EHINV to invalidate TLB entries */
39#define UNIQUE_ENTRYHI(idx) (CKSEG0 + ((idx) << (PAGE_SHIFT + 1)))
40
41atomic_t kvm_mips_instance; 38atomic_t kvm_mips_instance;
42EXPORT_SYMBOL(kvm_mips_instance); 39EXPORT_SYMBOL(kvm_mips_instance);
43 40
@@ -147,30 +144,6 @@ void kvm_mips_dump_guest_tlbs(struct kvm_vcpu *vcpu)
147 } 144 }
148} 145}
149 146
150void kvm_mips_dump_shadow_tlbs(struct kvm_vcpu *vcpu)
151{
152 int i;
153 volatile struct kvm_mips_tlb tlb;
154
155 printk("Shadow TLBs:\n");
156 for (i = 0; i < KVM_MIPS_GUEST_TLB_SIZE; i++) {
157 tlb = vcpu->arch.shadow_tlb[smp_processor_id()][i];
158 printk("TLB%c%3d Hi 0x%08lx ",
159 (tlb.tlb_lo0 | tlb.tlb_lo1) & MIPS3_PG_V ? ' ' : '*',
160 i, tlb.tlb_hi);
161 printk("Lo0=0x%09" PRIx64 " %c%c attr %lx ",
162 (uint64_t) mips3_tlbpfn_to_paddr(tlb.tlb_lo0),
163 (tlb.tlb_lo0 & MIPS3_PG_D) ? 'D' : ' ',
164 (tlb.tlb_lo0 & MIPS3_PG_G) ? 'G' : ' ',
165 (tlb.tlb_lo0 >> 3) & 7);
166 printk("Lo1=0x%09" PRIx64 " %c%c attr %lx sz=%lx\n",
167 (uint64_t) mips3_tlbpfn_to_paddr(tlb.tlb_lo1),
168 (tlb.tlb_lo1 & MIPS3_PG_D) ? 'D' : ' ',
169 (tlb.tlb_lo1 & MIPS3_PG_G) ? 'G' : ' ',
170 (tlb.tlb_lo1 >> 3) & 7, tlb.tlb_mask);
171 }
172}
173
174static int kvm_mips_map_page(struct kvm *kvm, gfn_t gfn) 147static int kvm_mips_map_page(struct kvm *kvm, gfn_t gfn)
175{ 148{
176 int srcu_idx, err = 0; 149 int srcu_idx, err = 0;
@@ -657,70 +630,6 @@ kvm_get_new_mmu_context(struct mm_struct *mm, unsigned long cpu,
657 cpu_context(cpu, mm) = asid_cache(cpu) = asid; 630 cpu_context(cpu, mm) = asid_cache(cpu) = asid;
658} 631}
659 632
660void kvm_shadow_tlb_put(struct kvm_vcpu *vcpu)
661{
662 unsigned long flags;
663 unsigned long old_entryhi;
664 unsigned long old_pagemask;
665 int entry = 0;
666 int cpu = smp_processor_id();
667
668 local_irq_save(flags);
669
670 old_entryhi = read_c0_entryhi();
671 old_pagemask = read_c0_pagemask();
672
673 for (entry = 0; entry < current_cpu_data.tlbsize; entry++) {
674 write_c0_index(entry);
675 mtc0_tlbw_hazard();
676 tlb_read();
677 tlbw_use_hazard();
678
679 vcpu->arch.shadow_tlb[cpu][entry].tlb_hi = read_c0_entryhi();
680 vcpu->arch.shadow_tlb[cpu][entry].tlb_lo0 = read_c0_entrylo0();
681 vcpu->arch.shadow_tlb[cpu][entry].tlb_lo1 = read_c0_entrylo1();
682 vcpu->arch.shadow_tlb[cpu][entry].tlb_mask = read_c0_pagemask();
683 }
684
685 write_c0_entryhi(old_entryhi);
686 write_c0_pagemask(old_pagemask);
687 mtc0_tlbw_hazard();
688
689 local_irq_restore(flags);
690
691}
692
693void kvm_shadow_tlb_load(struct kvm_vcpu *vcpu)
694{
695 unsigned long flags;
696 unsigned long old_ctx;
697 int entry;
698 int cpu = smp_processor_id();
699
700 local_irq_save(flags);
701
702 old_ctx = read_c0_entryhi();
703
704 for (entry = 0; entry < current_cpu_data.tlbsize; entry++) {
705 write_c0_entryhi(vcpu->arch.shadow_tlb[cpu][entry].tlb_hi);
706 mtc0_tlbw_hazard();
707 write_c0_entrylo0(vcpu->arch.shadow_tlb[cpu][entry].tlb_lo0);
708 write_c0_entrylo1(vcpu->arch.shadow_tlb[cpu][entry].tlb_lo1);
709
710 write_c0_index(entry);
711 mtc0_tlbw_hazard();
712
713 tlb_write_indexed();
714 tlbw_use_hazard();
715 }
716
717 tlbw_use_hazard();
718 write_c0_entryhi(old_ctx);
719 mtc0_tlbw_hazard();
720 local_irq_restore(flags);
721}
722
723
724void kvm_local_flush_tlb_all(void) 633void kvm_local_flush_tlb_all(void)
725{ 634{
726 unsigned long flags; 635 unsigned long flags;
@@ -749,30 +658,6 @@ void kvm_local_flush_tlb_all(void)
749 local_irq_restore(flags); 658 local_irq_restore(flags);
750} 659}
751 660
752void kvm_mips_init_shadow_tlb(struct kvm_vcpu *vcpu)
753{
754 int cpu, entry;
755
756 for_each_possible_cpu(cpu) {
757 for (entry = 0; entry < current_cpu_data.tlbsize; entry++) {
758 vcpu->arch.shadow_tlb[cpu][entry].tlb_hi =
759 UNIQUE_ENTRYHI(entry);
760 vcpu->arch.shadow_tlb[cpu][entry].tlb_lo0 = 0x0;
761 vcpu->arch.shadow_tlb[cpu][entry].tlb_lo1 = 0x0;
762 vcpu->arch.shadow_tlb[cpu][entry].tlb_mask =
763 read_c0_pagemask();
764#ifdef DEBUG
765 kvm_debug
766 ("shadow_tlb[%d][%d]: tlb_hi: %#lx, lo0: %#lx, lo1: %#lx\n",
767 cpu, entry,
768 vcpu->arch.shadow_tlb[cpu][entry].tlb_hi,
769 vcpu->arch.shadow_tlb[cpu][entry].tlb_lo0,
770 vcpu->arch.shadow_tlb[cpu][entry].tlb_lo1);
771#endif
772 }
773 }
774}
775
776/* Restore ASID once we are scheduled back after preemption */ 661/* Restore ASID once we are scheduled back after preemption */
777void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu) 662void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
778{ 663{
@@ -810,14 +695,6 @@ void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
810 vcpu->arch.last_sched_cpu, cpu, vcpu->vcpu_id); 695 vcpu->arch.last_sched_cpu, cpu, vcpu->vcpu_id);
811 } 696 }
812 697
813 /* Only reload shadow host TLB if new ASIDs haven't been allocated */
814#if 0
815 if ((atomic_read(&kvm_mips_instance) > 1) && !newasid) {
816 kvm_mips_flush_host_tlb(0);
817 kvm_shadow_tlb_load(vcpu);
818 }
819#endif
820
821 if (!newasid) { 698 if (!newasid) {
822 /* If we preempted while the guest was executing, then reload the pre-empted ASID */ 699 /* If we preempted while the guest was executing, then reload the pre-empted ASID */
823 if (current->flags & PF_VCPU) { 700 if (current->flags & PF_VCPU) {
@@ -863,12 +740,6 @@ void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
863 vcpu->arch.preempt_entryhi = read_c0_entryhi(); 740 vcpu->arch.preempt_entryhi = read_c0_entryhi();
864 vcpu->arch.last_sched_cpu = cpu; 741 vcpu->arch.last_sched_cpu = cpu;
865 742
866#if 0
867 if ((atomic_read(&kvm_mips_instance) > 1)) {
868 kvm_shadow_tlb_put(vcpu);
869 }
870#endif
871
872 if (((cpu_context(cpu, current->mm) ^ asid_cache(cpu)) & 743 if (((cpu_context(cpu, current->mm) ^ asid_cache(cpu)) &
873 ASID_VERSION_MASK)) { 744 ASID_VERSION_MASK)) {
874 kvm_debug("%s: Dropping MMU Context: %#lx\n", __func__, 745 kvm_debug("%s: Dropping MMU Context: %#lx\n", __func__,
@@ -930,10 +801,8 @@ uint32_t kvm_get_inst(uint32_t *opc, struct kvm_vcpu *vcpu)
930} 801}
931 802
932EXPORT_SYMBOL(kvm_local_flush_tlb_all); 803EXPORT_SYMBOL(kvm_local_flush_tlb_all);
933EXPORT_SYMBOL(kvm_shadow_tlb_put);
934EXPORT_SYMBOL(kvm_mips_handle_mapped_seg_tlb_fault); 804EXPORT_SYMBOL(kvm_mips_handle_mapped_seg_tlb_fault);
935EXPORT_SYMBOL(kvm_mips_handle_commpage_tlb_fault); 805EXPORT_SYMBOL(kvm_mips_handle_commpage_tlb_fault);
936EXPORT_SYMBOL(kvm_mips_init_shadow_tlb);
937EXPORT_SYMBOL(kvm_mips_dump_host_tlbs); 806EXPORT_SYMBOL(kvm_mips_dump_host_tlbs);
938EXPORT_SYMBOL(kvm_mips_handle_kseg0_tlb_fault); 807EXPORT_SYMBOL(kvm_mips_handle_kseg0_tlb_fault);
939EXPORT_SYMBOL(kvm_mips_host_tlb_lookup); 808EXPORT_SYMBOL(kvm_mips_host_tlb_lookup);
@@ -941,8 +810,6 @@ EXPORT_SYMBOL(kvm_mips_flush_host_tlb);
941EXPORT_SYMBOL(kvm_mips_guest_tlb_lookup); 810EXPORT_SYMBOL(kvm_mips_guest_tlb_lookup);
942EXPORT_SYMBOL(kvm_mips_host_tlb_inv); 811EXPORT_SYMBOL(kvm_mips_host_tlb_inv);
943EXPORT_SYMBOL(kvm_mips_translate_guest_kseg0_to_hpa); 812EXPORT_SYMBOL(kvm_mips_translate_guest_kseg0_to_hpa);
944EXPORT_SYMBOL(kvm_shadow_tlb_load);
945EXPORT_SYMBOL(kvm_mips_dump_shadow_tlbs);
946EXPORT_SYMBOL(kvm_mips_dump_guest_tlbs); 813EXPORT_SYMBOL(kvm_mips_dump_guest_tlbs);
947EXPORT_SYMBOL(kvm_get_inst); 814EXPORT_SYMBOL(kvm_get_inst);
948EXPORT_SYMBOL(kvm_arch_vcpu_load); 815EXPORT_SYMBOL(kvm_arch_vcpu_load);
diff --git a/arch/mips/lantiq/xway/clk.c b/arch/mips/lantiq/xway/clk.c
index 1ab576dc9bd1..8750dc0a1bf6 100644
--- a/arch/mips/lantiq/xway/clk.c
+++ b/arch/mips/lantiq/xway/clk.c
@@ -8,7 +8,6 @@
8 8
9#include <linux/io.h> 9#include <linux/io.h>
10#include <linux/export.h> 10#include <linux/export.h>
11#include <linux/init.h>
12#include <linux/clk.h> 11#include <linux/clk.h>
13 12
14#include <asm/time.h> 13#include <asm/time.h>
diff --git a/arch/mips/lantiq/xway/dma.c b/arch/mips/lantiq/xway/dma.c
index 08f7ebd9c774..78a91fa41944 100644
--- a/arch/mips/lantiq/xway/dma.c
+++ b/arch/mips/lantiq/xway/dma.c
@@ -220,10 +220,6 @@ ltq_dma_init(struct platform_device *pdev)
220 int i; 220 int i;
221 221
222 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 222 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
223 if (!res)
224 panic("Failed to get dma resource");
225
226 /* remap dma register range */
227 ltq_dma_membase = devm_ioremap_resource(&pdev->dev, res); 223 ltq_dma_membase = devm_ioremap_resource(&pdev->dev, res);
228 if (IS_ERR(ltq_dma_membase)) 224 if (IS_ERR(ltq_dma_membase))
229 panic("Failed to remap dma resource"); 225 panic("Failed to remap dma resource");
diff --git a/arch/mips/lasat/at93c.c b/arch/mips/lasat/at93c.c
index 793e234719a6..942f32b91d12 100644
--- a/arch/mips/lasat/at93c.c
+++ b/arch/mips/lasat/at93c.c
@@ -8,7 +8,6 @@
8#include <linux/delay.h> 8#include <linux/delay.h>
9#include <asm/lasat/lasat.h> 9#include <asm/lasat/lasat.h>
10#include <linux/module.h> 10#include <linux/module.h>
11#include <linux/init.h>
12 11
13#include "at93c.h" 12#include "at93c.h"
14 13
diff --git a/arch/mips/lasat/picvue.c b/arch/mips/lasat/picvue.c
index 7eb334892693..d613b97cd513 100644
--- a/arch/mips/lasat/picvue.c
+++ b/arch/mips/lasat/picvue.c
@@ -9,7 +9,6 @@
9#include <asm/bootinfo.h> 9#include <asm/bootinfo.h>
10#include <asm/lasat/lasat.h> 10#include <asm/lasat/lasat.h>
11#include <linux/module.h> 11#include <linux/module.h>
12#include <linux/init.h>
13#include <linux/errno.h> 12#include <linux/errno.h>
14#include <linux/string.h> 13#include <linux/string.h>
15 14
diff --git a/arch/mips/lib/uncached.c b/arch/mips/lib/uncached.c
index d8522f8e842a..09d5deea747f 100644
--- a/arch/mips/lib/uncached.c
+++ b/arch/mips/lib/uncached.c
@@ -8,7 +8,6 @@
8 * Author: Maciej W. Rozycki <macro@mips.com> 8 * Author: Maciej W. Rozycki <macro@mips.com>
9 */ 9 */
10 10
11#include <linux/init.h>
12 11
13#include <asm/addrspace.h> 12#include <asm/addrspace.h>
14#include <asm/bug.h> 13#include <asm/bug.h>
diff --git a/arch/mips/loongson/lemote-2f/clock.c b/arch/mips/loongson/lemote-2f/clock.c
index 4dc2f5fa3f67..aed32b88576c 100644
--- a/arch/mips/loongson/lemote-2f/clock.c
+++ b/arch/mips/loongson/lemote-2f/clock.c
@@ -10,7 +10,6 @@
10#include <linux/cpufreq.h> 10#include <linux/cpufreq.h>
11#include <linux/errno.h> 11#include <linux/errno.h>
12#include <linux/export.h> 12#include <linux/export.h>
13#include <linux/init.h>
14#include <linux/list.h> 13#include <linux/list.h>
15#include <linux/mutex.h> 14#include <linux/mutex.h>
16#include <linux/spinlock.h> 15#include <linux/spinlock.h>
diff --git a/arch/mips/math-emu/cp1emu.c b/arch/mips/math-emu/cp1emu.c
index efe008846ed0..506925b2c3f3 100644
--- a/arch/mips/math-emu/cp1emu.c
+++ b/arch/mips/math-emu/cp1emu.c
@@ -417,14 +417,20 @@ static int microMIPS32_to_MIPS32(union mips_instruction *insn_ptr)
417 case mm_mtc1_op: 417 case mm_mtc1_op:
418 case mm_cfc1_op: 418 case mm_cfc1_op:
419 case mm_ctc1_op: 419 case mm_ctc1_op:
420 case mm_mfhc1_op:
421 case mm_mthc1_op:
420 if (insn.mm_fp1_format.op == mm_mfc1_op) 422 if (insn.mm_fp1_format.op == mm_mfc1_op)
421 op = mfc_op; 423 op = mfc_op;
422 else if (insn.mm_fp1_format.op == mm_mtc1_op) 424 else if (insn.mm_fp1_format.op == mm_mtc1_op)
423 op = mtc_op; 425 op = mtc_op;
424 else if (insn.mm_fp1_format.op == mm_cfc1_op) 426 else if (insn.mm_fp1_format.op == mm_cfc1_op)
425 op = cfc_op; 427 op = cfc_op;
426 else 428 else if (insn.mm_fp1_format.op == mm_ctc1_op)
427 op = ctc_op; 429 op = ctc_op;
430 else if (insn.mm_fp1_format.op == mm_mfhc1_op)
431 op = mfhc_op;
432 else
433 op = mthc_op;
428 mips32_insn.fp1_format.opcode = cop1_op; 434 mips32_insn.fp1_format.opcode = cop1_op;
429 mips32_insn.fp1_format.op = op; 435 mips32_insn.fp1_format.op = op;
430 mips32_insn.fp1_format.rt = 436 mips32_insn.fp1_format.rt =
@@ -853,20 +859,20 @@ static int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
853 * In the Linux kernel, we support selection of FPR format on the 859 * In the Linux kernel, we support selection of FPR format on the
854 * basis of the Status.FR bit. If an FPU is not present, the FR bit 860 * basis of the Status.FR bit. If an FPU is not present, the FR bit
855 * is hardwired to zero, which would imply a 32-bit FPU even for 861 * is hardwired to zero, which would imply a 32-bit FPU even for
856 * 64-bit CPUs so we rather look at TIF_32BIT_REGS. 862 * 64-bit CPUs so we rather look at TIF_32BIT_FPREGS.
857 * FPU emu is slow and bulky and optimizing this function offers fairly 863 * FPU emu is slow and bulky and optimizing this function offers fairly
858 * sizeable benefits so we try to be clever and make this function return 864 * sizeable benefits so we try to be clever and make this function return
859 * a constant whenever possible, that is on 64-bit kernels without O32 865 * a constant whenever possible, that is on 64-bit kernels without O32
860 * compatibility enabled and on 32-bit kernels. 866 * compatibility enabled and on 32-bit without 64-bit FPU support.
861 */ 867 */
862static inline int cop1_64bit(struct pt_regs *xcp) 868static inline int cop1_64bit(struct pt_regs *xcp)
863{ 869{
864#if defined(CONFIG_64BIT) && !defined(CONFIG_MIPS32_O32) 870#if defined(CONFIG_64BIT) && !defined(CONFIG_MIPS32_O32)
865 return 1; 871 return 1;
866#elif defined(CONFIG_64BIT) && defined(CONFIG_MIPS32_O32) 872#elif defined(CONFIG_32BIT) && !defined(CONFIG_MIPS_O32_FP64_SUPPORT)
867 return !test_thread_flag(TIF_32BIT_REGS);
868#else
869 return 0; 873 return 0;
874#else
875 return !test_thread_flag(TIF_32BIT_FPREGS);
870#endif 876#endif
871} 877}
872 878
@@ -878,6 +884,10 @@ static inline int cop1_64bit(struct pt_regs *xcp)
878 ctx->fpr[x & ~1] >> 32 << 32 | (u32)(si) : \ 884 ctx->fpr[x & ~1] >> 32 << 32 | (u32)(si) : \
879 ctx->fpr[x & ~1] << 32 >> 32 | (u64)(si) << 32) 885 ctx->fpr[x & ~1] << 32 >> 32 | (u64)(si) << 32)
880 886
887#define SIFROMHREG(si, x) ((si) = (int)(ctx->fpr[x] >> 32))
888#define SITOHREG(si, x) (ctx->fpr[x] = \
889 ctx->fpr[x] << 32 >> 32 | (u64)(si) << 32)
890
881#define DIFROMREG(di, x) ((di) = ctx->fpr[x & ~(cop1_64bit(xcp) == 0)]) 891#define DIFROMREG(di, x) ((di) = ctx->fpr[x & ~(cop1_64bit(xcp) == 0)])
882#define DITOREG(di, x) (ctx->fpr[x & ~(cop1_64bit(xcp) == 0)] = (di)) 892#define DITOREG(di, x) (ctx->fpr[x & ~(cop1_64bit(xcp) == 0)] = (di))
883 893
@@ -1055,6 +1065,25 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
1055 break; 1065 break;
1056#endif 1066#endif
1057 1067
1068 case mfhc_op:
1069 if (!cpu_has_mips_r2)
1070 goto sigill;
1071
1072 /* copregister rd -> gpr[rt] */
1073 if (MIPSInst_RT(ir) != 0) {
1074 SIFROMHREG(xcp->regs[MIPSInst_RT(ir)],
1075 MIPSInst_RD(ir));
1076 }
1077 break;
1078
1079 case mthc_op:
1080 if (!cpu_has_mips_r2)
1081 goto sigill;
1082
1083 /* copregister rd <- gpr[rt] */
1084 SITOHREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
1085 break;
1086
1058 case mfc_op: 1087 case mfc_op:
1059 /* copregister rd -> gpr[rt] */ 1088 /* copregister rd -> gpr[rt] */
1060 if (MIPSInst_RT(ir) != 0) { 1089 if (MIPSInst_RT(ir) != 0) {
@@ -1263,6 +1292,7 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
1263#endif 1292#endif
1264 1293
1265 default: 1294 default:
1295sigill:
1266 return SIGILL; 1296 return SIGILL;
1267 } 1297 }
1268 1298
diff --git a/arch/mips/math-emu/kernel_linkage.c b/arch/mips/math-emu/kernel_linkage.c
index 1c586575fe17..3aeae07ed5b8 100644
--- a/arch/mips/math-emu/kernel_linkage.c
+++ b/arch/mips/math-emu/kernel_linkage.c
@@ -89,8 +89,9 @@ int fpu_emulator_save_context32(struct sigcontext32 __user *sc)
89{ 89{
90 int i; 90 int i;
91 int err = 0; 91 int err = 0;
92 int inc = test_thread_flag(TIF_32BIT_FPREGS) ? 2 : 1;
92 93
93 for (i = 0; i < 32; i+=2) { 94 for (i = 0; i < 32; i += inc) {
94 err |= 95 err |=
95 __put_user(current->thread.fpu.fpr[i], &sc->sc_fpregs[i]); 96 __put_user(current->thread.fpu.fpr[i], &sc->sc_fpregs[i]);
96 } 97 }
@@ -103,8 +104,9 @@ int fpu_emulator_restore_context32(struct sigcontext32 __user *sc)
103{ 104{
104 int i; 105 int i;
105 int err = 0; 106 int err = 0;
107 int inc = test_thread_flag(TIF_32BIT_FPREGS) ? 2 : 1;
106 108
107 for (i = 0; i < 32; i+=2) { 109 for (i = 0; i < 32; i += inc) {
108 err |= 110 err |=
109 __get_user(current->thread.fpu.fpr[i], &sc->sc_fpregs[i]); 111 __get_user(current->thread.fpu.fpr[i], &sc->sc_fpregs[i]);
110 } 112 }
diff --git a/arch/mips/mm/c-octeon.c b/arch/mips/mm/c-octeon.c
index c8efdb5b6ee0..f41a5c5b0865 100644
--- a/arch/mips/mm/c-octeon.c
+++ b/arch/mips/mm/c-octeon.c
@@ -6,7 +6,6 @@
6 * Copyright (C) 2005-2007 Cavium Networks 6 * Copyright (C) 2005-2007 Cavium Networks
7 */ 7 */
8#include <linux/export.h> 8#include <linux/export.h>
9#include <linux/init.h>
10#include <linux/kernel.h> 9#include <linux/kernel.h>
11#include <linux/sched.h> 10#include <linux/sched.h>
12#include <linux/smp.h> 11#include <linux/smp.h>
diff --git a/arch/mips/mm/c-r3k.c b/arch/mips/mm/c-r3k.c
index 2fcde0c8ea02..135ec313c1f6 100644
--- a/arch/mips/mm/c-r3k.c
+++ b/arch/mips/mm/c-r3k.c
@@ -9,7 +9,6 @@
9 * Copyright (C) 1998 Gleb Raiko & Vladimir Roganov 9 * Copyright (C) 1998 Gleb Raiko & Vladimir Roganov
10 * Copyright (C) 2001, 2004, 2007 Maciej W. Rozycki 10 * Copyright (C) 2001, 2004, 2007 Maciej W. Rozycki
11 */ 11 */
12#include <linux/init.h>
13#include <linux/kernel.h> 12#include <linux/kernel.h>
14#include <linux/sched.h> 13#include <linux/sched.h>
15#include <linux/smp.h> 14#include <linux/smp.h>
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index 49e572d879e1..c14259edd53f 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -1020,10 +1020,14 @@ static void probe_pcache(void)
1020 */ 1020 */
1021 config1 = read_c0_config1(); 1021 config1 = read_c0_config1();
1022 1022
1023 if ((lsize = ((config1 >> 19) & 7))) 1023 lsize = (config1 >> 19) & 7;
1024 c->icache.linesz = 2 << lsize; 1024
1025 else 1025 /* IL == 7 is reserved */
1026 c->icache.linesz = lsize; 1026 if (lsize == 7)
1027 panic("Invalid icache line size");
1028
1029 c->icache.linesz = lsize ? 2 << lsize : 0;
1030
1027 c->icache.sets = 32 << (((config1 >> 22) + 1) & 7); 1031 c->icache.sets = 32 << (((config1 >> 22) + 1) & 7);
1028 c->icache.ways = 1 + ((config1 >> 16) & 7); 1032 c->icache.ways = 1 + ((config1 >> 16) & 7);
1029 1033
@@ -1040,10 +1044,14 @@ static void probe_pcache(void)
1040 */ 1044 */
1041 c->dcache.flags = 0; 1045 c->dcache.flags = 0;
1042 1046
1043 if ((lsize = ((config1 >> 10) & 7))) 1047 lsize = (config1 >> 10) & 7;
1044 c->dcache.linesz = 2 << lsize; 1048
1045 else 1049 /* DL == 7 is reserved */
1046 c->dcache.linesz= lsize; 1050 if (lsize == 7)
1051 panic("Invalid dcache line size");
1052
1053 c->dcache.linesz = lsize ? 2 << lsize : 0;
1054
1047 c->dcache.sets = 32 << (((config1 >> 13) + 1) & 7); 1055 c->dcache.sets = 32 << (((config1 >> 13) + 1) & 7);
1048 c->dcache.ways = 1 + ((config1 >> 7) & 7); 1056 c->dcache.ways = 1 + ((config1 >> 7) & 7);
1049 1057
@@ -1105,6 +1113,8 @@ static void probe_pcache(void)
1105 case CPU_34K: 1113 case CPU_34K:
1106 case CPU_74K: 1114 case CPU_74K:
1107 case CPU_1004K: 1115 case CPU_1004K:
1116 case CPU_INTERAPTIV:
1117 case CPU_PROAPTIV:
1108 if (current_cpu_type() == CPU_74K) 1118 if (current_cpu_type() == CPU_74K)
1109 alias_74k_erratum(c); 1119 alias_74k_erratum(c);
1110 if ((read_c0_config7() & (1 << 16))) { 1120 if ((read_c0_config7() & (1 << 16))) {
diff --git a/arch/mips/mm/cache.c b/arch/mips/mm/cache.c
index 15f813c303b4..fde7e56d13fe 100644
--- a/arch/mips/mm/cache.c
+++ b/arch/mips/mm/cache.c
@@ -8,7 +8,6 @@
8 */ 8 */
9#include <linux/fs.h> 9#include <linux/fs.h>
10#include <linux/fcntl.h> 10#include <linux/fcntl.h>
11#include <linux/init.h>
12#include <linux/kernel.h> 11#include <linux/kernel.h>
13#include <linux/linkage.h> 12#include <linux/linkage.h>
14#include <linux/module.h> 13#include <linux/module.h>
diff --git a/arch/mips/mm/cex-sb1.S b/arch/mips/mm/cex-sb1.S
index 191cf6e0c725..5d5f29681a21 100644
--- a/arch/mips/mm/cex-sb1.S
+++ b/arch/mips/mm/cex-sb1.S
@@ -15,7 +15,6 @@
15 * along with this program; if not, write to the Free Software 15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
17 */ 17 */
18#include <linux/init.h>
19 18
20#include <asm/asm.h> 19#include <asm/asm.h>
21#include <asm/regdef.h> 20#include <asm/regdef.h>
diff --git a/arch/mips/mm/dma-default.c b/arch/mips/mm/dma-default.c
index 2e9418562258..44b6dff5aba2 100644
--- a/arch/mips/mm/dma-default.c
+++ b/arch/mips/mm/dma-default.c
@@ -23,6 +23,7 @@
23 23
24#include <dma-coherence.h> 24#include <dma-coherence.h>
25 25
26#ifdef CONFIG_DMA_MAYBE_COHERENT
26int coherentio = 0; /* User defined DMA coherency from command line. */ 27int coherentio = 0; /* User defined DMA coherency from command line. */
27EXPORT_SYMBOL_GPL(coherentio); 28EXPORT_SYMBOL_GPL(coherentio);
28int hw_coherentio = 0; /* Actual hardware supported DMA coherency setting. */ 29int hw_coherentio = 0; /* Actual hardware supported DMA coherency setting. */
@@ -42,6 +43,7 @@ static int __init setnocoherentio(char *str)
42 return 0; 43 return 0;
43} 44}
44early_param("nocoherentio", setnocoherentio); 45early_param("nocoherentio", setnocoherentio);
46#endif
45 47
46static inline struct page *dma_addr_to_page(struct device *dev, 48static inline struct page *dma_addr_to_page(struct device *dev,
47 dma_addr_t dma_addr) 49 dma_addr_t dma_addr)
diff --git a/arch/mips/mm/hugetlbpage.c b/arch/mips/mm/hugetlbpage.c
index 01fda4419ed0..77e0ae036e7c 100644
--- a/arch/mips/mm/hugetlbpage.c
+++ b/arch/mips/mm/hugetlbpage.c
@@ -11,7 +11,6 @@
11 * Copyright (C) 2008, 2009 Cavium Networks, Inc. 11 * Copyright (C) 2008, 2009 Cavium Networks, Inc.
12 */ 12 */
13 13
14#include <linux/init.h>
15#include <linux/fs.h> 14#include <linux/fs.h>
16#include <linux/mm.h> 15#include <linux/mm.h>
17#include <linux/hugetlb.h> 16#include <linux/hugetlb.h>
diff --git a/arch/mips/mm/init.c b/arch/mips/mm/init.c
index 12156176c7ca..6b59617760c1 100644
--- a/arch/mips/mm/init.c
+++ b/arch/mips/mm/init.c
@@ -171,8 +171,6 @@ void *kmap_coherent(struct page *page, unsigned long addr)
171 return (void*) vaddr; 171 return (void*) vaddr;
172} 172}
173 173
174#define UNIQUE_ENTRYHI(idx) (CKSEG0 + ((idx) << (PAGE_SHIFT + 1)))
175
176void kunmap_coherent(void) 174void kunmap_coherent(void)
177{ 175{
178#ifndef CONFIG_MIPS_MT_SMTC 176#ifndef CONFIG_MIPS_MT_SMTC
diff --git a/arch/mips/mm/page.c b/arch/mips/mm/page.c
index cbd81d17793a..58033c44690d 100644
--- a/arch/mips/mm/page.c
+++ b/arch/mips/mm/page.c
@@ -8,7 +8,6 @@
8 * Copyright (C) 2008 Thiemo Seufer 8 * Copyright (C) 2008 Thiemo Seufer
9 * Copyright (C) 2012 MIPS Technologies, Inc. 9 * Copyright (C) 2012 MIPS Technologies, Inc.
10 */ 10 */
11#include <linux/init.h>
12#include <linux/kernel.h> 11#include <linux/kernel.h>
13#include <linux/sched.h> 12#include <linux/sched.h>
14#include <linux/smp.h> 13#include <linux/smp.h>
diff --git a/arch/mips/mm/sc-mips.c b/arch/mips/mm/sc-mips.c
index 08d05aee8788..7a56aee5fce7 100644
--- a/arch/mips/mm/sc-mips.c
+++ b/arch/mips/mm/sc-mips.c
@@ -76,6 +76,8 @@ static inline int mips_sc_is_activated(struct cpuinfo_mips *c)
76 case CPU_34K: 76 case CPU_34K:
77 case CPU_74K: 77 case CPU_74K:
78 case CPU_1004K: 78 case CPU_1004K:
79 case CPU_INTERAPTIV:
80 case CPU_PROAPTIV:
79 case CPU_BMIPS5000: 81 case CPU_BMIPS5000:
80 if (config2 & (1 << 12)) 82 if (config2 & (1 << 12))
81 return 0; 83 return 0;
diff --git a/arch/mips/mm/sc-rm7k.c b/arch/mips/mm/sc-rm7k.c
index aaffbba33706..9ac1efcfbcc7 100644
--- a/arch/mips/mm/sc-rm7k.c
+++ b/arch/mips/mm/sc-rm7k.c
@@ -6,7 +6,6 @@
6 6
7#undef DEBUG 7#undef DEBUG
8 8
9#include <linux/init.h>
10#include <linux/kernel.h> 9#include <linux/kernel.h>
11#include <linux/mm.h> 10#include <linux/mm.h>
12#include <linux/bitops.h> 11#include <linux/bitops.h>
diff --git a/arch/mips/mm/tlb-r3k.c b/arch/mips/mm/tlb-r3k.c
index 9aca10994cd2..d657493ef561 100644
--- a/arch/mips/mm/tlb-r3k.c
+++ b/arch/mips/mm/tlb-r3k.c
@@ -10,7 +10,6 @@
10 * Copyright (C) 2002 Ralf Baechle 10 * Copyright (C) 2002 Ralf Baechle
11 * Copyright (C) 2002 Maciej W. Rozycki 11 * Copyright (C) 2002 Maciej W. Rozycki
12 */ 12 */
13#include <linux/init.h>
14#include <linux/kernel.h> 13#include <linux/kernel.h>
15#include <linux/sched.h> 14#include <linux/sched.h>
16#include <linux/smp.h> 15#include <linux/smp.h>
diff --git a/arch/mips/mm/tlb-r4k.c b/arch/mips/mm/tlb-r4k.c
index da3b0b9c9eae..ae4ca2450707 100644
--- a/arch/mips/mm/tlb-r4k.c
+++ b/arch/mips/mm/tlb-r4k.c
@@ -20,16 +20,11 @@
20#include <asm/bootinfo.h> 20#include <asm/bootinfo.h>
21#include <asm/mmu_context.h> 21#include <asm/mmu_context.h>
22#include <asm/pgtable.h> 22#include <asm/pgtable.h>
23#include <asm/tlb.h>
23#include <asm/tlbmisc.h> 24#include <asm/tlbmisc.h>
24 25
25extern void build_tlb_refill_handler(void); 26extern void build_tlb_refill_handler(void);
26 27
27/*
28 * Make sure all entries differ. If they're not different
29 * MIPS32 will take revenge ...
30 */
31#define UNIQUE_ENTRYHI(idx) (CKSEG0 + ((idx) << (PAGE_SHIFT + 1)))
32
33/* Atomicity and interruptability */ 28/* Atomicity and interruptability */
34#ifdef CONFIG_MIPS_MT_SMTC 29#ifdef CONFIG_MIPS_MT_SMTC
35 30
@@ -77,7 +72,7 @@ void local_flush_tlb_all(void)
77{ 72{
78 unsigned long flags; 73 unsigned long flags;
79 unsigned long old_ctx; 74 unsigned long old_ctx;
80 int entry; 75 int entry, ftlbhighset;
81 76
82 ENTER_CRITICAL(flags); 77 ENTER_CRITICAL(flags);
83 /* Save old context and create impossible VPN2 value */ 78 /* Save old context and create impossible VPN2 value */
@@ -88,13 +83,30 @@ void local_flush_tlb_all(void)
88 entry = read_c0_wired(); 83 entry = read_c0_wired();
89 84
90 /* Blast 'em all away. */ 85 /* Blast 'em all away. */
91 while (entry < current_cpu_data.tlbsize) { 86 if (cpu_has_tlbinv) {
92 /* Make sure all entries differ. */ 87 if (current_cpu_data.tlbsizevtlb) {
93 write_c0_entryhi(UNIQUE_ENTRYHI(entry)); 88 write_c0_index(0);
94 write_c0_index(entry); 89 mtc0_tlbw_hazard();
95 mtc0_tlbw_hazard(); 90 tlbinvf(); /* invalidate VTLB */
96 tlb_write_indexed(); 91 }
97 entry++; 92 ftlbhighset = current_cpu_data.tlbsizevtlb +
93 current_cpu_data.tlbsizeftlbsets;
94 for (entry = current_cpu_data.tlbsizevtlb;
95 entry < ftlbhighset;
96 entry++) {
97 write_c0_index(entry);
98 mtc0_tlbw_hazard();
99 tlbinvf(); /* invalidate one FTLB set */
100 }
101 } else {
102 while (entry < current_cpu_data.tlbsize) {
103 /* Make sure all entries differ. */
104 write_c0_entryhi(UNIQUE_ENTRYHI(entry));
105 write_c0_index(entry);
106 mtc0_tlbw_hazard();
107 tlb_write_indexed();
108 entry++;
109 }
98 } 110 }
99 tlbw_use_hazard(); 111 tlbw_use_hazard();
100 write_c0_entryhi(old_ctx); 112 write_c0_entryhi(old_ctx);
@@ -133,7 +145,9 @@ void local_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
133 start = round_down(start, PAGE_SIZE << 1); 145 start = round_down(start, PAGE_SIZE << 1);
134 end = round_up(end, PAGE_SIZE << 1); 146 end = round_up(end, PAGE_SIZE << 1);
135 size = (end - start) >> (PAGE_SHIFT + 1); 147 size = (end - start) >> (PAGE_SHIFT + 1);
136 if (size <= current_cpu_data.tlbsize/2) { 148 if (size <= (current_cpu_data.tlbsizeftlbsets ?
149 current_cpu_data.tlbsize / 8 :
150 current_cpu_data.tlbsize / 2)) {
137 int oldpid = read_c0_entryhi(); 151 int oldpid = read_c0_entryhi();
138 int newpid = cpu_asid(cpu, mm); 152 int newpid = cpu_asid(cpu, mm);
139 153
@@ -172,7 +186,9 @@ void local_flush_tlb_kernel_range(unsigned long start, unsigned long end)
172 ENTER_CRITICAL(flags); 186 ENTER_CRITICAL(flags);
173 size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT; 187 size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT;
174 size = (size + 1) >> 1; 188 size = (size + 1) >> 1;
175 if (size <= current_cpu_data.tlbsize / 2) { 189 if (size <= (current_cpu_data.tlbsizeftlbsets ?
190 current_cpu_data.tlbsize / 8 :
191 current_cpu_data.tlbsize / 2)) {
176 int pid = read_c0_entryhi(); 192 int pid = read_c0_entryhi();
177 193
178 start &= (PAGE_MASK << 1); 194 start &= (PAGE_MASK << 1);
diff --git a/arch/mips/mm/tlb-r8k.c b/arch/mips/mm/tlb-r8k.c
index 6a99733a4440..138a2ec7cc6b 100644
--- a/arch/mips/mm/tlb-r8k.c
+++ b/arch/mips/mm/tlb-r8k.c
@@ -8,7 +8,6 @@
8 * Carsten Langgaard, carstenl@mips.com 8 * Carsten Langgaard, carstenl@mips.com
9 * Copyright (C) 2002 MIPS Technologies, Inc. All rights reserved. 9 * Copyright (C) 2002 MIPS Technologies, Inc. All rights reserved.
10 */ 10 */
11#include <linux/init.h>
12#include <linux/sched.h> 11#include <linux/sched.h>
13#include <linux/smp.h> 12#include <linux/smp.h>
14#include <linux/mm.h> 13#include <linux/mm.h>
diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index 183f2b583e4d..b234b1b5ccad 100644
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -26,7 +26,6 @@
26#include <linux/types.h> 26#include <linux/types.h>
27#include <linux/smp.h> 27#include <linux/smp.h>
28#include <linux/string.h> 28#include <linux/string.h>
29#include <linux/init.h>
30#include <linux/cache.h> 29#include <linux/cache.h>
31 30
32#include <asm/cacheflush.h> 31#include <asm/cacheflush.h>
@@ -510,6 +509,7 @@ static void build_tlb_write_entry(u32 **p, struct uasm_label **l,
510 switch (current_cpu_type()) { 509 switch (current_cpu_type()) {
511 case CPU_M14KC: 510 case CPU_M14KC:
512 case CPU_74K: 511 case CPU_74K:
512 case CPU_PROAPTIV:
513 break; 513 break;
514 514
515 default: 515 default:
diff --git a/arch/mips/mm/uasm-micromips.c b/arch/mips/mm/uasm-micromips.c
index 060000fa653c..b8d580ca02e5 100644
--- a/arch/mips/mm/uasm-micromips.c
+++ b/arch/mips/mm/uasm-micromips.c
@@ -15,7 +15,6 @@
15 15
16#include <linux/kernel.h> 16#include <linux/kernel.h>
17#include <linux/types.h> 17#include <linux/types.h>
18#include <linux/init.h>
19 18
20#include <asm/inst.h> 19#include <asm/inst.h>
21#include <asm/elf.h> 20#include <asm/elf.h>
diff --git a/arch/mips/mm/uasm-mips.c b/arch/mips/mm/uasm-mips.c
index 0c724589854e..3abd609518c9 100644
--- a/arch/mips/mm/uasm-mips.c
+++ b/arch/mips/mm/uasm-mips.c
@@ -15,7 +15,6 @@
15 15
16#include <linux/kernel.h> 16#include <linux/kernel.h>
17#include <linux/types.h> 17#include <linux/types.h>
18#include <linux/init.h>
19 18
20#include <asm/inst.h> 19#include <asm/inst.h>
21#include <asm/elf.h> 20#include <asm/elf.h>
diff --git a/arch/mips/mti-malta/Makefile b/arch/mips/mti-malta/Makefile
index 72fdedbf76db..eae0ba3876d9 100644
--- a/arch/mips/mti-malta/Makefile
+++ b/arch/mips/mti-malta/Makefile
@@ -9,7 +9,5 @@ obj-y := malta-amon.o malta-display.o malta-init.o \
9 malta-int.o malta-memory.o malta-platform.o \ 9 malta-int.o malta-memory.o malta-platform.o \
10 malta-reset.o malta-setup.o malta-time.o 10 malta-reset.o malta-setup.o malta-time.o
11 11
12obj-$(CONFIG_EARLY_PRINTK) += malta-console.o
13
14# FIXME FIXME FIXME 12# FIXME FIXME FIXME
15obj-$(CONFIG_MIPS_MT_SMTC) += malta-smtc.o 13obj-$(CONFIG_MIPS_MT_SMTC) += malta-smtc.o
diff --git a/arch/mips/mti-malta/malta-amon.c b/arch/mips/mti-malta/malta-amon.c
index 1e4784458016..592ac0427426 100644
--- a/arch/mips/mti-malta/malta-amon.c
+++ b/arch/mips/mti-malta/malta-amon.c
@@ -1,30 +1,20 @@
1/* 1/*
2 * Copyright (C) 2007 MIPS Technologies, Inc. 2 * This file is subject to the terms and conditions of the GNU General Public
3 * All rights reserved. 3 * License. See the file "COPYING" in the main directory of this archive
4 4 * for more details.
5 * This program is free software; you can distribute it and/or modify it
6 * under the terms of the GNU General Public License (Version 2) as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * for more details.
13 * 5 *
14 * You should have received a copy of the GNU General Public License along 6 * Copyright (C) 2007 MIPS Technologies, Inc. All rights reserved.
15 * with this program; if not, write to the Free Software Foundation, Inc., 7 * Copyright (C) 2013 Imagination Technologies Ltd.
16 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
17 * 8 *
18 * Arbitrary Monitor interface 9 * Arbitrary Monitor Interface
19 */ 10 */
20
21#include <linux/kernel.h> 11#include <linux/kernel.h>
22#include <linux/init.h>
23#include <linux/smp.h> 12#include <linux/smp.h>
24 13
25#include <asm/addrspace.h> 14#include <asm/addrspace.h>
26#include <asm/mips-boards/launch.h>
27#include <asm/mipsmtregs.h> 15#include <asm/mipsmtregs.h>
16#include <asm/mips-boards/launch.h>
17#include <asm/vpe.h>
28 18
29int amon_cpu_avail(int cpu) 19int amon_cpu_avail(int cpu)
30{ 20{
@@ -48,7 +38,7 @@ int amon_cpu_avail(int cpu)
48 return 1; 38 return 1;
49} 39}
50 40
51void amon_cpu_start(int cpu, 41int amon_cpu_start(int cpu,
52 unsigned long pc, unsigned long sp, 42 unsigned long pc, unsigned long sp,
53 unsigned long gp, unsigned long a0) 43 unsigned long gp, unsigned long a0)
54{ 44{
@@ -56,10 +46,10 @@ void amon_cpu_start(int cpu,
56 (struct cpulaunch *)CKSEG0ADDR(CPULAUNCH); 46 (struct cpulaunch *)CKSEG0ADDR(CPULAUNCH);
57 47
58 if (!amon_cpu_avail(cpu)) 48 if (!amon_cpu_avail(cpu))
59 return; 49 return -1;
60 if (cpu == smp_processor_id()) { 50 if (cpu == smp_processor_id()) {
61 pr_debug("launch: I am cpu%d!\n", cpu); 51 pr_debug("launch: I am cpu%d!\n", cpu);
62 return; 52 return -1;
63 } 53 }
64 launch += cpu; 54 launch += cpu;
65 55
@@ -78,4 +68,21 @@ void amon_cpu_start(int cpu,
78 ; 68 ;
79 smp_rmb(); /* Target will be updating flags soon */ 69 smp_rmb(); /* Target will be updating flags soon */
80 pr_debug("launch: cpu%d gone!\n", cpu); 70 pr_debug("launch: cpu%d gone!\n", cpu);
71
72 return 0;
73}
74
75#ifdef CONFIG_MIPS_VPE_LOADER
76int vpe_run(struct vpe *v)
77{
78 struct vpe_notifications *n;
79
80 if (amon_cpu_start(aprp_cpu_index(), v->__start, 0, 0, 0) < 0)
81 return -1;
82
83 list_for_each_entry(n, &v->notify, list)
84 n->start(VPE_MODULE_MINOR);
85
86 return 0;
81} 87}
88#endif
diff --git a/arch/mips/mti-malta/malta-console.c b/arch/mips/mti-malta/malta-console.c
deleted file mode 100644
index 43bcfb4f8167..000000000000
--- a/arch/mips/mti-malta/malta-console.c
+++ /dev/null
@@ -1,47 +0,0 @@
1/*
2 * Carsten Langgaard, carstenl@mips.com
3 * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
4 *
5 * This program is free software; you can distribute it and/or modify it
6 * under the terms of the GNU General Public License (Version 2) as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * for more details.
13 *
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
17 *
18 * Putting things on the screen/serial line using YAMONs facilities.
19 */
20#include <linux/console.h>
21#include <linux/init.h>
22#include <linux/serial_reg.h>
23#include <asm/io.h>
24
25
26#define PORT(offset) (0x3f8 + (offset))
27
28
29static inline unsigned int serial_in(int offset)
30{
31 return inb(PORT(offset));
32}
33
34static inline void serial_out(int offset, int value)
35{
36 outb(value, PORT(offset));
37}
38
39int prom_putchar(char c)
40{
41 while ((serial_in(UART_LSR) & UART_LSR_THRE) == 0)
42 ;
43
44 serial_out(UART_TX, c);
45
46 return 1;
47}
diff --git a/arch/mips/mti-malta/malta-init.c b/arch/mips/mti-malta/malta-init.c
index ff8caffd3266..fcebfced26d0 100644
--- a/arch/mips/mti-malta/malta-init.c
+++ b/arch/mips/mti-malta/malta-init.c
@@ -14,6 +14,7 @@
14#include <linux/init.h> 14#include <linux/init.h>
15#include <linux/string.h> 15#include <linux/string.h>
16#include <linux/kernel.h> 16#include <linux/kernel.h>
17#include <linux/serial_8250.h>
17 18
18#include <asm/cacheflush.h> 19#include <asm/cacheflush.h>
19#include <asm/smp-ops.h> 20#include <asm/smp-ops.h>
@@ -44,32 +45,39 @@ static void __init console_config(void)
44 char parity = '\0', bits = '\0', flow = '\0'; 45 char parity = '\0', bits = '\0', flow = '\0';
45 char *s; 46 char *s;
46 47
47 if ((strstr(fw_getcmdline(), "console=")) == NULL) { 48 s = fw_getenv("modetty0");
48 s = fw_getenv("modetty0"); 49 if (s) {
49 if (s) { 50 while (*s >= '0' && *s <= '9')
50 while (*s >= '0' && *s <= '9') 51 baud = baud*10 + *s++ - '0';
51 baud = baud*10 + *s++ - '0'; 52 if (*s == ',')
52 if (*s == ',') 53 s++;
53 s++; 54 if (*s)
54 if (*s) 55 parity = *s++;
55 parity = *s++; 56 if (*s == ',')
56 if (*s == ',') 57 s++;
57 s++; 58 if (*s)
58 if (*s) 59 bits = *s++;
59 bits = *s++; 60 if (*s == ',')
60 if (*s == ',') 61 s++;
61 s++; 62 if (*s == 'h')
62 if (*s == 'h')
63 flow = 'r';
64 }
65 if (baud == 0)
66 baud = 38400;
67 if (parity != 'n' && parity != 'o' && parity != 'e')
68 parity = 'n';
69 if (bits != '7' && bits != '8')
70 bits = '8';
71 if (flow == '\0')
72 flow = 'r'; 63 flow = 'r';
64 }
65 if (baud == 0)
66 baud = 38400;
67 if (parity != 'n' && parity != 'o' && parity != 'e')
68 parity = 'n';
69 if (bits != '7' && bits != '8')
70 bits = '8';
71 if (flow == '\0')
72 flow = 'r';
73
74 if ((strstr(fw_getcmdline(), "earlycon=")) == NULL) {
75 sprintf(console_string, "uart8250,io,0x3f8,%d%c%c", baud,
76 parity, bits);
77 setup_early_serial8250_console(console_string);
78 }
79
80 if ((strstr(fw_getcmdline(), "console=")) == NULL) {
73 sprintf(console_string, " console=ttyS0,%d%c%c%c", baud, 81 sprintf(console_string, " console=ttyS0,%d%c%c%c", baud,
74 parity, bits, flow); 82 parity, bits, flow);
75 strcat(fw_getcmdline(), console_string); 83 strcat(fw_getcmdline(), console_string);
diff --git a/arch/mips/mti-malta/malta-int.c b/arch/mips/mti-malta/malta-int.c
index 0892575f829d..ca3e3a46a42f 100644
--- a/arch/mips/mti-malta/malta-int.c
+++ b/arch/mips/mti-malta/malta-int.c
@@ -1,25 +1,16 @@
1/* 1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
2 * Carsten Langgaard, carstenl@mips.com 6 * Carsten Langgaard, carstenl@mips.com
3 * Copyright (C) 2000, 2001, 2004 MIPS Technologies, Inc. 7 * Copyright (C) 2000, 2001, 2004 MIPS Technologies, Inc.
4 * Copyright (C) 2001 Ralf Baechle 8 * Copyright (C) 2001 Ralf Baechle
5 * 9 * Copyright (C) 2013 Imagination Technologies Ltd.
6 * This program is free software; you can distribute it and/or modify it
7 * under the terms of the GNU General Public License (Version 2) as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * for more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, write to the Free Software Foundation, Inc.,
17 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
18 * 10 *
19 * Routines for generic manipulation of the interrupts found on the MIPS 11 * Routines for generic manipulation of the interrupts found on the MIPS
20 * Malta board. 12 * Malta board. The interrupt controller is located in the South Bridge
21 * The interrupt controller is located in the South Bridge a PIIX4 device 13 * a PIIX4 device with two internal 82C95 interrupt controllers.
22 * with two internal 82C95 interrupt controllers.
23 */ 14 */
24#include <linux/init.h> 15#include <linux/init.h>
25#include <linux/irq.h> 16#include <linux/irq.h>
@@ -44,6 +35,7 @@
44#include <asm/gic.h> 35#include <asm/gic.h>
45#include <asm/gcmpregs.h> 36#include <asm/gcmpregs.h>
46#include <asm/setup.h> 37#include <asm/setup.h>
38#include <asm/rtlx.h>
47 39
48int gcmp_present = -1; 40int gcmp_present = -1;
49static unsigned long _msc01_biu_base; 41static unsigned long _msc01_biu_base;
@@ -90,7 +82,7 @@ static inline int mips_pcibios_iack(void)
90 BONITO_PCIMAP_CFG = 0; 82 BONITO_PCIMAP_CFG = 0;
91 break; 83 break;
92 default: 84 default:
93 printk(KERN_WARNING "Unknown system controller.\n"); 85 pr_emerg("Unknown system controller.\n");
94 return -1; 86 return -1;
95 } 87 }
96 return irq; 88 return irq;
@@ -126,6 +118,11 @@ static void malta_hw0_irqdispatch(void)
126 } 118 }
127 119
128 do_IRQ(MALTA_INT_BASE + irq); 120 do_IRQ(MALTA_INT_BASE + irq);
121
122#ifdef MIPS_VPE_APSP_API
123 if (aprp_hook)
124 aprp_hook();
125#endif
129} 126}
130 127
131static void malta_ipi_irqdispatch(void) 128static void malta_ipi_irqdispatch(void)
@@ -149,11 +146,11 @@ static void corehi_irqdispatch(void)
149 unsigned int intrcause, datalo, datahi; 146 unsigned int intrcause, datalo, datahi;
150 struct pt_regs *regs = get_irq_regs(); 147 struct pt_regs *regs = get_irq_regs();
151 148
152 printk(KERN_EMERG "CoreHI interrupt, shouldn't happen, we die here!\n"); 149 pr_emerg("CoreHI interrupt, shouldn't happen, we die here!\n");
153 printk(KERN_EMERG "epc : %08lx\nStatus: %08lx\n" 150 pr_emerg("epc : %08lx\nStatus: %08lx\n"
154 "Cause : %08lx\nbadVaddr : %08lx\n", 151 "Cause : %08lx\nbadVaddr : %08lx\n",
155 regs->cp0_epc, regs->cp0_status, 152 regs->cp0_epc, regs->cp0_status,
156 regs->cp0_cause, regs->cp0_badvaddr); 153 regs->cp0_cause, regs->cp0_badvaddr);
157 154
158 /* Read all the registers and then print them as there is a 155 /* Read all the registers and then print them as there is a
159 problem with interspersed printk's upsetting the Bonito controller. 156 problem with interspersed printk's upsetting the Bonito controller.
@@ -171,8 +168,8 @@ static void corehi_irqdispatch(void)
171 intrcause = GT_READ(GT_INTRCAUSE_OFS); 168 intrcause = GT_READ(GT_INTRCAUSE_OFS);
172 datalo = GT_READ(GT_CPUERR_ADDRLO_OFS); 169 datalo = GT_READ(GT_CPUERR_ADDRLO_OFS);
173 datahi = GT_READ(GT_CPUERR_ADDRHI_OFS); 170 datahi = GT_READ(GT_CPUERR_ADDRHI_OFS);
174 printk(KERN_EMERG "GT_INTRCAUSE = %08x\n", intrcause); 171 pr_emerg("GT_INTRCAUSE = %08x\n", intrcause);
175 printk(KERN_EMERG "GT_CPUERR_ADDR = %02x%08x\n", 172 pr_emerg("GT_CPUERR_ADDR = %02x%08x\n",
176 datahi, datalo); 173 datahi, datalo);
177 break; 174 break;
178 case MIPS_REVISION_SCON_BONITO: 175 case MIPS_REVISION_SCON_BONITO:
@@ -184,14 +181,14 @@ static void corehi_irqdispatch(void)
184 intedge = BONITO_INTEDGE; 181 intedge = BONITO_INTEDGE;
185 intsteer = BONITO_INTSTEER; 182 intsteer = BONITO_INTSTEER;
186 pcicmd = BONITO_PCICMD; 183 pcicmd = BONITO_PCICMD;
187 printk(KERN_EMERG "BONITO_INTISR = %08x\n", intisr); 184 pr_emerg("BONITO_INTISR = %08x\n", intisr);
188 printk(KERN_EMERG "BONITO_INTEN = %08x\n", inten); 185 pr_emerg("BONITO_INTEN = %08x\n", inten);
189 printk(KERN_EMERG "BONITO_INTPOL = %08x\n", intpol); 186 pr_emerg("BONITO_INTPOL = %08x\n", intpol);
190 printk(KERN_EMERG "BONITO_INTEDGE = %08x\n", intedge); 187 pr_emerg("BONITO_INTEDGE = %08x\n", intedge);
191 printk(KERN_EMERG "BONITO_INTSTEER = %08x\n", intsteer); 188 pr_emerg("BONITO_INTSTEER = %08x\n", intsteer);
192 printk(KERN_EMERG "BONITO_PCICMD = %08x\n", pcicmd); 189 pr_emerg("BONITO_PCICMD = %08x\n", pcicmd);
193 printk(KERN_EMERG "BONITO_PCIBADADDR = %08x\n", pcibadaddr); 190 pr_emerg("BONITO_PCIBADADDR = %08x\n", pcibadaddr);
194 printk(KERN_EMERG "BONITO_PCIMSTAT = %08x\n", pcimstat); 191 pr_emerg("BONITO_PCIMSTAT = %08x\n", pcimstat);
195 break; 192 break;
196 } 193 }
197 194
@@ -313,6 +310,11 @@ static void ipi_call_dispatch(void)
313 310
314static irqreturn_t ipi_resched_interrupt(int irq, void *dev_id) 311static irqreturn_t ipi_resched_interrupt(int irq, void *dev_id)
315{ 312{
313#ifdef MIPS_VPE_APSP_API
314 if (aprp_hook)
315 aprp_hook();
316#endif
317
316 scheduler_ipi(); 318 scheduler_ipi();
317 319
318 return IRQ_HANDLED; 320 return IRQ_HANDLED;
@@ -365,13 +367,13 @@ static struct irqaction corehi_irqaction = {
365 .flags = IRQF_NO_THREAD, 367 .flags = IRQF_NO_THREAD,
366}; 368};
367 369
368static msc_irqmap_t __initdata msc_irqmap[] = { 370static msc_irqmap_t msc_irqmap[] __initdata = {
369 {MSC01C_INT_TMR, MSC01_IRQ_EDGE, 0}, 371 {MSC01C_INT_TMR, MSC01_IRQ_EDGE, 0},
370 {MSC01C_INT_PCI, MSC01_IRQ_LEVEL, 0}, 372 {MSC01C_INT_PCI, MSC01_IRQ_LEVEL, 0},
371}; 373};
372static int __initdata msc_nr_irqs = ARRAY_SIZE(msc_irqmap); 374static int msc_nr_irqs __initdata = ARRAY_SIZE(msc_irqmap);
373 375
374static msc_irqmap_t __initdata msc_eicirqmap[] = { 376static msc_irqmap_t msc_eicirqmap[] __initdata = {
375 {MSC01E_INT_SW0, MSC01_IRQ_LEVEL, 0}, 377 {MSC01E_INT_SW0, MSC01_IRQ_LEVEL, 0},
376 {MSC01E_INT_SW1, MSC01_IRQ_LEVEL, 0}, 378 {MSC01E_INT_SW1, MSC01_IRQ_LEVEL, 0},
377 {MSC01E_INT_I8259A, MSC01_IRQ_LEVEL, 0}, 379 {MSC01E_INT_I8259A, MSC01_IRQ_LEVEL, 0},
@@ -384,7 +386,7 @@ static msc_irqmap_t __initdata msc_eicirqmap[] = {
384 {MSC01E_INT_CPUCTR, MSC01_IRQ_LEVEL, 0} 386 {MSC01E_INT_CPUCTR, MSC01_IRQ_LEVEL, 0}
385}; 387};
386 388
387static int __initdata msc_nr_eicirqs = ARRAY_SIZE(msc_eicirqmap); 389static int msc_nr_eicirqs __initdata = ARRAY_SIZE(msc_eicirqmap);
388 390
389/* 391/*
390 * This GIC specific tabular array defines the association between External 392 * This GIC specific tabular array defines the association between External
@@ -431,9 +433,12 @@ int __init gcmp_probe(unsigned long addr, unsigned long size)
431 if (gcmp_present >= 0) 433 if (gcmp_present >= 0)
432 return gcmp_present; 434 return gcmp_present;
433 435
434 _gcmp_base = (unsigned long) ioremap_nocache(GCMP_BASE_ADDR, GCMP_ADDRSPACE_SZ); 436 _gcmp_base = (unsigned long) ioremap_nocache(GCMP_BASE_ADDR,
435 _msc01_biu_base = (unsigned long) ioremap_nocache(MSC01_BIU_REG_BASE, MSC01_BIU_ADDRSPACE_SZ); 437 GCMP_ADDRSPACE_SZ);
436 gcmp_present = (GCMPGCB(GCMPB) & GCMP_GCB_GCMPB_GCMPBASE_MSK) == GCMP_BASE_ADDR; 438 _msc01_biu_base = (unsigned long) ioremap_nocache(MSC01_BIU_REG_BASE,
439 MSC01_BIU_ADDRSPACE_SZ);
440 gcmp_present = ((GCMPGCB(GCMPB) & GCMP_GCB_GCMPB_GCMPBASE_MSK) ==
441 GCMP_BASE_ADDR);
437 442
438 if (gcmp_present) 443 if (gcmp_present)
439 pr_debug("GCMP present\n"); 444 pr_debug("GCMP present\n");
@@ -443,9 +448,8 @@ int __init gcmp_probe(unsigned long addr, unsigned long size)
443/* Return the number of IOCU's present */ 448/* Return the number of IOCU's present */
444int __init gcmp_niocu(void) 449int __init gcmp_niocu(void)
445{ 450{
446 return gcmp_present ? 451 return gcmp_present ? ((GCMPGCB(GC) & GCMP_GCB_GC_NUMIOCU_MSK) >>
447 (GCMPGCB(GC) & GCMP_GCB_GC_NUMIOCU_MSK) >> GCMP_GCB_GC_NUMIOCU_SHF : 452 GCMP_GCB_GC_NUMIOCU_SHF) : 0;
448 0;
449} 453}
450 454
451/* Set GCMP region attributes */ 455/* Set GCMP region attributes */
@@ -594,11 +598,14 @@ void __init arch_init_irq(void)
594 set_vi_handler(MIPSCPU_INT_IPI1, malta_ipi_irqdispatch); 598 set_vi_handler(MIPSCPU_INT_IPI1, malta_ipi_irqdispatch);
595 } 599 }
596 /* Argh.. this really needs sorting out.. */ 600 /* Argh.. this really needs sorting out.. */
597 printk("CPU%d: status register was %08x\n", smp_processor_id(), read_c0_status()); 601 pr_info("CPU%d: status register was %08x\n",
602 smp_processor_id(), read_c0_status());
598 write_c0_status(read_c0_status() | STATUSF_IP3 | STATUSF_IP4); 603 write_c0_status(read_c0_status() | STATUSF_IP3 | STATUSF_IP4);
599 printk("CPU%d: status register now %08x\n", smp_processor_id(), read_c0_status()); 604 pr_info("CPU%d: status register now %08x\n",
605 smp_processor_id(), read_c0_status());
600 write_c0_status(0x1100dc00); 606 write_c0_status(0x1100dc00);
601 printk("CPU%d: status register frc %08x\n", smp_processor_id(), read_c0_status()); 607 pr_info("CPU%d: status register frc %08x\n",
608 smp_processor_id(), read_c0_status());
602 for (i = 0; i < nr_cpu_ids; i++) { 609 for (i = 0; i < nr_cpu_ids; i++) {
603 arch_init_ipiirq(MIPS_GIC_IRQ_BASE + 610 arch_init_ipiirq(MIPS_GIC_IRQ_BASE +
604 GIC_RESCHED_INT(i), &irq_resched); 611 GIC_RESCHED_INT(i), &irq_resched);
@@ -616,11 +623,15 @@ void __init arch_init_irq(void)
616 cpu_ipi_call_irq = MSC01E_INT_SW1; 623 cpu_ipi_call_irq = MSC01E_INT_SW1;
617 } else { 624 } else {
618 if (cpu_has_vint) { 625 if (cpu_has_vint) {
619 set_vi_handler (MIPS_CPU_IPI_RESCHED_IRQ, ipi_resched_dispatch); 626 set_vi_handler (MIPS_CPU_IPI_RESCHED_IRQ,
620 set_vi_handler (MIPS_CPU_IPI_CALL_IRQ, ipi_call_dispatch); 627 ipi_resched_dispatch);
628 set_vi_handler (MIPS_CPU_IPI_CALL_IRQ,
629 ipi_call_dispatch);
621 } 630 }
622 cpu_ipi_resched_irq = MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_RESCHED_IRQ; 631 cpu_ipi_resched_irq = MIPS_CPU_IRQ_BASE +
623 cpu_ipi_call_irq = MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_CALL_IRQ; 632 MIPS_CPU_IPI_RESCHED_IRQ;
633 cpu_ipi_call_irq = MIPS_CPU_IRQ_BASE +
634 MIPS_CPU_IPI_CALL_IRQ;
624 } 635 }
625 arch_init_ipiirq(cpu_ipi_resched_irq, &irq_resched); 636 arch_init_ipiirq(cpu_ipi_resched_irq, &irq_resched);
626 arch_init_ipiirq(cpu_ipi_call_irq, &irq_call); 637 arch_init_ipiirq(cpu_ipi_call_irq, &irq_call);
@@ -630,9 +641,7 @@ void __init arch_init_irq(void)
630 641
631void malta_be_init(void) 642void malta_be_init(void)
632{ 643{
633 if (gcmp_present) { 644 /* Could change CM error mask register. */
634 /* Could change CM error mask register */
635 }
636} 645}
637 646
638 647
@@ -712,14 +721,14 @@ int malta_be_handler(struct pt_regs *regs, int is_fixup)
712 if (cause < 16) { 721 if (cause < 16) {
713 unsigned long cca_bits = (cm_error >> 15) & 7; 722 unsigned long cca_bits = (cm_error >> 15) & 7;
714 unsigned long tr_bits = (cm_error >> 12) & 7; 723 unsigned long tr_bits = (cm_error >> 12) & 7;
715 unsigned long mcmd_bits = (cm_error >> 7) & 0x1f; 724 unsigned long cmd_bits = (cm_error >> 7) & 0x1f;
716 unsigned long stag_bits = (cm_error >> 3) & 15; 725 unsigned long stag_bits = (cm_error >> 3) & 15;
717 unsigned long sport_bits = (cm_error >> 0) & 7; 726 unsigned long sport_bits = (cm_error >> 0) & 7;
718 727
719 snprintf(buf, sizeof(buf), 728 snprintf(buf, sizeof(buf),
720 "CCA=%lu TR=%s MCmd=%s STag=%lu " 729 "CCA=%lu TR=%s MCmd=%s STag=%lu "
721 "SPort=%lu\n", 730 "SPort=%lu\n",
722 cca_bits, tr[tr_bits], mcmd[mcmd_bits], 731 cca_bits, tr[tr_bits], mcmd[cmd_bits],
723 stag_bits, sport_bits); 732 stag_bits, sport_bits);
724 } else { 733 } else {
725 /* glob state & sresp together */ 734 /* glob state & sresp together */
@@ -728,7 +737,7 @@ int malta_be_handler(struct pt_regs *regs, int is_fixup)
728 unsigned long c1_bits = (cm_error >> 12) & 7; 737 unsigned long c1_bits = (cm_error >> 12) & 7;
729 unsigned long c0_bits = (cm_error >> 9) & 7; 738 unsigned long c0_bits = (cm_error >> 9) & 7;
730 unsigned long sc_bit = (cm_error >> 8) & 1; 739 unsigned long sc_bit = (cm_error >> 8) & 1;
731 unsigned long mcmd_bits = (cm_error >> 3) & 0x1f; 740 unsigned long cmd_bits = (cm_error >> 3) & 0x1f;
732 unsigned long sport_bits = (cm_error >> 0) & 7; 741 unsigned long sport_bits = (cm_error >> 0) & 7;
733 snprintf(buf, sizeof(buf), 742 snprintf(buf, sizeof(buf),
734 "C3=%s C2=%s C1=%s C0=%s SC=%s " 743 "C3=%s C2=%s C1=%s C0=%s SC=%s "
@@ -736,16 +745,16 @@ int malta_be_handler(struct pt_regs *regs, int is_fixup)
736 core[c3_bits], core[c2_bits], 745 core[c3_bits], core[c2_bits],
737 core[c1_bits], core[c0_bits], 746 core[c1_bits], core[c0_bits],
738 sc_bit ? "True" : "False", 747 sc_bit ? "True" : "False",
739 mcmd[mcmd_bits], sport_bits); 748 mcmd[cmd_bits], sport_bits);
740 } 749 }
741 750
742 ocause = (cm_other & GCMP_GCB_GMEO_ERROR_2ND_MSK) >> 751 ocause = (cm_other & GCMP_GCB_GMEO_ERROR_2ND_MSK) >>
743 GCMP_GCB_GMEO_ERROR_2ND_SHF; 752 GCMP_GCB_GMEO_ERROR_2ND_SHF;
744 753
745 printk("CM_ERROR=%08lx %s <%s>\n", cm_error, 754 pr_err("CM_ERROR=%08lx %s <%s>\n", cm_error,
746 causes[cause], buf); 755 causes[cause], buf);
747 printk("CM_ADDR =%08lx\n", cm_addr); 756 pr_err("CM_ADDR =%08lx\n", cm_addr);
748 printk("CM_OTHER=%08lx %s\n", cm_other, causes[ocause]); 757 pr_err("CM_OTHER=%08lx %s\n", cm_other, causes[ocause]);
749 758
750 /* reprime cause register */ 759 /* reprime cause register */
751 GCMPGCB(GCMEC) = 0; 760 GCMPGCB(GCMEC) = 0;
diff --git a/arch/mips/mti-malta/malta-platform.c b/arch/mips/mti-malta/malta-platform.c
index 132f8663825e..e1dd1c1d3fde 100644
--- a/arch/mips/mti-malta/malta-platform.c
+++ b/arch/mips/mti-malta/malta-platform.c
@@ -47,6 +47,7 @@
47static struct plat_serial8250_port uart8250_data[] = { 47static struct plat_serial8250_port uart8250_data[] = {
48 SMC_PORT(0x3F8, 4), 48 SMC_PORT(0x3F8, 4),
49 SMC_PORT(0x2F8, 3), 49 SMC_PORT(0x2F8, 3),
50#ifndef CONFIG_MIPS_CMP
50 { 51 {
51 .mapbase = 0x1f000900, /* The CBUS UART */ 52 .mapbase = 0x1f000900, /* The CBUS UART */
52 .irq = MIPS_CPU_IRQ_BASE + MIPSCPU_INT_MB2, 53 .irq = MIPS_CPU_IRQ_BASE + MIPSCPU_INT_MB2,
@@ -55,6 +56,7 @@ static struct plat_serial8250_port uart8250_data[] = {
55 .flags = CBUS_UART_FLAGS, 56 .flags = CBUS_UART_FLAGS,
56 .regshift = 3, 57 .regshift = 3,
57 }, 58 },
59#endif
58 { }, 60 { },
59}; 61};
60 62
diff --git a/arch/mips/mti-malta/malta-time.c b/arch/mips/mti-malta/malta-time.c
index a18af5fce67e..319009912142 100644
--- a/arch/mips/mti-malta/malta-time.c
+++ b/arch/mips/mti-malta/malta-time.c
@@ -42,8 +42,6 @@
42#include <asm/mips-boards/generic.h> 42#include <asm/mips-boards/generic.h>
43#include <asm/mips-boards/maltaint.h> 43#include <asm/mips-boards/maltaint.h>
44 44
45unsigned long cpu_khz;
46
47static int mips_cpu_timer_irq; 45static int mips_cpu_timer_irq;
48static int mips_cpu_perf_irq; 46static int mips_cpu_perf_irq;
49extern int cp0_perfcount_irq; 47extern int cp0_perfcount_irq;
@@ -168,11 +166,24 @@ unsigned int get_c0_compare_int(void)
168 return mips_cpu_timer_irq; 166 return mips_cpu_timer_irq;
169} 167}
170 168
169static void __init init_rtc(void)
170{
171 /* stop the clock whilst setting it up */
172 CMOS_WRITE(RTC_SET | RTC_24H, RTC_CONTROL);
173
174 /* 32KHz time base */
175 CMOS_WRITE(RTC_REF_CLCK_32KHZ, RTC_FREQ_SELECT);
176
177 /* start the clock */
178 CMOS_WRITE(RTC_24H, RTC_CONTROL);
179}
180
171void __init plat_time_init(void) 181void __init plat_time_init(void)
172{ 182{
173 unsigned int prid = read_c0_prid() & (PRID_COMP_MASK | PRID_IMP_MASK); 183 unsigned int prid = read_c0_prid() & (PRID_COMP_MASK | PRID_IMP_MASK);
174 unsigned int freq; 184 unsigned int freq;
175 185
186 init_rtc();
176 estimate_frequencies(); 187 estimate_frequencies();
177 188
178 freq = mips_hpt_frequency; 189 freq = mips_hpt_frequency;
@@ -182,7 +193,6 @@ void __init plat_time_init(void)
182 freq = freqround(freq, 5000); 193 freq = freqround(freq, 5000);
183 printk("CPU frequency %d.%02d MHz\n", freq/1000000, 194 printk("CPU frequency %d.%02d MHz\n", freq/1000000,
184 (freq%1000000)*100/1000000); 195 (freq%1000000)*100/1000000);
185 cpu_khz = freq / 1000;
186 196
187 mips_scroll_message(); 197 mips_scroll_message();
188 198
diff --git a/arch/mips/mti-sead3/Makefile b/arch/mips/mti-sead3/Makefile
index be114209217c..071786fa234b 100644
--- a/arch/mips/mti-sead3/Makefile
+++ b/arch/mips/mti-sead3/Makefile
@@ -21,5 +21,7 @@ obj-$(CONFIG_EARLY_PRINTK) += sead3-console.o
21obj-$(CONFIG_USB_EHCI_HCD) += sead3-ehci.o 21obj-$(CONFIG_USB_EHCI_HCD) += sead3-ehci.o
22obj-$(CONFIG_OF) += sead3.dtb.o 22obj-$(CONFIG_OF) += sead3.dtb.o
23 23
24CFLAGS_sead3-setup.o = -I$(src)/../../../scripts/dtc/libfdt
25
24$(obj)/%.dtb: $(obj)/%.dts 26$(obj)/%.dtb: $(obj)/%.dts
25 $(call if_changed,dtc) 27 $(call if_changed,dtc)
diff --git a/arch/mips/mti-sead3/sead3-pic32-bus.c b/arch/mips/mti-sead3/sead3-pic32-bus.c
index eb2bf936d102..3b12aa5a7c88 100644
--- a/arch/mips/mti-sead3/sead3-pic32-bus.c
+++ b/arch/mips/mti-sead3/sead3-pic32-bus.c
@@ -8,7 +8,6 @@
8#include <linux/delay.h> 8#include <linux/delay.h>
9#include <linux/kernel.h> 9#include <linux/kernel.h>
10#include <linux/spinlock.h> 10#include <linux/spinlock.h>
11#include <linux/init.h>
12#include <linux/io.h> 11#include <linux/io.h>
13#include <linux/errno.h> 12#include <linux/errno.h>
14 13
diff --git a/arch/mips/mti-sead3/sead3-setup.c b/arch/mips/mti-sead3/sead3-setup.c
index 928ba84c8a78..bf7fe48bf2f9 100644
--- a/arch/mips/mti-sead3/sead3-setup.c
+++ b/arch/mips/mti-sead3/sead3-setup.c
@@ -4,13 +4,15 @@
4 * for more details. 4 * for more details.
5 * 5 *
6 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. 6 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
7 * Copyright (C) 2013 Imagination Technologies Ltd.
7 */ 8 */
8#include <linux/init.h> 9#include <linux/init.h>
10#include <linux/libfdt.h>
9#include <linux/of_platform.h> 11#include <linux/of_platform.h>
10#include <linux/of_fdt.h> 12#include <linux/of_fdt.h>
11#include <linux/bootmem.h>
12 13
13#include <asm/prom.h> 14#include <asm/prom.h>
15#include <asm/fw/fw.h>
14 16
15#include <asm/mips-boards/generic.h> 17#include <asm/mips-boards/generic.h>
16 18
@@ -19,8 +21,73 @@ const char *get_system_type(void)
19 return "MIPS SEAD3"; 21 return "MIPS SEAD3";
20} 22}
21 23
24static uint32_t get_memsize_from_cmdline(void)
25{
26 int memsize = 0;
27 char *p = arcs_cmdline;
28 char *s = "memsize=";
29
30 p = strstr(p, s);
31 if (p) {
32 p += strlen(s);
33 memsize = memparse(p, NULL);
34 }
35
36 return memsize;
37}
38
39static uint32_t get_memsize_from_env(void)
40{
41 int memsize = 0;
42 char *p;
43
44 p = fw_getenv("memsize");
45 if (p)
46 memsize = memparse(p, NULL);
47
48 return memsize;
49}
50
51static uint32_t get_memsize(void)
52{
53 uint32_t memsize;
54
55 memsize = get_memsize_from_cmdline();
56 if (memsize)
57 return memsize;
58
59 return get_memsize_from_env();
60}
61
62static void __init parse_memsize_param(void)
63{
64 int offset;
65 const uint64_t *prop_value;
66 int prop_len;
67 uint32_t memsize = get_memsize();
68
69 if (!memsize)
70 return;
71
72 offset = fdt_path_offset(&__dtb_start, "/memory");
73 if (offset > 0) {
74 uint64_t new_value;
75 /*
76 * reg contains 2 32-bits BE values, offset and size. We just
77 * want to replace the size value without affecting the offset
78 */
79 prop_value = fdt_getprop(&__dtb_start, offset, "reg", &prop_len);
80 new_value = be64_to_cpu(*prop_value);
81 new_value = (new_value & ~0xffffffffllu) | memsize;
82 fdt_setprop_inplace_u64(&__dtb_start, offset, "reg", new_value);
83 }
84}
85
22void __init plat_mem_setup(void) 86void __init plat_mem_setup(void)
23{ 87{
88 /* allow command line/bootloader env to override memory size in DT */
89 parse_memsize_param();
90
24 /* 91 /*
25 * Load the builtin devicetree. This causes the chosen node to be 92 * Load the builtin devicetree. This causes the chosen node to be
26 * parsed resulting in our memory appearing 93 * parsed resulting in our memory appearing
@@ -30,16 +97,15 @@ void __init plat_mem_setup(void)
30 97
31void __init device_tree_init(void) 98void __init device_tree_init(void)
32{ 99{
33 unsigned long base, size;
34
35 if (!initial_boot_params) 100 if (!initial_boot_params)
36 return; 101 return;
37 102
38 base = virt_to_phys((void *)initial_boot_params); 103 unflatten_and_copy_device_tree();
39 size = be32_to_cpu(initial_boot_params->totalsize); 104}
40
41 /* Before we do anything, lets reserve the dt blob */
42 reserve_bootmem(base, size, BOOTMEM_DEFAULT);
43 105
44 unflatten_device_tree(); 106static int __init customize_machine(void)
107{
108 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
109 return 0;
45} 110}
111arch_initcall(customize_machine);
diff --git a/arch/mips/mti-sead3/sead3-time.c b/arch/mips/mti-sead3/sead3-time.c
index 552d26c34386..678d03d53c60 100644
--- a/arch/mips/mti-sead3/sead3-time.c
+++ b/arch/mips/mti-sead3/sead3-time.c
@@ -13,8 +13,6 @@
13#include <asm/irq.h> 13#include <asm/irq.h>
14#include <asm/mips-boards/generic.h> 14#include <asm/mips-boards/generic.h>
15 15
16unsigned long cpu_khz;
17
18static int mips_cpu_timer_irq; 16static int mips_cpu_timer_irq;
19static int mips_cpu_perf_irq; 17static int mips_cpu_perf_irq;
20 18
@@ -109,8 +107,6 @@ void __init plat_time_init(void)
109 pr_debug("CPU frequency %d.%02d MHz\n", (est_freq / 1000000), 107 pr_debug("CPU frequency %d.%02d MHz\n", (est_freq / 1000000),
110 (est_freq % 1000000) * 100 / 1000000); 108 (est_freq % 1000000) * 100 / 1000000);
111 109
112 cpu_khz = est_freq / 1000;
113
114 mips_scroll_message(); 110 mips_scroll_message();
115 111
116 plat_perf_setup(); 112 plat_perf_setup();
diff --git a/arch/mips/mti-sead3/sead3.dts b/arch/mips/mti-sead3/sead3.dts
index 658f43787056..e4b317d414f1 100644
--- a/arch/mips/mti-sead3/sead3.dts
+++ b/arch/mips/mti-sead3/sead3.dts
@@ -15,10 +15,6 @@
15 }; 15 };
16 }; 16 };
17 17
18 chosen {
19 bootargs = "console=ttyS1,38400 rootdelay=10 root=/dev/sda3";
20 };
21
22 memory { 18 memory {
23 device_type = "memory"; 19 device_type = "memory";
24 reg = <0x0 0x08000000>; 20 reg = <0x0 0x08000000>;
diff --git a/arch/mips/netlogic/Kconfig b/arch/mips/netlogic/Kconfig
index 852a4ee09954..4eb683aef7d7 100644
--- a/arch/mips/netlogic/Kconfig
+++ b/arch/mips/netlogic/Kconfig
@@ -28,6 +28,15 @@ config DT_XLP_FVP
28 pointer to the kernel. The corresponding DTS file is at 28 pointer to the kernel. The corresponding DTS file is at
29 arch/mips/netlogic/dts/xlp_fvp.dts 29 arch/mips/netlogic/dts/xlp_fvp.dts
30 30
31config DT_XLP_GVP
32 bool "Built-in device tree for XLP GVP boards"
33 default y
34 help
35 Add an FDT blob for XLP GVP board into the kernel.
36 This DTB will be used if the firmware does not pass in a DTB
37 pointer to the kernel. The corresponding DTS file is at
38 arch/mips/netlogic/dts/xlp_gvp.dts
39
31config NLM_MULTINODE 40config NLM_MULTINODE
32 bool "Support for multi-chip boards" 41 bool "Support for multi-chip boards"
33 depends on NLM_XLP_BOARD 42 depends on NLM_XLP_BOARD
diff --git a/arch/mips/netlogic/common/earlycons.c b/arch/mips/netlogic/common/earlycons.c
index 1902fa22d277..769f93032c53 100644
--- a/arch/mips/netlogic/common/earlycons.c
+++ b/arch/mips/netlogic/common/earlycons.c
@@ -37,9 +37,11 @@
37 37
38#include <asm/mipsregs.h> 38#include <asm/mipsregs.h>
39#include <asm/netlogic/haldefs.h> 39#include <asm/netlogic/haldefs.h>
40#include <asm/netlogic/common.h>
40 41
41#if defined(CONFIG_CPU_XLP) 42#if defined(CONFIG_CPU_XLP)
42#include <asm/netlogic/xlp-hal/iomap.h> 43#include <asm/netlogic/xlp-hal/iomap.h>
44#include <asm/netlogic/xlp-hal/xlp.h>
43#include <asm/netlogic/xlp-hal/uart.h> 45#include <asm/netlogic/xlp-hal/uart.h>
44#elif defined(CONFIG_CPU_XLR) 46#elif defined(CONFIG_CPU_XLR)
45#include <asm/netlogic/xlr/iomap.h> 47#include <asm/netlogic/xlr/iomap.h>
diff --git a/arch/mips/netlogic/common/irq.c b/arch/mips/netlogic/common/irq.c
index 1c7e3a1b81ab..5afc4b7fce0f 100644
--- a/arch/mips/netlogic/common/irq.c
+++ b/arch/mips/netlogic/common/irq.c
@@ -180,6 +180,7 @@ static void __init nlm_init_percpu_irqs(void)
180#endif 180#endif
181} 181}
182 182
183
183void nlm_setup_pic_irq(int node, int picirq, int irq, int irt) 184void nlm_setup_pic_irq(int node, int picirq, int irq, int irt)
184{ 185{
185 struct nlm_pic_irq *pic_data; 186 struct nlm_pic_irq *pic_data;
@@ -207,32 +208,32 @@ void nlm_set_pic_extra_ack(int node, int irq, void (*xack)(struct irq_data *))
207 208
208static void nlm_init_node_irqs(int node) 209static void nlm_init_node_irqs(int node)
209{ 210{
210 int i, irt;
211 uint64_t irqmask;
212 struct nlm_soc_info *nodep; 211 struct nlm_soc_info *nodep;
212 int i, irt;
213 213
214 pr_info("Init IRQ for node %d\n", node); 214 pr_info("Init IRQ for node %d\n", node);
215 nodep = nlm_get_node(node); 215 nodep = nlm_get_node(node);
216 irqmask = PERCPU_IRQ_MASK; 216 nodep->irqmask = PERCPU_IRQ_MASK;
217 for (i = PIC_IRT_FIRST_IRQ; i <= PIC_IRT_LAST_IRQ; i++) { 217 for (i = PIC_IRT_FIRST_IRQ; i <= PIC_IRT_LAST_IRQ; i++) {
218 irt = nlm_irq_to_irt(i); 218 irt = nlm_irq_to_irt(i);
219 if (irt == -1) 219 if (irt == -1) /* unused irq */
220 continue; 220 continue;
221 nlm_setup_pic_irq(node, i, i, irt); 221 nodep->irqmask |= 1ull << i;
222 /* set interrupts to first cpu in node */ 222 if (irt == -2) /* not a direct PIC irq */
223 continue;
224
223 nlm_pic_init_irt(nodep->picbase, irt, i, 225 nlm_pic_init_irt(nodep->picbase, irt, i,
224 node * NLM_CPUS_PER_NODE, 0); 226 node * nlm_threads_per_node(), 0);
225 irqmask |= (1ull << i); 227 nlm_setup_pic_irq(node, i, i, irt);
226 } 228 }
227 nodep->irqmask = irqmask;
228} 229}
229 230
230void nlm_smp_irq_init(int hwcpuid) 231void nlm_smp_irq_init(int hwcpuid)
231{ 232{
232 int node, cpu; 233 int node, cpu;
233 234
234 node = hwcpuid / NLM_CPUS_PER_NODE; 235 node = nlm_cpuid_to_node(hwcpuid);
235 cpu = hwcpuid % NLM_CPUS_PER_NODE; 236 cpu = hwcpuid % nlm_threads_per_node();
236 237
237 if (cpu == 0 && node != 0) 238 if (cpu == 0 && node != 0)
238 nlm_init_node_irqs(node); 239 nlm_init_node_irqs(node);
@@ -256,13 +257,23 @@ asmlinkage void plat_irq_dispatch(void)
256 return; 257 return;
257 } 258 }
258 259
260#if defined(CONFIG_PCI_MSI) && defined(CONFIG_CPU_XLP)
261 /* PCI interrupts need a second level dispatch for MSI bits */
262 if (i >= PIC_PCIE_LINK_MSI_IRQ(0) && i <= PIC_PCIE_LINK_MSI_IRQ(3)) {
263 nlm_dispatch_msi(node, i);
264 return;
265 }
266 if (i >= PIC_PCIE_MSIX_IRQ(0) && i <= PIC_PCIE_MSIX_IRQ(3)) {
267 nlm_dispatch_msix(node, i);
268 return;
269 }
270
271#endif
259 /* top level irq handling */ 272 /* top level irq handling */
260 do_IRQ(nlm_irq_to_xirq(node, i)); 273 do_IRQ(nlm_irq_to_xirq(node, i));
261} 274}
262 275
263#ifdef CONFIG_OF 276#ifdef CONFIG_OF
264static struct irq_domain *xlp_pic_domain;
265
266static const struct irq_domain_ops xlp_pic_irq_domain_ops = { 277static const struct irq_domain_ops xlp_pic_irq_domain_ops = {
267 .xlate = irq_domain_xlate_onetwocell, 278 .xlate = irq_domain_xlate_onetwocell,
268}; 279};
@@ -271,8 +282,9 @@ static int __init xlp_of_pic_init(struct device_node *node,
271 struct device_node *parent) 282 struct device_node *parent)
272{ 283{
273 const int n_picirqs = PIC_IRT_LAST_IRQ - PIC_IRQ_BASE + 1; 284 const int n_picirqs = PIC_IRT_LAST_IRQ - PIC_IRQ_BASE + 1;
285 struct irq_domain *xlp_pic_domain;
274 struct resource res; 286 struct resource res;
275 int socid, ret; 287 int socid, ret, bus;
276 288
277 /* we need a hack to get the PIC's SoC chip id */ 289 /* we need a hack to get the PIC's SoC chip id */
278 ret = of_address_to_resource(node, 0, &res); 290 ret = of_address_to_resource(node, 0, &res);
@@ -280,7 +292,34 @@ static int __init xlp_of_pic_init(struct device_node *node,
280 pr_err("PIC %s: reg property not found!\n", node->name); 292 pr_err("PIC %s: reg property not found!\n", node->name);
281 return -EINVAL; 293 return -EINVAL;
282 } 294 }
283 socid = (res.start >> 18) & 0x3; 295
296 if (cpu_is_xlp9xx()) {
297 bus = (res.start >> 20) & 0xf;
298 for (socid = 0; socid < NLM_NR_NODES; socid++) {
299 if (!nlm_node_present(socid))
300 continue;
301 if (nlm_get_node(socid)->socbus == bus)
302 break;
303 }
304 if (socid == NLM_NR_NODES) {
305 pr_err("PIC %s: Node mapping for bus %d not found!\n",
306 node->name, bus);
307 return -EINVAL;
308 }
309 } else {
310 socid = (res.start >> 18) & 0x3;
311 if (!nlm_node_present(socid)) {
312 pr_err("PIC %s: node %d does not exist!\n",
313 node->name, socid);
314 return -EINVAL;
315 }
316 }
317
318 if (!nlm_node_present(socid)) {
319 pr_err("PIC %s: node %d does not exist!\n", node->name, socid);
320 return -EINVAL;
321 }
322
284 xlp_pic_domain = irq_domain_add_legacy(node, n_picirqs, 323 xlp_pic_domain = irq_domain_add_legacy(node, n_picirqs,
285 nlm_irq_to_xirq(socid, PIC_IRQ_BASE), PIC_IRQ_BASE, 324 nlm_irq_to_xirq(socid, PIC_IRQ_BASE), PIC_IRQ_BASE,
286 &xlp_pic_irq_domain_ops, NULL); 325 &xlp_pic_irq_domain_ops, NULL);
@@ -288,8 +327,7 @@ static int __init xlp_of_pic_init(struct device_node *node,
288 pr_err("PIC %s: Creating legacy domain failed!\n", node->name); 327 pr_err("PIC %s: Creating legacy domain failed!\n", node->name);
289 return -EINVAL; 328 return -EINVAL;
290 } 329 }
291 pr_info("Node %d: IRQ domain created for PIC@%pa\n", socid, 330 pr_info("Node %d: IRQ domain created for PIC@%pR\n", socid, &res);
292 &res.start);
293 return 0; 331 return 0;
294} 332}
295 333
diff --git a/arch/mips/netlogic/common/reset.S b/arch/mips/netlogic/common/reset.S
index adb18288a6c0..b231fe1e7a09 100644
--- a/arch/mips/netlogic/common/reset.S
+++ b/arch/mips/netlogic/common/reset.S
@@ -32,10 +32,10 @@
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */ 33 */
34 34
35#include <linux/init.h>
36 35
37#include <asm/asm.h> 36#include <asm/asm.h>
38#include <asm/asm-offsets.h> 37#include <asm/asm-offsets.h>
38#include <asm/cacheops.h>
39#include <asm/regdef.h> 39#include <asm/regdef.h>
40#include <asm/mipsregs.h> 40#include <asm/mipsregs.h>
41#include <asm/stackframe.h> 41#include <asm/stackframe.h>
@@ -50,8 +50,8 @@
50#include <asm/netlogic/xlp-hal/cpucontrol.h> 50#include <asm/netlogic/xlp-hal/cpucontrol.h>
51 51
52#define CP0_EBASE $15 52#define CP0_EBASE $15
53#define SYS_CPU_COHERENT_BASE(node) CKSEG1ADDR(XLP_DEFAULT_IO_BASE) + \ 53#define SYS_CPU_COHERENT_BASE CKSEG1ADDR(XLP_DEFAULT_IO_BASE) + \
54 XLP_IO_SYS_OFFSET(node) + XLP_IO_PCI_HDRSZ + \ 54 XLP_IO_SYS_OFFSET(0) + XLP_IO_PCI_HDRSZ + \
55 SYS_CPU_NONCOHERENT_MODE * 4 55 SYS_CPU_NONCOHERENT_MODE * 4
56 56
57/* Enable XLP features and workarounds in the LSU */ 57/* Enable XLP features and workarounds in the LSU */
@@ -74,35 +74,55 @@
74.endm 74.endm
75 75
76/* 76/*
77 * Low level flush for L1D cache on XLP, the normal cache ops does 77 * L1D cache has to be flushed before enabling threads in XLP.
78 * not do the complete and correct cache flush. 78 * On XLP8xx/XLP3xx, we do a low level flush using processor control
79 * registers. On XLPII CPUs, usual cache instructions work.
79 */ 80 */
80.macro xlp_flush_l1_dcache 81.macro xlp_flush_l1_dcache
82 mfc0 t0, CP0_EBASE, 0
83 andi t0, t0, 0xff00
84 slt t1, t0, 0x1200
85 beqz t1, 15f
86 nop
87
88 /* XLP8xx low level cache flush */
81 li t0, LSU_DEBUG_DATA0 89 li t0, LSU_DEBUG_DATA0
82 li t1, LSU_DEBUG_ADDR 90 li t1, LSU_DEBUG_ADDR
83 li t2, 0 /* index */ 91 li t2, 0 /* index */
84 li t3, 0x1000 /* loop count */ 92 li t3, 0x1000 /* loop count */
851: 9311:
86 sll v0, t2, 5 94 sll v0, t2, 5
87 mtcr zero, t0 95 mtcr zero, t0
88 ori v1, v0, 0x3 /* way0 | write_enable | write_active */ 96 ori v1, v0, 0x3 /* way0 | write_enable | write_active */
89 mtcr v1, t1 97 mtcr v1, t1
902: 9812:
91 mfcr v1, t1 99 mfcr v1, t1
92 andi v1, 0x1 /* wait for write_active == 0 */ 100 andi v1, 0x1 /* wait for write_active == 0 */
93 bnez v1, 2b 101 bnez v1, 12b
94 nop 102 nop
95 mtcr zero, t0 103 mtcr zero, t0
96 ori v1, v0, 0x7 /* way1 | write_enable | write_active */ 104 ori v1, v0, 0x7 /* way1 | write_enable | write_active */
97 mtcr v1, t1 105 mtcr v1, t1
983: 10613:
99 mfcr v1, t1 107 mfcr v1, t1
100 andi v1, 0x1 /* wait for write_active == 0 */ 108 andi v1, 0x1 /* wait for write_active == 0 */
101 bnez v1, 3b 109 bnez v1, 13b
102 nop 110 nop
103 addi t2, 1 111 addi t2, 1
104 bne t3, t2, 1b 112 bne t3, t2, 11b
113 nop
114 b 17f
115 nop
116
117 /* XLPII CPUs, Invalidate all 64k of L1 D-cache */
11815:
119 li t0, 0x80000000
120 li t1, 0x80010000
12116: cache Index_Writeback_Inv_D, 0(t0)
122 addiu t0, t0, 32
123 bne t0, t1, 16b
105 nop 124 nop
12517:
106.endm 126.endm
107 127
108/* 128/*
@@ -138,6 +158,13 @@ FEXPORT(nlm_reset_entry)
138 nop 158 nop
139 159
1401: /* Entry point on core wakeup */ 1601: /* Entry point on core wakeup */
161 mfc0 t0, CP0_EBASE, 0 /* processor ID */
162 andi t0, 0xff00
163 li t1, 0x1500 /* XLP 9xx */
164 beq t0, t1, 2f /* does not need to set coherent */
165 nop
166
167 /* set bit in SYS coherent register for the core */
141 mfc0 t0, CP0_EBASE, 1 168 mfc0 t0, CP0_EBASE, 1
142 mfc0 t1, CP0_EBASE, 1 169 mfc0 t1, CP0_EBASE, 1
143 srl t1, 5 170 srl t1, 5
@@ -149,7 +176,7 @@ FEXPORT(nlm_reset_entry)
149 li t1, 0x1 176 li t1, 0x1
150 sll t0, t1, t0 177 sll t0, t1, t0
151 nor t0, t0, zero /* t0 <- ~(1 << core) */ 178 nor t0, t0, zero /* t0 <- ~(1 << core) */
152 li t2, SYS_CPU_COHERENT_BASE(0) 179 li t2, SYS_CPU_COHERENT_BASE
153 add t2, t2, t3 /* t2 <- SYS offset for node */ 180 add t2, t2, t3 /* t2 <- SYS offset for node */
154 lw t1, 0(t2) 181 lw t1, 0(t2)
155 and t1, t1, t0 182 and t1, t1, t0
@@ -159,13 +186,13 @@ FEXPORT(nlm_reset_entry)
159 lw t1, 0(t2) 186 lw t1, 0(t2)
160 sync 187 sync
161 188
1892:
162 /* Configure LSU on Non-0 Cores. */ 190 /* Configure LSU on Non-0 Cores. */
163 xlp_config_lsu 191 xlp_config_lsu
164 /* FALL THROUGH */ 192 /* FALL THROUGH */
165 193
166/* 194/*
167 * Wake up sibling threads from the initial thread in 195 * Wake up sibling threads from the initial thread in a core.
168 * a core.
169 */ 196 */
170EXPORT(nlm_boot_siblings) 197EXPORT(nlm_boot_siblings)
171 /* core L1D flush before enable threads */ 198 /* core L1D flush before enable threads */
@@ -181,8 +208,10 @@ EXPORT(nlm_boot_siblings)
181 /* 208 /*
182 * The new hardware thread starts at the next instruction 209 * The new hardware thread starts at the next instruction
183 * For all the cases other than core 0 thread 0, we will 210 * For all the cases other than core 0 thread 0, we will
184 * jump to the secondary wait function. 211 * jump to the secondary wait function.
185 */ 212
213 * NOTE: All GPR contents are lost after the mtcr above!
214 */
186 mfc0 v0, CP0_EBASE, 1 215 mfc0 v0, CP0_EBASE, 1
187 andi v0, 0x3ff /* v0 <- node/core */ 216 andi v0, 0x3ff /* v0 <- node/core */
188 217
@@ -196,7 +225,7 @@ EXPORT(nlm_boot_siblings)
196#endif 225#endif
197 mtc0 t1, CP0_STATUS 226 mtc0 t1, CP0_STATUS
198 227
199 /* mark CPU ready, careful here, previous mtcr trashed registers */ 228 /* mark CPU ready */
200 li t3, CKSEG1ADDR(RESET_DATA_PHYS) 229 li t3, CKSEG1ADDR(RESET_DATA_PHYS)
201 ADDIU t1, t3, BOOT_CPU_READY 230 ADDIU t1, t3, BOOT_CPU_READY
202 sll v1, v0, 2 231 sll v1, v0, 2
diff --git a/arch/mips/netlogic/common/smp.c b/arch/mips/netlogic/common/smp.c
index c0eded01fde9..6baae15cc7b1 100644
--- a/arch/mips/netlogic/common/smp.c
+++ b/arch/mips/netlogic/common/smp.c
@@ -63,7 +63,7 @@ void nlm_send_ipi_single(int logical_cpu, unsigned int action)
63 uint64_t picbase; 63 uint64_t picbase;
64 64
65 cpu = cpu_logical_map(logical_cpu); 65 cpu = cpu_logical_map(logical_cpu);
66 node = cpu / NLM_CPUS_PER_NODE; 66 node = nlm_cpuid_to_node(cpu);
67 picbase = nlm_get_node(node)->picbase; 67 picbase = nlm_get_node(node)->picbase;
68 68
69 if (action & SMP_CALL_FUNCTION) 69 if (action & SMP_CALL_FUNCTION)
@@ -152,7 +152,7 @@ void nlm_boot_secondary(int logical_cpu, struct task_struct *idle)
152 int cpu, node; 152 int cpu, node;
153 153
154 cpu = cpu_logical_map(logical_cpu); 154 cpu = cpu_logical_map(logical_cpu);
155 node = cpu / NLM_CPUS_PER_NODE; 155 node = nlm_cpuid_to_node(logical_cpu);
156 nlm_next_sp = (unsigned long)__KSTK_TOS(idle); 156 nlm_next_sp = (unsigned long)__KSTK_TOS(idle);
157 nlm_next_gp = (unsigned long)task_thread_info(idle); 157 nlm_next_gp = (unsigned long)task_thread_info(idle);
158 158
@@ -164,7 +164,7 @@ void nlm_boot_secondary(int logical_cpu, struct task_struct *idle)
164void __init nlm_smp_setup(void) 164void __init nlm_smp_setup(void)
165{ 165{
166 unsigned int boot_cpu; 166 unsigned int boot_cpu;
167 int num_cpus, i, ncore; 167 int num_cpus, i, ncore, node;
168 volatile u32 *cpu_ready = nlm_get_boot_data(BOOT_CPU_READY); 168 volatile u32 *cpu_ready = nlm_get_boot_data(BOOT_CPU_READY);
169 char buf[64]; 169 char buf[64];
170 170
@@ -187,6 +187,8 @@ void __init nlm_smp_setup(void)
187 __cpu_number_map[i] = num_cpus; 187 __cpu_number_map[i] = num_cpus;
188 __cpu_logical_map[num_cpus] = i; 188 __cpu_logical_map[num_cpus] = i;
189 set_cpu_possible(num_cpus, true); 189 set_cpu_possible(num_cpus, true);
190 node = nlm_cpuid_to_node(i);
191 cpumask_set_cpu(num_cpus, &nlm_get_node(node)->cpumask);
190 ++num_cpus; 192 ++num_cpus;
191 } 193 }
192 } 194 }
diff --git a/arch/mips/netlogic/common/smpboot.S b/arch/mips/netlogic/common/smpboot.S
index aa6cff0a229b..8597657c27fc 100644
--- a/arch/mips/netlogic/common/smpboot.S
+++ b/arch/mips/netlogic/common/smpboot.S
@@ -32,7 +32,6 @@
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */ 33 */
34 34
35#include <linux/init.h>
36 35
37#include <asm/asm.h> 36#include <asm/asm.h>
38#include <asm/asm-offsets.h> 37#include <asm/asm-offsets.h>
@@ -98,7 +97,7 @@ END(nlm_boot_secondary_cpus)
98 * In case of RMIboot bootloader which is used on XLR boards, the CPUs 97 * In case of RMIboot bootloader which is used on XLR boards, the CPUs
99 * be already woken up and waiting in bootloader code. 98 * be already woken up and waiting in bootloader code.
100 * This will get them out of the bootloader code and into linux. Needed 99 * This will get them out of the bootloader code and into linux. Needed
101 * because the bootloader area will be taken and initialized by linux. 100 * because the bootloader area will be taken and initialized by linux.
102 */ 101 */
103NESTED(nlm_rmiboot_preboot, 16, sp) 102NESTED(nlm_rmiboot_preboot, 16, sp)
104 mfc0 t0, $15, 1 /* read ebase */ 103 mfc0 t0, $15, 1 /* read ebase */
@@ -133,6 +132,7 @@ NESTED(nlm_rmiboot_preboot, 16, sp)
133 or t1, t2, v1 /* put in new value */ 132 or t1, t2, v1 /* put in new value */
134 mtcr t1, t0 /* update core control */ 133 mtcr t1, t0 /* update core control */
135 134
135 /* wait for NMI to hit */
1361: wait 1361: wait
137 b 1b 137 b 1b
138 nop 138 nop
diff --git a/arch/mips/netlogic/dts/Makefile b/arch/mips/netlogic/dts/Makefile
index 0b9be5fd2e46..25c8e873ee25 100644
--- a/arch/mips/netlogic/dts/Makefile
+++ b/arch/mips/netlogic/dts/Makefile
@@ -1,3 +1,4 @@
1obj-$(CONFIG_DT_XLP_EVP) := xlp_evp.dtb.o 1obj-$(CONFIG_DT_XLP_EVP) := xlp_evp.dtb.o
2obj-$(CONFIG_DT_XLP_SVP) += xlp_svp.dtb.o 2obj-$(CONFIG_DT_XLP_SVP) += xlp_svp.dtb.o
3obj-$(CONFIG_DT_XLP_FVP) += xlp_fvp.dtb.o 3obj-$(CONFIG_DT_XLP_FVP) += xlp_fvp.dtb.o
4obj-$(CONFIG_DT_XLP_GVP) += xlp_gvp.dtb.o
diff --git a/arch/mips/netlogic/dts/xlp_gvp.dts b/arch/mips/netlogic/dts/xlp_gvp.dts
new file mode 100644
index 000000000000..047d27f54487
--- /dev/null
+++ b/arch/mips/netlogic/dts/xlp_gvp.dts
@@ -0,0 +1,76 @@
1/*
2 * XLP9XX Device Tree Source for GVP boards
3 */
4
5/dts-v1/;
6/ {
7 model = "netlogic,XLP-GVP";
8 compatible = "netlogic,xlp";
9 #address-cells = <2>;
10 #size-cells = <2>;
11
12 soc {
13 #address-cells = <2>;
14 #size-cells = <1>;
15 compatible = "simple-bus";
16 ranges = <0 0 0 0x18000000 0x04000000 // PCIe CFG
17 1 0 0 0x16000000 0x02000000>; // GBU chipselects
18
19 serial0: serial@30000 {
20 device_type = "serial";
21 compatible = "ns16550";
22 reg = <0 0x112100 0xa00>;
23 reg-shift = <2>;
24 reg-io-width = <4>;
25 clock-frequency = <125000000>;
26 interrupt-parent = <&pic>;
27 interrupts = <17>;
28 };
29 pic: pic@4000 {
30 interrupt-controller;
31 #address-cells = <0>;
32 #interrupt-cells = <1>;
33 reg = <0 0x110000 0x200>;
34 };
35
36 nor_flash@1,0 {
37 compatible = "cfi-flash";
38 #address-cells = <1>;
39 #size-cells = <1>;
40 bank-width = <2>;
41 reg = <1 0 0x1000000>;
42
43 partition@0 {
44 label = "x-loader";
45 reg = <0x0 0x100000>; /* 1M */
46 read-only;
47 };
48
49 partition@100000 {
50 label = "u-boot";
51 reg = <0x100000 0x100000>; /* 1M */
52 };
53
54 partition@200000 {
55 label = "kernel";
56 reg = <0x200000 0x500000>; /* 5M */
57 };
58
59 partition@700000 {
60 label = "rootfs";
61 reg = <0x700000 0x800000>; /* 8M */
62 };
63
64 partition@f00000 {
65 label = "env";
66 reg = <0xf00000 0x100000>; /* 1M */
67 read-only;
68 };
69 };
70
71 };
72
73 chosen {
74 bootargs = "console=ttyS0,115200 rdinit=/sbin/init";
75 };
76};
diff --git a/arch/mips/netlogic/xlp/dt.c b/arch/mips/netlogic/xlp/dt.c
index 8316d5454b17..5754097b9cde 100644
--- a/arch/mips/netlogic/xlp/dt.c
+++ b/arch/mips/netlogic/xlp/dt.c
@@ -42,13 +42,18 @@
42#include <asm/prom.h> 42#include <asm/prom.h>
43 43
44extern u32 __dtb_xlp_evp_begin[], __dtb_xlp_svp_begin[], 44extern u32 __dtb_xlp_evp_begin[], __dtb_xlp_svp_begin[],
45 __dtb_xlp_fvp_begin[], __dtb_start[]; 45 __dtb_xlp_fvp_begin[], __dtb_xlp_gvp_begin[], __dtb_start[];
46static void *xlp_fdt_blob; 46static void *xlp_fdt_blob;
47 47
48void __init *xlp_dt_init(void *fdtp) 48void __init *xlp_dt_init(void *fdtp)
49{ 49{
50 if (!fdtp) { 50 if (!fdtp) {
51 switch (current_cpu_data.processor_id & 0xff00) { 51 switch (current_cpu_data.processor_id & 0xff00) {
52#ifdef CONFIG_DT_XLP_GVP
53 case PRID_IMP_NETLOGIC_XLP9XX:
54 fdtp = __dtb_xlp_gvp_begin;
55 break;
56#endif
52#ifdef CONFIG_DT_XLP_FVP 57#ifdef CONFIG_DT_XLP_FVP
53 case PRID_IMP_NETLOGIC_XLP2XX: 58 case PRID_IMP_NETLOGIC_XLP2XX:
54 fdtp = __dtb_xlp_fvp_begin; 59 fdtp = __dtb_xlp_fvp_begin;
diff --git a/arch/mips/netlogic/xlp/nlm_hal.c b/arch/mips/netlogic/xlp/nlm_hal.c
index 56c50ba43c9b..997cd9ee10de 100644
--- a/arch/mips/netlogic/xlp/nlm_hal.c
+++ b/arch/mips/netlogic/xlp/nlm_hal.c
@@ -57,6 +57,10 @@ void nlm_node_init(int node)
57 nodep->sysbase = nlm_get_sys_regbase(node); 57 nodep->sysbase = nlm_get_sys_regbase(node);
58 nodep->picbase = nlm_get_pic_regbase(node); 58 nodep->picbase = nlm_get_pic_regbase(node);
59 nodep->ebase = read_c0_ebase() & (~((1 << 12) - 1)); 59 nodep->ebase = read_c0_ebase() & (~((1 << 12) - 1));
60 if (cpu_is_xlp9xx())
61 nodep->socbus = xlp9xx_get_socbus(node);
62 else
63 nodep->socbus = 0;
60 spin_lock_init(&nodep->piclock); 64 spin_lock_init(&nodep->piclock);
61} 65}
62 66
@@ -65,6 +69,26 @@ int nlm_irq_to_irt(int irq)
65 uint64_t pcibase; 69 uint64_t pcibase;
66 int devoff, irt; 70 int devoff, irt;
67 71
72 /* bypass for 9xx */
73 if (cpu_is_xlp9xx()) {
74 switch (irq) {
75 case PIC_9XX_XHCI_0_IRQ:
76 return 114;
77 case PIC_9XX_XHCI_1_IRQ:
78 return 115;
79 case PIC_UART_0_IRQ:
80 return 133;
81 case PIC_UART_1_IRQ:
82 return 134;
83 case PIC_PCIE_LINK_LEGACY_IRQ(0):
84 case PIC_PCIE_LINK_LEGACY_IRQ(1):
85 case PIC_PCIE_LINK_LEGACY_IRQ(2):
86 case PIC_PCIE_LINK_LEGACY_IRQ(3):
87 return 191 + irq - PIC_PCIE_LINK_LEGACY_IRQ_BASE;
88 }
89 return -1;
90 }
91
68 devoff = 0; 92 devoff = 0;
69 switch (irq) { 93 switch (irq) {
70 case PIC_UART_0_IRQ: 94 case PIC_UART_0_IRQ:
@@ -135,9 +159,17 @@ int nlm_irq_to_irt(int irq)
135 case PIC_I2C_3_IRQ: 159 case PIC_I2C_3_IRQ:
136 irt = irt + 3; break; 160 irt = irt + 3; break;
137 } 161 }
138 } else if (irq >= PIC_PCIE_LINK_0_IRQ && irq <= PIC_PCIE_LINK_3_IRQ) { 162 } else if (irq >= PIC_PCIE_LINK_LEGACY_IRQ(0) &&
163 irq <= PIC_PCIE_LINK_LEGACY_IRQ(3)) {
139 /* HW bug, PCI IRT entries are bad on early silicon, fix */ 164 /* HW bug, PCI IRT entries are bad on early silicon, fix */
140 irt = PIC_IRT_PCIE_LINK_INDEX(irq - PIC_PCIE_LINK_0_IRQ); 165 irt = PIC_IRT_PCIE_LINK_INDEX(irq -
166 PIC_PCIE_LINK_LEGACY_IRQ_BASE);
167 } else if (irq >= PIC_PCIE_LINK_MSI_IRQ(0) &&
168 irq <= PIC_PCIE_LINK_MSI_IRQ(3)) {
169 irt = -2;
170 } else if (irq >= PIC_PCIE_MSIX_IRQ(0) &&
171 irq <= PIC_PCIE_MSIX_IRQ(3)) {
172 irt = -2;
141 } else { 173 } else {
142 irt = -1; 174 irt = -1;
143 } 175 }
@@ -151,7 +183,10 @@ unsigned int nlm_get_core_frequency(int node, int core)
151 uint64_t num, sysbase; 183 uint64_t num, sysbase;
152 184
153 sysbase = nlm_get_node(node)->sysbase; 185 sysbase = nlm_get_node(node)->sysbase;
154 rstval = nlm_read_sys_reg(sysbase, SYS_POWER_ON_RESET_CFG); 186 if (cpu_is_xlp9xx())
187 rstval = nlm_read_sys_reg(sysbase, SYS_9XX_POWER_ON_RESET_CFG);
188 else
189 rstval = nlm_read_sys_reg(sysbase, SYS_POWER_ON_RESET_CFG);
155 if (cpu_is_xlpii()) { 190 if (cpu_is_xlpii()) {
156 num = 1000000ULL * (400 * 3 + 100 * (rstval >> 26)); 191 num = 1000000ULL * (400 * 3 + 100 * (rstval >> 26));
157 denom = 3; 192 denom = 3;
@@ -265,6 +300,10 @@ static unsigned int nlm_2xx_get_pic_frequency(int node)
265 300
266unsigned int nlm_get_pic_frequency(int node) 301unsigned int nlm_get_pic_frequency(int node)
267{ 302{
303 /* TODO Has to calculate freq as like 2xx */
304 if (cpu_is_xlp9xx())
305 return 250000000;
306
268 if (cpu_is_xlpii()) 307 if (cpu_is_xlpii())
269 return nlm_2xx_get_pic_frequency(node); 308 return nlm_2xx_get_pic_frequency(node);
270 else 309 else
@@ -284,21 +323,33 @@ int xlp_get_dram_map(int n, uint64_t *dram_map)
284{ 323{
285 uint64_t bridgebase, base, lim; 324 uint64_t bridgebase, base, lim;
286 uint32_t val; 325 uint32_t val;
326 unsigned int barreg, limreg, xlatreg;
287 int i, node, rv; 327 int i, node, rv;
288 328
289 /* Look only at mapping on Node 0, we don't handle crazy configs */ 329 /* Look only at mapping on Node 0, we don't handle crazy configs */
290 bridgebase = nlm_get_bridge_regbase(0); 330 bridgebase = nlm_get_bridge_regbase(0);
291 rv = 0; 331 rv = 0;
292 for (i = 0; i < 8; i++) { 332 for (i = 0; i < 8; i++) {
293 val = nlm_read_bridge_reg(bridgebase, 333 if (cpu_is_xlp9xx()) {
294 BRIDGE_DRAM_NODE_TRANSLN(i)); 334 barreg = BRIDGE_9XX_DRAM_BAR(i);
295 node = (val >> 1) & 0x3; 335 limreg = BRIDGE_9XX_DRAM_LIMIT(i);
296 if (n >= 0 && n != node) 336 xlatreg = BRIDGE_9XX_DRAM_NODE_TRANSLN(i);
297 continue; 337 } else {
298 val = nlm_read_bridge_reg(bridgebase, BRIDGE_DRAM_BAR(i)); 338 barreg = BRIDGE_DRAM_BAR(i);
339 limreg = BRIDGE_DRAM_LIMIT(i);
340 xlatreg = BRIDGE_DRAM_NODE_TRANSLN(i);
341 }
342 if (n >= 0) {
343 /* node specified, get node mapping of BAR */
344 val = nlm_read_bridge_reg(bridgebase, xlatreg);
345 node = (val >> 1) & 0x3;
346 if (n != node)
347 continue;
348 }
349 val = nlm_read_bridge_reg(bridgebase, barreg);
299 val = (val >> 12) & 0xfffff; 350 val = (val >> 12) & 0xfffff;
300 base = (uint64_t) val << 20; 351 base = (uint64_t) val << 20;
301 val = nlm_read_bridge_reg(bridgebase, BRIDGE_DRAM_LIMIT(i)); 352 val = nlm_read_bridge_reg(bridgebase, limreg);
302 val = (val >> 12) & 0xfffff; 353 val = (val >> 12) & 0xfffff;
303 if (val == 0) /* BAR not used */ 354 if (val == 0) /* BAR not used */
304 continue; 355 continue;
diff --git a/arch/mips/netlogic/xlp/setup.c b/arch/mips/netlogic/xlp/setup.c
index 54e75c77184b..8c60a2dd9ef6 100644
--- a/arch/mips/netlogic/xlp/setup.c
+++ b/arch/mips/netlogic/xlp/setup.c
@@ -51,12 +51,16 @@ uint64_t nlm_io_base;
51struct nlm_soc_info nlm_nodes[NLM_NR_NODES]; 51struct nlm_soc_info nlm_nodes[NLM_NR_NODES];
52cpumask_t nlm_cpumask = CPU_MASK_CPU0; 52cpumask_t nlm_cpumask = CPU_MASK_CPU0;
53unsigned int nlm_threads_per_core; 53unsigned int nlm_threads_per_core;
54unsigned int xlp_cores_per_node;
54 55
55static void nlm_linux_exit(void) 56static void nlm_linux_exit(void)
56{ 57{
57 uint64_t sysbase = nlm_get_node(0)->sysbase; 58 uint64_t sysbase = nlm_get_node(0)->sysbase;
58 59
59 nlm_write_sys_reg(sysbase, SYS_CHIP_RESET, 1); 60 if (cpu_is_xlp9xx())
61 nlm_write_sys_reg(sysbase, SYS_9XX_CHIP_RESET, 1);
62 else
63 nlm_write_sys_reg(sysbase, SYS_CHIP_RESET, 1);
60 for ( ; ; ) 64 for ( ; ; )
61 cpu_wait(); 65 cpu_wait();
62} 66}
@@ -92,6 +96,14 @@ static void __init xlp_init_mem_from_bars(void)
92 96
93void __init plat_mem_setup(void) 97void __init plat_mem_setup(void)
94{ 98{
99#ifdef CONFIG_SMP
100 nlm_wakeup_secondary_cpus();
101
102 /* update TLB size after waking up threads */
103 current_cpu_data.tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1;
104
105 register_smp_ops(&nlm_smp_ops);
106#endif
95 _machine_restart = (void (*)(char *))nlm_linux_exit; 107 _machine_restart = (void (*)(char *))nlm_linux_exit;
96 _machine_halt = nlm_linux_exit; 108 _machine_halt = nlm_linux_exit;
97 pm_power_off = nlm_linux_exit; 109 pm_power_off = nlm_linux_exit;
@@ -110,6 +122,7 @@ void __init plat_mem_setup(void)
110const char *get_system_type(void) 122const char *get_system_type(void)
111{ 123{
112 switch (read_c0_prid() & 0xff00) { 124 switch (read_c0_prid() & 0xff00) {
125 case PRID_IMP_NETLOGIC_XLP9XX:
113 case PRID_IMP_NETLOGIC_XLP2XX: 126 case PRID_IMP_NETLOGIC_XLP2XX:
114 return "Broadcom XLPII Series"; 127 return "Broadcom XLPII Series";
115 default: 128 default:
@@ -149,6 +162,10 @@ void __init prom_init(void)
149 void *reset_vec; 162 void *reset_vec;
150 163
151 nlm_io_base = CKSEG1ADDR(XLP_DEFAULT_IO_BASE); 164 nlm_io_base = CKSEG1ADDR(XLP_DEFAULT_IO_BASE);
165 if (cpu_is_xlp9xx())
166 xlp_cores_per_node = 32;
167 else
168 xlp_cores_per_node = 8;
152 nlm_init_boot_cpu(); 169 nlm_init_boot_cpu();
153 xlp_mmu_init(); 170 xlp_mmu_init();
154 nlm_node_init(0); 171 nlm_node_init(0);
@@ -162,11 +179,5 @@ void __init prom_init(void)
162 179
163#ifdef CONFIG_SMP 180#ifdef CONFIG_SMP
164 cpumask_setall(&nlm_cpumask); 181 cpumask_setall(&nlm_cpumask);
165 nlm_wakeup_secondary_cpus();
166
167 /* update TLB size after waking up threads */
168 current_cpu_data.tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1;
169
170 register_smp_ops(&nlm_smp_ops);
171#endif 182#endif
172} 183}
diff --git a/arch/mips/netlogic/xlp/usb-init-xlp2.c b/arch/mips/netlogic/xlp/usb-init-xlp2.c
index 36e9c22afc46..17ade1ce5dfd 100644
--- a/arch/mips/netlogic/xlp/usb-init-xlp2.c
+++ b/arch/mips/netlogic/xlp/usb-init-xlp2.c
@@ -37,6 +37,7 @@
37#include <linux/delay.h> 37#include <linux/delay.h>
38#include <linux/init.h> 38#include <linux/init.h>
39#include <linux/pci.h> 39#include <linux/pci.h>
40#include <linux/pci_ids.h>
40#include <linux/platform_device.h> 41#include <linux/platform_device.h>
41#include <linux/irq.h> 42#include <linux/irq.h>
42 43
@@ -83,12 +84,14 @@
83#define nlm_read_usb_reg(b, r) nlm_read_reg(b, r) 84#define nlm_read_usb_reg(b, r) nlm_read_reg(b, r)
84#define nlm_write_usb_reg(b, r, v) nlm_write_reg(b, r, v) 85#define nlm_write_usb_reg(b, r, v) nlm_write_reg(b, r, v)
85 86
86#define nlm_xlpii_get_usb_pcibase(node, inst) \ 87#define nlm_xlpii_get_usb_pcibase(node, inst) \
87 nlm_pcicfg_base(XLP2XX_IO_USB_OFFSET(node, inst)) 88 nlm_pcicfg_base(cpu_is_xlp9xx() ? \
89 XLP9XX_IO_USB_OFFSET(node, inst) : \
90 XLP2XX_IO_USB_OFFSET(node, inst))
88#define nlm_xlpii_get_usb_regbase(node, inst) \ 91#define nlm_xlpii_get_usb_regbase(node, inst) \
89 (nlm_xlpii_get_usb_pcibase(node, inst) + XLP_IO_PCI_HDRSZ) 92 (nlm_xlpii_get_usb_pcibase(node, inst) + XLP_IO_PCI_HDRSZ)
90 93
91static void xlpii_usb_ack(struct irq_data *data) 94static void xlp2xx_usb_ack(struct irq_data *data)
92{ 95{
93 u64 port_addr; 96 u64 port_addr;
94 97
@@ -109,6 +112,29 @@ static void xlpii_usb_ack(struct irq_data *data)
109 nlm_write_usb_reg(port_addr, XLPII_USB3_INT_REG, 0xffffffff); 112 nlm_write_usb_reg(port_addr, XLPII_USB3_INT_REG, 0xffffffff);
110} 113}
111 114
115static void xlp9xx_usb_ack(struct irq_data *data)
116{
117 u64 port_addr;
118 int node, irq;
119
120 /* Find the node and irq on the node */
121 irq = data->irq % NLM_IRQS_PER_NODE;
122 node = data->irq / NLM_IRQS_PER_NODE;
123
124 switch (irq) {
125 case PIC_9XX_XHCI_0_IRQ:
126 port_addr = nlm_xlpii_get_usb_regbase(node, 1);
127 break;
128 case PIC_9XX_XHCI_1_IRQ:
129 port_addr = nlm_xlpii_get_usb_regbase(node, 2);
130 break;
131 default:
132 pr_err("No matching USB irq %d node %d!\n", irq, node);
133 return;
134 }
135 nlm_write_usb_reg(port_addr, XLPII_USB3_INT_REG, 0xffffffff);
136}
137
112static void nlm_xlpii_usb_hw_reset(int node, int port) 138static void nlm_xlpii_usb_hw_reset(int node, int port)
113{ 139{
114 u64 port_addr, xhci_base, pci_base; 140 u64 port_addr, xhci_base, pci_base;
@@ -178,17 +204,33 @@ static void nlm_xlpii_usb_hw_reset(int node, int port)
178 204
179static int __init nlm_platform_xlpii_usb_init(void) 205static int __init nlm_platform_xlpii_usb_init(void)
180{ 206{
207 int node;
208
181 if (!cpu_is_xlpii()) 209 if (!cpu_is_xlpii())
182 return 0; 210 return 0;
183 211
184 pr_info("Initializing 2XX USB Interface\n"); 212 if (!cpu_is_xlp9xx()) {
185 nlm_xlpii_usb_hw_reset(0, 1); 213 /* XLP 2XX single node */
186 nlm_xlpii_usb_hw_reset(0, 2); 214 pr_info("Initializing 2XX USB Interface\n");
187 nlm_xlpii_usb_hw_reset(0, 3); 215 nlm_xlpii_usb_hw_reset(0, 1);
188 nlm_set_pic_extra_ack(0, PIC_2XX_XHCI_0_IRQ, xlpii_usb_ack); 216 nlm_xlpii_usb_hw_reset(0, 2);
189 nlm_set_pic_extra_ack(0, PIC_2XX_XHCI_1_IRQ, xlpii_usb_ack); 217 nlm_xlpii_usb_hw_reset(0, 3);
190 nlm_set_pic_extra_ack(0, PIC_2XX_XHCI_2_IRQ, xlpii_usb_ack); 218 nlm_set_pic_extra_ack(0, PIC_2XX_XHCI_0_IRQ, xlp2xx_usb_ack);
219 nlm_set_pic_extra_ack(0, PIC_2XX_XHCI_1_IRQ, xlp2xx_usb_ack);
220 nlm_set_pic_extra_ack(0, PIC_2XX_XHCI_2_IRQ, xlp2xx_usb_ack);
221 return 0;
222 }
191 223
224 /* XLP 9XX, multi-node */
225 pr_info("Initializing 9XX USB Interface\n");
226 for (node = 0; node < NLM_NR_NODES; node++) {
227 if (!nlm_node_present(node))
228 continue;
229 nlm_xlpii_usb_hw_reset(node, 1);
230 nlm_xlpii_usb_hw_reset(node, 2);
231 nlm_set_pic_extra_ack(node, PIC_9XX_XHCI_0_IRQ, xlp9xx_usb_ack);
232 nlm_set_pic_extra_ack(node, PIC_9XX_XHCI_1_IRQ, xlp9xx_usb_ack);
233 }
192 return 0; 234 return 0;
193} 235}
194 236
@@ -196,8 +238,26 @@ arch_initcall(nlm_platform_xlpii_usb_init);
196 238
197static u64 xlp_usb_dmamask = ~(u32)0; 239static u64 xlp_usb_dmamask = ~(u32)0;
198 240
199/* Fixup IRQ for USB devices on XLP the SoC PCIe bus */ 241/* Fixup the IRQ for USB devices which is exist on XLP9XX SOC PCIE bus */
200static void nlm_usb_fixup_final(struct pci_dev *dev) 242static void nlm_xlp9xx_usb_fixup_final(struct pci_dev *dev)
243{
244 int node;
245
246 node = xlp_socdev_to_node(dev);
247 dev->dev.dma_mask = &xlp_usb_dmamask;
248 dev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
249 switch (dev->devfn) {
250 case 0x21:
251 dev->irq = nlm_irq_to_xirq(node, PIC_9XX_XHCI_0_IRQ);
252 break;
253 case 0x22:
254 dev->irq = nlm_irq_to_xirq(node, PIC_9XX_XHCI_1_IRQ);
255 break;
256 }
257}
258
259/* Fixup the IRQ for USB devices which is exist on XLP2XX SOC PCIE bus */
260static void nlm_xlp2xx_usb_fixup_final(struct pci_dev *dev)
201{ 261{
202 dev->dev.dma_mask = &xlp_usb_dmamask; 262 dev->dev.dma_mask = &xlp_usb_dmamask;
203 dev->dev.coherent_dma_mask = DMA_BIT_MASK(32); 263 dev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
@@ -214,5 +274,7 @@ static void nlm_usb_fixup_final(struct pci_dev *dev)
214 } 274 }
215} 275}
216 276
277DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_XLP9XX_XHCI,
278 nlm_xlp9xx_usb_fixup_final);
217DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_NETLOGIC, PCI_DEVICE_ID_NLM_XHCI, 279DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_NETLOGIC, PCI_DEVICE_ID_NLM_XHCI,
218 nlm_usb_fixup_final); 280 nlm_xlp2xx_usb_fixup_final);
diff --git a/arch/mips/netlogic/xlp/wakeup.c b/arch/mips/netlogic/xlp/wakeup.c
index 682d5638dc01..9a92617a2af5 100644
--- a/arch/mips/netlogic/xlp/wakeup.c
+++ b/arch/mips/netlogic/xlp/wakeup.c
@@ -32,7 +32,6 @@
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */ 33 */
34 34
35#include <linux/init.h>
36#include <linux/kernel.h> 35#include <linux/kernel.h>
37#include <linux/threads.h> 36#include <linux/threads.h>
38 37
@@ -47,14 +46,14 @@
47#include <asm/netlogic/mips-extns.h> 46#include <asm/netlogic/mips-extns.h>
48 47
49#include <asm/netlogic/xlp-hal/iomap.h> 48#include <asm/netlogic/xlp-hal/iomap.h>
50#include <asm/netlogic/xlp-hal/pic.h>
51#include <asm/netlogic/xlp-hal/xlp.h> 49#include <asm/netlogic/xlp-hal/xlp.h>
50#include <asm/netlogic/xlp-hal/pic.h>
52#include <asm/netlogic/xlp-hal/sys.h> 51#include <asm/netlogic/xlp-hal/sys.h>
53 52
54static int xlp_wakeup_core(uint64_t sysbase, int node, int core) 53static int xlp_wakeup_core(uint64_t sysbase, int node, int core)
55{ 54{
56 uint32_t coremask, value; 55 uint32_t coremask, value;
57 int count; 56 int count, resetreg;
58 57
59 coremask = (1 << core); 58 coremask = (1 << core);
60 59
@@ -65,12 +64,24 @@ static int xlp_wakeup_core(uint64_t sysbase, int node, int core)
65 nlm_write_sys_reg(sysbase, SYS_CORE_DFS_DIS_CTRL, value); 64 nlm_write_sys_reg(sysbase, SYS_CORE_DFS_DIS_CTRL, value);
66 } 65 }
67 66
67 /* On 9XX, mark coherent first */
68 if (cpu_is_xlp9xx()) {
69 value = nlm_read_sys_reg(sysbase, SYS_9XX_CPU_NONCOHERENT_MODE);
70 value &= ~coremask;
71 nlm_write_sys_reg(sysbase, SYS_9XX_CPU_NONCOHERENT_MODE, value);
72 }
73
68 /* Remove CPU Reset */ 74 /* Remove CPU Reset */
69 value = nlm_read_sys_reg(sysbase, SYS_CPU_RESET); 75 resetreg = cpu_is_xlp9xx() ? SYS_9XX_CPU_RESET : SYS_CPU_RESET;
76 value = nlm_read_sys_reg(sysbase, resetreg);
70 value &= ~coremask; 77 value &= ~coremask;
71 nlm_write_sys_reg(sysbase, SYS_CPU_RESET, value); 78 nlm_write_sys_reg(sysbase, resetreg, value);
79
80 /* We are done on 9XX */
81 if (cpu_is_xlp9xx())
82 return 1;
72 83
73 /* Poll for CPU to mark itself coherent */ 84 /* Poll for CPU to mark itself coherent on other type of XLP */
74 count = 100000; 85 count = 100000;
75 do { 86 do {
76 value = nlm_read_sys_reg(sysbase, SYS_CPU_NONCOHERENT_MODE); 87 value = nlm_read_sys_reg(sysbase, SYS_CPU_NONCOHERENT_MODE);
@@ -84,7 +95,7 @@ static int wait_for_cpus(int cpu, int bootcpu)
84 volatile uint32_t *cpu_ready = nlm_get_boot_data(BOOT_CPU_READY); 95 volatile uint32_t *cpu_ready = nlm_get_boot_data(BOOT_CPU_READY);
85 int i, count, notready; 96 int i, count, notready;
86 97
87 count = 0x20000000; 98 count = 0x800000;
88 do { 99 do {
89 notready = nlm_threads_per_core; 100 notready = nlm_threads_per_core;
90 for (i = 0; i < nlm_threads_per_core; i++) 101 for (i = 0; i < nlm_threads_per_core; i++)
@@ -98,27 +109,62 @@ static int wait_for_cpus(int cpu, int bootcpu)
98static void xlp_enable_secondary_cores(const cpumask_t *wakeup_mask) 109static void xlp_enable_secondary_cores(const cpumask_t *wakeup_mask)
99{ 110{
100 struct nlm_soc_info *nodep; 111 struct nlm_soc_info *nodep;
101 uint64_t syspcibase; 112 uint64_t syspcibase, fusebase;
102 uint32_t syscoremask; 113 uint32_t syscoremask, mask, fusemask;
103 int core, n, cpu; 114 int core, n, cpu;
104 115
105 for (n = 0; n < NLM_NR_NODES; n++) { 116 for (n = 0; n < NLM_NR_NODES; n++) {
106 syspcibase = nlm_get_sys_pcibase(n); 117 if (n != 0) {
107 if (nlm_read_reg(syspcibase, 0) == 0xffffffff) 118 /* check if node exists and is online */
108 break; 119 if (cpu_is_xlp9xx()) {
120 int b = xlp9xx_get_socbus(n);
121 pr_info("Node %d SoC PCI bus %d.\n", n, b);
122 if (b == 0)
123 break;
124 } else {
125 syspcibase = nlm_get_sys_pcibase(n);
126 if (nlm_read_reg(syspcibase, 0) == 0xffffffff)
127 break;
128 }
129 nlm_node_init(n);
130 }
109 131
110 /* read cores in reset from SYS */ 132 /* read cores in reset from SYS */
111 if (n != 0)
112 nlm_node_init(n);
113 nodep = nlm_get_node(n); 133 nodep = nlm_get_node(n);
114 syscoremask = nlm_read_sys_reg(nodep->sysbase, SYS_CPU_RESET); 134
135 if (cpu_is_xlp9xx()) {
136 fusebase = nlm_get_fuse_regbase(n);
137 fusemask = nlm_read_reg(fusebase, FUSE_9XX_DEVCFG6);
138 mask = 0xfffff;
139 } else {
140 fusemask = nlm_read_sys_reg(nodep->sysbase,
141 SYS_EFUSE_DEVICE_CFG_STATUS0);
142 switch (read_c0_prid() & 0xff00) {
143 case PRID_IMP_NETLOGIC_XLP3XX:
144 mask = 0xf;
145 break;
146 case PRID_IMP_NETLOGIC_XLP2XX:
147 mask = 0x3;
148 break;
149 case PRID_IMP_NETLOGIC_XLP8XX:
150 default:
151 mask = 0xff;
152 break;
153 }
154 }
155
156 /*
157 * Fused out cores are set in the fusemask, and the remaining
158 * cores are renumbered to range 0 .. nactive-1
159 */
160 syscoremask = (1 << hweight32(~fusemask & mask)) - 1;
161
115 /* The boot cpu */ 162 /* The boot cpu */
116 if (n == 0) { 163 if (n == 0)
117 syscoremask |= 1;
118 nodep->coremask = 1; 164 nodep->coremask = 1;
119 }
120 165
121 for (core = 0; core < NLM_CORES_PER_NODE; core++) { 166 pr_info("Node %d - SYS/FUSE coremask %x\n", n, syscoremask);
167 for (core = 0; core < nlm_cores_per_node(); core++) {
122 /* we will be on node 0 core 0 */ 168 /* we will be on node 0 core 0 */
123 if (n == 0 && core == 0) 169 if (n == 0 && core == 0)
124 continue; 170 continue;
@@ -128,7 +174,7 @@ static void xlp_enable_secondary_cores(const cpumask_t *wakeup_mask)
128 continue; 174 continue;
129 175
130 /* see if at least the first hw thread is enabled */ 176 /* see if at least the first hw thread is enabled */
131 cpu = (n * NLM_CORES_PER_NODE + core) 177 cpu = (n * nlm_cores_per_node() + core)
132 * NLM_THREADS_PER_CORE; 178 * NLM_THREADS_PER_CORE;
133 if (!cpumask_test_cpu(cpu, wakeup_mask)) 179 if (!cpumask_test_cpu(cpu, wakeup_mask))
134 continue; 180 continue;
@@ -141,7 +187,8 @@ static void xlp_enable_secondary_cores(const cpumask_t *wakeup_mask)
141 nodep->coremask |= 1u << core; 187 nodep->coremask |= 1u << core;
142 188
143 /* spin until the hw threads sets their ready */ 189 /* spin until the hw threads sets their ready */
144 wait_for_cpus(cpu, 0); 190 if (!wait_for_cpus(cpu, 0))
191 pr_err("Node %d : timeout core %d\n", n, core);
145 } 192 }
146 } 193 }
147} 194}
@@ -153,7 +200,8 @@ void xlp_wakeup_secondary_cpus()
153 * first wakeup core 0 threads 200 * first wakeup core 0 threads
154 */ 201 */
155 xlp_boot_core0_siblings(); 202 xlp_boot_core0_siblings();
156 wait_for_cpus(0, 0); 203 if (!wait_for_cpus(0, 0))
204 pr_err("Node 0 : timeout core 0\n");
157 205
158 /* now get other cores out of reset */ 206 /* now get other cores out of reset */
159 xlp_enable_secondary_cores(&nlm_cpumask); 207 xlp_enable_secondary_cores(&nlm_cpumask);
diff --git a/arch/mips/netlogic/xlr/platform.c b/arch/mips/netlogic/xlr/platform.c
index 7b96a91f4773..4785932af248 100644
--- a/arch/mips/netlogic/xlr/platform.c
+++ b/arch/mips/netlogic/xlr/platform.c
@@ -23,7 +23,7 @@
23#include <asm/netlogic/xlr/pic.h> 23#include <asm/netlogic/xlr/pic.h>
24#include <asm/netlogic/xlr/xlr.h> 24#include <asm/netlogic/xlr/xlr.h>
25 25
26unsigned int nlm_xlr_uart_in(struct uart_port *p, int offset) 26static unsigned int nlm_xlr_uart_in(struct uart_port *p, int offset)
27{ 27{
28 uint64_t uartbase; 28 uint64_t uartbase;
29 unsigned int value; 29 unsigned int value;
@@ -41,7 +41,7 @@ unsigned int nlm_xlr_uart_in(struct uart_port *p, int offset)
41 return value; 41 return value;
42} 42}
43 43
44void nlm_xlr_uart_out(struct uart_port *p, int offset, int value) 44static void nlm_xlr_uart_out(struct uart_port *p, int offset, int value)
45{ 45{
46 uint64_t uartbase; 46 uint64_t uartbase;
47 47
diff --git a/arch/mips/netlogic/xlr/setup.c b/arch/mips/netlogic/xlr/setup.c
index 921be5f77797..d118b9aa7647 100644
--- a/arch/mips/netlogic/xlr/setup.c
+++ b/arch/mips/netlogic/xlr/setup.c
@@ -60,25 +60,6 @@ unsigned int nlm_threads_per_core = 1;
60struct nlm_soc_info nlm_nodes[NLM_NR_NODES]; 60struct nlm_soc_info nlm_nodes[NLM_NR_NODES];
61cpumask_t nlm_cpumask = CPU_MASK_CPU0; 61cpumask_t nlm_cpumask = CPU_MASK_CPU0;
62 62
63static void __init nlm_early_serial_setup(void)
64{
65 struct uart_port s;
66 unsigned long uart_base;
67
68 uart_base = (unsigned long)nlm_mmio_base(NETLOGIC_IO_UART_0_OFFSET);
69 memset(&s, 0, sizeof(s));
70 s.flags = ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST;
71 s.iotype = UPIO_MEM32;
72 s.regshift = 2;
73 s.irq = PIC_UART_0_IRQ;
74 s.uartclk = PIC_CLK_HZ;
75 s.serial_in = nlm_xlr_uart_in;
76 s.serial_out = nlm_xlr_uart_out;
77 s.mapbase = uart_base;
78 s.membase = (unsigned char __iomem *)uart_base;
79 early_serial_setup(&s);
80}
81
82static void nlm_linux_exit(void) 63static void nlm_linux_exit(void)
83{ 64{
84 uint64_t gpiobase; 65 uint64_t gpiobase;
@@ -214,7 +195,6 @@ void __init prom_init(void)
214 memcpy(reset_vec, (void *)nlm_reset_entry, 195 memcpy(reset_vec, (void *)nlm_reset_entry,
215 (nlm_reset_entry_end - nlm_reset_entry)); 196 (nlm_reset_entry_end - nlm_reset_entry));
216 197
217 nlm_early_serial_setup();
218 build_arcs_cmdline(argv); 198 build_arcs_cmdline(argv);
219 prom_add_memory(); 199 prom_add_memory();
220 200
diff --git a/arch/mips/netlogic/xlr/wakeup.c b/arch/mips/netlogic/xlr/wakeup.c
index 9fb81fa6272a..d61cba1e9c65 100644
--- a/arch/mips/netlogic/xlr/wakeup.c
+++ b/arch/mips/netlogic/xlr/wakeup.c
@@ -32,7 +32,6 @@
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */ 33 */
34 34
35#include <linux/init.h>
36#include <linux/delay.h> 35#include <linux/delay.h>
37#include <linux/threads.h> 36#include <linux/threads.h>
38 37
@@ -70,7 +69,7 @@ int xlr_wakeup_secondary_cpus(void)
70 69
71 /* Fill up the coremask early */ 70 /* Fill up the coremask early */
72 nodep->coremask = 1; 71 nodep->coremask = 1;
73 for (i = 1; i < NLM_CORES_PER_NODE; i++) { 72 for (i = 1; i < nlm_cores_per_node(); i++) {
74 for (j = 1000000; j > 0; j--) { 73 for (j = 1000000; j > 0; j--) {
75 if (cpu_ready[i * NLM_THREADS_PER_CORE]) 74 if (cpu_ready[i * NLM_THREADS_PER_CORE])
76 break; 75 break;
diff --git a/arch/mips/oprofile/common.c b/arch/mips/oprofile/common.c
index 4d1736fc1955..2a86e38872a7 100644
--- a/arch/mips/oprofile/common.c
+++ b/arch/mips/oprofile/common.c
@@ -86,6 +86,8 @@ int __init oprofile_arch_init(struct oprofile_operations *ops)
86 case CPU_34K: 86 case CPU_34K:
87 case CPU_1004K: 87 case CPU_1004K:
88 case CPU_74K: 88 case CPU_74K:
89 case CPU_INTERAPTIV:
90 case CPU_PROAPTIV:
89 case CPU_LOONGSON1: 91 case CPU_LOONGSON1:
90 case CPU_SB1: 92 case CPU_SB1:
91 case CPU_SB1A: 93 case CPU_SB1A:
diff --git a/arch/mips/oprofile/op_model_mipsxx.c b/arch/mips/oprofile/op_model_mipsxx.c
index 3a2b6e9f25cf..4d94d75ec6f9 100644
--- a/arch/mips/oprofile/op_model_mipsxx.c
+++ b/arch/mips/oprofile/op_model_mipsxx.c
@@ -376,6 +376,14 @@ static int __init mipsxx_init(void)
376 op_model_mipsxx_ops.cpu_type = "mips/74K"; 376 op_model_mipsxx_ops.cpu_type = "mips/74K";
377 break; 377 break;
378 378
379 case CPU_INTERAPTIV:
380 op_model_mipsxx_ops.cpu_type = "mips/interAptiv";
381 break;
382
383 case CPU_PROAPTIV:
384 op_model_mipsxx_ops.cpu_type = "mips/proAptiv";
385 break;
386
379 case CPU_5KC: 387 case CPU_5KC:
380 op_model_mipsxx_ops.cpu_type = "mips/5K"; 388 op_model_mipsxx_ops.cpu_type = "mips/5K";
381 break; 389 break;
diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile
index 719e4557e22e..137f2a6feb25 100644
--- a/arch/mips/pci/Makefile
+++ b/arch/mips/pci/Makefile
@@ -60,4 +60,5 @@ obj-$(CONFIG_CPU_XLP) += pci-xlp.o
60 60
61ifdef CONFIG_PCI_MSI 61ifdef CONFIG_PCI_MSI
62obj-$(CONFIG_CAVIUM_OCTEON_SOC) += msi-octeon.o 62obj-$(CONFIG_CAVIUM_OCTEON_SOC) += msi-octeon.o
63obj-$(CONFIG_CPU_XLP) += msi-xlp.o
63endif 64endif
diff --git a/arch/mips/pci/fixup-malta.c b/arch/mips/pci/fixup-malta.c
index df36e2327c54..7a0eda782e35 100644
--- a/arch/mips/pci/fixup-malta.c
+++ b/arch/mips/pci/fixup-malta.c
@@ -54,6 +54,7 @@ int pcibios_plat_dev_init(struct pci_dev *dev)
54static void malta_piix_func0_fixup(struct pci_dev *pdev) 54static void malta_piix_func0_fixup(struct pci_dev *pdev)
55{ 55{
56 unsigned char reg_val; 56 unsigned char reg_val;
57 u32 reg_val32;
57 /* PIIX PIRQC[A:D] irq mappings */ 58 /* PIIX PIRQC[A:D] irq mappings */
58 static int piixirqmap[PIIX4_FUNC0_PIRQRC_IRQ_ROUTING_MAX] = { 59 static int piixirqmap[PIIX4_FUNC0_PIRQRC_IRQ_ROUTING_MAX] = {
59 0, 0, 0, 3, 60 0, 0, 0, 3,
@@ -83,6 +84,16 @@ static void malta_piix_func0_fixup(struct pci_dev *pdev)
83 pci_write_config_byte(pdev, PIIX4_FUNC0_TOM, reg_val | 84 pci_write_config_byte(pdev, PIIX4_FUNC0_TOM, reg_val |
84 PIIX4_FUNC0_TOM_TOP_OF_MEMORY_MASK); 85 PIIX4_FUNC0_TOM_TOP_OF_MEMORY_MASK);
85 } 86 }
87
88 /* Mux SERIRQ to its pin */
89 pci_read_config_dword(pdev, PIIX4_FUNC0_GENCFG, &reg_val32);
90 pci_write_config_dword(pdev, PIIX4_FUNC0_GENCFG,
91 reg_val32 | PIIX4_FUNC0_GENCFG_SERIRQ);
92
93 /* Enable SERIRQ */
94 pci_read_config_byte(pdev, PIIX4_FUNC0_SERIRQC, &reg_val);
95 reg_val |= PIIX4_FUNC0_SERIRQC_EN | PIIX4_FUNC0_SERIRQC_CONT;
96 pci_write_config_byte(pdev, PIIX4_FUNC0_SERIRQC, reg_val);
86} 97}
87 98
88DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_0, 99DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_0,
diff --git a/arch/mips/pci/fixup-rc32434.c b/arch/mips/pci/fixup-rc32434.c
index d0f6ecbf35f7..7fcafd5da7da 100644
--- a/arch/mips/pci/fixup-rc32434.c
+++ b/arch/mips/pci/fixup-rc32434.c
@@ -27,7 +27,6 @@
27#include <linux/types.h> 27#include <linux/types.h>
28#include <linux/pci.h> 28#include <linux/pci.h>
29#include <linux/kernel.h> 29#include <linux/kernel.h>
30#include <linux/init.h>
31 30
32#include <asm/mach-rc32434/rc32434.h> 31#include <asm/mach-rc32434/rc32434.h>
33#include <asm/mach-rc32434/irq.h> 32#include <asm/mach-rc32434/irq.h>
diff --git a/arch/mips/pci/fixup-sb1250.c b/arch/mips/pci/fixup-sb1250.c
index 1441becdcb6c..8feae9154baf 100644
--- a/arch/mips/pci/fixup-sb1250.c
+++ b/arch/mips/pci/fixup-sb1250.c
@@ -8,7 +8,6 @@
8 * 2 of the License, or (at your option) any later version. 8 * 2 of the License, or (at your option) any later version.
9 */ 9 */
10 10
11#include <linux/init.h>
12#include <linux/pci.h> 11#include <linux/pci.h>
13 12
14/* 13/*
diff --git a/arch/mips/pci/msi-xlp.c b/arch/mips/pci/msi-xlp.c
new file mode 100644
index 000000000000..afd8405e0188
--- /dev/null
+++ b/arch/mips/pci/msi-xlp.c
@@ -0,0 +1,494 @@
1/*
2 * Copyright (c) 2003-2012 Broadcom Corporation
3 * All Rights Reserved
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the Broadcom
9 * license below:
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
20 * distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#include <linux/types.h>
36#include <linux/pci.h>
37#include <linux/kernel.h>
38#include <linux/init.h>
39#include <linux/msi.h>
40#include <linux/mm.h>
41#include <linux/irq.h>
42#include <linux/irqdesc.h>
43#include <linux/console.h>
44
45#include <asm/io.h>
46
47#include <asm/netlogic/interrupt.h>
48#include <asm/netlogic/haldefs.h>
49#include <asm/netlogic/common.h>
50#include <asm/netlogic/mips-extns.h>
51
52#include <asm/netlogic/xlp-hal/iomap.h>
53#include <asm/netlogic/xlp-hal/xlp.h>
54#include <asm/netlogic/xlp-hal/pic.h>
55#include <asm/netlogic/xlp-hal/pcibus.h>
56#include <asm/netlogic/xlp-hal/bridge.h>
57
58#define XLP_MSIVEC_PER_LINK 32
59#define XLP_MSIXVEC_TOTAL 32
60#define XLP_MSIXVEC_PER_LINK 8
61
62/* 128 MSI irqs per node, mapped starting at NLM_MSI_VEC_BASE */
63static inline int nlm_link_msiirq(int link, int msivec)
64{
65 return NLM_MSI_VEC_BASE + link * XLP_MSIVEC_PER_LINK + msivec;
66}
67
68static inline int nlm_irq_msivec(int irq)
69{
70 return irq % XLP_MSIVEC_PER_LINK;
71}
72
73static inline int nlm_irq_msilink(int irq)
74{
75 return (irq % (XLP_MSIVEC_PER_LINK * PCIE_NLINKS)) /
76 XLP_MSIVEC_PER_LINK;
77}
78
79/*
80 * Only 32 MSI-X vectors are possible because there are only 32 PIC
81 * interrupts for MSI. We split them statically and use 8 MSI-X vectors
82 * per link - this keeps the allocation and lookup simple.
83 */
84static inline int nlm_link_msixirq(int link, int bit)
85{
86 return NLM_MSIX_VEC_BASE + link * XLP_MSIXVEC_PER_LINK + bit;
87}
88
89static inline int nlm_irq_msixvec(int irq)
90{
91 return irq % XLP_MSIXVEC_TOTAL; /* works when given xirq */
92}
93
94static inline int nlm_irq_msixlink(int irq)
95{
96 return nlm_irq_msixvec(irq) / XLP_MSIXVEC_PER_LINK;
97}
98
99/*
100 * Per link MSI and MSI-X information, set as IRQ handler data for
101 * MSI and MSI-X interrupts.
102 */
103struct xlp_msi_data {
104 struct nlm_soc_info *node;
105 uint64_t lnkbase;
106 uint32_t msi_enabled_mask;
107 uint32_t msi_alloc_mask;
108 uint32_t msix_alloc_mask;
109 spinlock_t msi_lock;
110};
111
112/*
113 * MSI Chip definitions
114 *
115 * On XLP, there is a PIC interrupt associated with each PCIe link on the
116 * chip (which appears as a PCI bridge to us). This gives us 32 MSI irqa
117 * per link and 128 overall.
118 *
119 * When a device connected to the link raises a MSI interrupt, we get a
120 * link interrupt and we then have to look at PCIE_MSI_STATUS register at
121 * the bridge to map it to the IRQ
122 */
123static void xlp_msi_enable(struct irq_data *d)
124{
125 struct xlp_msi_data *md = irq_data_get_irq_handler_data(d);
126 unsigned long flags;
127 int vec;
128
129 vec = nlm_irq_msivec(d->irq);
130 spin_lock_irqsave(&md->msi_lock, flags);
131 md->msi_enabled_mask |= 1u << vec;
132 nlm_write_reg(md->lnkbase, PCIE_MSI_EN, md->msi_enabled_mask);
133 spin_unlock_irqrestore(&md->msi_lock, flags);
134}
135
136static void xlp_msi_disable(struct irq_data *d)
137{
138 struct xlp_msi_data *md = irq_data_get_irq_handler_data(d);
139 unsigned long flags;
140 int vec;
141
142 vec = nlm_irq_msivec(d->irq);
143 spin_lock_irqsave(&md->msi_lock, flags);
144 md->msi_enabled_mask &= ~(1u << vec);
145 nlm_write_reg(md->lnkbase, PCIE_MSI_EN, md->msi_enabled_mask);
146 spin_unlock_irqrestore(&md->msi_lock, flags);
147}
148
149static void xlp_msi_mask_ack(struct irq_data *d)
150{
151 struct xlp_msi_data *md = irq_data_get_irq_handler_data(d);
152 int link, vec;
153
154 link = nlm_irq_msilink(d->irq);
155 vec = nlm_irq_msivec(d->irq);
156 xlp_msi_disable(d);
157
158 /* Ack MSI on bridge */
159 nlm_write_reg(md->lnkbase, PCIE_MSI_STATUS, 1u << vec);
160
161 /* Ack at eirr and PIC */
162 ack_c0_eirr(PIC_PCIE_LINK_MSI_IRQ(link));
163 nlm_pic_ack(md->node->picbase, PIC_IRT_PCIE_LINK_INDEX(link));
164}
165
166static struct irq_chip xlp_msi_chip = {
167 .name = "XLP-MSI",
168 .irq_enable = xlp_msi_enable,
169 .irq_disable = xlp_msi_disable,
170 .irq_mask_ack = xlp_msi_mask_ack,
171 .irq_unmask = xlp_msi_enable,
172};
173
174/*
175 * The MSI-X interrupt handling is different from MSI, there are 32
176 * MSI-X interrupts generated by the PIC and each of these correspond
177 * to a MSI-X vector (0-31) that can be assigned.
178 *
179 * We divide the MSI-X vectors to 8 per link and do a per-link
180 * allocation
181 *
182 * Enable and disable done using standard MSI functions.
183 */
184static void xlp_msix_mask_ack(struct irq_data *d)
185{
186 struct xlp_msi_data *md = irq_data_get_irq_handler_data(d);
187 int link, msixvec;
188
189 msixvec = nlm_irq_msixvec(d->irq);
190 link = nlm_irq_msixlink(d->irq);
191 mask_msi_irq(d);
192
193 /* Ack MSI on bridge */
194 nlm_write_reg(md->lnkbase, PCIE_MSIX_STATUS, 1u << msixvec);
195
196 /* Ack at eirr and PIC */
197 ack_c0_eirr(PIC_PCIE_MSIX_IRQ(link));
198 nlm_pic_ack(md->node->picbase, PIC_IRT_PCIE_MSIX_INDEX(msixvec));
199}
200
201static struct irq_chip xlp_msix_chip = {
202 .name = "XLP-MSIX",
203 .irq_enable = unmask_msi_irq,
204 .irq_disable = mask_msi_irq,
205 .irq_mask_ack = xlp_msix_mask_ack,
206 .irq_unmask = unmask_msi_irq,
207};
208
209void destroy_irq(unsigned int irq)
210{
211 /* nothing to do yet */
212}
213
214void arch_teardown_msi_irq(unsigned int irq)
215{
216 destroy_irq(irq);
217}
218
219/*
220 * Setup a PCIe link for MSI. By default, the links are in
221 * legacy interrupt mode. We will switch them to MSI mode
222 * at the first MSI request.
223 */
224static void xlp_config_link_msi(uint64_t lnkbase, int lirq, uint64_t msiaddr)
225{
226 u32 val;
227
228 val = nlm_read_reg(lnkbase, PCIE_INT_EN0);
229 if ((val & 0x200) == 0) {
230 val |= 0x200; /* MSI Interrupt enable */
231 nlm_write_reg(lnkbase, PCIE_INT_EN0, val);
232 }
233
234 val = nlm_read_reg(lnkbase, 0x1); /* CMD */
235 if ((val & 0x0400) == 0) {
236 val |= 0x0400;
237 nlm_write_reg(lnkbase, 0x1, val);
238 }
239
240 /* Update IRQ in the PCI irq reg */
241 val = nlm_read_pci_reg(lnkbase, 0xf);
242 val &= ~0x1fu;
243 val |= (1 << 8) | lirq;
244 nlm_write_pci_reg(lnkbase, 0xf, val);
245
246 /* MSI addr */
247 nlm_write_reg(lnkbase, PCIE_BRIDGE_MSI_ADDRH, msiaddr >> 32);
248 nlm_write_reg(lnkbase, PCIE_BRIDGE_MSI_ADDRL, msiaddr & 0xffffffff);
249
250 /* MSI cap for bridge */
251 val = nlm_read_reg(lnkbase, PCIE_BRIDGE_MSI_CAP);
252 if ((val & (1 << 16)) == 0) {
253 val |= 0xb << 16; /* mmc32, msi enable */
254 nlm_write_reg(lnkbase, PCIE_BRIDGE_MSI_CAP, val);
255 }
256}
257
258/*
259 * Allocate a MSI vector on a link
260 */
261static int xlp_setup_msi(uint64_t lnkbase, int node, int link,
262 struct msi_desc *desc)
263{
264 struct xlp_msi_data *md;
265 struct msi_msg msg;
266 unsigned long flags;
267 int msivec, irt, lirq, xirq, ret;
268 uint64_t msiaddr;
269
270 /* Get MSI data for the link */
271 lirq = PIC_PCIE_LINK_MSI_IRQ(link);
272 xirq = nlm_irq_to_xirq(node, nlm_link_msiirq(link, 0));
273 md = irq_get_handler_data(xirq);
274 msiaddr = MSI_LINK_ADDR(node, link);
275
276 spin_lock_irqsave(&md->msi_lock, flags);
277 if (md->msi_alloc_mask == 0) {
278 /* switch the link IRQ to MSI range */
279 xlp_config_link_msi(lnkbase, lirq, msiaddr);
280 irt = PIC_IRT_PCIE_LINK_INDEX(link);
281 nlm_setup_pic_irq(node, lirq, lirq, irt);
282 nlm_pic_init_irt(nlm_get_node(node)->picbase, irt, lirq,
283 node * nlm_threads_per_node(), 1 /*en */);
284 }
285
286 /* allocate a MSI vec, and tell the bridge about it */
287 msivec = fls(md->msi_alloc_mask);
288 if (msivec == XLP_MSIVEC_PER_LINK) {
289 spin_unlock_irqrestore(&md->msi_lock, flags);
290 return -ENOMEM;
291 }
292 md->msi_alloc_mask |= (1u << msivec);
293 spin_unlock_irqrestore(&md->msi_lock, flags);
294
295 msg.address_hi = msiaddr >> 32;
296 msg.address_lo = msiaddr & 0xffffffff;
297 msg.data = 0xc00 | msivec;
298
299 xirq = xirq + msivec; /* msi mapped to global irq space */
300 ret = irq_set_msi_desc(xirq, desc);
301 if (ret < 0) {
302 destroy_irq(xirq);
303 return ret;
304 }
305
306 write_msi_msg(xirq, &msg);
307 return 0;
308}
309
310/*
311 * Switch a link to MSI-X mode
312 */
313static void xlp_config_link_msix(uint64_t lnkbase, int lirq, uint64_t msixaddr)
314{
315 u32 val;
316
317 val = nlm_read_reg(lnkbase, 0x2C);
318 if ((val & 0x80000000U) == 0) {
319 val |= 0x80000000U;
320 nlm_write_reg(lnkbase, 0x2C, val);
321 }
322 val = nlm_read_reg(lnkbase, PCIE_INT_EN0);
323 if ((val & 0x200) == 0) {
324 val |= 0x200; /* MSI Interrupt enable */
325 nlm_write_reg(lnkbase, PCIE_INT_EN0, val);
326 }
327
328 val = nlm_read_reg(lnkbase, 0x1); /* CMD */
329 if ((val & 0x0400) == 0) {
330 val |= 0x0400;
331 nlm_write_reg(lnkbase, 0x1, val);
332 }
333
334 /* Update IRQ in the PCI irq reg */
335 val = nlm_read_pci_reg(lnkbase, 0xf);
336 val &= ~0x1fu;
337 val |= (1 << 8) | lirq;
338 nlm_write_pci_reg(lnkbase, 0xf, val);
339
340 /* MSI-X addresses */
341 nlm_write_reg(lnkbase, PCIE_BRIDGE_MSIX_ADDR_BASE, msixaddr >> 8);
342 nlm_write_reg(lnkbase, PCIE_BRIDGE_MSIX_ADDR_LIMIT,
343 (msixaddr + MSI_ADDR_SZ) >> 8);
344}
345
346/*
347 * Allocate a MSI-X vector
348 */
349static int xlp_setup_msix(uint64_t lnkbase, int node, int link,
350 struct msi_desc *desc)
351{
352 struct xlp_msi_data *md;
353 struct msi_msg msg;
354 unsigned long flags;
355 int t, msixvec, lirq, xirq, ret;
356 uint64_t msixaddr;
357
358 /* Get MSI data for the link */
359 lirq = PIC_PCIE_MSIX_IRQ(link);
360 xirq = nlm_irq_to_xirq(node, nlm_link_msixirq(link, 0));
361 md = irq_get_handler_data(xirq);
362 msixaddr = MSIX_LINK_ADDR(node, link);
363
364 spin_lock_irqsave(&md->msi_lock, flags);
365 /* switch the PCIe link to MSI-X mode at the first alloc */
366 if (md->msix_alloc_mask == 0)
367 xlp_config_link_msix(lnkbase, lirq, msixaddr);
368
369 /* allocate a MSI-X vec, and tell the bridge about it */
370 t = fls(md->msix_alloc_mask);
371 if (t == XLP_MSIXVEC_PER_LINK) {
372 spin_unlock_irqrestore(&md->msi_lock, flags);
373 return -ENOMEM;
374 }
375 md->msix_alloc_mask |= (1u << t);
376 spin_unlock_irqrestore(&md->msi_lock, flags);
377
378 xirq += t;
379 msixvec = nlm_irq_msixvec(xirq);
380 msg.address_hi = msixaddr >> 32;
381 msg.address_lo = msixaddr & 0xffffffff;
382 msg.data = 0xc00 | msixvec;
383
384 ret = irq_set_msi_desc(xirq, desc);
385 if (ret < 0) {
386 destroy_irq(xirq);
387 return ret;
388 }
389
390 write_msi_msg(xirq, &msg);
391 return 0;
392}
393
394int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
395{
396 struct pci_dev *lnkdev;
397 uint64_t lnkbase;
398 int node, link, slot;
399
400 lnkdev = xlp_get_pcie_link(dev);
401 if (lnkdev == NULL) {
402 dev_err(&dev->dev, "Could not find bridge\n");
403 return 1;
404 }
405 slot = PCI_SLOT(lnkdev->devfn);
406 link = PCI_FUNC(lnkdev->devfn);
407 node = slot / 8;
408 lnkbase = nlm_get_pcie_base(node, link);
409
410 if (desc->msi_attrib.is_msix)
411 return xlp_setup_msix(lnkbase, node, link, desc);
412 else
413 return xlp_setup_msi(lnkbase, node, link, desc);
414}
415
416void __init xlp_init_node_msi_irqs(int node, int link)
417{
418 struct nlm_soc_info *nodep;
419 struct xlp_msi_data *md;
420 int irq, i, irt, msixvec;
421
422 pr_info("[%d %d] Init node PCI IRT\n", node, link);
423 nodep = nlm_get_node(node);
424
425 /* Alloc an MSI block for the link */
426 md = kzalloc(sizeof(*md), GFP_KERNEL);
427 spin_lock_init(&md->msi_lock);
428 md->msi_enabled_mask = 0;
429 md->msi_alloc_mask = 0;
430 md->msix_alloc_mask = 0;
431 md->node = nodep;
432 md->lnkbase = nlm_get_pcie_base(node, link);
433
434 /* extended space for MSI interrupts */
435 irq = nlm_irq_to_xirq(node, nlm_link_msiirq(link, 0));
436 for (i = irq; i < irq + XLP_MSIVEC_PER_LINK; i++) {
437 irq_set_chip_and_handler(i, &xlp_msi_chip, handle_level_irq);
438 irq_set_handler_data(i, md);
439 }
440
441 for (i = 0; i < XLP_MSIXVEC_PER_LINK; i++) {
442 /* Initialize MSI-X irts to generate one interrupt per link */
443 msixvec = link * XLP_MSIXVEC_PER_LINK + i;
444 irt = PIC_IRT_PCIE_MSIX_INDEX(msixvec);
445 nlm_pic_init_irt(nodep->picbase, irt, PIC_PCIE_MSIX_IRQ(link),
446 node * nlm_threads_per_node(), 1 /* enable */);
447
448 /* Initialize MSI-X extended irq space for the link */
449 irq = nlm_irq_to_xirq(node, nlm_link_msixirq(link, i));
450 irq_set_chip_and_handler(irq, &xlp_msix_chip, handle_level_irq);
451 irq_set_handler_data(irq, md);
452 }
453
454}
455
456void nlm_dispatch_msi(int node, int lirq)
457{
458 struct xlp_msi_data *md;
459 int link, i, irqbase;
460 u32 status;
461
462 link = lirq - PIC_PCIE_LINK_MSI_IRQ_BASE;
463 irqbase = nlm_irq_to_xirq(node, nlm_link_msiirq(link, 0));
464 md = irq_get_handler_data(irqbase);
465 status = nlm_read_reg(md->lnkbase, PCIE_MSI_STATUS) &
466 md->msi_enabled_mask;
467 while (status) {
468 i = __ffs(status);
469 do_IRQ(irqbase + i);
470 status &= status - 1;
471 }
472}
473
474void nlm_dispatch_msix(int node, int lirq)
475{
476 struct xlp_msi_data *md;
477 int link, i, irqbase;
478 u32 status;
479
480 link = lirq - PIC_PCIE_MSIX_IRQ_BASE;
481 irqbase = nlm_irq_to_xirq(node, nlm_link_msixirq(link, 0));
482 md = irq_get_handler_data(irqbase);
483 status = nlm_read_reg(md->lnkbase, PCIE_MSIX_STATUS);
484
485 /* narrow it down to the MSI-x vectors for our link */
486 status = (status >> (link * XLP_MSIXVEC_PER_LINK)) &
487 ((1 << XLP_MSIXVEC_PER_LINK) - 1);
488
489 while (status) {
490 i = __ffs(status);
491 do_IRQ(irqbase + i);
492 status &= status - 1;
493 }
494}
diff --git a/arch/mips/pci/ops-bcm63xx.c b/arch/mips/pci/ops-bcm63xx.c
index 6144bb337e44..13eea696bbe7 100644
--- a/arch/mips/pci/ops-bcm63xx.c
+++ b/arch/mips/pci/ops-bcm63xx.c
@@ -9,7 +9,6 @@
9#include <linux/types.h> 9#include <linux/types.h>
10#include <linux/pci.h> 10#include <linux/pci.h>
11#include <linux/kernel.h> 11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/delay.h> 12#include <linux/delay.h>
14#include <linux/io.h> 13#include <linux/io.h>
15 14
diff --git a/arch/mips/pci/ops-bonito64.c b/arch/mips/pci/ops-bonito64.c
index 830352e3aeda..c06205a87348 100644
--- a/arch/mips/pci/ops-bonito64.c
+++ b/arch/mips/pci/ops-bonito64.c
@@ -22,7 +22,6 @@
22#include <linux/types.h> 22#include <linux/types.h>
23#include <linux/pci.h> 23#include <linux/pci.h>
24#include <linux/kernel.h> 24#include <linux/kernel.h>
25#include <linux/init.h>
26 25
27#include <asm/mips-boards/bonito64.h> 26#include <asm/mips-boards/bonito64.h>
28 27
diff --git a/arch/mips/pci/ops-lantiq.c b/arch/mips/pci/ops-lantiq.c
index 16e7c2526d77..e5738ee26f4f 100644
--- a/arch/mips/pci/ops-lantiq.c
+++ b/arch/mips/pci/ops-lantiq.c
@@ -9,7 +9,6 @@
9#include <linux/types.h> 9#include <linux/types.h>
10#include <linux/pci.h> 10#include <linux/pci.h>
11#include <linux/kernel.h> 11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/delay.h> 12#include <linux/delay.h>
14#include <linux/mm.h> 13#include <linux/mm.h>
15#include <asm/addrspace.h> 14#include <asm/addrspace.h>
diff --git a/arch/mips/pci/ops-loongson2.c b/arch/mips/pci/ops-loongson2.c
index 98254afa0287..24138bb0cbe1 100644
--- a/arch/mips/pci/ops-loongson2.c
+++ b/arch/mips/pci/ops-loongson2.c
@@ -14,7 +14,6 @@
14#include <linux/types.h> 14#include <linux/types.h>
15#include <linux/pci.h> 15#include <linux/pci.h>
16#include <linux/kernel.h> 16#include <linux/kernel.h>
17#include <linux/init.h>
18#include <linux/export.h> 17#include <linux/export.h>
19 18
20#include <loongson.h> 19#include <loongson.h>
diff --git a/arch/mips/pci/ops-mace.c b/arch/mips/pci/ops-mace.c
index 1cfb5588699f..6b5821febc38 100644
--- a/arch/mips/pci/ops-mace.c
+++ b/arch/mips/pci/ops-mace.c
@@ -6,7 +6,6 @@
6 * Copyright (C) 2000, 2001 Keith M Wesolowski 6 * Copyright (C) 2000, 2001 Keith M Wesolowski
7 */ 7 */
8#include <linux/kernel.h> 8#include <linux/kernel.h>
9#include <linux/init.h>
10#include <linux/pci.h> 9#include <linux/pci.h>
11#include <linux/types.h> 10#include <linux/types.h>
12#include <asm/pci.h> 11#include <asm/pci.h>
diff --git a/arch/mips/pci/ops-msc.c b/arch/mips/pci/ops-msc.c
index 92a8543361bb..dbbf3657896c 100644
--- a/arch/mips/pci/ops-msc.c
+++ b/arch/mips/pci/ops-msc.c
@@ -24,7 +24,6 @@
24#include <linux/types.h> 24#include <linux/types.h>
25#include <linux/pci.h> 25#include <linux/pci.h>
26#include <linux/kernel.h> 26#include <linux/kernel.h>
27#include <linux/init.h>
28 27
29#include <asm/mips-boards/msc01_pci.h> 28#include <asm/mips-boards/msc01_pci.h>
30 29
diff --git a/arch/mips/pci/ops-nile4.c b/arch/mips/pci/ops-nile4.c
index 499e35c3eb35..a1a7c9f4096e 100644
--- a/arch/mips/pci/ops-nile4.c
+++ b/arch/mips/pci/ops-nile4.c
@@ -1,5 +1,4 @@
1#include <linux/kernel.h> 1#include <linux/kernel.h>
2#include <linux/init.h>
3#include <linux/pci.h> 2#include <linux/pci.h>
4#include <asm/bootinfo.h> 3#include <asm/bootinfo.h>
5 4
diff --git a/arch/mips/pci/ops-rc32434.c b/arch/mips/pci/ops-rc32434.c
index 7c7182e2350a..874ed6df9768 100644
--- a/arch/mips/pci/ops-rc32434.c
+++ b/arch/mips/pci/ops-rc32434.c
@@ -26,7 +26,6 @@
26 * 675 Mass Ave, Cambridge, MA 02139, USA. 26 * 675 Mass Ave, Cambridge, MA 02139, USA.
27 */ 27 */
28#include <linux/delay.h> 28#include <linux/delay.h>
29#include <linux/init.h>
30#include <linux/io.h> 29#include <linux/io.h>
31#include <linux/pci.h> 30#include <linux/pci.h>
32#include <linux/types.h> 31#include <linux/types.h>
diff --git a/arch/mips/pci/pci-ip27.c b/arch/mips/pci/pci-ip27.c
index 162b4cb29dba..0f09eafa5e3a 100644
--- a/arch/mips/pci/pci-ip27.c
+++ b/arch/mips/pci/pci-ip27.c
@@ -7,7 +7,6 @@
7 * Copyright (C) 1999, 2000, 04 Ralf Baechle (ralf@linux-mips.org) 7 * Copyright (C) 1999, 2000, 04 Ralf Baechle (ralf@linux-mips.org)
8 * Copyright (C) 1999, 2000 Silicon Graphics, Inc. 8 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
9 */ 9 */
10#include <linux/init.h>
11#include <linux/kernel.h> 10#include <linux/kernel.h>
12#include <linux/export.h> 11#include <linux/export.h>
13#include <linux/pci.h> 12#include <linux/pci.h>
diff --git a/arch/mips/pci/pci-malta.c b/arch/mips/pci/pci-malta.c
index 37134ddfeaa5..f1a73890dd4f 100644
--- a/arch/mips/pci/pci-malta.c
+++ b/arch/mips/pci/pci-malta.c
@@ -241,9 +241,9 @@ void __init mips_pcibios_init(void)
241 return; 241 return;
242 } 242 }
243 243
244 /* Change start address to avoid conflicts with ACPI and SMB devices */ 244 /* PIIX4 ACPI starts at 0x1000 */
245 if (controller->io_resource->start < 0x00002000UL) 245 if (controller->io_resource->start < 0x00001000UL)
246 controller->io_resource->start = 0x00002000UL; 246 controller->io_resource->start = 0x00001000UL;
247 247
248 iomem_resource.end &= 0xfffffffffULL; /* 64 GB */ 248 iomem_resource.end &= 0xfffffffffULL; /* 64 GB */
249 ioport_resource.end = controller->io_resource->end; 249 ioport_resource.end = controller->io_resource->end;
diff --git a/arch/mips/pci/pci-rt3883.c b/arch/mips/pci/pci-rt3883.c
index adeff2bfe4cd..72919aeef42b 100644
--- a/arch/mips/pci/pci-rt3883.c
+++ b/arch/mips/pci/pci-rt3883.c
@@ -436,9 +436,6 @@ static int rt3883_pci_probe(struct platform_device *pdev)
436 return -ENOMEM; 436 return -ENOMEM;
437 437
438 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 438 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
439 if (!res)
440 return -EINVAL;
441
442 rpc->base = devm_ioremap_resource(dev, res); 439 rpc->base = devm_ioremap_resource(dev, res);
443 if (IS_ERR(rpc->base)) 440 if (IS_ERR(rpc->base))
444 return PTR_ERR(rpc->base); 441 return PTR_ERR(rpc->base);
diff --git a/arch/mips/pci/pci-xlp.c b/arch/mips/pci/pci-xlp.c
index 653d2db9e0c5..7babf01600cb 100644
--- a/arch/mips/pci/pci-xlp.c
+++ b/arch/mips/pci/pci-xlp.c
@@ -47,10 +47,11 @@
47#include <asm/netlogic/interrupt.h> 47#include <asm/netlogic/interrupt.h>
48#include <asm/netlogic/haldefs.h> 48#include <asm/netlogic/haldefs.h>
49#include <asm/netlogic/common.h> 49#include <asm/netlogic/common.h>
50#include <asm/netlogic/mips-extns.h>
50 51
51#include <asm/netlogic/xlp-hal/iomap.h> 52#include <asm/netlogic/xlp-hal/iomap.h>
52#include <asm/netlogic/xlp-hal/pic.h>
53#include <asm/netlogic/xlp-hal/xlp.h> 53#include <asm/netlogic/xlp-hal/xlp.h>
54#include <asm/netlogic/xlp-hal/pic.h>
54#include <asm/netlogic/xlp-hal/pcibus.h> 55#include <asm/netlogic/xlp-hal/pcibus.h>
55#include <asm/netlogic/xlp-hal/bridge.h> 56#include <asm/netlogic/xlp-hal/bridge.h>
56 57
@@ -66,9 +67,22 @@ static inline u32 pci_cfg_read_32bit(struct pci_bus *bus, unsigned int devfn,
66 u32 *cfgaddr; 67 u32 *cfgaddr;
67 68
68 where &= ~3; 69 where &= ~3;
69 if (bus->number == 0 && PCI_SLOT(devfn) == 1 && where == 0x954) 70 if (cpu_is_xlp9xx()) {
71 /* be very careful on SoC buses */
72 if (bus->number == 0) {
73 /* Scan only existing nodes - uboot bug? */
74 if (PCI_SLOT(devfn) != 0 ||
75 !nlm_node_present(PCI_FUNC(devfn)))
76 return 0xffffffff;
77 } else if (bus->parent->number == 0) { /* SoC bus */
78 if (PCI_SLOT(devfn) == 0) /* b.0.0 hangs */
79 return 0xffffffff;
80 if (devfn == 44) /* b.5.4 hangs */
81 return 0xffffffff;
82 }
83 } else if (bus->number == 0 && PCI_SLOT(devfn) == 1 && where == 0x954) {
70 return 0xffffffff; 84 return 0xffffffff;
71 85 }
72 cfgaddr = (u32 *)(pci_config_base + 86 cfgaddr = (u32 *)(pci_config_base +
73 pci_cfg_addr(bus->number, devfn, where)); 87 pci_cfg_addr(bus->number, devfn, where));
74 data = *cfgaddr; 88 data = *cfgaddr;
@@ -162,27 +176,39 @@ struct pci_controller nlm_pci_controller = {
162 .io_offset = 0x00000000UL, 176 .io_offset = 0x00000000UL,
163}; 177};
164 178
165static struct pci_dev *xlp_get_pcie_link(const struct pci_dev *dev) 179struct pci_dev *xlp_get_pcie_link(const struct pci_dev *dev)
166{ 180{
167 struct pci_bus *bus, *p; 181 struct pci_bus *bus, *p;
168 182
169 /* Find the bridge on bus 0 */
170 bus = dev->bus; 183 bus = dev->bus;
171 for (p = bus->parent; p && p->number != 0; p = p->parent)
172 bus = p;
173 184
174 return p ? bus->self : NULL; 185 if (cpu_is_xlp9xx()) {
186 /* find bus with grand parent number == 0 */
187 for (p = bus->parent; p && p->parent && p->parent->number != 0;
188 p = p->parent)
189 bus = p;
190 return (p && p->parent) ? bus->self : NULL;
191 } else {
192 /* Find the bridge on bus 0 */
193 for (p = bus->parent; p && p->number != 0; p = p->parent)
194 bus = p;
195
196 return p ? bus->self : NULL;
197 }
175} 198}
176 199
177static inline int nlm_pci_link_to_irq(int link) 200int xlp_socdev_to_node(const struct pci_dev *lnkdev)
178{ 201{
179 return PIC_PCIE_LINK_0_IRQ + link; 202 if (cpu_is_xlp9xx())
203 return PCI_FUNC(lnkdev->bus->self->devfn);
204 else
205 return PCI_SLOT(lnkdev->devfn) / 8;
180} 206}
181 207
182int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) 208int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
183{ 209{
184 struct pci_dev *lnkdev; 210 struct pci_dev *lnkdev;
185 int lnkslot, lnkfunc; 211 int lnkfunc, node;
186 212
187 /* 213 /*
188 * For XLP PCIe, there is an IRQ per Link, find out which 214 * For XLP PCIe, there is an IRQ per Link, find out which
@@ -191,9 +217,11 @@ int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
191 lnkdev = xlp_get_pcie_link(dev); 217 lnkdev = xlp_get_pcie_link(dev);
192 if (lnkdev == NULL) 218 if (lnkdev == NULL)
193 return 0; 219 return 0;
220
194 lnkfunc = PCI_FUNC(lnkdev->devfn); 221 lnkfunc = PCI_FUNC(lnkdev->devfn);
195 lnkslot = PCI_SLOT(lnkdev->devfn); 222 node = xlp_socdev_to_node(lnkdev);
196 return nlm_irq_to_xirq(lnkslot / 8, nlm_pci_link_to_irq(lnkfunc)); 223
224 return nlm_irq_to_xirq(node, PIC_PCIE_LINK_LEGACY_IRQ(lnkfunc));
197} 225}
198 226
199/* Do platform specific device initialization at pci_enable_device() time */ 227/* Do platform specific device initialization at pci_enable_device() time */
@@ -220,17 +248,38 @@ static void xlp_config_pci_bswap(int node, int link)
220 * Enable byte swap in hardware. Program each link's PCIe SWAP regions 248 * Enable byte swap in hardware. Program each link's PCIe SWAP regions
221 * from the link's address ranges. 249 * from the link's address ranges.
222 */ 250 */
223 reg = nlm_read_bridge_reg(nbubase, BRIDGE_PCIEMEM_BASE0 + link); 251 if (cpu_is_xlp9xx()) {
224 nlm_write_pci_reg(lnkbase, PCIE_BYTE_SWAP_MEM_BASE, reg); 252 reg = nlm_read_bridge_reg(nbubase,
225 253 BRIDGE_9XX_PCIEMEM_BASE0 + link);
226 reg = nlm_read_bridge_reg(nbubase, BRIDGE_PCIEMEM_LIMIT0 + link); 254 nlm_write_pci_reg(lnkbase, PCIE_9XX_BYTE_SWAP_MEM_BASE, reg);
227 nlm_write_pci_reg(lnkbase, PCIE_BYTE_SWAP_MEM_LIM, reg | 0xfff); 255
228 256 reg = nlm_read_bridge_reg(nbubase,
229 reg = nlm_read_bridge_reg(nbubase, BRIDGE_PCIEIO_BASE0 + link); 257 BRIDGE_9XX_PCIEMEM_LIMIT0 + link);
230 nlm_write_pci_reg(lnkbase, PCIE_BYTE_SWAP_IO_BASE, reg); 258 nlm_write_pci_reg(lnkbase,
231 259 PCIE_9XX_BYTE_SWAP_MEM_LIM, reg | 0xfff);
232 reg = nlm_read_bridge_reg(nbubase, BRIDGE_PCIEIO_LIMIT0 + link); 260
233 nlm_write_pci_reg(lnkbase, PCIE_BYTE_SWAP_IO_LIM, reg | 0xfff); 261 reg = nlm_read_bridge_reg(nbubase,
262 BRIDGE_9XX_PCIEIO_BASE0 + link);
263 nlm_write_pci_reg(lnkbase, PCIE_9XX_BYTE_SWAP_IO_BASE, reg);
264
265 reg = nlm_read_bridge_reg(nbubase,
266 BRIDGE_9XX_PCIEIO_LIMIT0 + link);
267 nlm_write_pci_reg(lnkbase,
268 PCIE_9XX_BYTE_SWAP_IO_LIM, reg | 0xfff);
269 } else {
270 reg = nlm_read_bridge_reg(nbubase, BRIDGE_PCIEMEM_BASE0 + link);
271 nlm_write_pci_reg(lnkbase, PCIE_BYTE_SWAP_MEM_BASE, reg);
272
273 reg = nlm_read_bridge_reg(nbubase,
274 BRIDGE_PCIEMEM_LIMIT0 + link);
275 nlm_write_pci_reg(lnkbase, PCIE_BYTE_SWAP_MEM_LIM, reg | 0xfff);
276
277 reg = nlm_read_bridge_reg(nbubase, BRIDGE_PCIEIO_BASE0 + link);
278 nlm_write_pci_reg(lnkbase, PCIE_BYTE_SWAP_IO_BASE, reg);
279
280 reg = nlm_read_bridge_reg(nbubase, BRIDGE_PCIEIO_LIMIT0 + link);
281 nlm_write_pci_reg(lnkbase, PCIE_BYTE_SWAP_IO_LIM, reg | 0xfff);
282 }
234} 283}
235#else 284#else
236/* Swap configuration not needed in little-endian mode */ 285/* Swap configuration not needed in little-endian mode */
@@ -239,7 +288,6 @@ static inline void xlp_config_pci_bswap(int node, int link) {}
239 288
240static int __init pcibios_init(void) 289static int __init pcibios_init(void)
241{ 290{
242 struct nlm_soc_info *nodep;
243 uint64_t pciebase; 291 uint64_t pciebase;
244 int link, n; 292 int link, n;
245 u32 reg; 293 u32 reg;
@@ -253,20 +301,20 @@ static int __init pcibios_init(void)
253 ioport_resource.end = ~0; 301 ioport_resource.end = ~0;
254 302
255 for (n = 0; n < NLM_NR_NODES; n++) { 303 for (n = 0; n < NLM_NR_NODES; n++) {
256 nodep = nlm_get_node(n); 304 if (!nlm_node_present(n))
257 if (!nodep->coremask) 305 continue;
258 continue; /* node does not exist */
259 306
260 for (link = 0; link < 4; link++) { 307 for (link = 0; link < PCIE_NLINKS; link++) {
261 pciebase = nlm_get_pcie_base(n, link); 308 pciebase = nlm_get_pcie_base(n, link);
262 if (nlm_read_pci_reg(pciebase, 0) == 0xffffffff) 309 if (nlm_read_pci_reg(pciebase, 0) == 0xffffffff)
263 continue; 310 continue;
264 xlp_config_pci_bswap(n, link); 311 xlp_config_pci_bswap(n, link);
312 xlp_init_node_msi_irqs(n, link);
265 313
266 /* put in intpin and irq - u-boot does not */ 314 /* put in intpin and irq - u-boot does not */
267 reg = nlm_read_pci_reg(pciebase, 0xf); 315 reg = nlm_read_pci_reg(pciebase, 0xf);
268 reg &= ~0x1fu; 316 reg &= ~0x1ffu;
269 reg |= (1 << 8) | nlm_pci_link_to_irq(link); 317 reg |= (1 << 8) | PIC_PCIE_LINK_LEGACY_IRQ(link);
270 nlm_write_pci_reg(pciebase, 0xf, reg); 318 nlm_write_pci_reg(pciebase, 0xf, reg);
271 pr_info("XLP PCIe: Link %d-%d initialized.\n", n, link); 319 pr_info("XLP PCIe: Link %d-%d initialized.\n", n, link);
272 } 320 }
diff --git a/arch/mips/pmcs-msp71xx/Kconfig b/arch/mips/pmcs-msp71xx/Kconfig
index 3482b8c8640c..6073ca456d11 100644
--- a/arch/mips/pmcs-msp71xx/Kconfig
+++ b/arch/mips/pmcs-msp71xx/Kconfig
@@ -6,6 +6,7 @@ config PMC_MSP4200_EVAL
6 bool "PMC-Sierra MSP4200 Eval Board" 6 bool "PMC-Sierra MSP4200 Eval Board"
7 select IRQ_MSP_SLP 7 select IRQ_MSP_SLP
8 select HW_HAS_PCI 8 select HW_HAS_PCI
9 select MIPS_L1_CACHE_SHIFT_4
9 10
10config PMC_MSP4200_GW 11config PMC_MSP4200_GW
11 bool "PMC-Sierra MSP4200 VoIP Gateway" 12 bool "PMC-Sierra MSP4200 VoIP Gateway"
diff --git a/arch/mips/ralink/Kconfig b/arch/mips/ralink/Kconfig
index 424f03496d14..1bfd1c17b3c2 100644
--- a/arch/mips/ralink/Kconfig
+++ b/arch/mips/ralink/Kconfig
@@ -15,6 +15,7 @@ choice
15 15
16 config SOC_RT288X 16 config SOC_RT288X
17 bool "RT288x" 17 bool "RT288x"
18 select MIPS_L1_CACHE_SHIFT_4
18 19
19 config SOC_RT305X 20 config SOC_RT305X
20 bool "RT305x" 21 bool "RT305x"
diff --git a/arch/mips/sgi-ip27/ip27-console.c b/arch/mips/sgi-ip27/ip27-console.c
index b952d5b1af86..45fdfbcbd4c6 100644
--- a/arch/mips/sgi-ip27/ip27-console.c
+++ b/arch/mips/sgi-ip27/ip27-console.c
@@ -5,7 +5,6 @@
5 * 5 *
6 * Copyright (C) 2001, 2002 Ralf Baechle 6 * Copyright (C) 2001, 2002 Ralf Baechle
7 */ 7 */
8#include <linux/init.h>
9 8
10#include <asm/page.h> 9#include <asm/page.h>
11#include <asm/sn/addrs.h> 10#include <asm/sn/addrs.h>
diff --git a/arch/mips/sgi-ip27/ip27-irq-pci.c b/arch/mips/sgi-ip27/ip27-irq-pci.c
index ec22ec5600f3..2a1c40784bd9 100644
--- a/arch/mips/sgi-ip27/ip27-irq-pci.c
+++ b/arch/mips/sgi-ip27/ip27-irq-pci.c
@@ -8,7 +8,6 @@
8 8
9#undef DEBUG 9#undef DEBUG
10 10
11#include <linux/init.h>
12#include <linux/irq.h> 11#include <linux/irq.h>
13#include <linux/errno.h> 12#include <linux/errno.h>
14#include <linux/signal.h> 13#include <linux/signal.h>
diff --git a/arch/mips/sgi-ip27/ip27-klconfig.c b/arch/mips/sgi-ip27/ip27-klconfig.c
index 7afe14688003..c873d62ff083 100644
--- a/arch/mips/sgi-ip27/ip27-klconfig.c
+++ b/arch/mips/sgi-ip27/ip27-klconfig.c
@@ -2,7 +2,6 @@
2 * Copyright (C) 1999, 2000 Ralf Baechle (ralf@gnu.org) 2 * Copyright (C) 1999, 2000 Ralf Baechle (ralf@gnu.org)
3 * Copyright (C) 1999, 2000 Silicon Graphics, Inc. 3 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
4 */ 4 */
5#include <linux/init.h>
6#include <linux/kernel.h> 5#include <linux/kernel.h>
7#include <linux/sched.h> 6#include <linux/sched.h>
8#include <linux/interrupt.h> 7#include <linux/interrupt.h>
diff --git a/arch/mips/sgi-ip27/ip27-xtalk.c b/arch/mips/sgi-ip27/ip27-xtalk.c
index d59b820f528d..20f582a2137a 100644
--- a/arch/mips/sgi-ip27/ip27-xtalk.c
+++ b/arch/mips/sgi-ip27/ip27-xtalk.c
@@ -7,7 +7,6 @@
7 * Generic XTALK initialization code 7 * Generic XTALK initialization code
8 */ 8 */
9 9
10#include <linux/init.h>
11#include <linux/kernel.h> 10#include <linux/kernel.h>
12#include <linux/smp.h> 11#include <linux/smp.h>
13#include <asm/sn/types.h> 12#include <asm/sn/types.h>
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-04 02:19:04 -0500