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authorLinus Torvalds <torvalds@linux-foundation.org>2015-04-17 15:50:54 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2015-04-17 15:50:54 -0400
commitbfaf245022b4b8661af2e35f467cf0e91943c24c (patch)
treeb5a6ee49a047557a791eb897c8c9545a155e36b7 /arch/mips
parent96d928ed75c4ba4253e82910a697ec7b06ace8b4 (diff)
parent3e20a26b02bd4f24945c87407df51948dd488620 (diff)
Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus
Pull MIPS updates from Ralf Baechle: "This is the main pull request for MIPS for Linux 4.1. Most noteworthy: - Add more Octeon-optimized crypto functions - Octeon crypto preemption and locking fixes - Little endian support for Octeon - Use correct CSR to soft reset Octeons - Support LEDs on the Octeon-based DSR-1000N - Fix PCI interrupt mapping for the Octeon-based DSR-1000N - Mark prom_free_prom_memory() as __init for a number of systems - Support for Imagination's Pistachio SOC. This includes arch and CLK bits. I'd like to merge pinctrl bits later - Improve parallelism of csum_partial for certain pipelines - Organize DTB files in subdirs like other architectures - Implement read_sched_clock for all MIPS platforms other than Octeon - Massive series of 38 fixes and cleanups for the FPU emulator / kernel - Further FPU remulator work to support new features. This sits on a separate branch which also has been pulled into the 4.1 KVM branch - Clean up and fixes for the SEAD3 eval board; remove unused file - Various updates for Netlogic platforms - A number of small updates for Loongson 3 platforms - Increase the memory limit for ATH79 platforms to 256MB - A fair number of fixes and updates for BCM47xx platforms - Finish the implementation of XPA support - MIPS FDC support. No, not floppy controller but Fast Debug Channel :) - Detect the R16000 used in SGI legacy platforms - Fix Kconfig dependencies for the SSB bus support" * 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (265 commits) MIPS: Makefile: Fix MIPS ASE detection code MIPS: asm: elf: Set O32 default FPU flags MIPS: BCM47XX: Fix detecting Microsoft MN-700 & Asus WL500G MIPS: Kconfig: Disable SMP/CPS for 64-bit MIPS: Hibernate: flush TLB entries earlier MIPS: smp-cps: cpu_set FPU mask if FPU present MIPS: lose_fpu(): Disable FPU when MSA enabled MIPS: ralink: add missing symbol for RALINK_ILL_ACC MIPS: ralink: Fix bad config symbol in PCI makefile. SSB: fix Kconfig dependencies MIPS: Malta: Detect and fix bad memsize values Revert "MIPS: Avoid pipeline stalls on some MIPS32R2 cores." MIPS: Octeon: Delete override of cpu_has_mips_r2_exec_hazard. MIPS: Fix cpu_has_mips_r2_exec_hazard. MIPS: kernel: entry.S: Set correct ISA level for mips_ihb MIPS: asm: spinlock: Fix addiu instruction for R10000_LLSC_WAR case MIPS: r4kcache: Use correct base register for MIPS R6 cache flushes MIPS: Kconfig: Fix typo for the r2-to-r6 emulator kernel parameter MIPS: unaligned: Fix regular load/store instruction emulation for EVA MIPS: unaligned: Surround load/store macros in do {} while statements ...
Diffstat (limited to 'arch/mips')
-rw-r--r--arch/mips/Kbuild.platforms3
-rw-r--r--arch/mips/Kconfig116
-rw-r--r--arch/mips/Makefile21
-rw-r--r--arch/mips/ar7/platform.c5
-rw-r--r--arch/mips/ath79/common.h2
-rw-r--r--arch/mips/bcm3384/Platform7
-rw-r--r--arch/mips/bcm3384/dma.c81
-rw-r--r--arch/mips/bcm3384/irq.c193
-rw-r--r--arch/mips/bcm3384/setup.c97
-rw-r--r--arch/mips/bcm47xx/bcm47xx_private.h4
-rw-r--r--arch/mips/bcm47xx/board.c61
-rw-r--r--arch/mips/bcm47xx/buttons.c18
-rw-r--r--arch/mips/bcm47xx/leds.c10
-rw-r--r--arch/mips/bcm47xx/nvram.c77
-rw-r--r--arch/mips/bcm47xx/prom.c3
-rw-r--r--arch/mips/bcm47xx/serial.c8
-rw-r--r--arch/mips/bcm47xx/setup.c13
-rw-r--r--arch/mips/bcm47xx/sprom.c675
-rw-r--r--arch/mips/bcm47xx/time.c2
-rw-r--r--arch/mips/bcm63xx/prom.c4
-rw-r--r--arch/mips/bcm63xx/setup.c4
-rw-r--r--arch/mips/bmips/Kconfig62
-rw-r--r--arch/mips/bmips/Makefile (renamed from arch/mips/bcm3384/Makefile)0
-rw-r--r--arch/mips/bmips/Platform7
-rw-r--r--arch/mips/bmips/dma.c117
-rw-r--r--arch/mips/bmips/irq.c38
-rw-r--r--arch/mips/bmips/setup.c194
-rw-r--r--arch/mips/boot/compressed/Makefile9
-rw-r--r--arch/mips/boot/compressed/decompress.c5
-rw-r--r--arch/mips/boot/dts/Makefile33
-rw-r--r--arch/mips/boot/dts/bcm3384.dtsi109
-rw-r--r--arch/mips/boot/dts/brcm/Makefile19
-rw-r--r--arch/mips/boot/dts/brcm/bcm3384_viper.dtsi108
-rw-r--r--arch/mips/boot/dts/brcm/bcm3384_zephyr.dtsi126
-rw-r--r--arch/mips/boot/dts/brcm/bcm6328.dtsi86
-rw-r--r--arch/mips/boot/dts/brcm/bcm6368.dtsi93
-rw-r--r--arch/mips/boot/dts/brcm/bcm7125.dtsi139
-rw-r--r--arch/mips/boot/dts/brcm/bcm7346.dtsi224
-rw-r--r--arch/mips/boot/dts/brcm/bcm7358.dtsi161
-rw-r--r--arch/mips/boot/dts/brcm/bcm7360.dtsi161
-rw-r--r--arch/mips/boot/dts/brcm/bcm7362.dtsi167
-rw-r--r--arch/mips/boot/dts/brcm/bcm7420.dtsi184
-rw-r--r--arch/mips/boot/dts/brcm/bcm7425.dtsi225
-rw-r--r--arch/mips/boot/dts/brcm/bcm93384wvg.dts (renamed from arch/mips/boot/dts/bcm93384wvg.dts)9
-rw-r--r--arch/mips/boot/dts/brcm/bcm93384wvg_viper.dts25
-rw-r--r--arch/mips/boot/dts/brcm/bcm96368mvwg.dts31
-rw-r--r--arch/mips/boot/dts/brcm/bcm97125cbmb.dts31
-rw-r--r--arch/mips/boot/dts/brcm/bcm97346dbsmb.dts58
-rw-r--r--arch/mips/boot/dts/brcm/bcm97358svmb.dts34
-rw-r--r--arch/mips/boot/dts/brcm/bcm97360svmb.dts34
-rw-r--r--arch/mips/boot/dts/brcm/bcm97362svmb.dts34
-rw-r--r--arch/mips/boot/dts/brcm/bcm97420c.dts45
-rw-r--r--arch/mips/boot/dts/brcm/bcm97425svmb.dts60
-rw-r--r--arch/mips/boot/dts/brcm/bcm9ejtagprb.dts22
-rw-r--r--arch/mips/boot/dts/cavium-octeon/Makefile9
-rw-r--r--arch/mips/boot/dts/cavium-octeon/octeon_3xxx.dts (renamed from arch/mips/boot/dts/octeon_3xxx.dts)12
-rw-r--r--arch/mips/boot/dts/cavium-octeon/octeon_68xx.dts (renamed from arch/mips/boot/dts/octeon_68xx.dts)0
-rw-r--r--arch/mips/boot/dts/lantiq/Makefile9
-rw-r--r--arch/mips/boot/dts/lantiq/danube.dtsi (renamed from arch/mips/boot/dts/danube.dtsi)0
-rw-r--r--arch/mips/boot/dts/lantiq/easy50712.dts (renamed from arch/mips/boot/dts/easy50712.dts)0
-rw-r--r--arch/mips/boot/dts/mti/Makefile9
-rw-r--r--arch/mips/boot/dts/mti/sead3.dts (renamed from arch/mips/boot/dts/sead3.dts)0
-rw-r--r--arch/mips/boot/dts/netlogic/Makefile13
-rw-r--r--arch/mips/boot/dts/netlogic/xlp_evp.dts (renamed from arch/mips/boot/dts/xlp_evp.dts)0
-rw-r--r--arch/mips/boot/dts/netlogic/xlp_fvp.dts (renamed from arch/mips/boot/dts/xlp_fvp.dts)0
-rw-r--r--arch/mips/boot/dts/netlogic/xlp_gvp.dts (renamed from arch/mips/boot/dts/xlp_gvp.dts)0
-rw-r--r--arch/mips/boot/dts/netlogic/xlp_rvp.dts77
-rw-r--r--arch/mips/boot/dts/netlogic/xlp_svp.dts (renamed from arch/mips/boot/dts/xlp_svp.dts)0
-rw-r--r--arch/mips/boot/dts/ralink/Makefile12
-rw-r--r--arch/mips/boot/dts/ralink/mt7620a.dtsi (renamed from arch/mips/boot/dts/mt7620a.dtsi)0
-rw-r--r--arch/mips/boot/dts/ralink/mt7620a_eval.dts (renamed from arch/mips/boot/dts/mt7620a_eval.dts)0
-rw-r--r--arch/mips/boot/dts/ralink/rt2880.dtsi (renamed from arch/mips/boot/dts/rt2880.dtsi)0
-rw-r--r--arch/mips/boot/dts/ralink/rt2880_eval.dts (renamed from arch/mips/boot/dts/rt2880_eval.dts)0
-rw-r--r--arch/mips/boot/dts/ralink/rt3050.dtsi (renamed from arch/mips/boot/dts/rt3050.dtsi)0
-rw-r--r--arch/mips/boot/dts/ralink/rt3052_eval.dts (renamed from arch/mips/boot/dts/rt3052_eval.dts)0
-rw-r--r--arch/mips/boot/dts/ralink/rt3883.dtsi (renamed from arch/mips/boot/dts/rt3883.dtsi)0
-rw-r--r--arch/mips/boot/dts/ralink/rt3883_eval.dts (renamed from arch/mips/boot/dts/rt3883_eval.dts)0
-rw-r--r--arch/mips/cavium-octeon/crypto/octeon-crypto.h80
-rw-r--r--arch/mips/cavium-octeon/dma-octeon.c2
-rw-r--r--arch/mips/cavium-octeon/executive/cvmx-l2c.c45
-rw-r--r--arch/mips/cavium-octeon/flash_setup.c83
-rw-r--r--arch/mips/cavium-octeon/octeon-platform.c19
-rw-r--r--arch/mips/cavium-octeon/octeon_boot.h23
-rw-r--r--arch/mips/cavium-octeon/setup.c10
-rw-r--r--arch/mips/configs/bmips_be_defconfig (renamed from arch/mips/configs/bcm3384_defconfig)11
-rw-r--r--arch/mips/configs/bmips_stb_defconfig88
-rw-r--r--arch/mips/configs/maltaup_xpa_defconfig439
-rw-r--r--arch/mips/configs/pistachio_defconfig336
-rw-r--r--arch/mips/dec/int-handler.S7
-rw-r--r--arch/mips/dec/setup.c16
-rw-r--r--arch/mips/include/asm/asm-eva.h137
-rw-r--r--arch/mips/include/asm/asmmacro-32.h96
-rw-r--r--arch/mips/include/asm/bitops.h7
-rw-r--r--arch/mips/include/asm/bmips.h16
-rw-r--r--arch/mips/include/asm/cacheflush.h38
-rw-r--r--arch/mips/include/asm/cdmm.h98
-rw-r--r--arch/mips/include/asm/cevt-r4k.h19
-rw-r--r--arch/mips/include/asm/checksum.h6
-rw-r--r--arch/mips/include/asm/cmpxchg.h11
-rw-r--r--arch/mips/include/asm/cpu-features.h48
-rw-r--r--arch/mips/include/asm/cpu-info.h2
-rw-r--r--arch/mips/include/asm/cpu-type.h1
-rw-r--r--arch/mips/include/asm/cpu.h8
-rw-r--r--arch/mips/include/asm/dma-mapping.h2
-rw-r--r--arch/mips/include/asm/elf.h12
-rw-r--r--arch/mips/include/asm/fpu.h7
-rw-r--r--arch/mips/include/asm/fpu_emulator.h6
-rw-r--r--arch/mips/include/asm/irq.h3
-rw-r--r--arch/mips/include/asm/mach-ar7/war.h24
-rw-r--r--arch/mips/include/asm/mach-ath25/dma-coherence.h14
-rw-r--r--arch/mips/include/asm/mach-ath25/war.h25
-rw-r--r--arch/mips/include/asm/mach-au1x00/war.h24
-rw-r--r--arch/mips/include/asm/mach-bcm3384/war.h24
-rw-r--r--arch/mips/include/asm/mach-bcm47xx/bcm47xx.h1
-rw-r--r--arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h4
-rw-r--r--arch/mips/include/asm/mach-bcm47xx/bcm47xx_nvram.h21
-rw-r--r--arch/mips/include/asm/mach-bcm47xx/war.h24
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/dma-coherence.h10
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/war.h24
-rw-r--r--arch/mips/include/asm/mach-bmips/dma-coherence.h (renamed from arch/mips/include/asm/mach-bcm3384/dma-coherence.h)12
-rw-r--r--arch/mips/include/asm/mach-bmips/spaces.h18
-rw-r--r--arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h1
-rw-r--r--arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h4
-rw-r--r--arch/mips/include/asm/mach-cavium-octeon/mangle-port.h74
-rw-r--r--arch/mips/include/asm/mach-cobalt/cpu-feature-overrides.h1
-rw-r--r--arch/mips/include/asm/mach-cobalt/war.h24
-rw-r--r--arch/mips/include/asm/mach-dec/cpu-feature-overrides.h1
-rw-r--r--arch/mips/include/asm/mach-dec/war.h24
-rw-r--r--arch/mips/include/asm/mach-emma2rh/war.h24
-rw-r--r--arch/mips/include/asm/mach-generic/dma-coherence.h6
-rw-r--r--arch/mips/include/asm/mach-generic/war.h (renamed from arch/mips/include/asm/mach-ath79/war.h)6
-rw-r--r--arch/mips/include/asm/mach-ip22/cpu-feature-overrides.h1
-rw-r--r--arch/mips/include/asm/mach-ip27/dma-coherence.h4
-rw-r--r--arch/mips/include/asm/mach-ip32/cpu-feature-overrides.h1
-rw-r--r--arch/mips/include/asm/mach-ip32/dma-coherence.h4
-rw-r--r--arch/mips/include/asm/mach-jazz/dma-coherence.h4
-rw-r--r--arch/mips/include/asm/mach-jazz/war.h24
-rw-r--r--arch/mips/include/asm/mach-jz4740/war.h24
-rw-r--r--arch/mips/include/asm/mach-lantiq/war.h23
-rw-r--r--arch/mips/include/asm/mach-lasat/war.h24
-rw-r--r--arch/mips/include/asm/mach-loongson/cpu-feature-overrides.h1
-rw-r--r--arch/mips/include/asm/mach-loongson/dma-coherence.h4
-rw-r--r--arch/mips/include/asm/mach-loongson/loongson.h4
-rw-r--r--arch/mips/include/asm/mach-loongson/war.h24
-rw-r--r--arch/mips/include/asm/mach-loongson1/war.h24
-rw-r--r--arch/mips/include/asm/mach-netlogic/multi-node.h9
-rw-r--r--arch/mips/include/asm/mach-netlogic/topology.h15
-rw-r--r--arch/mips/include/asm/mach-netlogic/war.h25
-rw-r--r--arch/mips/include/asm/mach-paravirt/war.h25
-rw-r--r--arch/mips/include/asm/mach-pistachio/gpio.h21
-rw-r--r--arch/mips/include/asm/mach-pistachio/irq.h18
-rw-r--r--arch/mips/include/asm/mach-pnx833x/war.h24
-rw-r--r--arch/mips/include/asm/mach-ralink/war.h24
-rw-r--r--arch/mips/include/asm/mach-rm/cpu-feature-overrides.h1
-rw-r--r--arch/mips/include/asm/mach-tx39xx/war.h24
-rw-r--r--arch/mips/include/asm/mach-vr41xx/war.h24
-rw-r--r--arch/mips/include/asm/mips-boards/sead3-addr.h83
-rw-r--r--arch/mips/include/asm/mips-r2-to-r6-emul.h9
-rw-r--r--arch/mips/include/asm/mipsregs.h312
-rw-r--r--arch/mips/include/asm/netlogic/common.h21
-rw-r--r--arch/mips/include/asm/netlogic/mips-extns.h8
-rw-r--r--arch/mips/include/asm/netlogic/xlp-hal/cpucontrol.h2
-rw-r--r--arch/mips/include/asm/netlogic/xlp-hal/sys.h3
-rw-r--r--arch/mips/include/asm/netlogic/xlp-hal/xlp.h3
-rw-r--r--arch/mips/include/asm/octeon/cvmx-address.h67
-rw-r--r--arch/mips/include/asm/octeon/cvmx-bootinfo.h55
-rw-r--r--arch/mips/include/asm/octeon/cvmx-bootmem.h14
-rw-r--r--arch/mips/include/asm/octeon/cvmx-fau.h22
-rw-r--r--arch/mips/include/asm/octeon/cvmx-fpa.h7
-rw-r--r--arch/mips/include/asm/octeon/cvmx-l2c.h9
-rw-r--r--arch/mips/include/asm/octeon/cvmx-packet.h8
-rw-r--r--arch/mips/include/asm/octeon/cvmx-pko.h31
-rw-r--r--arch/mips/include/asm/octeon/cvmx-pow.h247
-rw-r--r--arch/mips/include/asm/octeon/cvmx-wqe.h71
-rw-r--r--arch/mips/include/asm/octeon/cvmx.h8
-rw-r--r--arch/mips/include/asm/octeon/octeon.h2
-rw-r--r--arch/mips/include/asm/octeon/pci-octeon.h3
-rw-r--r--arch/mips/include/asm/page.h2
-rw-r--r--arch/mips/include/asm/pci.h2
-rw-r--r--arch/mips/include/asm/pci/bridge.h1
-rw-r--r--arch/mips/include/asm/pgtable-32.h15
-rw-r--r--arch/mips/include/asm/pgtable-64.h10
-rw-r--r--arch/mips/include/asm/pgtable-bits.h96
-rw-r--r--arch/mips/include/asm/pgtable.h83
-rw-r--r--arch/mips/include/asm/r4kcache.h89
-rw-r--r--arch/mips/include/asm/sgi/sgi.h15
-rw-r--r--arch/mips/include/asm/spinlock.h2
-rw-r--r--arch/mips/include/asm/thread_info.h4
-rw-r--r--arch/mips/jz4740/Platform1
-rw-r--r--arch/mips/jz4740/time.c8
-rw-r--r--arch/mips/kernel/branch.c6
-rw-r--r--arch/mips/kernel/cevt-r4k.c33
-rw-r--r--arch/mips/kernel/cevt-txx9.c9
-rw-r--r--arch/mips/kernel/cpu-probe.c200
-rw-r--r--arch/mips/kernel/csrc-bcm1480.c12
-rw-r--r--arch/mips/kernel/csrc-ioasic.c13
-rw-r--r--arch/mips/kernel/csrc-r4k.c8
-rw-r--r--arch/mips/kernel/csrc-sb1250.c23
-rw-r--r--arch/mips/kernel/elf.c14
-rw-r--r--arch/mips/kernel/entry.S3
-rw-r--r--arch/mips/kernel/idle.c13
-rw-r--r--arch/mips/kernel/mips-r2-to-r6-emul.c15
-rw-r--r--arch/mips/kernel/perf_event_mipsxx.c83
-rw-r--r--arch/mips/kernel/proc.c1
-rw-r--r--arch/mips/kernel/process.c10
-rw-r--r--arch/mips/kernel/prom.c5
-rw-r--r--arch/mips/kernel/ptrace.c10
-rw-r--r--arch/mips/kernel/r2300_switch.S7
-rw-r--r--arch/mips/kernel/r4k_switch.S7
-rw-r--r--arch/mips/kernel/reset.c25
-rw-r--r--arch/mips/kernel/setup.c2
-rw-r--r--arch/mips/kernel/smp-cps.c6
-rw-r--r--arch/mips/kernel/smp.c6
-rw-r--r--arch/mips/kernel/traps.c276
-rw-r--r--arch/mips/kernel/unaligned.c346
-rw-r--r--arch/mips/lantiq/prom.c2
-rw-r--r--arch/mips/lantiq/xway/vmmc.c1
-rw-r--r--arch/mips/lasat/sysctl.c15
-rw-r--r--arch/mips/lib/csum_partial.S38
-rw-r--r--arch/mips/loongson/common/env.c9
-rw-r--r--arch/mips/loongson/common/pci.c6
-rw-r--r--arch/mips/loongson/loongson-3/cop2-ex.c2
-rw-r--r--arch/mips/loongson/loongson-3/irq.c1
-rw-r--r--arch/mips/math-emu/Makefile15
-rw-r--r--arch/mips/math-emu/cp1emu.c288
-rw-r--r--arch/mips/math-emu/dp_add.c14
-rw-r--r--arch/mips/math-emu/dp_cmp.c13
-rw-r--r--arch/mips/math-emu/dp_div.c9
-rw-r--r--arch/mips/math-emu/dp_fsp.c16
-rw-r--r--arch/mips/math-emu/dp_mul.c9
-rw-r--r--arch/mips/math-emu/dp_simple.c55
-rw-r--r--arch/mips/math-emu/dp_sqrt.c13
-rw-r--r--arch/mips/math-emu/dp_sub.c14
-rw-r--r--arch/mips/math-emu/dsemul.c6
-rw-r--r--arch/mips/math-emu/ieee754.h111
-rw-r--r--arch/mips/math-emu/ieee754dp.c25
-rw-r--r--arch/mips/math-emu/ieee754dp.h1
-rw-r--r--arch/mips/math-emu/ieee754int.h5
-rw-r--r--arch/mips/math-emu/ieee754sp.c25
-rw-r--r--arch/mips/math-emu/ieee754sp.h1
-rw-r--r--arch/mips/math-emu/me-debugfs.c1
-rw-r--r--arch/mips/math-emu/sp_add.c14
-rw-r--r--arch/mips/math-emu/sp_cmp.c13
-rw-r--r--arch/mips/math-emu/sp_div.c9
-rw-r--r--arch/mips/math-emu/sp_fdp.c22
-rw-r--r--arch/mips/math-emu/sp_mul.c9
-rw-r--r--arch/mips/math-emu/sp_simple.c55
-rw-r--r--arch/mips/math-emu/sp_sqrt.c13
-rw-r--r--arch/mips/math-emu/sp_sub.c14
-rw-r--r--arch/mips/mm/c-r4k.c33
-rw-r--r--arch/mips/mm/cache.c39
-rw-r--r--arch/mips/mm/dma-default.c4
-rw-r--r--arch/mips/mm/init.c7
-rw-r--r--arch/mips/mm/page.c1
-rw-r--r--arch/mips/mm/tlb-r4k.c15
-rw-r--r--arch/mips/mm/tlbex.c116
-rw-r--r--arch/mips/mti-malta/malta-memory.c13
-rw-r--r--arch/mips/mti-malta/malta-time.c20
-rw-r--r--arch/mips/mti-sead3/Makefile7
-rw-r--r--arch/mips/mti-sead3/leds-sead3.c41
-rw-r--r--arch/mips/mti-sead3/sead3-ehci.c53
-rw-r--r--arch/mips/mti-sead3/sead3-i2c-dev.c33
-rw-r--r--arch/mips/mti-sead3/sead3-i2c-drv.c404
-rw-r--r--arch/mips/mti-sead3/sead3-i2c.c31
-rw-r--r--arch/mips/mti-sead3/sead3-init.c2
-rw-r--r--arch/mips/mti-sead3/sead3-leds.c79
-rw-r--r--arch/mips/mti-sead3/sead3-mtd.c53
-rw-r--r--arch/mips/mti-sead3/sead3-net.c57
-rw-r--r--arch/mips/mti-sead3/sead3-platform.c184
-rw-r--r--arch/mips/netlogic/Kconfig9
-rw-r--r--arch/mips/netlogic/common/irq.c10
-rw-r--r--arch/mips/netlogic/common/reset.S22
-rw-r--r--arch/mips/netlogic/common/smp.c25
-rw-r--r--arch/mips/netlogic/common/time.c1
-rw-r--r--arch/mips/netlogic/xlp/ahci-init-xlp2.c13
-rw-r--r--arch/mips/netlogic/xlp/ahci-init.c2
-rw-r--r--arch/mips/netlogic/xlp/dt.c10
-rw-r--r--arch/mips/netlogic/xlp/nlm_hal.c57
-rw-r--r--arch/mips/netlogic/xlp/setup.c7
-rw-r--r--arch/mips/netlogic/xlp/usb-init-xlp2.c10
-rw-r--r--arch/mips/netlogic/xlp/wakeup.c10
-rw-r--r--arch/mips/oprofile/common.c1
-rw-r--r--arch/mips/oprofile/op_model_mipsxx.c15
-rw-r--r--arch/mips/pci/Makefile2
-rw-r--r--arch/mips/pci/msi-xlp.c19
-rw-r--r--arch/mips/pci/pci-ar2315.c1
-rw-r--r--arch/mips/pci/pci-octeon.c8
-rw-r--r--arch/mips/pci/pci-rt2880.c1
-rw-r--r--arch/mips/pci/pci.c5
-rw-r--r--arch/mips/pci/pcie-octeon.c8
-rw-r--r--arch/mips/pistachio/Makefile1
-rw-r--r--arch/mips/pistachio/Platform8
-rw-r--r--arch/mips/pistachio/init.c131
-rw-r--r--arch/mips/pistachio/irq.c28
-rw-r--r--arch/mips/pistachio/time.c52
-rw-r--r--arch/mips/power/Makefile2
-rw-r--r--arch/mips/power/hibernate.c10
-rw-r--r--arch/mips/power/hibernate_asm.S (renamed from arch/mips/power/hibernate.S)5
-rw-r--r--arch/mips/ralink/Kconfig5
-rw-r--r--arch/mips/sgi-ip27/ip27-timer.c8
-rw-r--r--arch/mips/sgi-ip32/ip32-platform.c5
301 files changed, 7837 insertions, 3773 deletions
diff --git a/arch/mips/Kbuild.platforms b/arch/mips/Kbuild.platforms
index e5fc463b36d0..39cf40da5f14 100644
--- a/arch/mips/Kbuild.platforms
+++ b/arch/mips/Kbuild.platforms
@@ -4,9 +4,9 @@ platforms += alchemy
4platforms += ar7 4platforms += ar7
5platforms += ath25 5platforms += ath25
6platforms += ath79 6platforms += ath79
7platforms += bcm3384
8platforms += bcm47xx 7platforms += bcm47xx
9platforms += bcm63xx 8platforms += bcm63xx
9platforms += bmips
10platforms += cavium-octeon 10platforms += cavium-octeon
11platforms += cobalt 11platforms += cobalt
12platforms += dec 12platforms += dec
@@ -21,6 +21,7 @@ platforms += mti-malta
21platforms += mti-sead3 21platforms += mti-sead3
22platforms += netlogic 22platforms += netlogic
23platforms += paravirt 23platforms += paravirt
24platforms += pistachio
24platforms += pmcs-msp71xx 25platforms += pmcs-msp71xx
25platforms += pnx833x 26platforms += pnx833x
26platforms += ralink 27platforms += ralink
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index a326c4cb8cf0..2198837c256f 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -43,6 +43,7 @@ config MIPS
43 select GENERIC_SMP_IDLE_THREAD 43 select GENERIC_SMP_IDLE_THREAD
44 select BUILDTIME_EXTABLE_SORT 44 select BUILDTIME_EXTABLE_SORT
45 select GENERIC_CLOCKEVENTS 45 select GENERIC_CLOCKEVENTS
46 select GENERIC_SCHED_CLOCK if !CAVIUM_OCTEON_SOC
46 select GENERIC_CMOS_UPDATE 47 select GENERIC_CMOS_UPDATE
47 select HAVE_MOD_ARCH_SPECIFIC 48 select HAVE_MOD_ARCH_SPECIFIC
48 select VIRT_TO_BUS 49 select VIRT_TO_BUS
@@ -55,6 +56,8 @@ config MIPS
55 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST 56 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
56 select ARCH_BINFMT_ELF_STATE 57 select ARCH_BINFMT_ELF_STATE
57 select SYSCTL_EXCEPTION_TRACE 58 select SYSCTL_EXCEPTION_TRACE
59 select HAVE_VIRT_CPU_ACCOUNTING_GEN
60 select HAVE_IRQ_TIME_ACCOUNTING
58 61
59menu "Machine selection" 62menu "Machine selection"
60 63
@@ -131,8 +134,8 @@ config ATH79
131 help 134 help
132 Support for the Atheros AR71XX/AR724X/AR913X SoCs. 135 Support for the Atheros AR71XX/AR724X/AR913X SoCs.
133 136
134config BCM3384 137config BMIPS_GENERIC
135 bool "Broadcom BCM3384 based boards" 138 bool "Broadcom Generic BMIPS kernel"
136 select BOOT_RAW 139 select BOOT_RAW
137 select NO_EXCEPT_FILL 140 select NO_EXCEPT_FILL
138 select USE_OF 141 select USE_OF
@@ -140,22 +143,30 @@ config BCM3384
140 select CSRC_R4K 143 select CSRC_R4K
141 select SYNC_R4K 144 select SYNC_R4K
142 select COMMON_CLK 145 select COMMON_CLK
143 select DMA_NONCOHERENT 146 select BCM7038_L1_IRQ
147 select BCM7120_L2_IRQ
148 select BRCMSTB_L2_IRQ
144 select IRQ_CPU 149 select IRQ_CPU
150 select RAW_IRQ_ACCESSORS
151 select DMA_NONCOHERENT
145 select SYS_SUPPORTS_32BIT_KERNEL 152 select SYS_SUPPORTS_32BIT_KERNEL
153 select SYS_SUPPORTS_LITTLE_ENDIAN
146 select SYS_SUPPORTS_BIG_ENDIAN 154 select SYS_SUPPORTS_BIG_ENDIAN
147 select SYS_SUPPORTS_HIGHMEM 155 select SYS_SUPPORTS_HIGHMEM
156 select SYS_HAS_CPU_BMIPS32_3300
157 select SYS_HAS_CPU_BMIPS4350
158 select SYS_HAS_CPU_BMIPS4380
148 select SYS_HAS_CPU_BMIPS5000 159 select SYS_HAS_CPU_BMIPS5000
149 select SWAP_IO_SPACE 160 select SWAP_IO_SPACE
150 select USB_EHCI_BIG_ENDIAN_DESC 161 select USB_EHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
151 select USB_EHCI_BIG_ENDIAN_MMIO 162 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
152 select USB_OHCI_BIG_ENDIAN_DESC 163 select USB_OHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
153 select USB_OHCI_BIG_ENDIAN_MMIO 164 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
154 help 165 help
155 Support for BCM3384 based boards. BCM3384/BCM33843 is a cable modem 166 Build a generic DT-based kernel image that boots on select
156 chipset with a Linux application processor that is often used to 167 BCM33xx cable modem chips, BCM63xx DSL chips, and BCM7xxx set-top
157 provide Samba services, a CUPS print server, and/or advanced routing 168 box chips. Note that CONFIG_CPU_BIG_ENDIAN/CONFIG_CPU_LITTLE_ENDIAN
158 features. 169 must be set appropriately for your board.
159 170
160config BCM47XX 171config BCM47XX
161 bool "Broadcom BCM47XX based boards" 172 bool "Broadcom BCM47XX based boards"
@@ -352,6 +363,33 @@ config MACH_LOONGSON1
352 the ICT (Institute of Computing Technology) and the Chinese Academy 363 the ICT (Institute of Computing Technology) and the Chinese Academy
353 of Sciences. 364 of Sciences.
354 365
366config MACH_PISTACHIO
367 bool "IMG Pistachio SoC based boards"
368 select ARCH_REQUIRE_GPIOLIB
369 select BOOT_ELF32
370 select BOOT_RAW
371 select CEVT_R4K
372 select CLKSRC_MIPS_GIC
373 select COMMON_CLK
374 select CSRC_R4K
375 select DMA_MAYBE_COHERENT
376 select IRQ_CPU
377 select LIBFDT
378 select MFD_SYSCON
379 select MIPS_CPU_SCACHE
380 select MIPS_GIC
381 select PINCTRL
382 select REGULATOR
383 select SYS_HAS_CPU_MIPS32_R2
384 select SYS_SUPPORTS_32BIT_KERNEL
385 select SYS_SUPPORTS_LITTLE_ENDIAN
386 select SYS_SUPPORTS_MIPS_CPS
387 select SYS_SUPPORTS_MULTITHREADING
388 select SYS_SUPPORTS_ZBOOT
389 select USE_OF
390 help
391 This enables support for the IMG Pistachio SoC platform.
392
355config MIPS_MALTA 393config MIPS_MALTA
356 bool "MIPS Malta board" 394 bool "MIPS Malta board"
357 select ARCH_MAY_HAVE_PC_FDC 395 select ARCH_MAY_HAVE_PC_FDC
@@ -377,6 +415,7 @@ config MIPS_MALTA
377 select SYS_HAS_CPU_MIPS32_R1 415 select SYS_HAS_CPU_MIPS32_R1
378 select SYS_HAS_CPU_MIPS32_R2 416 select SYS_HAS_CPU_MIPS32_R2
379 select SYS_HAS_CPU_MIPS32_R3_5 417 select SYS_HAS_CPU_MIPS32_R3_5
418 select SYS_HAS_CPU_MIPS32_R5
380 select SYS_HAS_CPU_MIPS32_R6 419 select SYS_HAS_CPU_MIPS32_R6
381 select SYS_HAS_CPU_MIPS64_R1 420 select SYS_HAS_CPU_MIPS64_R1
382 select SYS_HAS_CPU_MIPS64_R2 421 select SYS_HAS_CPU_MIPS64_R2
@@ -386,6 +425,7 @@ config MIPS_MALTA
386 select SYS_SUPPORTS_32BIT_KERNEL 425 select SYS_SUPPORTS_32BIT_KERNEL
387 select SYS_SUPPORTS_64BIT_KERNEL 426 select SYS_SUPPORTS_64BIT_KERNEL
388 select SYS_SUPPORTS_BIG_ENDIAN 427 select SYS_SUPPORTS_BIG_ENDIAN
428 select SYS_SUPPORTS_HIGHMEM
389 select SYS_SUPPORTS_LITTLE_ENDIAN 429 select SYS_SUPPORTS_LITTLE_ENDIAN
390 select SYS_SUPPORTS_MICROMIPS 430 select SYS_SUPPORTS_MICROMIPS
391 select SYS_SUPPORTS_MIPS_CMP 431 select SYS_SUPPORTS_MIPS_CMP
@@ -779,7 +819,8 @@ config CAVIUM_OCTEON_SOC
779 select SYS_SUPPORTS_64BIT_KERNEL 819 select SYS_SUPPORTS_64BIT_KERNEL
780 select SYS_SUPPORTS_BIG_ENDIAN 820 select SYS_SUPPORTS_BIG_ENDIAN
781 select EDAC_SUPPORT 821 select EDAC_SUPPORT
782 select SYS_SUPPORTS_HOTPLUG_CPU 822 select SYS_SUPPORTS_LITTLE_ENDIAN
823 select SYS_SUPPORTS_HOTPLUG_CPU if CPU_BIG_ENDIAN
783 select SYS_HAS_EARLY_PRINTK 824 select SYS_HAS_EARLY_PRINTK
784 select SYS_HAS_CPU_CAVIUM_OCTEON 825 select SYS_HAS_CPU_CAVIUM_OCTEON
785 select SWAP_IO_SPACE 826 select SWAP_IO_SPACE
@@ -793,6 +834,7 @@ config CAVIUM_OCTEON_SOC
793 select SYS_SUPPORTS_SMP 834 select SYS_SUPPORTS_SMP
794 select NR_CPUS_DEFAULT_16 835 select NR_CPUS_DEFAULT_16
795 select BUILTIN_DTB 836 select BUILTIN_DTB
837 select MTD_COMPLEX_MAPPINGS
796 help 838 help
797 This option supports all of the Octeon reference boards from Cavium 839 This option supports all of the Octeon reference boards from Cavium
798 Networks. It builds a kernel that dynamically determines the Octeon 840 Networks. It builds a kernel that dynamically determines the Octeon
@@ -887,6 +929,7 @@ source "arch/mips/ath25/Kconfig"
887source "arch/mips/ath79/Kconfig" 929source "arch/mips/ath79/Kconfig"
888source "arch/mips/bcm47xx/Kconfig" 930source "arch/mips/bcm47xx/Kconfig"
889source "arch/mips/bcm63xx/Kconfig" 931source "arch/mips/bcm63xx/Kconfig"
932source "arch/mips/bmips/Kconfig"
890source "arch/mips/jazz/Kconfig" 933source "arch/mips/jazz/Kconfig"
891source "arch/mips/jz4740/Kconfig" 934source "arch/mips/jz4740/Kconfig"
892source "arch/mips/lantiq/Kconfig" 935source "arch/mips/lantiq/Kconfig"
@@ -1202,10 +1245,10 @@ config MIPS_L1_CACHE_SHIFT_7
1202 1245
1203config MIPS_L1_CACHE_SHIFT 1246config MIPS_L1_CACHE_SHIFT
1204 int 1247 int
1205 default "4" if MIPS_L1_CACHE_SHIFT_4
1206 default "5" if MIPS_L1_CACHE_SHIFT_5
1207 default "6" if MIPS_L1_CACHE_SHIFT_6
1208 default "7" if MIPS_L1_CACHE_SHIFT_7 1248 default "7" if MIPS_L1_CACHE_SHIFT_7
1249 default "6" if MIPS_L1_CACHE_SHIFT_6
1250 default "5" if MIPS_L1_CACHE_SHIFT_5
1251 default "4" if MIPS_L1_CACHE_SHIFT_4
1209 default "5" 1252 default "5"
1210 1253
1211config HAVE_STD_PC_SERIAL_PORT 1254config HAVE_STD_PC_SERIAL_PORT
@@ -1572,6 +1615,7 @@ config CPU_XLP
1572 select WEAK_REORDERING_BEYOND_LLSC 1615 select WEAK_REORDERING_BEYOND_LLSC
1573 select CPU_HAS_PREFETCH 1616 select CPU_HAS_PREFETCH
1574 select CPU_MIPSR2 1617 select CPU_MIPSR2
1618 select CPU_SUPPORTS_HUGEPAGES
1575 help 1619 help
1576 Netlogic Microsystems XLP processors. 1620 Netlogic Microsystems XLP processors.
1577endchoice 1621endchoice
@@ -1596,6 +1640,33 @@ config CPU_MIPS32_3_5_EVA
1596 One of its primary benefits is an increase in the maximum size 1640 One of its primary benefits is an increase in the maximum size
1597 of lowmem (up to 3GB). If unsure, say 'N' here. 1641 of lowmem (up to 3GB). If unsure, say 'N' here.
1598 1642
1643config CPU_MIPS32_R5_FEATURES
1644 bool "MIPS32 Release 5 Features"
1645 depends on SYS_HAS_CPU_MIPS32_R5
1646 depends on CPU_MIPS32_R2
1647 help
1648 Choose this option to build a kernel for release 2 or later of the
1649 MIPS32 architecture including features from release 5 such as
1650 support for Extended Physical Addressing (XPA).
1651
1652config CPU_MIPS32_R5_XPA
1653 bool "Extended Physical Addressing (XPA)"
1654 depends on CPU_MIPS32_R5_FEATURES
1655 depends on !EVA
1656 depends on !PAGE_SIZE_4KB
1657 depends on SYS_SUPPORTS_HIGHMEM
1658 select XPA
1659 select HIGHMEM
1660 select ARCH_PHYS_ADDR_T_64BIT
1661 default n
1662 help
1663 Choose this option if you want to enable the Extended Physical
1664 Addressing (XPA) on your MIPS32 core (such as P5600 series). The
1665 benefit is to increase physical addressing equal to or greater
1666 than 40 bits. Note that this has the side effect of turning on
1667 64-bit addressing which in turn makes the PTEs 64-bit in size.
1668 If unsure, say 'N' here.
1669
1599if CPU_LOONGSON2F 1670if CPU_LOONGSON2F
1600config CPU_NOP_WORKAROUNDS 1671config CPU_NOP_WORKAROUNDS
1601 bool 1672 bool
@@ -1699,6 +1770,9 @@ config SYS_HAS_CPU_MIPS32_R2
1699config SYS_HAS_CPU_MIPS32_R3_5 1770config SYS_HAS_CPU_MIPS32_R3_5
1700 bool 1771 bool
1701 1772
1773config SYS_HAS_CPU_MIPS32_R5
1774 bool
1775
1702config SYS_HAS_CPU_MIPS32_R6 1776config SYS_HAS_CPU_MIPS32_R6
1703 bool 1777 bool
1704 1778
@@ -1836,6 +1910,9 @@ config CPU_MIPSR6
1836config EVA 1910config EVA
1837 bool 1911 bool
1838 1912
1913config XPA
1914 bool
1915
1839config SYS_SUPPORTS_32BIT_KERNEL 1916config SYS_SUPPORTS_32BIT_KERNEL
1840 bool 1917 bool
1841config SYS_SUPPORTS_64BIT_KERNEL 1918config SYS_SUPPORTS_64BIT_KERNEL
@@ -2072,7 +2149,7 @@ config MIPSR2_TO_R6_EMULATOR
2072 help 2149 help
2073 Choose this option if you want to run non-R6 MIPS userland code. 2150 Choose this option if you want to run non-R6 MIPS userland code.
2074 Even if you say 'Y' here, the emulator will still be disabled by 2151 Even if you say 'Y' here, the emulator will still be disabled by
2075 default. You can enable it using the 'mipsr2emul' kernel option. 2152 default. You can enable it using the 'mipsr2emu' kernel option.
2076 The only reason this is a build-time option is to save ~14K from the 2153 The only reason this is a build-time option is to save ~14K from the
2077 final kernel image. 2154 final kernel image.
2078comment "MIPS R2-to-R6 emulator is only available for UP kernels" 2155comment "MIPS R2-to-R6 emulator is only available for UP kernels"
@@ -2142,7 +2219,7 @@ config MIPS_CMP
2142 2219
2143config MIPS_CPS 2220config MIPS_CPS
2144 bool "MIPS Coherent Processing System support" 2221 bool "MIPS Coherent Processing System support"
2145 depends on SYS_SUPPORTS_MIPS_CPS 2222 depends on SYS_SUPPORTS_MIPS_CPS && !64BIT
2146 select MIPS_CM 2223 select MIPS_CM
2147 select MIPS_CPC 2224 select MIPS_CPC
2148 select MIPS_CPS_PM if HOTPLUG_CPU 2225 select MIPS_CPS_PM if HOTPLUG_CPU
@@ -2348,7 +2425,7 @@ config NODES_SHIFT
2348 2425
2349config HW_PERF_EVENTS 2426config HW_PERF_EVENTS
2350 bool "Enable hardware performance counter support for perf events" 2427 bool "Enable hardware performance counter support for perf events"
2351 depends on PERF_EVENTS && OPROFILE=n && (CPU_MIPS32 || CPU_MIPS64 || CPU_R10000 || CPU_SB1 || CPU_CAVIUM_OCTEON || CPU_XLP) 2428 depends on PERF_EVENTS && OPROFILE=n && (CPU_MIPS32 || CPU_MIPS64 || CPU_R10000 || CPU_SB1 || CPU_CAVIUM_OCTEON || CPU_XLP || CPU_LOONGSON3)
2352 default y 2429 default y
2353 help 2430 help
2354 Enable hardware performance counter support for perf events. If 2431 Enable hardware performance counter support for perf events. If
@@ -2500,6 +2577,9 @@ config HZ
2500 default 1000 if HZ_1000 2577 default 1000 if HZ_1000
2501 default 1024 if HZ_1024 2578 default 1024 if HZ_1024
2502 2579
2580config SCHED_HRTICK
2581 def_bool HIGH_RES_TIMERS
2582
2503source "kernel/Kconfig.preempt" 2583source "kernel/Kconfig.preempt"
2504 2584
2505config KEXEC 2585config KEXEC
diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index d152dfbc360d..5200f649dd4e 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -197,11 +197,17 @@ endif
197# Warning: the 64-bit MIPS architecture does not support the `smartmips' extension 197# Warning: the 64-bit MIPS architecture does not support the `smartmips' extension
198# Pass -Wa,--no-warn to disable all assembler warnings until the kernel code has 198# Pass -Wa,--no-warn to disable all assembler warnings until the kernel code has
199# been fixed properly. 199# been fixed properly.
200mips-cflags := "$(cflags-y)" 200mips-cflags := $(cflags-y)
201cflags-$(CONFIG_CPU_HAS_SMARTMIPS) += $(call cc-option,$(mips-cflags),-msmartmips) -Wa,--no-warn 201ifeq ($(CONFIG_CPU_HAS_SMARTMIPS),y)
202cflags-$(CONFIG_CPU_MICROMIPS) += $(call cc-option,$(mips-cflags),-mmicromips) 202smartmips-ase := $(call cc-option-yn,$(mips-cflags) -msmartmips)
203cflags-$(smartmips-ase) += -msmartmips -Wa,--no-warn
204endif
205ifeq ($(CONFIG_CPU_MICROMIPS),y)
206micromips-ase := $(call cc-option-yn,$(mips-cflags) -mmicromips)
207cflags-$(micromips-ase) += -mmicromips
208endif
203ifeq ($(CONFIG_CPU_HAS_MSA),y) 209ifeq ($(CONFIG_CPU_HAS_MSA),y)
204toolchain-msa := $(call cc-option-yn,-$(mips-cflags),mhard-float -mfp64 -Wa$(comma)-mmsa) 210toolchain-msa := $(call cc-option-yn,$(mips-cflags) -mhard-float -mfp64 -Wa$(comma)-mmsa)
205cflags-$(toolchain-msa) += -DTOOLCHAIN_SUPPORTS_MSA 211cflags-$(toolchain-msa) += -DTOOLCHAIN_SUPPORTS_MSA
206endif 212endif
207 213
@@ -365,7 +371,11 @@ core-$(CONFIG_BUILTIN_DTB) += arch/mips/boot/dts/
365 371
366PHONY += dtbs 372PHONY += dtbs
367dtbs: scripts 373dtbs: scripts
368 $(Q)$(MAKE) $(build)=arch/mips/boot/dts dtbs 374 $(Q)$(MAKE) $(build)=arch/mips/boot/dts
375
376PHONY += dtbs_install
377dtbs_install:
378 $(Q)$(MAKE) $(dtbinst)=arch/mips/boot/dts
369 379
370archprepare: 380archprepare:
371ifdef CONFIG_MIPS32_N32 381ifdef CONFIG_MIPS32_N32
@@ -407,6 +417,7 @@ define archhelp
407 echo ' uImage.lzma - U-Boot image (lzma)' 417 echo ' uImage.lzma - U-Boot image (lzma)'
408 echo ' uImage.lzo - U-Boot image (lzo)' 418 echo ' uImage.lzo - U-Boot image (lzo)'
409 echo ' dtbs - Device-tree blobs for enabled boards' 419 echo ' dtbs - Device-tree blobs for enabled boards'
420 echo ' dtbs_install - Install dtbs to $(INSTALL_DTBS_PATH)'
410 echo 421 echo
411 echo ' These will be default as appropriate for a configured platform.' 422 echo ' These will be default as appropriate for a configured platform.'
412endef 423endef
diff --git a/arch/mips/ar7/platform.c b/arch/mips/ar7/platform.c
index af2441dbfc12..be9ff1673ded 100644
--- a/arch/mips/ar7/platform.c
+++ b/arch/mips/ar7/platform.c
@@ -307,10 +307,7 @@ static void __init cpmac_get_mac(int instance, unsigned char *dev_addr)
307 } 307 }
308 308
309 if (mac) { 309 if (mac) {
310 if (sscanf(mac, "%hhx:%hhx:%hhx:%hhx:%hhx:%hhx", 310 if (!mac_pton(mac, dev_addr)) {
311 &dev_addr[0], &dev_addr[1],
312 &dev_addr[2], &dev_addr[3],
313 &dev_addr[4], &dev_addr[5]) != 6) {
314 pr_warn("cannot parse mac address, using random address\n"); 311 pr_warn("cannot parse mac address, using random address\n");
315 eth_random_addr(dev_addr); 312 eth_random_addr(dev_addr);
316 } 313 }
diff --git a/arch/mips/ath79/common.h b/arch/mips/ath79/common.h
index a3120714f0b7..c39de61f9b36 100644
--- a/arch/mips/ath79/common.h
+++ b/arch/mips/ath79/common.h
@@ -17,7 +17,7 @@
17#include <linux/types.h> 17#include <linux/types.h>
18 18
19#define ATH79_MEM_SIZE_MIN (2 * 1024 * 1024) 19#define ATH79_MEM_SIZE_MIN (2 * 1024 * 1024)
20#define ATH79_MEM_SIZE_MAX (128 * 1024 * 1024) 20#define ATH79_MEM_SIZE_MAX (256 * 1024 * 1024)
21 21
22void ath79_clocks_init(void); 22void ath79_clocks_init(void);
23unsigned long ath79_get_sys_clk_rate(const char *id); 23unsigned long ath79_get_sys_clk_rate(const char *id);
diff --git a/arch/mips/bcm3384/Platform b/arch/mips/bcm3384/Platform
deleted file mode 100644
index 8e1ca0819e1b..000000000000
--- a/arch/mips/bcm3384/Platform
+++ /dev/null
@@ -1,7 +0,0 @@
1#
2# Broadcom BCM3384 boards
3#
4platform-$(CONFIG_BCM3384) += bcm3384/
5cflags-$(CONFIG_BCM3384) += \
6 -I$(srctree)/arch/mips/include/asm/mach-bcm3384/
7load-$(CONFIG_BCM3384) := 0xffffffff80010000
diff --git a/arch/mips/bcm3384/dma.c b/arch/mips/bcm3384/dma.c
deleted file mode 100644
index ea42012fd4f5..000000000000
--- a/arch/mips/bcm3384/dma.c
+++ /dev/null
@@ -1,81 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2014 Kevin Cernekee <cernekee@gmail.com>
7 */
8
9#include <linux/device.h>
10#include <linux/dma-direction.h>
11#include <linux/dma-mapping.h>
12#include <linux/init.h>
13#include <linux/mm.h>
14#include <linux/of.h>
15#include <linux/pci.h>
16#include <linux/types.h>
17#include <dma-coherence.h>
18
19/*
20 * BCM3384 has configurable address translation windows which allow the
21 * peripherals' DMA addresses to be different from the Zephyr-visible
22 * physical addresses. e.g. usb_dma_addr = zephyr_pa ^ 0x08000000
23 *
24 * If our DT "memory" node has a "dma-xor-mask" property we will enable this
25 * translation using the provided offset.
26 */
27static u32 bcm3384_dma_xor_mask;
28static u32 bcm3384_dma_xor_limit = 0xffffffff;
29
30/*
31 * PCI collapses the memory hole at 0x10000000 - 0x1fffffff.
32 * On systems with a dma-xor-mask, this range is guaranteed to live above
33 * the dma-xor-limit.
34 */
35#define BCM3384_MEM_HOLE_PA 0x10000000
36#define BCM3384_MEM_HOLE_SIZE 0x10000000
37
38static dma_addr_t bcm3384_phys_to_dma(struct device *dev, phys_addr_t pa)
39{
40 if (dev && dev_is_pci(dev) &&
41 pa >= (BCM3384_MEM_HOLE_PA + BCM3384_MEM_HOLE_SIZE))
42 return pa - BCM3384_MEM_HOLE_SIZE;
43 if (pa <= bcm3384_dma_xor_limit)
44 return pa ^ bcm3384_dma_xor_mask;
45 return pa;
46}
47
48dma_addr_t plat_map_dma_mem(struct device *dev, void *addr, size_t size)
49{
50 return bcm3384_phys_to_dma(dev, virt_to_phys(addr));
51}
52
53dma_addr_t plat_map_dma_mem_page(struct device *dev, struct page *page)
54{
55 return bcm3384_phys_to_dma(dev, page_to_phys(page));
56}
57
58unsigned long plat_dma_addr_to_phys(struct device *dev, dma_addr_t dma_addr)
59{
60 if (dev && dev_is_pci(dev) &&
61 dma_addr >= BCM3384_MEM_HOLE_PA)
62 return dma_addr + BCM3384_MEM_HOLE_SIZE;
63 if ((dma_addr ^ bcm3384_dma_xor_mask) <= bcm3384_dma_xor_limit)
64 return dma_addr ^ bcm3384_dma_xor_mask;
65 return dma_addr;
66}
67
68static int __init bcm3384_init_dma_xor(void)
69{
70 struct device_node *np = of_find_node_by_type(NULL, "memory");
71
72 if (!np)
73 return 0;
74
75 of_property_read_u32(np, "dma-xor-mask", &bcm3384_dma_xor_mask);
76 of_property_read_u32(np, "dma-xor-limit", &bcm3384_dma_xor_limit);
77
78 of_node_put(np);
79 return 0;
80}
81arch_initcall(bcm3384_init_dma_xor);
diff --git a/arch/mips/bcm3384/irq.c b/arch/mips/bcm3384/irq.c
deleted file mode 100644
index fd94fe849af6..000000000000
--- a/arch/mips/bcm3384/irq.c
+++ /dev/null
@@ -1,193 +0,0 @@
1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License version 2 as published
4 * by the Free Software Foundation.
5 *
6 * Partially based on arch/mips/ralink/irq.c
7 *
8 * Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>
9 * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
10 * Copyright (C) 2014 Kevin Cernekee <cernekee@gmail.com>
11 */
12
13#include <linux/io.h>
14#include <linux/bitops.h>
15#include <linux/of_platform.h>
16#include <linux/of_address.h>
17#include <linux/of_irq.h>
18#include <linux/irqdomain.h>
19#include <linux/interrupt.h>
20#include <linux/slab.h>
21#include <linux/spinlock.h>
22
23#include <asm/bmips.h>
24#include <asm/irq_cpu.h>
25#include <asm/mipsregs.h>
26
27/* INTC register offsets */
28#define INTC_REG_ENABLE 0x00
29#define INTC_REG_STATUS 0x04
30
31#define MAX_WORDS 2
32#define IRQS_PER_WORD 32
33
34struct bcm3384_intc {
35 int n_words;
36 void __iomem *reg[MAX_WORDS];
37 u32 enable[MAX_WORDS];
38 spinlock_t lock;
39};
40
41static void bcm3384_intc_irq_unmask(struct irq_data *d)
42{
43 struct bcm3384_intc *priv = d->domain->host_data;
44 unsigned long flags;
45 int idx = d->hwirq / IRQS_PER_WORD;
46 int bit = d->hwirq % IRQS_PER_WORD;
47
48 spin_lock_irqsave(&priv->lock, flags);
49 priv->enable[idx] |= BIT(bit);
50 __raw_writel(priv->enable[idx], priv->reg[idx] + INTC_REG_ENABLE);
51 spin_unlock_irqrestore(&priv->lock, flags);
52}
53
54static void bcm3384_intc_irq_mask(struct irq_data *d)
55{
56 struct bcm3384_intc *priv = d->domain->host_data;
57 unsigned long flags;
58 int idx = d->hwirq / IRQS_PER_WORD;
59 int bit = d->hwirq % IRQS_PER_WORD;
60
61 spin_lock_irqsave(&priv->lock, flags);
62 priv->enable[idx] &= ~BIT(bit);
63 __raw_writel(priv->enable[idx], priv->reg[idx] + INTC_REG_ENABLE);
64 spin_unlock_irqrestore(&priv->lock, flags);
65}
66
67static struct irq_chip bcm3384_intc_irq_chip = {
68 .name = "INTC",
69 .irq_unmask = bcm3384_intc_irq_unmask,
70 .irq_mask = bcm3384_intc_irq_mask,
71 .irq_mask_ack = bcm3384_intc_irq_mask,
72};
73
74unsigned int get_c0_compare_int(void)
75{
76 return CP0_LEGACY_COMPARE_IRQ;
77}
78
79static void bcm3384_intc_irq_handler(unsigned int irq, struct irq_desc *desc)
80{
81 struct irq_domain *domain = irq_get_handler_data(irq);
82 struct bcm3384_intc *priv = domain->host_data;
83 unsigned long flags;
84 unsigned int idx;
85
86 for (idx = 0; idx < priv->n_words; idx++) {
87 unsigned long pending;
88 int hwirq;
89
90 spin_lock_irqsave(&priv->lock, flags);
91 pending = __raw_readl(priv->reg[idx] + INTC_REG_STATUS) &
92 priv->enable[idx];
93 spin_unlock_irqrestore(&priv->lock, flags);
94
95 for_each_set_bit(hwirq, &pending, IRQS_PER_WORD) {
96 generic_handle_irq(irq_find_mapping(domain,
97 hwirq + idx * IRQS_PER_WORD));
98 }
99 }
100}
101
102asmlinkage void plat_irq_dispatch(void)
103{
104 unsigned long pending =
105 (read_c0_status() & read_c0_cause() & ST0_IM) >> STATUSB_IP0;
106 int bit;
107
108 for_each_set_bit(bit, &pending, 8)
109 do_IRQ(MIPS_CPU_IRQ_BASE + bit);
110}
111
112static int intc_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
113{
114 irq_set_chip_and_handler(irq, &bcm3384_intc_irq_chip, handle_level_irq);
115 return 0;
116}
117
118static const struct irq_domain_ops irq_domain_ops = {
119 .xlate = irq_domain_xlate_onecell,
120 .map = intc_map,
121};
122
123static int __init ioremap_one_pair(struct bcm3384_intc *priv,
124 struct device_node *node,
125 int idx)
126{
127 struct resource res;
128
129 if (of_address_to_resource(node, idx, &res))
130 return 0;
131
132 if (request_mem_region(res.start, resource_size(&res),
133 res.name) < 0)
134 pr_err("Failed to request INTC register region\n");
135
136 priv->reg[idx] = ioremap_nocache(res.start, resource_size(&res));
137 if (!priv->reg[idx])
138 panic("Failed to ioremap INTC register range");
139
140 /* start up with everything masked before we hook the parent IRQ */
141 __raw_writel(0, priv->reg[idx] + INTC_REG_ENABLE);
142 priv->enable[idx] = 0;
143
144 return IRQS_PER_WORD;
145}
146
147static int __init intc_of_init(struct device_node *node,
148 struct device_node *parent)
149{
150 struct irq_domain *domain;
151 unsigned int parent_irq, n_irqs = 0;
152 struct bcm3384_intc *priv;
153
154 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
155 if (!priv)
156 panic("Failed to allocate bcm3384_intc struct");
157
158 spin_lock_init(&priv->lock);
159
160 parent_irq = irq_of_parse_and_map(node, 0);
161 if (!parent_irq)
162 panic("Failed to get INTC IRQ");
163
164 n_irqs += ioremap_one_pair(priv, node, 0);
165 n_irqs += ioremap_one_pair(priv, node, 1);
166
167 if (!n_irqs)
168 panic("Failed to map INTC registers");
169
170 priv->n_words = n_irqs / IRQS_PER_WORD;
171 domain = irq_domain_add_linear(node, n_irqs, &irq_domain_ops, priv);
172 if (!domain)
173 panic("Failed to add irqdomain");
174
175 irq_set_chained_handler(parent_irq, bcm3384_intc_irq_handler);
176 irq_set_handler_data(parent_irq, domain);
177
178 return 0;
179}
180
181static struct of_device_id of_irq_ids[] __initdata = {
182 { .compatible = "mti,cpu-interrupt-controller",
183 .data = mips_cpu_irq_of_init },
184 { .compatible = "brcm,bcm3384-intc",
185 .data = intc_of_init },
186 {},
187};
188
189void __init arch_init_irq(void)
190{
191 bmips_tp1_irqs = 0;
192 of_irq_init(of_irq_ids);
193}
diff --git a/arch/mips/bcm3384/setup.c b/arch/mips/bcm3384/setup.c
deleted file mode 100644
index d84b8400b874..000000000000
--- a/arch/mips/bcm3384/setup.c
+++ /dev/null
@@ -1,97 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
7 * Copyright (C) 2014 Kevin Cernekee <cernekee@gmail.com>
8 */
9
10#include <linux/init.h>
11#include <linux/bootmem.h>
12#include <linux/clk-provider.h>
13#include <linux/ioport.h>
14#include <linux/of.h>
15#include <linux/of_fdt.h>
16#include <linux/of_platform.h>
17#include <linux/smp.h>
18#include <asm/addrspace.h>
19#include <asm/bmips.h>
20#include <asm/bootinfo.h>
21#include <asm/prom.h>
22#include <asm/smp-ops.h>
23#include <asm/time.h>
24
25void __init prom_init(void)
26{
27 register_bmips_smp_ops();
28}
29
30void __init prom_free_prom_memory(void)
31{
32}
33
34const char *get_system_type(void)
35{
36 return "BCM3384";
37}
38
39void __init plat_time_init(void)
40{
41 struct device_node *np;
42 u32 freq;
43
44 np = of_find_node_by_name(NULL, "cpus");
45 if (!np)
46 panic("missing 'cpus' DT node");
47 if (of_property_read_u32(np, "mips-hpt-frequency", &freq) < 0)
48 panic("missing 'mips-hpt-frequency' property");
49 of_node_put(np);
50
51 mips_hpt_frequency = freq;
52}
53
54void __init plat_mem_setup(void)
55{
56 void *dtb = __dtb_start;
57
58 set_io_port_base(0);
59 ioport_resource.start = 0;
60 ioport_resource.end = ~0;
61
62 /* intended to somewhat resemble ARM; see Documentation/arm/Booting */
63 if (fw_arg0 == 0 && fw_arg1 == 0xffffffff)
64 dtb = phys_to_virt(fw_arg2);
65
66 __dt_setup_arch(dtb);
67
68 strlcpy(arcs_cmdline, boot_command_line, COMMAND_LINE_SIZE);
69}
70
71void __init device_tree_init(void)
72{
73 struct device_node *np;
74
75 unflatten_and_copy_device_tree();
76
77 /* Disable SMP boot unless both CPUs are listed in DT and !disabled */
78 np = of_find_node_by_name(NULL, "cpus");
79 if (np && of_get_available_child_count(np) <= 1)
80 bmips_smp_enabled = 0;
81 of_node_put(np);
82}
83
84int __init plat_of_setup(void)
85{
86 return __dt_register_buses("brcm,bcm3384", "simple-bus");
87}
88
89arch_initcall(plat_of_setup);
90
91static int __init plat_dev_init(void)
92{
93 of_clk_init(NULL);
94 return 0;
95}
96
97device_initcall(plat_dev_init);
diff --git a/arch/mips/bcm47xx/bcm47xx_private.h b/arch/mips/bcm47xx/bcm47xx_private.h
index ea909a56a3ee..41796befa9df 100644
--- a/arch/mips/bcm47xx/bcm47xx_private.h
+++ b/arch/mips/bcm47xx/bcm47xx_private.h
@@ -1,6 +1,10 @@
1#ifndef LINUX_BCM47XX_PRIVATE_H_ 1#ifndef LINUX_BCM47XX_PRIVATE_H_
2#define LINUX_BCM47XX_PRIVATE_H_ 2#define LINUX_BCM47XX_PRIVATE_H_
3 3
4#ifndef pr_fmt
5#define pr_fmt(fmt) "bcm47xx: " fmt
6#endif
7
4#include <linux/kernel.h> 8#include <linux/kernel.h>
5 9
6/* prom.c */ 10/* prom.c */
diff --git a/arch/mips/bcm47xx/board.c b/arch/mips/bcm47xx/board.c
index b3ae068ca4fa..bd56415f2f3b 100644
--- a/arch/mips/bcm47xx/board.c
+++ b/arch/mips/bcm47xx/board.c
@@ -1,8 +1,8 @@
1#include <linux/errno.h> 1#include <linux/errno.h>
2#include <linux/export.h> 2#include <linux/export.h>
3#include <linux/string.h> 3#include <linux/string.h>
4#include <bcm47xx.h>
4#include <bcm47xx_board.h> 5#include <bcm47xx_board.h>
5#include <bcm47xx_nvram.h>
6 6
7struct bcm47xx_board_type { 7struct bcm47xx_board_type {
8 const enum bcm47xx_board board; 8 const enum bcm47xx_board board;
@@ -40,20 +40,6 @@ struct bcm47xx_board_type_list1 bcm47xx_board_list_model_name[] __initconst = {
40 { {0}, NULL}, 40 { {0}, NULL},
41}; 41};
42 42
43/* model_no */
44static const
45struct bcm47xx_board_type_list1 bcm47xx_board_list_model_no[] __initconst = {
46 {{BCM47XX_BOARD_ASUS_WL700GE, "Asus WL700"}, "WL700"},
47 { {0}, NULL},
48};
49
50/* machine_name */
51static const
52struct bcm47xx_board_type_list1 bcm47xx_board_list_machine_name[] __initconst = {
53 {{BCM47XX_BOARD_LINKSYS_WRTSL54GS, "Linksys WRTSL54GS"}, "WRTSL54GS"},
54 { {0}, NULL},
55};
56
57/* hardware_version */ 43/* hardware_version */
58static const 44static const
59struct bcm47xx_board_type_list1 bcm47xx_board_list_hardware_version[] __initconst = { 45struct bcm47xx_board_type_list1 bcm47xx_board_list_hardware_version[] __initconst = {
@@ -165,9 +151,11 @@ static const
165struct bcm47xx_board_type_list1 bcm47xx_board_list_board_id[] __initconst = { 151struct bcm47xx_board_type_list1 bcm47xx_board_list_board_id[] __initconst = {
166 {{BCM47XX_BOARD_NETGEAR_WGR614V8, "Netgear WGR614 V8"}, "U12H072T00_NETGEAR"}, 152 {{BCM47XX_BOARD_NETGEAR_WGR614V8, "Netgear WGR614 V8"}, "U12H072T00_NETGEAR"},
167 {{BCM47XX_BOARD_NETGEAR_WGR614V9, "Netgear WGR614 V9"}, "U12H094T00_NETGEAR"}, 153 {{BCM47XX_BOARD_NETGEAR_WGR614V9, "Netgear WGR614 V9"}, "U12H094T00_NETGEAR"},
154 {{BCM47XX_BOARD_NETGEAR_WGR614_V10, "Netgear WGR614 V10"}, "U12H139T01_NETGEAR"},
168 {{BCM47XX_BOARD_NETGEAR_WNDR3300, "Netgear WNDR3300"}, "U12H093T00_NETGEAR"}, 155 {{BCM47XX_BOARD_NETGEAR_WNDR3300, "Netgear WNDR3300"}, "U12H093T00_NETGEAR"},
169 {{BCM47XX_BOARD_NETGEAR_WNDR3400V1, "Netgear WNDR3400 V1"}, "U12H155T00_NETGEAR"}, 156 {{BCM47XX_BOARD_NETGEAR_WNDR3400V1, "Netgear WNDR3400 V1"}, "U12H155T00_NETGEAR"},
170 {{BCM47XX_BOARD_NETGEAR_WNDR3400V2, "Netgear WNDR3400 V2"}, "U12H187T00_NETGEAR"}, 157 {{BCM47XX_BOARD_NETGEAR_WNDR3400V2, "Netgear WNDR3400 V2"}, "U12H187T00_NETGEAR"},
158 {{BCM47XX_BOARD_NETGEAR_WNDR3400_V3, "Netgear WNDR3400 V3"}, "U12H208T00_NETGEAR"},
171 {{BCM47XX_BOARD_NETGEAR_WNDR3400VCNA, "Netgear WNDR3400 Vcna"}, "U12H155T01_NETGEAR"}, 159 {{BCM47XX_BOARD_NETGEAR_WNDR3400VCNA, "Netgear WNDR3400 Vcna"}, "U12H155T01_NETGEAR"},
172 {{BCM47XX_BOARD_NETGEAR_WNDR3700V3, "Netgear WNDR3700 V3"}, "U12H194T00_NETGEAR"}, 160 {{BCM47XX_BOARD_NETGEAR_WNDR3700V3, "Netgear WNDR3700 V3"}, "U12H194T00_NETGEAR"},
173 {{BCM47XX_BOARD_NETGEAR_WNDR4000, "Netgear WNDR4000"}, "U12H181T00_NETGEAR"}, 161 {{BCM47XX_BOARD_NETGEAR_WNDR4000, "Netgear WNDR4000"}, "U12H181T00_NETGEAR"},
@@ -202,6 +190,20 @@ struct bcm47xx_board_type_list2 bcm47xx_board_list_board_type_rev[] __initconst
202 { {0}, NULL}, 190 { {0}, NULL},
203}; 191};
204 192
193/*
194 * Some devices don't use any common NVRAM entry for identification and they
195 * have only one model specific variable.
196 * They don't deserve own arrays, let's group them there using key-value array.
197 */
198static const
199struct bcm47xx_board_type_list2 bcm47xx_board_list_key_value[] __initconst = {
200 {{BCM47XX_BOARD_ASUS_WL700GE, "Asus WL700"}, "model_no", "WL700"},
201 {{BCM47XX_BOARD_LINKSYS_WRT300N_V1, "Linksys WRT300N V1"}, "router_name", "WRT300N"},
202 {{BCM47XX_BOARD_LINKSYS_WRT600N_V11, "Linksys WRT600N V1.1"}, "Model_Name", "WRT600N"},
203 {{BCM47XX_BOARD_LINKSYS_WRTSL54GS, "Linksys WRTSL54GS"}, "machine_name", "WRTSL54GS"},
204 { {0}, NULL},
205};
206
205static const 207static const
206struct bcm47xx_board_type bcm47xx_board_unknown[] __initconst = { 208struct bcm47xx_board_type bcm47xx_board_unknown[] __initconst = {
207 {BCM47XX_BOARD_UNKNOWN, "Unknown Board"}, 209 {BCM47XX_BOARD_UNKNOWN, "Unknown Board"},
@@ -225,20 +227,6 @@ static __init const struct bcm47xx_board_type *bcm47xx_board_get_nvram(void)
225 } 227 }
226 } 228 }
227 229
228 if (bcm47xx_nvram_getenv("model_no", buf1, sizeof(buf1)) >= 0) {
229 for (e1 = bcm47xx_board_list_model_no; e1->value1; e1++) {
230 if (strstarts(buf1, e1->value1))
231 return &e1->board;
232 }
233 }
234
235 if (bcm47xx_nvram_getenv("machine_name", buf1, sizeof(buf1)) >= 0) {
236 for (e1 = bcm47xx_board_list_machine_name; e1->value1; e1++) {
237 if (strstarts(buf1, e1->value1))
238 return &e1->board;
239 }
240 }
241
242 if (bcm47xx_nvram_getenv("hardware_version", buf1, sizeof(buf1)) >= 0) { 230 if (bcm47xx_nvram_getenv("hardware_version", buf1, sizeof(buf1)) >= 0) {
243 for (e1 = bcm47xx_board_list_hardware_version; e1->value1; e1++) { 231 for (e1 = bcm47xx_board_list_hardware_version; e1->value1; e1++) {
244 if (strstarts(buf1, e1->value1)) 232 if (strstarts(buf1, e1->value1))
@@ -247,8 +235,8 @@ static __init const struct bcm47xx_board_type *bcm47xx_board_get_nvram(void)
247 } 235 }
248 236
249 if (bcm47xx_nvram_getenv("hardware_version", buf1, sizeof(buf1)) >= 0 && 237 if (bcm47xx_nvram_getenv("hardware_version", buf1, sizeof(buf1)) >= 0 &&
250 bcm47xx_nvram_getenv("boardtype", buf2, sizeof(buf2)) >= 0) { 238 bcm47xx_nvram_getenv("boardnum", buf2, sizeof(buf2)) >= 0) {
251 for (e2 = bcm47xx_board_list_boot_hw; e2->value1; e2++) { 239 for (e2 = bcm47xx_board_list_hw_version_num; e2->value1; e2++) {
252 if (!strstarts(buf1, e2->value1) && 240 if (!strstarts(buf1, e2->value1) &&
253 !strcmp(buf2, e2->value2)) 241 !strcmp(buf2, e2->value2))
254 return &e2->board; 242 return &e2->board;
@@ -314,6 +302,14 @@ static __init const struct bcm47xx_board_type *bcm47xx_board_get_nvram(void)
314 return &e2->board; 302 return &e2->board;
315 } 303 }
316 } 304 }
305
306 for (e2 = bcm47xx_board_list_key_value; e2->value1; e2++) {
307 if (bcm47xx_nvram_getenv(e2->value1, buf1, sizeof(buf1)) >= 0) {
308 if (!strcmp(buf1, e2->value2))
309 return &e2->board;
310 }
311 }
312
317 return bcm47xx_board_unknown; 313 return bcm47xx_board_unknown;
318} 314}
319 315
@@ -330,9 +326,8 @@ void __init bcm47xx_board_detect(void)
330 err = bcm47xx_nvram_getenv("boardtype", buf, sizeof(buf)); 326 err = bcm47xx_nvram_getenv("boardtype", buf, sizeof(buf));
331 327
332 /* init of nvram failed, probably too early now */ 328 /* init of nvram failed, probably too early now */
333 if (err == -ENXIO) { 329 if (err == -ENXIO)
334 return; 330 return;
335 }
336 331
337 board_detected = bcm47xx_board_get_nvram(); 332 board_detected = bcm47xx_board_get_nvram();
338 bcm47xx_board.board = board_detected->board; 333 bcm47xx_board.board = board_detected->board;
diff --git a/arch/mips/bcm47xx/buttons.c b/arch/mips/bcm47xx/buttons.c
index 913182bcafb8..276276a8c6d7 100644
--- a/arch/mips/bcm47xx/buttons.c
+++ b/arch/mips/bcm47xx/buttons.c
@@ -252,6 +252,12 @@ bcm47xx_buttons_linksys_wrt160nv3[] __initconst = {
252}; 252};
253 253
254static const struct gpio_keys_button 254static const struct gpio_keys_button
255bcm47xx_buttons_linksys_wrt300n_v1[] __initconst = {
256 BCM47XX_GPIO_KEY(4, KEY_WPS_BUTTON),
257 BCM47XX_GPIO_KEY(6, KEY_RESTART),
258};
259
260static const struct gpio_keys_button
255bcm47xx_buttons_linksys_wrt300nv11[] __initconst = { 261bcm47xx_buttons_linksys_wrt300nv11[] __initconst = {
256 BCM47XX_GPIO_KEY(4, KEY_UNKNOWN), 262 BCM47XX_GPIO_KEY(4, KEY_UNKNOWN),
257 BCM47XX_GPIO_KEY(6, KEY_RESTART), 263 BCM47XX_GPIO_KEY(6, KEY_RESTART),
@@ -327,6 +333,12 @@ bcm47xx_buttons_netgear_wndr3400v1[] __initconst = {
327}; 333};
328 334
329static const struct gpio_keys_button 335static const struct gpio_keys_button
336bcm47xx_buttons_netgear_wndr3400_v3[] __initconst = {
337 BCM47XX_GPIO_KEY(12, KEY_RESTART),
338 BCM47XX_GPIO_KEY(23, KEY_WPS_BUTTON),
339};
340
341static const struct gpio_keys_button
330bcm47xx_buttons_netgear_wndr3700v3[] __initconst = { 342bcm47xx_buttons_netgear_wndr3700v3[] __initconst = {
331 BCM47XX_GPIO_KEY(2, KEY_RFKILL), 343 BCM47XX_GPIO_KEY(2, KEY_RFKILL),
332 BCM47XX_GPIO_KEY(3, KEY_RESTART), 344 BCM47XX_GPIO_KEY(3, KEY_RESTART),
@@ -516,6 +528,9 @@ int __init bcm47xx_buttons_register(void)
516 case BCM47XX_BOARD_LINKSYS_WRT160NV3: 528 case BCM47XX_BOARD_LINKSYS_WRT160NV3:
517 err = bcm47xx_copy_bdata(bcm47xx_buttons_linksys_wrt160nv3); 529 err = bcm47xx_copy_bdata(bcm47xx_buttons_linksys_wrt160nv3);
518 break; 530 break;
531 case BCM47XX_BOARD_LINKSYS_WRT300N_V1:
532 err = bcm47xx_copy_bdata(bcm47xx_buttons_linksys_wrt300n_v1);
533 break;
519 case BCM47XX_BOARD_LINKSYS_WRT300NV11: 534 case BCM47XX_BOARD_LINKSYS_WRT300NV11:
520 err = bcm47xx_copy_bdata(bcm47xx_buttons_linksys_wrt300nv11); 535 err = bcm47xx_copy_bdata(bcm47xx_buttons_linksys_wrt300nv11);
521 break; 536 break;
@@ -557,6 +572,9 @@ int __init bcm47xx_buttons_register(void)
557 case BCM47XX_BOARD_NETGEAR_WNDR3400V1: 572 case BCM47XX_BOARD_NETGEAR_WNDR3400V1:
558 err = bcm47xx_copy_bdata(bcm47xx_buttons_netgear_wndr3400v1); 573 err = bcm47xx_copy_bdata(bcm47xx_buttons_netgear_wndr3400v1);
559 break; 574 break;
575 case BCM47XX_BOARD_NETGEAR_WNDR3400_V3:
576 err = bcm47xx_copy_bdata(bcm47xx_buttons_netgear_wndr3400_v3);
577 break;
560 case BCM47XX_BOARD_NETGEAR_WNDR3700V3: 578 case BCM47XX_BOARD_NETGEAR_WNDR3700V3:
561 err = bcm47xx_copy_bdata(bcm47xx_buttons_netgear_wndr3700v3); 579 err = bcm47xx_copy_bdata(bcm47xx_buttons_netgear_wndr3700v3);
562 break; 580 break;
diff --git a/arch/mips/bcm47xx/leds.c b/arch/mips/bcm47xx/leds.c
index 903a656d4119..0e4ade342333 100644
--- a/arch/mips/bcm47xx/leds.c
+++ b/arch/mips/bcm47xx/leds.c
@@ -292,6 +292,13 @@ bcm47xx_leds_linksys_wrt160nv3[] __initconst = {
292}; 292};
293 293
294static const struct gpio_led 294static const struct gpio_led
295bcm47xx_leds_linksys_wrt300n_v1[] __initconst = {
296 BCM47XX_GPIO_LED(1, "green", "power", 0, LEDS_GPIO_DEFSTATE_ON),
297 BCM47XX_GPIO_LED(3, "amber", "wps", 1, LEDS_GPIO_DEFSTATE_OFF),
298 BCM47XX_GPIO_LED(5, "green", "wps", 1, LEDS_GPIO_DEFSTATE_OFF),
299};
300
301static const struct gpio_led
295bcm47xx_leds_linksys_wrt300nv11[] __initconst = { 302bcm47xx_leds_linksys_wrt300nv11[] __initconst = {
296 BCM47XX_GPIO_LED(1, "unk", "power", 0, LEDS_GPIO_DEFSTATE_ON), 303 BCM47XX_GPIO_LED(1, "unk", "power", 0, LEDS_GPIO_DEFSTATE_ON),
297 BCM47XX_GPIO_LED(3, "amber", "wps", 1, LEDS_GPIO_DEFSTATE_OFF), 304 BCM47XX_GPIO_LED(3, "amber", "wps", 1, LEDS_GPIO_DEFSTATE_OFF),
@@ -585,6 +592,9 @@ void __init bcm47xx_leds_register(void)
585 case BCM47XX_BOARD_LINKSYS_WRT160NV3: 592 case BCM47XX_BOARD_LINKSYS_WRT160NV3:
586 bcm47xx_set_pdata(bcm47xx_leds_linksys_wrt160nv3); 593 bcm47xx_set_pdata(bcm47xx_leds_linksys_wrt160nv3);
587 break; 594 break;
595 case BCM47XX_BOARD_LINKSYS_WRT300N_V1:
596 bcm47xx_set_pdata(bcm47xx_leds_linksys_wrt300n_v1);
597 break;
588 case BCM47XX_BOARD_LINKSYS_WRT300NV11: 598 case BCM47XX_BOARD_LINKSYS_WRT300NV11:
589 bcm47xx_set_pdata(bcm47xx_leds_linksys_wrt300nv11); 599 bcm47xx_set_pdata(bcm47xx_leds_linksys_wrt300nv11);
590 break; 600 break;
diff --git a/arch/mips/bcm47xx/nvram.c b/arch/mips/bcm47xx/nvram.c
index c5c381c43f17..ba632ff08a13 100644
--- a/arch/mips/bcm47xx/nvram.c
+++ b/arch/mips/bcm47xx/nvram.c
@@ -11,15 +11,18 @@
11 * option) any later version. 11 * option) any later version.
12 */ 12 */
13 13
14#include <linux/io.h>
14#include <linux/types.h> 15#include <linux/types.h>
15#include <linux/module.h> 16#include <linux/module.h>
16#include <linux/kernel.h> 17#include <linux/kernel.h>
17#include <linux/string.h> 18#include <linux/string.h>
18#include <linux/mtd/mtd.h> 19#include <linux/mtd/mtd.h>
19#include <bcm47xx_nvram.h> 20#include <linux/bcm47xx_nvram.h>
20 21
21#define NVRAM_MAGIC 0x48534C46 /* 'FLSH' */ 22#define NVRAM_MAGIC 0x48534C46 /* 'FLSH' */
22#define NVRAM_SPACE 0x8000 23#define NVRAM_SPACE 0x10000
24#define NVRAM_MAX_GPIO_ENTRIES 32
25#define NVRAM_MAX_GPIO_VALUE_LEN 30
23 26
24#define FLASH_MIN 0x00020000 /* Minimum flash size */ 27#define FLASH_MIN 0x00020000 /* Minimum flash size */
25 28
@@ -91,20 +94,18 @@ static int nvram_find_and_copy(void __iomem *iobase, u32 lim)
91 return -ENXIO; 94 return -ENXIO;
92 95
93found: 96found:
94
95 if (header->len > size) 97 if (header->len > size)
96 pr_err("The nvram size accoridng to the header seems to be bigger than the partition on flash\n"); 98 pr_err("The nvram size accoridng to the header seems to be bigger than the partition on flash\n");
97 if (header->len > NVRAM_SPACE) 99 if (header->len > NVRAM_SPACE)
98 pr_err("nvram on flash (%i bytes) is bigger than the reserved space in memory, will just copy the first %i bytes\n", 100 pr_err("nvram on flash (%i bytes) is bigger than the reserved space in memory, will just copy the first %i bytes\n",
99 header->len, NVRAM_SPACE); 101 header->len, NVRAM_SPACE);
100 102
101 src = (u32 *) header; 103 src = (u32 *)header;
102 dst = (u32 *) nvram_buf; 104 dst = (u32 *)nvram_buf;
103 for (i = 0; i < sizeof(struct nvram_header); i += 4) 105 for (i = 0; i < sizeof(struct nvram_header); i += 4)
104 *dst++ = *src++; 106 *dst++ = __raw_readl(src++);
105 for (; i < header->len && i < NVRAM_SPACE && i < size; i += 4) 107 for (; i < header->len && i < NVRAM_SPACE && i < size; i += 4)
106 *dst++ = le32_to_cpu(*src++); 108 *dst++ = readl(src++);
107 memset(dst, 0x0, NVRAM_SPACE - i);
108 109
109 return 0; 110 return 0;
110} 111}
@@ -138,37 +139,28 @@ static int nvram_init(void)
138 struct mtd_info *mtd; 139 struct mtd_info *mtd;
139 struct nvram_header header; 140 struct nvram_header header;
140 size_t bytes_read; 141 size_t bytes_read;
141 int err, i; 142 int err;
142 143
143 mtd = get_mtd_device_nm("nvram"); 144 mtd = get_mtd_device_nm("nvram");
144 if (IS_ERR(mtd)) 145 if (IS_ERR(mtd))
145 return -ENODEV; 146 return -ENODEV;
146 147
147 for (i = 0; i < ARRAY_SIZE(nvram_sizes); i++) { 148 err = mtd_read(mtd, 0, sizeof(header), &bytes_read, (uint8_t *)&header);
148 loff_t from = mtd->size - nvram_sizes[i]; 149 if (!err && header.magic == NVRAM_MAGIC) {
150 u8 *dst = (uint8_t *)nvram_buf;
151 size_t len = header.len;
149 152
150 if (from < 0) 153 if (header.len > NVRAM_SPACE) {
151 continue; 154 pr_err("nvram on flash (%i bytes) is bigger than the reserved space in memory, will just copy the first %i bytes\n",
152 155 header.len, NVRAM_SPACE);
153 err = mtd_read(mtd, from, sizeof(header), &bytes_read, 156 len = NVRAM_SPACE;
154 (uint8_t *)&header); 157 }
155 if (!err && header.magic == NVRAM_MAGIC) {
156 u8 *dst = (uint8_t *)nvram_buf;
157 size_t len = header.len;
158
159 if (header.len > NVRAM_SPACE) {
160 pr_err("nvram on flash (%i bytes) is bigger than the reserved space in memory, will just copy the first %i bytes\n",
161 header.len, NVRAM_SPACE);
162 len = NVRAM_SPACE;
163 }
164 158
165 err = mtd_read(mtd, from, len, &bytes_read, dst); 159 err = mtd_read(mtd, 0, len, &bytes_read, dst);
166 if (err) 160 if (err)
167 return err; 161 return err;
168 memset(dst + bytes_read, 0x0, NVRAM_SPACE - bytes_read);
169 162
170 return 0; 163 return 0;
171 }
172 } 164 }
173#endif 165#endif
174 166
@@ -178,7 +170,7 @@ static int nvram_init(void)
178int bcm47xx_nvram_getenv(const char *name, char *val, size_t val_len) 170int bcm47xx_nvram_getenv(const char *name, char *val, size_t val_len)
179{ 171{
180 char *var, *value, *end, *eq; 172 char *var, *value, *end, *eq;
181 int err; 173 int data_left, err;
182 174
183 if (!name) 175 if (!name)
184 return -EINVAL; 176 return -EINVAL;
@@ -192,16 +184,18 @@ int bcm47xx_nvram_getenv(const char *name, char *val, size_t val_len)
192 /* Look for name=value and return value */ 184 /* Look for name=value and return value */
193 var = &nvram_buf[sizeof(struct nvram_header)]; 185 var = &nvram_buf[sizeof(struct nvram_header)];
194 end = nvram_buf + sizeof(nvram_buf) - 2; 186 end = nvram_buf + sizeof(nvram_buf) - 2;
195 end[0] = end[1] = '\0'; 187 end[0] = '\0';
188 end[1] = '\0';
196 for (; *var; var = value + strlen(value) + 1) { 189 for (; *var; var = value + strlen(value) + 1) {
197 eq = strchr(var, '='); 190 data_left = end - var;
191
192 eq = strnchr(var, data_left, '=');
198 if (!eq) 193 if (!eq)
199 break; 194 break;
200 value = eq + 1; 195 value = eq + 1;
201 if ((eq - var) == strlen(name) && 196 if (eq - var == strlen(name) &&
202 strncmp(var, name, (eq - var)) == 0) { 197 strncmp(var, name, eq - var) == 0)
203 return snprintf(val, val_len, "%s", value); 198 return snprintf(val, val_len, "%s", value);
204 }
205 } 199 }
206 return -ENOENT; 200 return -ENOENT;
207} 201}
@@ -210,10 +204,11 @@ EXPORT_SYMBOL(bcm47xx_nvram_getenv);
210int bcm47xx_nvram_gpio_pin(const char *name) 204int bcm47xx_nvram_gpio_pin(const char *name)
211{ 205{
212 int i, err; 206 int i, err;
213 char nvram_var[10]; 207 char nvram_var[] = "gpioXX";
214 char buf[30]; 208 char buf[NVRAM_MAX_GPIO_VALUE_LEN];
215 209
216 for (i = 0; i < 32; i++) { 210 /* TODO: Optimize it to don't call getenv so many times */
211 for (i = 0; i < NVRAM_MAX_GPIO_ENTRIES; i++) {
217 err = snprintf(nvram_var, sizeof(nvram_var), "gpio%i", i); 212 err = snprintf(nvram_var, sizeof(nvram_var), "gpio%i", i);
218 if (err <= 0) 213 if (err <= 0)
219 continue; 214 continue;
diff --git a/arch/mips/bcm47xx/prom.c b/arch/mips/bcm47xx/prom.c
index 1b170bf5f7f0..ab698bad6d62 100644
--- a/arch/mips/bcm47xx/prom.c
+++ b/arch/mips/bcm47xx/prom.c
@@ -35,7 +35,6 @@
35#include <bcm47xx.h> 35#include <bcm47xx.h>
36#include <bcm47xx_board.h> 36#include <bcm47xx_board.h>
37 37
38
39static char bcm47xx_system_type[20] = "Broadcom BCM47XX"; 38static char bcm47xx_system_type[20] = "Broadcom BCM47XX";
40 39
41const char *get_system_type(void) 40const char *get_system_type(void)
@@ -83,7 +82,7 @@ static __init void prom_init_mem(void)
83 /* Loop condition may be not enough, off may be over 1 MiB */ 82 /* Loop condition may be not enough, off may be over 1 MiB */
84 if (off + mem >= max) { 83 if (off + mem >= max) {
85 mem = max; 84 mem = max;
86 printk(KERN_DEBUG "assume 128MB RAM\n"); 85 pr_debug("Assume 128MB RAM\n");
87 break; 86 break;
88 } 87 }
89 if (!memcmp(prom_init, prom_init + mem, 32)) 88 if (!memcmp(prom_init, prom_init + mem, 32))
diff --git a/arch/mips/bcm47xx/serial.c b/arch/mips/bcm47xx/serial.c
index 2f5bbd68e9a0..df761d38f7fc 100644
--- a/arch/mips/bcm47xx/serial.c
+++ b/arch/mips/bcm47xx/serial.c
@@ -36,8 +36,8 @@ static int __init uart8250_init_ssb(void)
36 struct plat_serial8250_port *p = &(uart8250_data[i]); 36 struct plat_serial8250_port *p = &(uart8250_data[i]);
37 struct ssb_serial_port *ssb_port = &(mcore->serial_ports[i]); 37 struct ssb_serial_port *ssb_port = &(mcore->serial_ports[i]);
38 38
39 p->mapbase = (unsigned int) ssb_port->regs; 39 p->mapbase = (unsigned int)ssb_port->regs;
40 p->membase = (void *) ssb_port->regs; 40 p->membase = (void *)ssb_port->regs;
41 p->irq = ssb_port->irq + 2; 41 p->irq = ssb_port->irq + 2;
42 p->uartclk = ssb_port->baud_base; 42 p->uartclk = ssb_port->baud_base;
43 p->regshift = ssb_port->reg_shift; 43 p->regshift = ssb_port->reg_shift;
@@ -62,8 +62,8 @@ static int __init uart8250_init_bcma(void)
62 struct bcma_serial_port *bcma_port; 62 struct bcma_serial_port *bcma_port;
63 bcma_port = &(cc->serial_ports[i]); 63 bcma_port = &(cc->serial_ports[i]);
64 64
65 p->mapbase = (unsigned int) bcma_port->regs; 65 p->mapbase = (unsigned int)bcma_port->regs;
66 p->membase = (void *) bcma_port->regs; 66 p->membase = (void *)bcma_port->regs;
67 p->irq = bcma_port->irq; 67 p->irq = bcma_port->irq;
68 p->uartclk = bcma_port->baud_base; 68 p->uartclk = bcma_port->baud_base;
69 p->regshift = bcma_port->reg_shift; 69 p->regshift = bcma_port->reg_shift;
diff --git a/arch/mips/bcm47xx/setup.c b/arch/mips/bcm47xx/setup.c
index e43b5046cb30..82ff9fd2ab6e 100644
--- a/arch/mips/bcm47xx/setup.c
+++ b/arch/mips/bcm47xx/setup.c
@@ -42,7 +42,6 @@
42#include <asm/reboot.h> 42#include <asm/reboot.h>
43#include <asm/time.h> 43#include <asm/time.h>
44#include <bcm47xx.h> 44#include <bcm47xx.h>
45#include <bcm47xx_nvram.h>
46#include <bcm47xx_board.h> 45#include <bcm47xx_board.h>
47 46
48union bcm47xx_bus bcm47xx_bus; 47union bcm47xx_bus bcm47xx_bus;
@@ -53,7 +52,7 @@ EXPORT_SYMBOL(bcm47xx_bus_type);
53 52
54static void bcm47xx_machine_restart(char *command) 53static void bcm47xx_machine_restart(char *command)
55{ 54{
56 printk(KERN_ALERT "Please stand by while rebooting the system...\n"); 55 pr_alert("Please stand by while rebooting the system...\n");
57 local_irq_disable(); 56 local_irq_disable();
58 /* Set the watchdog timer to reset immediately */ 57 /* Set the watchdog timer to reset immediately */
59 switch (bcm47xx_bus_type) { 58 switch (bcm47xx_bus_type) {
@@ -108,7 +107,7 @@ static int bcm47xx_get_invariants(struct ssb_bus *bus,
108 char buf[20]; 107 char buf[20];
109 108
110 /* Fill boardinfo structure */ 109 /* Fill boardinfo structure */
111 memset(&(iv->boardinfo), 0 , sizeof(struct ssb_boardinfo)); 110 memset(&iv->boardinfo, 0 , sizeof(struct ssb_boardinfo));
112 111
113 bcm47xx_fill_ssb_boardinfo(&iv->boardinfo, NULL); 112 bcm47xx_fill_ssb_boardinfo(&iv->boardinfo, NULL);
114 113
@@ -127,7 +126,7 @@ static void __init bcm47xx_register_ssb(void)
127 char buf[100]; 126 char buf[100];
128 struct ssb_mipscore *mcore; 127 struct ssb_mipscore *mcore;
129 128
130 err = ssb_bus_ssbbus_register(&(bcm47xx_bus.ssb), SSB_ENUM_BASE, 129 err = ssb_bus_ssbbus_register(&bcm47xx_bus.ssb, SSB_ENUM_BASE,
131 bcm47xx_get_invariants); 130 bcm47xx_get_invariants);
132 if (err) 131 if (err)
133 panic("Failed to initialize SSB bus (err %d)", err); 132 panic("Failed to initialize SSB bus (err %d)", err);
@@ -137,7 +136,7 @@ static void __init bcm47xx_register_ssb(void)
137 if (strstr(buf, "console=ttyS1")) { 136 if (strstr(buf, "console=ttyS1")) {
138 struct ssb_serial_port port; 137 struct ssb_serial_port port;
139 138
140 printk(KERN_DEBUG "Swapping serial ports!\n"); 139 pr_debug("Swapping serial ports!\n");
141 /* swap serial ports */ 140 /* swap serial ports */
142 memcpy(&port, &mcore->serial_ports[0], sizeof(port)); 141 memcpy(&port, &mcore->serial_ports[0], sizeof(port));
143 memcpy(&mcore->serial_ports[0], &mcore->serial_ports[1], 142 memcpy(&mcore->serial_ports[0], &mcore->serial_ports[1],
@@ -169,7 +168,7 @@ void __init plat_mem_setup(void)
169 struct cpuinfo_mips *c = &current_cpu_data; 168 struct cpuinfo_mips *c = &current_cpu_data;
170 169
171 if ((c->cputype == CPU_74K) || (c->cputype == CPU_1074K)) { 170 if ((c->cputype == CPU_74K) || (c->cputype == CPU_1074K)) {
172 printk(KERN_INFO "bcm47xx: using bcma bus\n"); 171 pr_info("Using bcma bus\n");
173#ifdef CONFIG_BCM47XX_BCMA 172#ifdef CONFIG_BCM47XX_BCMA
174 bcm47xx_bus_type = BCM47XX_BUS_TYPE_BCMA; 173 bcm47xx_bus_type = BCM47XX_BUS_TYPE_BCMA;
175 bcm47xx_sprom_register_fallbacks(); 174 bcm47xx_sprom_register_fallbacks();
@@ -180,7 +179,7 @@ void __init plat_mem_setup(void)
180#endif 179#endif
181#endif 180#endif
182 } else { 181 } else {
183 printk(KERN_INFO "bcm47xx: using ssb bus\n"); 182 pr_info("Using ssb bus\n");
184#ifdef CONFIG_BCM47XX_SSB 183#ifdef CONFIG_BCM47XX_SSB
185 bcm47xx_bus_type = BCM47XX_BUS_TYPE_SSB; 184 bcm47xx_bus_type = BCM47XX_BUS_TYPE_SSB;
186 bcm47xx_sprom_register_fallbacks(); 185 bcm47xx_sprom_register_fallbacks();
diff --git a/arch/mips/bcm47xx/sprom.c b/arch/mips/bcm47xx/sprom.c
index 2eff7fe99c6b..68ebf2322f8b 100644
--- a/arch/mips/bcm47xx/sprom.c
+++ b/arch/mips/bcm47xx/sprom.c
@@ -27,7 +27,6 @@
27 */ 27 */
28 28
29#include <bcm47xx.h> 29#include <bcm47xx.h>
30#include <bcm47xx_nvram.h>
31#include <linux/if_ether.h> 30#include <linux/if_ether.h>
32#include <linux/etherdevice.h> 31#include <linux/etherdevice.h>
33 32
@@ -181,94 +180,245 @@ static void nvram_read_alpha2(const char *prefix, const char *name,
181 memcpy(val, buf, 2); 180 memcpy(val, buf, 2);
182} 181}
183 182
183/* This is one-function-only macro, it uses local "sprom" variable! */
184#define ENTRY(_revmask, _type, _prefix, _name, _val, _allset, _fallback) \
185 if (_revmask & BIT(sprom->revision)) \
186 nvram_read_ ## _type(_prefix, NULL, _name, &sprom->_val, \
187 _allset, _fallback)
188/*
189 * Special version of filling function that can be safely called for any SPROM
190 * revision. For every NVRAM to SPROM mapping it contains bitmask of revisions
191 * for which the mapping is valid.
192 * It obviously requires some hexadecimal/bitmasks knowledge, but allows
193 * writing cleaner code (easy revisions handling).
194 * Note that while SPROM revision 0 was never used, we still keep BIT(0)
195 * reserved for it, just to keep numbering sane.
196 */
197static void bcm47xx_sprom_fill_auto(struct ssb_sprom *sprom,
198 const char *prefix, bool fallback)
199{
200 const char *pre = prefix;
201 bool fb = fallback;
202
203 ENTRY(0xfffffffe, u16, pre, "boardrev", board_rev, 0, true);
204 ENTRY(0x00000002, u16, pre, "boardflags", boardflags_lo, 0, fb);
205 ENTRY(0xfffffffc, u16, pre, "boardtype", board_type, 0, true);
206 ENTRY(0xfffffffe, u16, pre, "boardnum", board_num, 0, fb);
207 ENTRY(0x00000002, u8, pre, "cc", country_code, 0, fb);
208 ENTRY(0xfffffff8, u8, pre, "regrev", regrev, 0, fb);
209
210 ENTRY(0xfffffffe, u8, pre, "ledbh0", gpio0, 0xff, fb);
211 ENTRY(0xfffffffe, u8, pre, "ledbh1", gpio1, 0xff, fb);
212 ENTRY(0xfffffffe, u8, pre, "ledbh2", gpio2, 0xff, fb);
213 ENTRY(0xfffffffe, u8, pre, "ledbh3", gpio3, 0xff, fb);
214
215 ENTRY(0x0000070e, u16, pre, "pa0b0", pa0b0, 0, fb);
216 ENTRY(0x0000070e, u16, pre, "pa0b1", pa0b1, 0, fb);
217 ENTRY(0x0000070e, u16, pre, "pa0b2", pa0b2, 0, fb);
218 ENTRY(0x0000070e, u8, pre, "pa0itssit", itssi_bg, 0, fb);
219 ENTRY(0x0000070e, u8, pre, "pa0maxpwr", maxpwr_bg, 0, fb);
220
221 ENTRY(0x0000070c, u8, pre, "opo", opo, 0, fb);
222 ENTRY(0xfffffffe, u8, pre, "aa2g", ant_available_bg, 0, fb);
223 ENTRY(0xfffffffe, u8, pre, "aa5g", ant_available_a, 0, fb);
224 ENTRY(0x000007fe, s8, pre, "ag0", antenna_gain.a0, 0, fb);
225 ENTRY(0x000007fe, s8, pre, "ag1", antenna_gain.a1, 0, fb);
226 ENTRY(0x000007f0, s8, pre, "ag2", antenna_gain.a2, 0, fb);
227 ENTRY(0x000007f0, s8, pre, "ag3", antenna_gain.a3, 0, fb);
228
229 ENTRY(0x0000070e, u16, pre, "pa1b0", pa1b0, 0, fb);
230 ENTRY(0x0000070e, u16, pre, "pa1b1", pa1b1, 0, fb);
231 ENTRY(0x0000070e, u16, pre, "pa1b2", pa1b2, 0, fb);
232 ENTRY(0x0000070c, u16, pre, "pa1lob0", pa1lob0, 0, fb);
233 ENTRY(0x0000070c, u16, pre, "pa1lob1", pa1lob1, 0, fb);
234 ENTRY(0x0000070c, u16, pre, "pa1lob2", pa1lob2, 0, fb);
235 ENTRY(0x0000070c, u16, pre, "pa1hib0", pa1hib0, 0, fb);
236 ENTRY(0x0000070c, u16, pre, "pa1hib1", pa1hib1, 0, fb);
237 ENTRY(0x0000070c, u16, pre, "pa1hib2", pa1hib2, 0, fb);
238 ENTRY(0x0000070e, u8, pre, "pa1itssit", itssi_a, 0, fb);
239 ENTRY(0x0000070e, u8, pre, "pa1maxpwr", maxpwr_a, 0, fb);
240 ENTRY(0x0000070c, u8, pre, "pa1lomaxpwr", maxpwr_al, 0, fb);
241 ENTRY(0x0000070c, u8, pre, "pa1himaxpwr", maxpwr_ah, 0, fb);
242
243 ENTRY(0x00000708, u8, pre, "bxa2g", bxa2g, 0, fb);
244 ENTRY(0x00000708, u8, pre, "rssisav2g", rssisav2g, 0, fb);
245 ENTRY(0x00000708, u8, pre, "rssismc2g", rssismc2g, 0, fb);
246 ENTRY(0x00000708, u8, pre, "rssismf2g", rssismf2g, 0, fb);
247 ENTRY(0x00000708, u8, pre, "bxa5g", bxa5g, 0, fb);
248 ENTRY(0x00000708, u8, pre, "rssisav5g", rssisav5g, 0, fb);
249 ENTRY(0x00000708, u8, pre, "rssismc5g", rssismc5g, 0, fb);
250 ENTRY(0x00000708, u8, pre, "rssismf5g", rssismf5g, 0, fb);
251 ENTRY(0x00000708, u8, pre, "tri2g", tri2g, 0, fb);
252 ENTRY(0x00000708, u8, pre, "tri5g", tri5g, 0, fb);
253 ENTRY(0x00000708, u8, pre, "tri5gl", tri5gl, 0, fb);
254 ENTRY(0x00000708, u8, pre, "tri5gh", tri5gh, 0, fb);
255 ENTRY(0x00000708, s8, pre, "rxpo2g", rxpo2g, 0, fb);
256 ENTRY(0x00000708, s8, pre, "rxpo5g", rxpo5g, 0, fb);
257 ENTRY(0xfffffff0, u8, pre, "txchain", txchain, 0xf, fb);
258 ENTRY(0xfffffff0, u8, pre, "rxchain", rxchain, 0xf, fb);
259 ENTRY(0xfffffff0, u8, pre, "antswitch", antswitch, 0xff, fb);
260 ENTRY(0x00000700, u8, pre, "tssipos2g", fem.ghz2.tssipos, 0, fb);
261 ENTRY(0x00000700, u8, pre, "extpagain2g", fem.ghz2.extpa_gain, 0, fb);
262 ENTRY(0x00000700, u8, pre, "pdetrange2g", fem.ghz2.pdet_range, 0, fb);
263 ENTRY(0x00000700, u8, pre, "triso2g", fem.ghz2.tr_iso, 0, fb);
264 ENTRY(0x00000700, u8, pre, "antswctl2g", fem.ghz2.antswlut, 0, fb);
265 ENTRY(0x00000700, u8, pre, "tssipos5g", fem.ghz5.tssipos, 0, fb);
266 ENTRY(0x00000700, u8, pre, "extpagain5g", fem.ghz5.extpa_gain, 0, fb);
267 ENTRY(0x00000700, u8, pre, "pdetrange5g", fem.ghz5.pdet_range, 0, fb);
268 ENTRY(0x00000700, u8, pre, "triso5g", fem.ghz5.tr_iso, 0, fb);
269 ENTRY(0x00000700, u8, pre, "antswctl5g", fem.ghz5.antswlut, 0, fb);
270 ENTRY(0x000000f0, u8, pre, "txpid2ga0", txpid2g[0], 0, fb);
271 ENTRY(0x000000f0, u8, pre, "txpid2ga1", txpid2g[1], 0, fb);
272 ENTRY(0x000000f0, u8, pre, "txpid2ga2", txpid2g[2], 0, fb);
273 ENTRY(0x000000f0, u8, pre, "txpid2ga3", txpid2g[3], 0, fb);
274 ENTRY(0x000000f0, u8, pre, "txpid5ga0", txpid5g[0], 0, fb);
275 ENTRY(0x000000f0, u8, pre, "txpid5ga1", txpid5g[1], 0, fb);
276 ENTRY(0x000000f0, u8, pre, "txpid5ga2", txpid5g[2], 0, fb);
277 ENTRY(0x000000f0, u8, pre, "txpid5ga3", txpid5g[3], 0, fb);
278 ENTRY(0x000000f0, u8, pre, "txpid5gla0", txpid5gl[0], 0, fb);
279 ENTRY(0x000000f0, u8, pre, "txpid5gla1", txpid5gl[1], 0, fb);
280 ENTRY(0x000000f0, u8, pre, "txpid5gla2", txpid5gl[2], 0, fb);
281 ENTRY(0x000000f0, u8, pre, "txpid5gla3", txpid5gl[3], 0, fb);
282 ENTRY(0x000000f0, u8, pre, "txpid5gha0", txpid5gh[0], 0, fb);
283 ENTRY(0x000000f0, u8, pre, "txpid5gha1", txpid5gh[1], 0, fb);
284 ENTRY(0x000000f0, u8, pre, "txpid5gha2", txpid5gh[2], 0, fb);
285 ENTRY(0x000000f0, u8, pre, "txpid5gha3", txpid5gh[3], 0, fb);
286
287 ENTRY(0xffffff00, u8, pre, "tempthresh", tempthresh, 0, fb);
288 ENTRY(0xffffff00, u8, pre, "tempoffset", tempoffset, 0, fb);
289 ENTRY(0xffffff00, u16, pre, "rawtempsense", rawtempsense, 0, fb);
290 ENTRY(0xffffff00, u8, pre, "measpower", measpower, 0, fb);
291 ENTRY(0xffffff00, u8, pre, "tempsense_slope", tempsense_slope, 0, fb);
292 ENTRY(0xffffff00, u8, pre, "tempcorrx", tempcorrx, 0, fb);
293 ENTRY(0xffffff00, u8, pre, "tempsense_option", tempsense_option, 0, fb);
294 ENTRY(0x00000700, u8, pre, "freqoffset_corr", freqoffset_corr, 0, fb);
295 ENTRY(0x00000700, u8, pre, "iqcal_swp_dis", iqcal_swp_dis, 0, fb);
296 ENTRY(0x00000700, u8, pre, "hw_iqcal_en", hw_iqcal_en, 0, fb);
297 ENTRY(0x00000700, u8, pre, "elna2g", elna2g, 0, fb);
298 ENTRY(0x00000700, u8, pre, "elna5g", elna5g, 0, fb);
299 ENTRY(0xffffff00, u8, pre, "phycal_tempdelta", phycal_tempdelta, 0, fb);
300 ENTRY(0xffffff00, u8, pre, "temps_period", temps_period, 0, fb);
301 ENTRY(0xffffff00, u8, pre, "temps_hysteresis", temps_hysteresis, 0, fb);
302 ENTRY(0xffffff00, u8, pre, "measpower1", measpower1, 0, fb);
303 ENTRY(0xffffff00, u8, pre, "measpower2", measpower2, 0, fb);
304
305 ENTRY(0x000001f0, u16, pre, "cck2gpo", cck2gpo, 0, fb);
306 ENTRY(0x000001f0, u32, pre, "ofdm2gpo", ofdm2gpo, 0, fb);
307 ENTRY(0x000001f0, u32, pre, "ofdm5gpo", ofdm5gpo, 0, fb);
308 ENTRY(0x000001f0, u32, pre, "ofdm5glpo", ofdm5glpo, 0, fb);
309 ENTRY(0x000001f0, u32, pre, "ofdm5ghpo", ofdm5ghpo, 0, fb);
310 ENTRY(0x000001f0, u16, pre, "mcs2gpo0", mcs2gpo[0], 0, fb);
311 ENTRY(0x000001f0, u16, pre, "mcs2gpo1", mcs2gpo[1], 0, fb);
312 ENTRY(0x000001f0, u16, pre, "mcs2gpo2", mcs2gpo[2], 0, fb);
313 ENTRY(0x000001f0, u16, pre, "mcs2gpo3", mcs2gpo[3], 0, fb);
314 ENTRY(0x000001f0, u16, pre, "mcs2gpo4", mcs2gpo[4], 0, fb);
315 ENTRY(0x000001f0, u16, pre, "mcs2gpo5", mcs2gpo[5], 0, fb);
316 ENTRY(0x000001f0, u16, pre, "mcs2gpo6", mcs2gpo[6], 0, fb);
317 ENTRY(0x000001f0, u16, pre, "mcs2gpo7", mcs2gpo[7], 0, fb);
318 ENTRY(0x000001f0, u16, pre, "mcs5gpo0", mcs5gpo[0], 0, fb);
319 ENTRY(0x000001f0, u16, pre, "mcs5gpo1", mcs5gpo[1], 0, fb);
320 ENTRY(0x000001f0, u16, pre, "mcs5gpo2", mcs5gpo[2], 0, fb);
321 ENTRY(0x000001f0, u16, pre, "mcs5gpo3", mcs5gpo[3], 0, fb);
322 ENTRY(0x000001f0, u16, pre, "mcs5gpo4", mcs5gpo[4], 0, fb);
323 ENTRY(0x000001f0, u16, pre, "mcs5gpo5", mcs5gpo[5], 0, fb);
324 ENTRY(0x000001f0, u16, pre, "mcs5gpo6", mcs5gpo[6], 0, fb);
325 ENTRY(0x000001f0, u16, pre, "mcs5gpo7", mcs5gpo[7], 0, fb);
326 ENTRY(0x000001f0, u16, pre, "mcs5glpo0", mcs5glpo[0], 0, fb);
327 ENTRY(0x000001f0, u16, pre, "mcs5glpo1", mcs5glpo[1], 0, fb);
328 ENTRY(0x000001f0, u16, pre, "mcs5glpo2", mcs5glpo[2], 0, fb);
329 ENTRY(0x000001f0, u16, pre, "mcs5glpo3", mcs5glpo[3], 0, fb);
330 ENTRY(0x000001f0, u16, pre, "mcs5glpo4", mcs5glpo[4], 0, fb);
331 ENTRY(0x000001f0, u16, pre, "mcs5glpo5", mcs5glpo[5], 0, fb);
332 ENTRY(0x000001f0, u16, pre, "mcs5glpo6", mcs5glpo[6], 0, fb);
333 ENTRY(0x000001f0, u16, pre, "mcs5glpo7", mcs5glpo[7], 0, fb);
334 ENTRY(0x000001f0, u16, pre, "mcs5ghpo0", mcs5ghpo[0], 0, fb);
335 ENTRY(0x000001f0, u16, pre, "mcs5ghpo1", mcs5ghpo[1], 0, fb);
336 ENTRY(0x000001f0, u16, pre, "mcs5ghpo2", mcs5ghpo[2], 0, fb);
337 ENTRY(0x000001f0, u16, pre, "mcs5ghpo3", mcs5ghpo[3], 0, fb);
338 ENTRY(0x000001f0, u16, pre, "mcs5ghpo4", mcs5ghpo[4], 0, fb);
339 ENTRY(0x000001f0, u16, pre, "mcs5ghpo5", mcs5ghpo[5], 0, fb);
340 ENTRY(0x000001f0, u16, pre, "mcs5ghpo6", mcs5ghpo[6], 0, fb);
341 ENTRY(0x000001f0, u16, pre, "mcs5ghpo7", mcs5ghpo[7], 0, fb);
342 ENTRY(0x000001f0, u16, pre, "cddpo", cddpo, 0, fb);
343 ENTRY(0x000001f0, u16, pre, "stbcpo", stbcpo, 0, fb);
344 ENTRY(0x000001f0, u16, pre, "bw40po", bw40po, 0, fb);
345 ENTRY(0x000001f0, u16, pre, "bwduppo", bwduppo, 0, fb);
346
347 ENTRY(0xfffffe00, u16, pre, "cckbw202gpo", cckbw202gpo, 0, fb);
348 ENTRY(0xfffffe00, u16, pre, "cckbw20ul2gpo", cckbw20ul2gpo, 0, fb);
349 ENTRY(0x00000600, u32, pre, "legofdmbw202gpo", legofdmbw202gpo, 0, fb);
350 ENTRY(0x00000600, u32, pre, "legofdmbw20ul2gpo", legofdmbw20ul2gpo, 0, fb);
351 ENTRY(0x00000600, u32, pre, "legofdmbw205glpo", legofdmbw205glpo, 0, fb);
352 ENTRY(0x00000600, u32, pre, "legofdmbw20ul5glpo", legofdmbw20ul5glpo, 0, fb);
353 ENTRY(0x00000600, u32, pre, "legofdmbw205gmpo", legofdmbw205gmpo, 0, fb);
354 ENTRY(0x00000600, u32, pre, "legofdmbw20ul5gmpo", legofdmbw20ul5gmpo, 0, fb);
355 ENTRY(0x00000600, u32, pre, "legofdmbw205ghpo", legofdmbw205ghpo, 0, fb);
356 ENTRY(0x00000600, u32, pre, "legofdmbw20ul5ghpo", legofdmbw20ul5ghpo, 0, fb);
357 ENTRY(0xfffffe00, u32, pre, "mcsbw202gpo", mcsbw202gpo, 0, fb);
358 ENTRY(0x00000600, u32, pre, "mcsbw20ul2gpo", mcsbw20ul2gpo, 0, fb);
359 ENTRY(0xfffffe00, u32, pre, "mcsbw402gpo", mcsbw402gpo, 0, fb);
360 ENTRY(0xfffffe00, u32, pre, "mcsbw205glpo", mcsbw205glpo, 0, fb);
361 ENTRY(0x00000600, u32, pre, "mcsbw20ul5glpo", mcsbw20ul5glpo, 0, fb);
362 ENTRY(0xfffffe00, u32, pre, "mcsbw405glpo", mcsbw405glpo, 0, fb);
363 ENTRY(0xfffffe00, u32, pre, "mcsbw205gmpo", mcsbw205gmpo, 0, fb);
364 ENTRY(0x00000600, u32, pre, "mcsbw20ul5gmpo", mcsbw20ul5gmpo, 0, fb);
365 ENTRY(0xfffffe00, u32, pre, "mcsbw405gmpo", mcsbw405gmpo, 0, fb);
366 ENTRY(0xfffffe00, u32, pre, "mcsbw205ghpo", mcsbw205ghpo, 0, fb);
367 ENTRY(0x00000600, u32, pre, "mcsbw20ul5ghpo", mcsbw20ul5ghpo, 0, fb);
368 ENTRY(0xfffffe00, u32, pre, "mcsbw405ghpo", mcsbw405ghpo, 0, fb);
369 ENTRY(0x00000600, u16, pre, "mcs32po", mcs32po, 0, fb);
370 ENTRY(0x00000600, u16, pre, "legofdm40duppo", legofdm40duppo, 0, fb);
371 ENTRY(0x00000700, u8, pre, "pcieingress_war", pcieingress_war, 0, fb);
372
373 /* TODO: rev 11 support */
374 ENTRY(0x00000700, u8, pre, "rxgainerr2ga0", rxgainerr2ga[0], 0, fb);
375 ENTRY(0x00000700, u8, pre, "rxgainerr2ga1", rxgainerr2ga[1], 0, fb);
376 ENTRY(0x00000700, u8, pre, "rxgainerr2ga2", rxgainerr2ga[2], 0, fb);
377 ENTRY(0x00000700, u8, pre, "rxgainerr5gla0", rxgainerr5gla[0], 0, fb);
378 ENTRY(0x00000700, u8, pre, "rxgainerr5gla1", rxgainerr5gla[1], 0, fb);
379 ENTRY(0x00000700, u8, pre, "rxgainerr5gla2", rxgainerr5gla[2], 0, fb);
380 ENTRY(0x00000700, u8, pre, "rxgainerr5gma0", rxgainerr5gma[0], 0, fb);
381 ENTRY(0x00000700, u8, pre, "rxgainerr5gma1", rxgainerr5gma[1], 0, fb);
382 ENTRY(0x00000700, u8, pre, "rxgainerr5gma2", rxgainerr5gma[2], 0, fb);
383 ENTRY(0x00000700, u8, pre, "rxgainerr5gha0", rxgainerr5gha[0], 0, fb);
384 ENTRY(0x00000700, u8, pre, "rxgainerr5gha1", rxgainerr5gha[1], 0, fb);
385 ENTRY(0x00000700, u8, pre, "rxgainerr5gha2", rxgainerr5gha[2], 0, fb);
386 ENTRY(0x00000700, u8, pre, "rxgainerr5gua0", rxgainerr5gua[0], 0, fb);
387 ENTRY(0x00000700, u8, pre, "rxgainerr5gua1", rxgainerr5gua[1], 0, fb);
388 ENTRY(0x00000700, u8, pre, "rxgainerr5gua2", rxgainerr5gua[2], 0, fb);
389
390 ENTRY(0xfffffe00, u8, pre, "sar2g", sar2g, 0, fb);
391 ENTRY(0xfffffe00, u8, pre, "sar5g", sar5g, 0, fb);
392
393 /* TODO: rev 11 support */
394 ENTRY(0x00000700, u8, pre, "noiselvl2ga0", noiselvl2ga[0], 0, fb);
395 ENTRY(0x00000700, u8, pre, "noiselvl2ga1", noiselvl2ga[1], 0, fb);
396 ENTRY(0x00000700, u8, pre, "noiselvl2ga2", noiselvl2ga[2], 0, fb);
397 ENTRY(0x00000700, u8, pre, "noiselvl5gla0", noiselvl5gla[0], 0, fb);
398 ENTRY(0x00000700, u8, pre, "noiselvl5gla1", noiselvl5gla[1], 0, fb);
399 ENTRY(0x00000700, u8, pre, "noiselvl5gla2", noiselvl5gla[2], 0, fb);
400 ENTRY(0x00000700, u8, pre, "noiselvl5gma0", noiselvl5gma[0], 0, fb);
401 ENTRY(0x00000700, u8, pre, "noiselvl5gma1", noiselvl5gma[1], 0, fb);
402 ENTRY(0x00000700, u8, pre, "noiselvl5gma2", noiselvl5gma[2], 0, fb);
403 ENTRY(0x00000700, u8, pre, "noiselvl5gha0", noiselvl5gha[0], 0, fb);
404 ENTRY(0x00000700, u8, pre, "noiselvl5gha1", noiselvl5gha[1], 0, fb);
405 ENTRY(0x00000700, u8, pre, "noiselvl5gha2", noiselvl5gha[2], 0, fb);
406 ENTRY(0x00000700, u8, pre, "noiselvl5gua0", noiselvl5gua[0], 0, fb);
407 ENTRY(0x00000700, u8, pre, "noiselvl5gua1", noiselvl5gua[1], 0, fb);
408 ENTRY(0x00000700, u8, pre, "noiselvl5gua2", noiselvl5gua[2], 0, fb);
409}
410#undef ENTRY /* It's specififc, uses local variable, don't use it (again). */
411
184static void bcm47xx_fill_sprom_r1234589(struct ssb_sprom *sprom, 412static void bcm47xx_fill_sprom_r1234589(struct ssb_sprom *sprom,
185 const char *prefix, bool fallback) 413 const char *prefix, bool fallback)
186{ 414{
187 nvram_read_u16(prefix, NULL, "devid", &sprom->dev_id, 0, fallback); 415 nvram_read_u16(prefix, NULL, "devid", &sprom->dev_id, 0, fallback);
188 nvram_read_u8(prefix, NULL, "ledbh0", &sprom->gpio0, 0xff, fallback);
189 nvram_read_u8(prefix, NULL, "ledbh1", &sprom->gpio1, 0xff, fallback);
190 nvram_read_u8(prefix, NULL, "ledbh2", &sprom->gpio2, 0xff, fallback);
191 nvram_read_u8(prefix, NULL, "ledbh3", &sprom->gpio3, 0xff, fallback);
192 nvram_read_u8(prefix, NULL, "aa2g", &sprom->ant_available_bg, 0,
193 fallback);
194 nvram_read_u8(prefix, NULL, "aa5g", &sprom->ant_available_a, 0,
195 fallback);
196 nvram_read_s8(prefix, NULL, "ag0", &sprom->antenna_gain.a0, 0,
197 fallback);
198 nvram_read_s8(prefix, NULL, "ag1", &sprom->antenna_gain.a1, 0,
199 fallback);
200 nvram_read_alpha2(prefix, "ccode", sprom->alpha2, fallback); 416 nvram_read_alpha2(prefix, "ccode", sprom->alpha2, fallback);
201} 417}
202 418
203static void bcm47xx_fill_sprom_r12389(struct ssb_sprom *sprom,
204 const char *prefix, bool fallback)
205{
206 nvram_read_u16(prefix, NULL, "pa0b0", &sprom->pa0b0, 0, fallback);
207 nvram_read_u16(prefix, NULL, "pa0b1", &sprom->pa0b1, 0, fallback);
208 nvram_read_u16(prefix, NULL, "pa0b2", &sprom->pa0b2, 0, fallback);
209 nvram_read_u8(prefix, NULL, "pa0itssit", &sprom->itssi_bg, 0, fallback);
210 nvram_read_u8(prefix, NULL, "pa0maxpwr", &sprom->maxpwr_bg, 0,
211 fallback);
212 nvram_read_u16(prefix, NULL, "pa1b0", &sprom->pa1b0, 0, fallback);
213 nvram_read_u16(prefix, NULL, "pa1b1", &sprom->pa1b1, 0, fallback);
214 nvram_read_u16(prefix, NULL, "pa1b2", &sprom->pa1b2, 0, fallback);
215 nvram_read_u8(prefix, NULL, "pa1itssit", &sprom->itssi_a, 0, fallback);
216 nvram_read_u8(prefix, NULL, "pa1maxpwr", &sprom->maxpwr_a, 0, fallback);
217}
218
219static void bcm47xx_fill_sprom_r1(struct ssb_sprom *sprom, const char *prefix,
220 bool fallback)
221{
222 nvram_read_u16(prefix, NULL, "boardflags", &sprom->boardflags_lo, 0,
223 fallback);
224 nvram_read_u8(prefix, NULL, "cc", &sprom->country_code, 0, fallback);
225}
226
227static void bcm47xx_fill_sprom_r2389(struct ssb_sprom *sprom,
228 const char *prefix, bool fallback)
229{
230 nvram_read_u8(prefix, NULL, "opo", &sprom->opo, 0, fallback);
231 nvram_read_u16(prefix, NULL, "pa1lob0", &sprom->pa1lob0, 0, fallback);
232 nvram_read_u16(prefix, NULL, "pa1lob1", &sprom->pa1lob1, 0, fallback);
233 nvram_read_u16(prefix, NULL, "pa1lob2", &sprom->pa1lob2, 0, fallback);
234 nvram_read_u16(prefix, NULL, "pa1hib0", &sprom->pa1hib0, 0, fallback);
235 nvram_read_u16(prefix, NULL, "pa1hib1", &sprom->pa1hib1, 0, fallback);
236 nvram_read_u16(prefix, NULL, "pa1hib2", &sprom->pa1hib2, 0, fallback);
237 nvram_read_u8(prefix, NULL, "pa1lomaxpwr", &sprom->maxpwr_al, 0,
238 fallback);
239 nvram_read_u8(prefix, NULL, "pa1himaxpwr", &sprom->maxpwr_ah, 0,
240 fallback);
241}
242
243static void bcm47xx_fill_sprom_r389(struct ssb_sprom *sprom, const char *prefix,
244 bool fallback)
245{
246 nvram_read_u8(prefix, NULL, "bxa2g", &sprom->bxa2g, 0, fallback);
247 nvram_read_u8(prefix, NULL, "rssisav2g", &sprom->rssisav2g, 0,
248 fallback);
249 nvram_read_u8(prefix, NULL, "rssismc2g", &sprom->rssismc2g, 0,
250 fallback);
251 nvram_read_u8(prefix, NULL, "rssismf2g", &sprom->rssismf2g, 0,
252 fallback);
253 nvram_read_u8(prefix, NULL, "bxa5g", &sprom->bxa5g, 0, fallback);
254 nvram_read_u8(prefix, NULL, "rssisav5g", &sprom->rssisav5g, 0,
255 fallback);
256 nvram_read_u8(prefix, NULL, "rssismc5g", &sprom->rssismc5g, 0,
257 fallback);
258 nvram_read_u8(prefix, NULL, "rssismf5g", &sprom->rssismf5g, 0,
259 fallback);
260 nvram_read_u8(prefix, NULL, "tri2g", &sprom->tri2g, 0, fallback);
261 nvram_read_u8(prefix, NULL, "tri5g", &sprom->tri5g, 0, fallback);
262 nvram_read_u8(prefix, NULL, "tri5gl", &sprom->tri5gl, 0, fallback);
263 nvram_read_u8(prefix, NULL, "tri5gh", &sprom->tri5gh, 0, fallback);
264 nvram_read_s8(prefix, NULL, "rxpo2g", &sprom->rxpo2g, 0, fallback);
265 nvram_read_s8(prefix, NULL, "rxpo5g", &sprom->rxpo5g, 0, fallback);
266}
267
268static void bcm47xx_fill_sprom_r3(struct ssb_sprom *sprom, const char *prefix, 419static void bcm47xx_fill_sprom_r3(struct ssb_sprom *sprom, const char *prefix,
269 bool fallback) 420 bool fallback)
270{ 421{
271 nvram_read_u8(prefix, NULL, "regrev", &sprom->regrev, 0, fallback);
272 nvram_read_leddc(prefix, "leddc", &sprom->leddc_on_time, 422 nvram_read_leddc(prefix, "leddc", &sprom->leddc_on_time,
273 &sprom->leddc_off_time, fallback); 423 &sprom->leddc_off_time, fallback);
274} 424}
@@ -276,309 +426,10 @@ static void bcm47xx_fill_sprom_r3(struct ssb_sprom *sprom, const char *prefix,
276static void bcm47xx_fill_sprom_r4589(struct ssb_sprom *sprom, 426static void bcm47xx_fill_sprom_r4589(struct ssb_sprom *sprom,
277 const char *prefix, bool fallback) 427 const char *prefix, bool fallback)
278{ 428{
279 nvram_read_u8(prefix, NULL, "regrev", &sprom->regrev, 0, fallback);
280 nvram_read_s8(prefix, NULL, "ag2", &sprom->antenna_gain.a2, 0,
281 fallback);
282 nvram_read_s8(prefix, NULL, "ag3", &sprom->antenna_gain.a3, 0,
283 fallback);
284 nvram_read_u8(prefix, NULL, "txchain", &sprom->txchain, 0xf, fallback);
285 nvram_read_u8(prefix, NULL, "rxchain", &sprom->rxchain, 0xf, fallback);
286 nvram_read_u8(prefix, NULL, "antswitch", &sprom->antswitch, 0xff,
287 fallback);
288 nvram_read_leddc(prefix, "leddc", &sprom->leddc_on_time, 429 nvram_read_leddc(prefix, "leddc", &sprom->leddc_on_time,
289 &sprom->leddc_off_time, fallback); 430 &sprom->leddc_off_time, fallback);
290} 431}
291 432
292static void bcm47xx_fill_sprom_r458(struct ssb_sprom *sprom, const char *prefix,
293 bool fallback)
294{
295 nvram_read_u16(prefix, NULL, "cck2gpo", &sprom->cck2gpo, 0, fallback);
296 nvram_read_u32(prefix, NULL, "ofdm2gpo", &sprom->ofdm2gpo, 0, fallback);
297 nvram_read_u32(prefix, NULL, "ofdm5gpo", &sprom->ofdm5gpo, 0, fallback);
298 nvram_read_u32(prefix, NULL, "ofdm5glpo", &sprom->ofdm5glpo, 0,
299 fallback);
300 nvram_read_u32(prefix, NULL, "ofdm5ghpo", &sprom->ofdm5ghpo, 0,
301 fallback);
302 nvram_read_u16(prefix, NULL, "cddpo", &sprom->cddpo, 0, fallback);
303 nvram_read_u16(prefix, NULL, "stbcpo", &sprom->stbcpo, 0, fallback);
304 nvram_read_u16(prefix, NULL, "bw40po", &sprom->bw40po, 0, fallback);
305 nvram_read_u16(prefix, NULL, "bwduppo", &sprom->bwduppo, 0, fallback);
306 nvram_read_u16(prefix, NULL, "mcs2gpo0", &sprom->mcs2gpo[0], 0,
307 fallback);
308 nvram_read_u16(prefix, NULL, "mcs2gpo1", &sprom->mcs2gpo[1], 0,
309 fallback);
310 nvram_read_u16(prefix, NULL, "mcs2gpo2", &sprom->mcs2gpo[2], 0,
311 fallback);
312 nvram_read_u16(prefix, NULL, "mcs2gpo3", &sprom->mcs2gpo[3], 0,
313 fallback);
314 nvram_read_u16(prefix, NULL, "mcs2gpo4", &sprom->mcs2gpo[4], 0,
315 fallback);
316 nvram_read_u16(prefix, NULL, "mcs2gpo5", &sprom->mcs2gpo[5], 0,
317 fallback);
318 nvram_read_u16(prefix, NULL, "mcs2gpo6", &sprom->mcs2gpo[6], 0,
319 fallback);
320 nvram_read_u16(prefix, NULL, "mcs2gpo7", &sprom->mcs2gpo[7], 0,
321 fallback);
322 nvram_read_u16(prefix, NULL, "mcs5gpo0", &sprom->mcs5gpo[0], 0,
323 fallback);
324 nvram_read_u16(prefix, NULL, "mcs5gpo1", &sprom->mcs5gpo[1], 0,
325 fallback);
326 nvram_read_u16(prefix, NULL, "mcs5gpo2", &sprom->mcs5gpo[2], 0,
327 fallback);
328 nvram_read_u16(prefix, NULL, "mcs5gpo3", &sprom->mcs5gpo[3], 0,
329 fallback);
330 nvram_read_u16(prefix, NULL, "mcs5gpo4", &sprom->mcs5gpo[4], 0,
331 fallback);
332 nvram_read_u16(prefix, NULL, "mcs5gpo5", &sprom->mcs5gpo[5], 0,
333 fallback);
334 nvram_read_u16(prefix, NULL, "mcs5gpo6", &sprom->mcs5gpo[6], 0,
335 fallback);
336 nvram_read_u16(prefix, NULL, "mcs5gpo7", &sprom->mcs5gpo[7], 0,
337 fallback);
338 nvram_read_u16(prefix, NULL, "mcs5glpo0", &sprom->mcs5glpo[0], 0,
339 fallback);
340 nvram_read_u16(prefix, NULL, "mcs5glpo1", &sprom->mcs5glpo[1], 0,
341 fallback);
342 nvram_read_u16(prefix, NULL, "mcs5glpo2", &sprom->mcs5glpo[2], 0,
343 fallback);
344 nvram_read_u16(prefix, NULL, "mcs5glpo3", &sprom->mcs5glpo[3], 0,
345 fallback);
346 nvram_read_u16(prefix, NULL, "mcs5glpo4", &sprom->mcs5glpo[4], 0,
347 fallback);
348 nvram_read_u16(prefix, NULL, "mcs5glpo5", &sprom->mcs5glpo[5], 0,
349 fallback);
350 nvram_read_u16(prefix, NULL, "mcs5glpo6", &sprom->mcs5glpo[6], 0,
351 fallback);
352 nvram_read_u16(prefix, NULL, "mcs5glpo7", &sprom->mcs5glpo[7], 0,
353 fallback);
354 nvram_read_u16(prefix, NULL, "mcs5ghpo0", &sprom->mcs5ghpo[0], 0,
355 fallback);
356 nvram_read_u16(prefix, NULL, "mcs5ghpo1", &sprom->mcs5ghpo[1], 0,
357 fallback);
358 nvram_read_u16(prefix, NULL, "mcs5ghpo2", &sprom->mcs5ghpo[2], 0,
359 fallback);
360 nvram_read_u16(prefix, NULL, "mcs5ghpo3", &sprom->mcs5ghpo[3], 0,
361 fallback);
362 nvram_read_u16(prefix, NULL, "mcs5ghpo4", &sprom->mcs5ghpo[4], 0,
363 fallback);
364 nvram_read_u16(prefix, NULL, "mcs5ghpo5", &sprom->mcs5ghpo[5], 0,
365 fallback);
366 nvram_read_u16(prefix, NULL, "mcs5ghpo6", &sprom->mcs5ghpo[6], 0,
367 fallback);
368 nvram_read_u16(prefix, NULL, "mcs5ghpo7", &sprom->mcs5ghpo[7], 0,
369 fallback);
370}
371
372static void bcm47xx_fill_sprom_r45(struct ssb_sprom *sprom, const char *prefix,
373 bool fallback)
374{
375 nvram_read_u8(prefix, NULL, "txpid2ga0", &sprom->txpid2g[0], 0,
376 fallback);
377 nvram_read_u8(prefix, NULL, "txpid2ga1", &sprom->txpid2g[1], 0,
378 fallback);
379 nvram_read_u8(prefix, NULL, "txpid2ga2", &sprom->txpid2g[2], 0,
380 fallback);
381 nvram_read_u8(prefix, NULL, "txpid2ga3", &sprom->txpid2g[3], 0,
382 fallback);
383 nvram_read_u8(prefix, NULL, "txpid5ga0", &sprom->txpid5g[0], 0,
384 fallback);
385 nvram_read_u8(prefix, NULL, "txpid5ga1", &sprom->txpid5g[1], 0,
386 fallback);
387 nvram_read_u8(prefix, NULL, "txpid5ga2", &sprom->txpid5g[2], 0,
388 fallback);
389 nvram_read_u8(prefix, NULL, "txpid5ga3", &sprom->txpid5g[3], 0,
390 fallback);
391 nvram_read_u8(prefix, NULL, "txpid5gla0", &sprom->txpid5gl[0], 0,
392 fallback);
393 nvram_read_u8(prefix, NULL, "txpid5gla1", &sprom->txpid5gl[1], 0,
394 fallback);
395 nvram_read_u8(prefix, NULL, "txpid5gla2", &sprom->txpid5gl[2], 0,
396 fallback);
397 nvram_read_u8(prefix, NULL, "txpid5gla3", &sprom->txpid5gl[3], 0,
398 fallback);
399 nvram_read_u8(prefix, NULL, "txpid5gha0", &sprom->txpid5gh[0], 0,
400 fallback);
401 nvram_read_u8(prefix, NULL, "txpid5gha1", &sprom->txpid5gh[1], 0,
402 fallback);
403 nvram_read_u8(prefix, NULL, "txpid5gha2", &sprom->txpid5gh[2], 0,
404 fallback);
405 nvram_read_u8(prefix, NULL, "txpid5gha3", &sprom->txpid5gh[3], 0,
406 fallback);
407}
408
409static void bcm47xx_fill_sprom_r89(struct ssb_sprom *sprom, const char *prefix,
410 bool fallback)
411{
412 nvram_read_u8(prefix, NULL, "tssipos2g", &sprom->fem.ghz2.tssipos, 0,
413 fallback);
414 nvram_read_u8(prefix, NULL, "extpagain2g",
415 &sprom->fem.ghz2.extpa_gain, 0, fallback);
416 nvram_read_u8(prefix, NULL, "pdetrange2g",
417 &sprom->fem.ghz2.pdet_range, 0, fallback);
418 nvram_read_u8(prefix, NULL, "triso2g", &sprom->fem.ghz2.tr_iso, 0,
419 fallback);
420 nvram_read_u8(prefix, NULL, "antswctl2g", &sprom->fem.ghz2.antswlut, 0,
421 fallback);
422 nvram_read_u8(prefix, NULL, "tssipos5g", &sprom->fem.ghz5.tssipos, 0,
423 fallback);
424 nvram_read_u8(prefix, NULL, "extpagain5g",
425 &sprom->fem.ghz5.extpa_gain, 0, fallback);
426 nvram_read_u8(prefix, NULL, "pdetrange5g",
427 &sprom->fem.ghz5.pdet_range, 0, fallback);
428 nvram_read_u8(prefix, NULL, "triso5g", &sprom->fem.ghz5.tr_iso, 0,
429 fallback);
430 nvram_read_u8(prefix, NULL, "antswctl5g", &sprom->fem.ghz5.antswlut, 0,
431 fallback);
432 nvram_read_u8(prefix, NULL, "tempthresh", &sprom->tempthresh, 0,
433 fallback);
434 nvram_read_u8(prefix, NULL, "tempoffset", &sprom->tempoffset, 0,
435 fallback);
436 nvram_read_u16(prefix, NULL, "rawtempsense", &sprom->rawtempsense, 0,
437 fallback);
438 nvram_read_u8(prefix, NULL, "measpower", &sprom->measpower, 0,
439 fallback);
440 nvram_read_u8(prefix, NULL, "tempsense_slope",
441 &sprom->tempsense_slope, 0, fallback);
442 nvram_read_u8(prefix, NULL, "tempcorrx", &sprom->tempcorrx, 0,
443 fallback);
444 nvram_read_u8(prefix, NULL, "tempsense_option",
445 &sprom->tempsense_option, 0, fallback);
446 nvram_read_u8(prefix, NULL, "freqoffset_corr",
447 &sprom->freqoffset_corr, 0, fallback);
448 nvram_read_u8(prefix, NULL, "iqcal_swp_dis", &sprom->iqcal_swp_dis, 0,
449 fallback);
450 nvram_read_u8(prefix, NULL, "hw_iqcal_en", &sprom->hw_iqcal_en, 0,
451 fallback);
452 nvram_read_u8(prefix, NULL, "elna2g", &sprom->elna2g, 0, fallback);
453 nvram_read_u8(prefix, NULL, "elna5g", &sprom->elna5g, 0, fallback);
454 nvram_read_u8(prefix, NULL, "phycal_tempdelta",
455 &sprom->phycal_tempdelta, 0, fallback);
456 nvram_read_u8(prefix, NULL, "temps_period", &sprom->temps_period, 0,
457 fallback);
458 nvram_read_u8(prefix, NULL, "temps_hysteresis",
459 &sprom->temps_hysteresis, 0, fallback);
460 nvram_read_u8(prefix, NULL, "measpower1", &sprom->measpower1, 0,
461 fallback);
462 nvram_read_u8(prefix, NULL, "measpower2", &sprom->measpower2, 0,
463 fallback);
464 nvram_read_u8(prefix, NULL, "rxgainerr2ga0",
465 &sprom->rxgainerr2ga[0], 0, fallback);
466 nvram_read_u8(prefix, NULL, "rxgainerr2ga1",
467 &sprom->rxgainerr2ga[1], 0, fallback);
468 nvram_read_u8(prefix, NULL, "rxgainerr2ga2",
469 &sprom->rxgainerr2ga[2], 0, fallback);
470 nvram_read_u8(prefix, NULL, "rxgainerr5gla0",
471 &sprom->rxgainerr5gla[0], 0, fallback);
472 nvram_read_u8(prefix, NULL, "rxgainerr5gla1",
473 &sprom->rxgainerr5gla[1], 0, fallback);
474 nvram_read_u8(prefix, NULL, "rxgainerr5gla2",
475 &sprom->rxgainerr5gla[2], 0, fallback);
476 nvram_read_u8(prefix, NULL, "rxgainerr5gma0",
477 &sprom->rxgainerr5gma[0], 0, fallback);
478 nvram_read_u8(prefix, NULL, "rxgainerr5gma1",
479 &sprom->rxgainerr5gma[1], 0, fallback);
480 nvram_read_u8(prefix, NULL, "rxgainerr5gma2",
481 &sprom->rxgainerr5gma[2], 0, fallback);
482 nvram_read_u8(prefix, NULL, "rxgainerr5gha0",
483 &sprom->rxgainerr5gha[0], 0, fallback);
484 nvram_read_u8(prefix, NULL, "rxgainerr5gha1",
485 &sprom->rxgainerr5gha[1], 0, fallback);
486 nvram_read_u8(prefix, NULL, "rxgainerr5gha2",
487 &sprom->rxgainerr5gha[2], 0, fallback);
488 nvram_read_u8(prefix, NULL, "rxgainerr5gua0",
489 &sprom->rxgainerr5gua[0], 0, fallback);
490 nvram_read_u8(prefix, NULL, "rxgainerr5gua1",
491 &sprom->rxgainerr5gua[1], 0, fallback);
492 nvram_read_u8(prefix, NULL, "rxgainerr5gua2",
493 &sprom->rxgainerr5gua[2], 0, fallback);
494 nvram_read_u8(prefix, NULL, "noiselvl2ga0", &sprom->noiselvl2ga[0], 0,
495 fallback);
496 nvram_read_u8(prefix, NULL, "noiselvl2ga1", &sprom->noiselvl2ga[1], 0,
497 fallback);
498 nvram_read_u8(prefix, NULL, "noiselvl2ga2", &sprom->noiselvl2ga[2], 0,
499 fallback);
500 nvram_read_u8(prefix, NULL, "noiselvl5gla0",
501 &sprom->noiselvl5gla[0], 0, fallback);
502 nvram_read_u8(prefix, NULL, "noiselvl5gla1",
503 &sprom->noiselvl5gla[1], 0, fallback);
504 nvram_read_u8(prefix, NULL, "noiselvl5gla2",
505 &sprom->noiselvl5gla[2], 0, fallback);
506 nvram_read_u8(prefix, NULL, "noiselvl5gma0",
507 &sprom->noiselvl5gma[0], 0, fallback);
508 nvram_read_u8(prefix, NULL, "noiselvl5gma1",
509 &sprom->noiselvl5gma[1], 0, fallback);
510 nvram_read_u8(prefix, NULL, "noiselvl5gma2",
511 &sprom->noiselvl5gma[2], 0, fallback);
512 nvram_read_u8(prefix, NULL, "noiselvl5gha0",
513 &sprom->noiselvl5gha[0], 0, fallback);
514 nvram_read_u8(prefix, NULL, "noiselvl5gha1",
515 &sprom->noiselvl5gha[1], 0, fallback);
516 nvram_read_u8(prefix, NULL, "noiselvl5gha2",
517 &sprom->noiselvl5gha[2], 0, fallback);
518 nvram_read_u8(prefix, NULL, "noiselvl5gua0",
519 &sprom->noiselvl5gua[0], 0, fallback);
520 nvram_read_u8(prefix, NULL, "noiselvl5gua1",
521 &sprom->noiselvl5gua[1], 0, fallback);
522 nvram_read_u8(prefix, NULL, "noiselvl5gua2",
523 &sprom->noiselvl5gua[2], 0, fallback);
524 nvram_read_u8(prefix, NULL, "pcieingress_war",
525 &sprom->pcieingress_war, 0, fallback);
526}
527
528static void bcm47xx_fill_sprom_r9(struct ssb_sprom *sprom, const char *prefix,
529 bool fallback)
530{
531 nvram_read_u16(prefix, NULL, "cckbw202gpo", &sprom->cckbw202gpo, 0,
532 fallback);
533 nvram_read_u16(prefix, NULL, "cckbw20ul2gpo", &sprom->cckbw20ul2gpo, 0,
534 fallback);
535 nvram_read_u32(prefix, NULL, "legofdmbw202gpo",
536 &sprom->legofdmbw202gpo, 0, fallback);
537 nvram_read_u32(prefix, NULL, "legofdmbw20ul2gpo",
538 &sprom->legofdmbw20ul2gpo, 0, fallback);
539 nvram_read_u32(prefix, NULL, "legofdmbw205glpo",
540 &sprom->legofdmbw205glpo, 0, fallback);
541 nvram_read_u32(prefix, NULL, "legofdmbw20ul5glpo",
542 &sprom->legofdmbw20ul5glpo, 0, fallback);
543 nvram_read_u32(prefix, NULL, "legofdmbw205gmpo",
544 &sprom->legofdmbw205gmpo, 0, fallback);
545 nvram_read_u32(prefix, NULL, "legofdmbw20ul5gmpo",
546 &sprom->legofdmbw20ul5gmpo, 0, fallback);
547 nvram_read_u32(prefix, NULL, "legofdmbw205ghpo",
548 &sprom->legofdmbw205ghpo, 0, fallback);
549 nvram_read_u32(prefix, NULL, "legofdmbw20ul5ghpo",
550 &sprom->legofdmbw20ul5ghpo, 0, fallback);
551 nvram_read_u32(prefix, NULL, "mcsbw202gpo", &sprom->mcsbw202gpo, 0,
552 fallback);
553 nvram_read_u32(prefix, NULL, "mcsbw20ul2gpo", &sprom->mcsbw20ul2gpo, 0,
554 fallback);
555 nvram_read_u32(prefix, NULL, "mcsbw402gpo", &sprom->mcsbw402gpo, 0,
556 fallback);
557 nvram_read_u32(prefix, NULL, "mcsbw205glpo", &sprom->mcsbw205glpo, 0,
558 fallback);
559 nvram_read_u32(prefix, NULL, "mcsbw20ul5glpo",
560 &sprom->mcsbw20ul5glpo, 0, fallback);
561 nvram_read_u32(prefix, NULL, "mcsbw405glpo", &sprom->mcsbw405glpo, 0,
562 fallback);
563 nvram_read_u32(prefix, NULL, "mcsbw205gmpo", &sprom->mcsbw205gmpo, 0,
564 fallback);
565 nvram_read_u32(prefix, NULL, "mcsbw20ul5gmpo",
566 &sprom->mcsbw20ul5gmpo, 0, fallback);
567 nvram_read_u32(prefix, NULL, "mcsbw405gmpo", &sprom->mcsbw405gmpo, 0,
568 fallback);
569 nvram_read_u32(prefix, NULL, "mcsbw205ghpo", &sprom->mcsbw205ghpo, 0,
570 fallback);
571 nvram_read_u32(prefix, NULL, "mcsbw20ul5ghpo",
572 &sprom->mcsbw20ul5ghpo, 0, fallback);
573 nvram_read_u32(prefix, NULL, "mcsbw405ghpo", &sprom->mcsbw405ghpo, 0,
574 fallback);
575 nvram_read_u16(prefix, NULL, "mcs32po", &sprom->mcs32po, 0, fallback);
576 nvram_read_u16(prefix, NULL, "legofdm40duppo",
577 &sprom->legofdm40duppo, 0, fallback);
578 nvram_read_u8(prefix, NULL, "sar2g", &sprom->sar2g, 0, fallback);
579 nvram_read_u8(prefix, NULL, "sar5g", &sprom->sar5g, 0, fallback);
580}
581
582static void bcm47xx_fill_sprom_path_r4589(struct ssb_sprom *sprom, 433static void bcm47xx_fill_sprom_path_r4589(struct ssb_sprom *sprom,
583 const char *prefix, bool fallback) 434 const char *prefix, bool fallback)
584{ 435{
@@ -715,10 +566,6 @@ static void bcm47xx_fill_sprom_ethernet(struct ssb_sprom *sprom,
715static void bcm47xx_fill_board_data(struct ssb_sprom *sprom, const char *prefix, 566static void bcm47xx_fill_board_data(struct ssb_sprom *sprom, const char *prefix,
716 bool fallback) 567 bool fallback)
717{ 568{
718 nvram_read_u16(prefix, NULL, "boardrev", &sprom->board_rev, 0, true);
719 nvram_read_u16(prefix, NULL, "boardnum", &sprom->board_num, 0,
720 fallback);
721 nvram_read_u16(prefix, NULL, "boardtype", &sprom->board_type, 0, true);
722 nvram_read_u32_2(prefix, "boardflags", &sprom->boardflags_lo, 569 nvram_read_u32_2(prefix, "boardflags", &sprom->boardflags_lo,
723 &sprom->boardflags_hi, fallback); 570 &sprom->boardflags_hi, fallback);
724 nvram_read_u32_2(prefix, "boardflags2", &sprom->boardflags2_lo, 571 nvram_read_u32_2(prefix, "boardflags2", &sprom->boardflags2_lo,
@@ -736,58 +583,39 @@ void bcm47xx_fill_sprom(struct ssb_sprom *sprom, const char *prefix,
736 switch (sprom->revision) { 583 switch (sprom->revision) {
737 case 1: 584 case 1:
738 bcm47xx_fill_sprom_r1234589(sprom, prefix, fallback); 585 bcm47xx_fill_sprom_r1234589(sprom, prefix, fallback);
739 bcm47xx_fill_sprom_r12389(sprom, prefix, fallback);
740 bcm47xx_fill_sprom_r1(sprom, prefix, fallback);
741 break; 586 break;
742 case 2: 587 case 2:
743 bcm47xx_fill_sprom_r1234589(sprom, prefix, fallback); 588 bcm47xx_fill_sprom_r1234589(sprom, prefix, fallback);
744 bcm47xx_fill_sprom_r12389(sprom, prefix, fallback);
745 bcm47xx_fill_sprom_r2389(sprom, prefix, fallback);
746 break; 589 break;
747 case 3: 590 case 3:
748 bcm47xx_fill_sprom_r1234589(sprom, prefix, fallback); 591 bcm47xx_fill_sprom_r1234589(sprom, prefix, fallback);
749 bcm47xx_fill_sprom_r12389(sprom, prefix, fallback);
750 bcm47xx_fill_sprom_r2389(sprom, prefix, fallback);
751 bcm47xx_fill_sprom_r389(sprom, prefix, fallback);
752 bcm47xx_fill_sprom_r3(sprom, prefix, fallback); 592 bcm47xx_fill_sprom_r3(sprom, prefix, fallback);
753 break; 593 break;
754 case 4: 594 case 4:
755 case 5: 595 case 5:
756 bcm47xx_fill_sprom_r1234589(sprom, prefix, fallback); 596 bcm47xx_fill_sprom_r1234589(sprom, prefix, fallback);
757 bcm47xx_fill_sprom_r4589(sprom, prefix, fallback); 597 bcm47xx_fill_sprom_r4589(sprom, prefix, fallback);
758 bcm47xx_fill_sprom_r458(sprom, prefix, fallback);
759 bcm47xx_fill_sprom_r45(sprom, prefix, fallback);
760 bcm47xx_fill_sprom_path_r4589(sprom, prefix, fallback); 598 bcm47xx_fill_sprom_path_r4589(sprom, prefix, fallback);
761 bcm47xx_fill_sprom_path_r45(sprom, prefix, fallback); 599 bcm47xx_fill_sprom_path_r45(sprom, prefix, fallback);
762 break; 600 break;
763 case 8: 601 case 8:
764 bcm47xx_fill_sprom_r1234589(sprom, prefix, fallback); 602 bcm47xx_fill_sprom_r1234589(sprom, prefix, fallback);
765 bcm47xx_fill_sprom_r12389(sprom, prefix, fallback);
766 bcm47xx_fill_sprom_r2389(sprom, prefix, fallback);
767 bcm47xx_fill_sprom_r389(sprom, prefix, fallback);
768 bcm47xx_fill_sprom_r4589(sprom, prefix, fallback); 603 bcm47xx_fill_sprom_r4589(sprom, prefix, fallback);
769 bcm47xx_fill_sprom_r458(sprom, prefix, fallback);
770 bcm47xx_fill_sprom_r89(sprom, prefix, fallback);
771 bcm47xx_fill_sprom_path_r4589(sprom, prefix, fallback); 604 bcm47xx_fill_sprom_path_r4589(sprom, prefix, fallback);
772 break; 605 break;
773 case 9: 606 case 9:
774 bcm47xx_fill_sprom_r1234589(sprom, prefix, fallback); 607 bcm47xx_fill_sprom_r1234589(sprom, prefix, fallback);
775 bcm47xx_fill_sprom_r12389(sprom, prefix, fallback);
776 bcm47xx_fill_sprom_r2389(sprom, prefix, fallback);
777 bcm47xx_fill_sprom_r389(sprom, prefix, fallback);
778 bcm47xx_fill_sprom_r4589(sprom, prefix, fallback); 608 bcm47xx_fill_sprom_r4589(sprom, prefix, fallback);
779 bcm47xx_fill_sprom_r89(sprom, prefix, fallback);
780 bcm47xx_fill_sprom_r9(sprom, prefix, fallback);
781 bcm47xx_fill_sprom_path_r4589(sprom, prefix, fallback); 609 bcm47xx_fill_sprom_path_r4589(sprom, prefix, fallback);
782 break; 610 break;
783 default: 611 default:
784 pr_warn("Unsupported SPROM revision %d detected. Will extract" 612 pr_warn("Unsupported SPROM revision %d detected. Will extract v1\n",
785 " v1\n", sprom->revision); 613 sprom->revision);
786 sprom->revision = 1; 614 sprom->revision = 1;
787 bcm47xx_fill_sprom_r1234589(sprom, prefix, fallback); 615 bcm47xx_fill_sprom_r1234589(sprom, prefix, fallback);
788 bcm47xx_fill_sprom_r12389(sprom, prefix, fallback);
789 bcm47xx_fill_sprom_r1(sprom, prefix, fallback);
790 } 616 }
617
618 bcm47xx_sprom_fill_auto(sprom, prefix, fallback);
791} 619}
792 620
793#ifdef CONFIG_BCM47XX_SSB 621#ifdef CONFIG_BCM47XX_SSB
@@ -829,13 +657,45 @@ static int bcm47xx_get_sprom_ssb(struct ssb_bus *bus, struct ssb_sprom *out)
829 bcm47xx_fill_sprom(out, prefix, false); 657 bcm47xx_fill_sprom(out, prefix, false);
830 return 0; 658 return 0;
831 } else { 659 } else {
832 pr_warn("bcm47xx: unable to fill SPROM for given bustype.\n"); 660 pr_warn("Unable to fill SPROM for given bustype.\n");
833 return -EINVAL; 661 return -EINVAL;
834 } 662 }
835} 663}
836#endif 664#endif
837 665
838#if defined(CONFIG_BCM47XX_BCMA) 666#if defined(CONFIG_BCM47XX_BCMA)
667/*
668 * Having many NVRAM entries for PCI devices led to repeating prefixes like
669 * pci/1/1/ all the time and wasting flash space. So at some point Broadcom
670 * decided to introduce prefixes like 0: 1: 2: etc.
671 * If we find e.g. devpath0=pci/2/1 or devpath0=pci/2/1/ we should use 0:
672 * instead of pci/2/1/.
673 */
674static void bcm47xx_sprom_apply_prefix_alias(char *prefix, size_t prefix_size)
675{
676 size_t prefix_len = strlen(prefix);
677 size_t short_len = prefix_len - 1;
678 char nvram_var[10];
679 char buf[20];
680 int i;
681
682 /* Passed prefix has to end with a slash */
683 if (prefix_len <= 0 || prefix[prefix_len - 1] != '/')
684 return;
685
686 for (i = 0; i < 3; i++) {
687 if (snprintf(nvram_var, sizeof(nvram_var), "devpath%d", i) <= 0)
688 continue;
689 if (bcm47xx_nvram_getenv(nvram_var, buf, sizeof(buf)) < 0)
690 continue;
691 if (!strcmp(buf, prefix) ||
692 (short_len && strlen(buf) == short_len && !strncmp(buf, prefix, short_len))) {
693 snprintf(prefix, prefix_size, "%d:", i);
694 return;
695 }
696 }
697}
698
839static int bcm47xx_get_sprom_bcma(struct bcma_bus *bus, struct ssb_sprom *out) 699static int bcm47xx_get_sprom_bcma(struct bcma_bus *bus, struct ssb_sprom *out)
840{ 700{
841 char prefix[10]; 701 char prefix[10];
@@ -847,6 +707,7 @@ static int bcm47xx_get_sprom_bcma(struct bcma_bus *bus, struct ssb_sprom *out)
847 snprintf(prefix, sizeof(prefix), "pci/%u/%u/", 707 snprintf(prefix, sizeof(prefix), "pci/%u/%u/",
848 bus->host_pci->bus->number + 1, 708 bus->host_pci->bus->number + 1,
849 PCI_SLOT(bus->host_pci->devfn)); 709 PCI_SLOT(bus->host_pci->devfn));
710 bcm47xx_sprom_apply_prefix_alias(prefix, sizeof(prefix));
850 bcm47xx_fill_sprom(out, prefix, false); 711 bcm47xx_fill_sprom(out, prefix, false);
851 return 0; 712 return 0;
852 case BCMA_HOSTTYPE_SOC: 713 case BCMA_HOSTTYPE_SOC:
@@ -861,7 +722,7 @@ static int bcm47xx_get_sprom_bcma(struct bcma_bus *bus, struct ssb_sprom *out)
861 } 722 }
862 return 0; 723 return 0;
863 default: 724 default:
864 pr_warn("bcm47xx: unable to fill SPROM for given bustype.\n"); 725 pr_warn("Unable to fill SPROM for given bustype.\n");
865 return -EINVAL; 726 return -EINVAL;
866 } 727 }
867} 728}
diff --git a/arch/mips/bcm47xx/time.c b/arch/mips/bcm47xx/time.c
index 2c85d9254b5e..74224cf2e84d 100644
--- a/arch/mips/bcm47xx/time.c
+++ b/arch/mips/bcm47xx/time.c
@@ -22,12 +22,10 @@
22 * 675 Mass Ave, Cambridge, MA 02139, USA. 22 * 675 Mass Ave, Cambridge, MA 02139, USA.
23 */ 23 */
24 24
25
26#include <linux/init.h> 25#include <linux/init.h>
27#include <linux/ssb/ssb.h> 26#include <linux/ssb/ssb.h>
28#include <asm/time.h> 27#include <asm/time.h>
29#include <bcm47xx.h> 28#include <bcm47xx.h>
30#include <bcm47xx_nvram.h>
31#include <bcm47xx_board.h> 29#include <bcm47xx_board.h>
32 30
33void __init plat_time_init(void) 31void __init plat_time_init(void)
diff --git a/arch/mips/bcm63xx/prom.c b/arch/mips/bcm63xx/prom.c
index e1f27d653f60..7019e2967009 100644
--- a/arch/mips/bcm63xx/prom.c
+++ b/arch/mips/bcm63xx/prom.c
@@ -17,7 +17,6 @@
17#include <bcm63xx_cpu.h> 17#include <bcm63xx_cpu.h>
18#include <bcm63xx_io.h> 18#include <bcm63xx_io.h>
19#include <bcm63xx_regs.h> 19#include <bcm63xx_regs.h>
20#include <bcm63xx_gpio.h>
21 20
22void __init prom_init(void) 21void __init prom_init(void)
23{ 22{
@@ -53,9 +52,6 @@ void __init prom_init(void)
53 reg &= ~mask; 52 reg &= ~mask;
54 bcm_perf_writel(reg, PERF_CKCTL_REG); 53 bcm_perf_writel(reg, PERF_CKCTL_REG);
55 54
56 /* register gpiochip */
57 bcm63xx_gpio_init();
58
59 /* do low level board init */ 55 /* do low level board init */
60 board_prom_init(); 56 board_prom_init();
61 57
diff --git a/arch/mips/bcm63xx/setup.c b/arch/mips/bcm63xx/setup.c
index 6660c7ddf87b..240fb4ffa55c 100644
--- a/arch/mips/bcm63xx/setup.c
+++ b/arch/mips/bcm63xx/setup.c
@@ -20,6 +20,7 @@
20#include <bcm63xx_cpu.h> 20#include <bcm63xx_cpu.h>
21#include <bcm63xx_regs.h> 21#include <bcm63xx_regs.h>
22#include <bcm63xx_io.h> 22#include <bcm63xx_io.h>
23#include <bcm63xx_gpio.h>
23 24
24void bcm63xx_machine_halt(void) 25void bcm63xx_machine_halt(void)
25{ 26{
@@ -160,6 +161,9 @@ void __init plat_mem_setup(void)
160 161
161int __init bcm63xx_register_devices(void) 162int __init bcm63xx_register_devices(void)
162{ 163{
164 /* register gpiochip */
165 bcm63xx_gpio_init();
166
163 return board_register_devices(); 167 return board_register_devices();
164} 168}
165 169
diff --git a/arch/mips/bmips/Kconfig b/arch/mips/bmips/Kconfig
new file mode 100644
index 000000000000..f35c84c019df
--- /dev/null
+++ b/arch/mips/bmips/Kconfig
@@ -0,0 +1,62 @@
1if BMIPS_GENERIC
2
3choice
4 prompt "Built-in device tree"
5 help
6 Legacy bootloaders do not pass a DTB pointer to the kernel, so
7 if a "wrapper" is not being used, the kernel will need to include
8 a device tree that matches the target board.
9
10 The builtin DTB will only be used if the firmware does not supply
11 a valid DTB.
12
13config DT_NONE
14 bool "None"
15
16config DT_BCM93384WVG
17 bool "BCM93384WVG Zephyr CPU"
18 select BUILTIN_DTB
19
20config DT_BCM93384WVG_VIPER
21 bool "BCM93384WVG Viper CPU (EXPERIMENTAL)"
22 select BUILTIN_DTB
23
24config DT_BCM96368MVWG
25 bool "BCM96368MVWG"
26 select BUILTIN_DTB
27
28config DT_BCM9EJTAGPRB
29 bool "BCM9EJTAGPRB"
30 select BUILTIN_DTB
31
32config DT_BCM97125CBMB
33 bool "BCM97125CBMB"
34 select BUILTIN_DTB
35
36config DT_BCM97346DBSMB
37 bool "BCM97346DBSMB"
38 select BUILTIN_DTB
39
40config DT_BCM97358SVMB
41 bool "BCM97358SVMB"
42 select BUILTIN_DTB
43
44config DT_BCM97360SVMB
45 bool "BCM97360SVMB"
46 select BUILTIN_DTB
47
48config DT_BCM97362SVMB
49 bool "BCM97362SVMB"
50 select BUILTIN_DTB
51
52config DT_BCM97420C
53 bool "BCM97420C"
54 select BUILTIN_DTB
55
56config DT_BCM97425SVMB
57 bool "BCM97425SVMB"
58 select BUILTIN_DTB
59
60endchoice
61
62endif
diff --git a/arch/mips/bcm3384/Makefile b/arch/mips/bmips/Makefile
index a393955cba08..a393955cba08 100644
--- a/arch/mips/bcm3384/Makefile
+++ b/arch/mips/bmips/Makefile
diff --git a/arch/mips/bmips/Platform b/arch/mips/bmips/Platform
new file mode 100644
index 000000000000..5f127fd7f4b5
--- /dev/null
+++ b/arch/mips/bmips/Platform
@@ -0,0 +1,7 @@
1#
2# Broadcom Generic BMIPS kernel
3#
4platform-$(CONFIG_BMIPS_GENERIC) += bmips/
5cflags-$(CONFIG_BMIPS_GENERIC) += \
6 -I$(srctree)/arch/mips/include/asm/mach-bmips/
7load-$(CONFIG_BMIPS_GENERIC) := 0xffffffff80010000
diff --git a/arch/mips/bmips/dma.c b/arch/mips/bmips/dma.c
new file mode 100644
index 000000000000..04790f4e1805
--- /dev/null
+++ b/arch/mips/bmips/dma.c
@@ -0,0 +1,117 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2014 Kevin Cernekee <cernekee@gmail.com>
7 */
8
9#define pr_fmt(fmt) "bmips-dma: " fmt
10
11#include <linux/device.h>
12#include <linux/dma-direction.h>
13#include <linux/dma-mapping.h>
14#include <linux/init.h>
15#include <linux/io.h>
16#include <linux/of.h>
17#include <linux/printk.h>
18#include <linux/slab.h>
19#include <linux/types.h>
20#include <dma-coherence.h>
21
22/*
23 * BCM338x has configurable address translation windows which allow the
24 * peripherals' DMA addresses to be different from the Zephyr-visible
25 * physical addresses. e.g. usb_dma_addr = zephyr_pa ^ 0x08000000
26 *
27 * If the "brcm,ubus" node has a "dma-ranges" property we will enable this
28 * translation globally using the provided information. This implements a
29 * very limited subset of "dma-ranges" support and it will probably be
30 * replaced by a more generic version later.
31 */
32
33struct bmips_dma_range {
34 u32 child_addr;
35 u32 parent_addr;
36 u32 size;
37};
38
39static struct bmips_dma_range *bmips_dma_ranges;
40
41#define FLUSH_RAC 0x100
42
43static dma_addr_t bmips_phys_to_dma(struct device *dev, phys_addr_t pa)
44{
45 struct bmips_dma_range *r;
46
47 for (r = bmips_dma_ranges; r && r->size; r++) {
48 if (pa >= r->child_addr &&
49 pa < (r->child_addr + r->size))
50 return pa - r->child_addr + r->parent_addr;
51 }
52 return pa;
53}
54
55dma_addr_t plat_map_dma_mem(struct device *dev, void *addr, size_t size)
56{
57 return bmips_phys_to_dma(dev, virt_to_phys(addr));
58}
59
60dma_addr_t plat_map_dma_mem_page(struct device *dev, struct page *page)
61{
62 return bmips_phys_to_dma(dev, page_to_phys(page));
63}
64
65unsigned long plat_dma_addr_to_phys(struct device *dev, dma_addr_t dma_addr)
66{
67 struct bmips_dma_range *r;
68
69 for (r = bmips_dma_ranges; r && r->size; r++) {
70 if (dma_addr >= r->parent_addr &&
71 dma_addr < (r->parent_addr + r->size))
72 return dma_addr - r->parent_addr + r->child_addr;
73 }
74 return dma_addr;
75}
76
77static int __init bmips_init_dma_ranges(void)
78{
79 struct device_node *np =
80 of_find_compatible_node(NULL, NULL, "brcm,ubus");
81 const __be32 *data;
82 struct bmips_dma_range *r;
83 int len;
84
85 if (!np)
86 return 0;
87
88 data = of_get_property(np, "dma-ranges", &len);
89 if (!data)
90 goto out_good;
91
92 len /= sizeof(*data) * 3;
93 if (!len)
94 goto out_bad;
95
96 /* add a dummy (zero) entry at the end as a sentinel */
97 bmips_dma_ranges = kzalloc(sizeof(struct bmips_dma_range) * (len + 1),
98 GFP_KERNEL);
99 if (!bmips_dma_ranges)
100 goto out_bad;
101
102 for (r = bmips_dma_ranges; len; len--, r++) {
103 r->child_addr = be32_to_cpup(data++);
104 r->parent_addr = be32_to_cpup(data++);
105 r->size = be32_to_cpup(data++);
106 }
107
108out_good:
109 of_node_put(np);
110 return 0;
111
112out_bad:
113 pr_err("error parsing dma-ranges property\n");
114 of_node_put(np);
115 return -EINVAL;
116}
117arch_initcall(bmips_init_dma_ranges);
diff --git a/arch/mips/bmips/irq.c b/arch/mips/bmips/irq.c
new file mode 100644
index 000000000000..14552e58ff7e
--- /dev/null
+++ b/arch/mips/bmips/irq.c
@@ -0,0 +1,38 @@
1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License version 2 as published
4 * by the Free Software Foundation.
5 *
6 * Copyright (C) 2014 Broadcom Corporation
7 * Author: Kevin Cernekee <cernekee@gmail.com>
8 */
9
10#include <linux/of.h>
11#include <linux/irqchip.h>
12
13#include <asm/bmips.h>
14#include <asm/irq.h>
15#include <asm/irq_cpu.h>
16#include <asm/time.h>
17
18unsigned int get_c0_compare_int(void)
19{
20 return CP0_LEGACY_COMPARE_IRQ;
21}
22
23void __init arch_init_irq(void)
24{
25 struct device_node *dn;
26
27 /* Only the STB (bcm7038) controller supports SMP IRQ affinity */
28 dn = of_find_compatible_node(NULL, NULL, "brcm,bcm7038-l1-intc");
29 if (dn)
30 of_node_put(dn);
31 else
32 bmips_tp1_irqs = 0;
33
34 irqchip_init();
35}
36
37OF_DECLARE_2(irqchip, mips_cpu_intc, "mti,cpu-interrupt-controller",
38 mips_cpu_irq_of_init);
diff --git a/arch/mips/bmips/setup.c b/arch/mips/bmips/setup.c
new file mode 100644
index 000000000000..fae800e8b1e1
--- /dev/null
+++ b/arch/mips/bmips/setup.c
@@ -0,0 +1,194 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
7 * Copyright (C) 2014 Kevin Cernekee <cernekee@gmail.com>
8 */
9
10#include <linux/init.h>
11#include <linux/bitops.h>
12#include <linux/bootmem.h>
13#include <linux/clk-provider.h>
14#include <linux/ioport.h>
15#include <linux/kernel.h>
16#include <linux/io.h>
17#include <linux/of.h>
18#include <linux/of_fdt.h>
19#include <linux/of_platform.h>
20#include <linux/smp.h>
21#include <asm/addrspace.h>
22#include <asm/bmips.h>
23#include <asm/bootinfo.h>
24#include <asm/cpu-type.h>
25#include <asm/mipsregs.h>
26#include <asm/prom.h>
27#include <asm/smp-ops.h>
28#include <asm/time.h>
29#include <asm/traps.h>
30
31#define RELO_NORMAL_VEC BIT(18)
32
33#define REG_BCM6328_OTP ((void __iomem *)CKSEG1ADDR(0x1000062c))
34#define BCM6328_TP1_DISABLED BIT(9)
35
36static const unsigned long kbase = VMLINUX_LOAD_ADDRESS & 0xfff00000;
37
38struct bmips_quirk {
39 const char *compatible;
40 void (*quirk_fn)(void);
41};
42
43static void kbase_setup(void)
44{
45 __raw_writel(kbase | RELO_NORMAL_VEC,
46 BMIPS_GET_CBR() + BMIPS_RELO_VECTOR_CONTROL_1);
47 ebase = kbase;
48}
49
50static void bcm3384_viper_quirks(void)
51{
52 /*
53 * Some experimental CM boxes are set up to let CM own the Viper TP0
54 * and let Linux own TP1. This requires moving the kernel
55 * load address to a non-conflicting region (e.g. via
56 * CONFIG_PHYSICAL_START) and supplying an alternate DTB.
57 * If we detect this condition, we need to move the MIPS exception
58 * vectors up to an area that we own.
59 *
60 * This is distinct from the OTHER special case mentioned in
61 * smp-bmips.c (boot on TP1, but enable SMP, then TP0 becomes our
62 * logical CPU#1). For the Viper TP1 case, SMP is off limits.
63 *
64 * Also note that many BMIPS435x CPUs do not have a
65 * BMIPS_RELO_VECTOR_CONTROL_1 register, so it isn't safe to just
66 * write VMLINUX_LOAD_ADDRESS into that register on every SoC.
67 */
68 board_ebase_setup = &kbase_setup;
69 bmips_smp_enabled = 0;
70}
71
72static void bcm63xx_fixup_cpu1(void)
73{
74 /*
75 * The bootloader has set up the CPU1 reset vector at
76 * 0xa000_0200.
77 * This conflicts with the special interrupt vector (IV).
78 * The bootloader has also set up CPU1 to respond to the wrong
79 * IPI interrupt.
80 * Here we will start up CPU1 in the background and ask it to
81 * reconfigure itself then go back to sleep.
82 */
83 memcpy((void *)0xa0000200, &bmips_smp_movevec, 0x20);
84 __sync();
85 set_c0_cause(C_SW0);
86 cpumask_set_cpu(1, &bmips_booted_mask);
87}
88
89static void bcm6328_quirks(void)
90{
91 /* Check CPU1 status in OTP (it is usually disabled) */
92 if (__raw_readl(REG_BCM6328_OTP) & BCM6328_TP1_DISABLED)
93 bmips_smp_enabled = 0;
94 else
95 bcm63xx_fixup_cpu1();
96}
97
98static void bcm6368_quirks(void)
99{
100 bcm63xx_fixup_cpu1();
101}
102
103static const struct bmips_quirk bmips_quirk_list[] = {
104 { "brcm,bcm3384-viper", &bcm3384_viper_quirks },
105 { "brcm,bcm33843-viper", &bcm3384_viper_quirks },
106 { "brcm,bcm6328", &bcm6328_quirks },
107 { "brcm,bcm6368", &bcm6368_quirks },
108 { },
109};
110
111void __init prom_init(void)
112{
113 register_bmips_smp_ops();
114}
115
116void __init prom_free_prom_memory(void)
117{
118}
119
120const char *get_system_type(void)
121{
122 return "Generic BMIPS kernel";
123}
124
125void __init plat_time_init(void)
126{
127 struct device_node *np;
128 u32 freq;
129
130 np = of_find_node_by_name(NULL, "cpus");
131 if (!np)
132 panic("missing 'cpus' DT node");
133 if (of_property_read_u32(np, "mips-hpt-frequency", &freq) < 0)
134 panic("missing 'mips-hpt-frequency' property");
135 of_node_put(np);
136
137 mips_hpt_frequency = freq;
138}
139
140void __init plat_mem_setup(void)
141{
142 void *dtb;
143 const struct bmips_quirk *q;
144
145 set_io_port_base(0);
146 ioport_resource.start = 0;
147 ioport_resource.end = ~0;
148
149 /* intended to somewhat resemble ARM; see Documentation/arm/Booting */
150 if (fw_arg0 == 0 && fw_arg1 == 0xffffffff)
151 dtb = phys_to_virt(fw_arg2);
152 else if (__dtb_start != __dtb_end)
153 dtb = (void *)__dtb_start;
154 else
155 panic("no dtb found");
156
157 __dt_setup_arch(dtb);
158 strlcpy(arcs_cmdline, boot_command_line, COMMAND_LINE_SIZE);
159
160 for (q = bmips_quirk_list; q->quirk_fn; q++) {
161 if (of_flat_dt_is_compatible(of_get_flat_dt_root(),
162 q->compatible)) {
163 q->quirk_fn();
164 }
165 }
166}
167
168void __init device_tree_init(void)
169{
170 struct device_node *np;
171
172 unflatten_and_copy_device_tree();
173
174 /* Disable SMP boot unless both CPUs are listed in DT and !disabled */
175 np = of_find_node_by_name(NULL, "cpus");
176 if (np && of_get_available_child_count(np) <= 1)
177 bmips_smp_enabled = 0;
178 of_node_put(np);
179}
180
181int __init plat_of_setup(void)
182{
183 return __dt_register_buses("simple-bus", NULL);
184}
185
186arch_initcall(plat_of_setup);
187
188static int __init plat_dev_init(void)
189{
190 of_clk_init(NULL);
191 return 0;
192}
193
194device_initcall(plat_dev_init);
diff --git a/arch/mips/boot/compressed/Makefile b/arch/mips/boot/compressed/Makefile
index 61af6b6ab13d..dc91bde10d62 100644
--- a/arch/mips/boot/compressed/Makefile
+++ b/arch/mips/boot/compressed/Makefile
@@ -12,6 +12,8 @@
12# Author: Wu Zhangjin <wuzhangjin@gmail.com> 12# Author: Wu Zhangjin <wuzhangjin@gmail.com>
13# 13#
14 14
15include $(srctree)/arch/mips/Kbuild.platforms
16
15# set the default size of the mallocing area for decompressing 17# set the default size of the mallocing area for decompressing
16BOOT_HEAP_SIZE := 0x400000 18BOOT_HEAP_SIZE := 0x400000
17 19
@@ -30,9 +32,10 @@ KBUILD_AFLAGS := $(LINUXINCLUDE) $(KBUILD_AFLAGS) -D__ASSEMBLY__ \
30targets := head.o decompress.o string.o dbg.o uart-16550.o uart-alchemy.o 32targets := head.o decompress.o string.o dbg.o uart-16550.o uart-alchemy.o
31 33
32# decompressor objects (linked with vmlinuz) 34# decompressor objects (linked with vmlinuz)
33vmlinuzobjs-y := $(obj)/head.o $(obj)/decompress.o $(obj)/string.o $(obj)/dbg.o 35vmlinuzobjs-y := $(obj)/head.o $(obj)/decompress.o $(obj)/string.o
34 36
35ifdef CONFIG_DEBUG_ZBOOT 37ifdef CONFIG_DEBUG_ZBOOT
38vmlinuzobjs-$(CONFIG_DEBUG_ZBOOT) += $(obj)/dbg.o
36vmlinuzobjs-$(CONFIG_SYS_SUPPORTS_ZBOOT_UART16550) += $(obj)/uart-16550.o 39vmlinuzobjs-$(CONFIG_SYS_SUPPORTS_ZBOOT_UART16550) += $(obj)/uart-16550.o
37vmlinuzobjs-$(CONFIG_MIPS_ALCHEMY) += $(obj)/uart-alchemy.o 40vmlinuzobjs-$(CONFIG_MIPS_ALCHEMY) += $(obj)/uart-alchemy.o
38endif 41endif
@@ -66,8 +69,8 @@ $(obj)/piggy.o: $(obj)/dummy.o $(obj)/vmlinux.bin.z FORCE
66# Calculate the load address of the compressed kernel image 69# Calculate the load address of the compressed kernel image
67hostprogs-y := calc_vmlinuz_load_addr 70hostprogs-y := calc_vmlinuz_load_addr
68 71
69ifeq ($(CONFIG_MACH_JZ4740),y) 72ifneq ($(zload-y),)
70VMLINUZ_LOAD_ADDRESS := 0x80600000 73VMLINUZ_LOAD_ADDRESS := $(zload-y)
71else 74else
72VMLINUZ_LOAD_ADDRESS = $(shell $(obj)/calc_vmlinuz_load_addr \ 75VMLINUZ_LOAD_ADDRESS = $(shell $(obj)/calc_vmlinuz_load_addr \
73 $(obj)/vmlinux.bin $(VMLINUX_LOAD_ADDRESS)) 76 $(obj)/vmlinux.bin $(VMLINUX_LOAD_ADDRESS))
diff --git a/arch/mips/boot/compressed/decompress.c b/arch/mips/boot/compressed/decompress.c
index 31903cf9709d..54831069a206 100644
--- a/arch/mips/boot/compressed/decompress.c
+++ b/arch/mips/boot/compressed/decompress.c
@@ -28,8 +28,13 @@ unsigned long free_mem_end_ptr;
28extern unsigned char __image_begin, __image_end; 28extern unsigned char __image_begin, __image_end;
29 29
30/* debug interfaces */ 30/* debug interfaces */
31#ifdef CONFIG_DEBUG_ZBOOT
31extern void puts(const char *s); 32extern void puts(const char *s);
32extern void puthex(unsigned long long val); 33extern void puthex(unsigned long long val);
34#else
35#define puts(s) do {} while (0)
36#define puthex(val) do {} while (0)
37#endif
33 38
34void error(char *x) 39void error(char *x)
35{ 40{
diff --git a/arch/mips/boot/dts/Makefile b/arch/mips/boot/dts/Makefile
index 4f49fa477f14..5d95e4bd709a 100644
--- a/arch/mips/boot/dts/Makefile
+++ b/arch/mips/boot/dts/Makefile
@@ -1,21 +1,12 @@
1dtb-$(CONFIG_BCM3384) += bcm93384wvg.dtb 1dts-dirs += brcm
2dtb-$(CONFIG_CAVIUM_OCTEON_SOC) += octeon_3xxx.dtb octeon_68xx.dtb 2dts-dirs += cavium-octeon
3dtb-$(CONFIG_DT_EASY50712) += easy50712.dtb 3dts-dirs += lantiq
4dtb-$(CONFIG_DT_XLP_EVP) += xlp_evp.dtb 4dts-dirs += mti
5dtb-$(CONFIG_DT_XLP_SVP) += xlp_svp.dtb 5dts-dirs += netlogic
6dtb-$(CONFIG_DT_XLP_FVP) += xlp_fvp.dtb 6dts-dirs += ralink
7dtb-$(CONFIG_DT_XLP_GVP) += xlp_gvp.dtb 7
8dtb-$(CONFIG_DTB_RT2880_EVAL) += rt2880_eval.dtb 8obj-y := $(addsuffix /, $(dts-dirs))
9dtb-$(CONFIG_DTB_RT305X_EVAL) += rt3052_eval.dtb 9
10dtb-$(CONFIG_DTB_RT3883_EVAL) += rt3883_eval.dtb 10always := $(dtb-y)
11dtb-$(CONFIG_DTB_MT7620A_EVAL) += mt7620a_eval.dtb 11subdir-y := $(dts-dirs)
12dtb-$(CONFIG_MIPS_SEAD3) += sead3.dtb 12clean-files := *.dtb *.dtb.S
13
14obj-y += $(patsubst %.dtb, %.dtb.o, $(dtb-y))
15
16targets += dtbs
17targets += $(dtb-y)
18
19dtbs: $(addprefix $(obj)/, $(dtb-y))
20
21clean-files += *.dtb *.dtb.S
diff --git a/arch/mips/boot/dts/bcm3384.dtsi b/arch/mips/boot/dts/bcm3384.dtsi
deleted file mode 100644
index 21b074a99c94..000000000000
--- a/arch/mips/boot/dts/bcm3384.dtsi
+++ /dev/null
@@ -1,109 +0,0 @@
1/ {
2 #address-cells = <1>;
3 #size-cells = <1>;
4 compatible = "brcm,bcm3384", "brcm,bcm33843";
5
6 cpus {
7 #address-cells = <1>;
8 #size-cells = <0>;
9
10 /* On BMIPS5000 this is 1/8th of the CPU core clock */
11 mips-hpt-frequency = <100000000>;
12
13 cpu@0 {
14 compatible = "brcm,bmips5000";
15 device_type = "cpu";
16 reg = <0>;
17 };
18
19 cpu@1 {
20 compatible = "brcm,bmips5000";
21 device_type = "cpu";
22 reg = <1>;
23 };
24 };
25
26 clocks {
27 #address-cells = <1>;
28 #size-cells = <0>;
29
30 periph_clk: periph_clk@0 {
31 compatible = "fixed-clock";
32 #clock-cells = <0>;
33 clock-frequency = <54000000>;
34 };
35 };
36
37 aliases {
38 uart0 = &uart0;
39 };
40
41 cpu_intc: cpu_intc@0 {
42 #address-cells = <0>;
43 compatible = "mti,cpu-interrupt-controller";
44
45 interrupt-controller;
46 #interrupt-cells = <1>;
47 };
48
49 periph_intc: periph_intc@14e00038 {
50 compatible = "brcm,bcm3384-intc";
51 reg = <0x14e00038 0x8 0x14e00340 0x8>;
52
53 interrupt-controller;
54 #interrupt-cells = <1>;
55
56 interrupt-parent = <&cpu_intc>;
57 interrupts = <4>;
58 };
59
60 zmips_intc: zmips_intc@104b0060 {
61 compatible = "brcm,bcm3384-intc";
62 reg = <0x104b0060 0x8>;
63
64 interrupt-controller;
65 #interrupt-cells = <1>;
66
67 interrupt-parent = <&periph_intc>;
68 interrupts = <29>;
69 };
70
71 iop_intc: iop_intc@14e00058 {
72 compatible = "brcm,bcm3384-intc";
73 reg = <0x14e00058 0x8>;
74
75 interrupt-controller;
76 #interrupt-cells = <1>;
77
78 interrupt-parent = <&cpu_intc>;
79 interrupts = <6>;
80 };
81
82 uart0: serial@14e00520 {
83 compatible = "brcm,bcm6345-uart";
84 reg = <0x14e00520 0x18>;
85 interrupt-parent = <&periph_intc>;
86 interrupts = <2>;
87 clocks = <&periph_clk>;
88 status = "disabled";
89 };
90
91 ehci0: usb@15400300 {
92 compatible = "brcm,bcm3384-ehci", "generic-ehci";
93 reg = <0x15400300 0x100>;
94 big-endian;
95 interrupt-parent = <&periph_intc>;
96 interrupts = <41>;
97 status = "disabled";
98 };
99
100 ohci0: usb@15400400 {
101 compatible = "brcm,bcm3384-ohci", "generic-ohci";
102 reg = <0x15400400 0x100>;
103 big-endian;
104 no-big-frame-no;
105 interrupt-parent = <&periph_intc>;
106 interrupts = <40>;
107 status = "disabled";
108 };
109};
diff --git a/arch/mips/boot/dts/brcm/Makefile b/arch/mips/boot/dts/brcm/Makefile
new file mode 100644
index 000000000000..1c8353bfe003
--- /dev/null
+++ b/arch/mips/boot/dts/brcm/Makefile
@@ -0,0 +1,19 @@
1dtb-$(CONFIG_DT_BCM93384WVG) += bcm93384wvg.dtb
2dtb-$(CONFIG_DT_BCM93384WVG_VIPER) += bcm93384wvg_viper.dtb
3dtb-$(CONFIG_DT_BCM96368MVWG) += bcm96368mvwg.dtb
4dtb-$(CONFIG_DT_BCM9EJTAGPRB) += bcm9ejtagprb.dtb
5dtb-$(CONFIG_DT_BCM97125CBMB) += bcm97125cbmb.dtb
6dtb-$(CONFIG_DT_BCM97346DBSMB) += bcm97346dbsmb.dtb
7dtb-$(CONFIG_DT_BCM97358SVMB) += bcm97358svmb.dtb
8dtb-$(CONFIG_DT_BCM97360SVMB) += bcm97360svmb.dtb
9dtb-$(CONFIG_DT_BCM97362SVMB) += bcm97362svmb.dtb
10dtb-$(CONFIG_DT_BCM97420C) += bcm97420c.dtb
11dtb-$(CONFIG_DT_BCM97425SVMB) += bcm97425svmb.dtb
12
13obj-y += $(patsubst %.dtb, %.dtb.o, $(dtb-y))
14
15# Force kbuild to make empty built-in.o if necessary
16obj- += dummy.o
17
18always := $(dtb-y)
19clean-files := *.dtb *.dtb.S
diff --git a/arch/mips/boot/dts/brcm/bcm3384_viper.dtsi b/arch/mips/boot/dts/brcm/bcm3384_viper.dtsi
new file mode 100644
index 000000000000..aa406b43c65f
--- /dev/null
+++ b/arch/mips/boot/dts/brcm/bcm3384_viper.dtsi
@@ -0,0 +1,108 @@
1/ {
2 #address-cells = <1>;
3 #size-cells = <1>;
4 compatible = "brcm,bcm3384-viper", "brcm,bcm33843-viper";
5
6 memory@0 {
7 device_type = "memory";
8
9 /* Typical ranges. The bootloader should fill these in. */
10 reg = <0x06000000 0x02000000>,
11 <0x0e000000 0x02000000>;
12 };
13
14 cpus {
15 #address-cells = <1>;
16 #size-cells = <0>;
17
18 /* 1/2 of the CPU core clock (standard MIPS behavior) */
19 mips-hpt-frequency = <300000000>;
20
21 cpu@0 {
22 compatible = "brcm,bmips4350";
23 device_type = "cpu";
24 reg = <0>;
25 };
26 };
27
28 cpu_intc: cpu_intc {
29 #address-cells = <0>;
30 compatible = "mti,cpu-interrupt-controller";
31
32 interrupt-controller;
33 #interrupt-cells = <1>;
34 };
35
36 clocks {
37 periph_clk: periph_clk {
38 compatible = "fixed-clock";
39 #clock-cells = <0>;
40 clock-frequency = <54000000>;
41 };
42 };
43
44 aliases {
45 uart0 = &uart0;
46 };
47
48 ubus {
49 #address-cells = <1>;
50 #size-cells = <1>;
51
52 compatible = "brcm,ubus", "simple-bus";
53 ranges;
54 /* No dma-ranges on Viper. */
55
56 periph_intc: periph_intc@14e00048 {
57 compatible = "brcm,bcm3380-l2-intc";
58 reg = <0x14e00048 0x4 0x14e0004c 0x4>,
59 <0x14e00350 0x4 0x14e00354 0x4>;
60
61 interrupt-controller;
62 #interrupt-cells = <1>;
63
64 interrupt-parent = <&cpu_intc>;
65 interrupts = <4>;
66 };
67
68 cmips_intc: cmips_intc@151f8048 {
69 compatible = "brcm,bcm3380-l2-intc";
70 reg = <0x151f8048 0x4 0x151f804c 0x4>;
71
72 interrupt-controller;
73 #interrupt-cells = <1>;
74
75 interrupt-parent = <&periph_intc>;
76 interrupts = <30>;
77 brcm,int-map-mask = <0xffffffff>;
78 };
79
80 uart0: serial@14e00520 {
81 compatible = "brcm,bcm6345-uart";
82 reg = <0x14e00520 0x18>;
83 interrupt-parent = <&periph_intc>;
84 interrupts = <2>;
85 clocks = <&periph_clk>;
86 status = "disabled";
87 };
88
89 ehci0: usb@15400300 {
90 compatible = "brcm,bcm3384-ehci", "generic-ehci";
91 reg = <0x15400300 0x100>;
92 big-endian;
93 interrupt-parent = <&periph_intc>;
94 interrupts = <41>;
95 status = "disabled";
96 };
97
98 ohci0: usb@15400400 {
99 compatible = "brcm,bcm3384-ohci", "generic-ohci";
100 reg = <0x15400400 0x100>;
101 big-endian;
102 no-big-frame-no;
103 interrupt-parent = <&periph_intc>;
104 interrupts = <40>;
105 status = "disabled";
106 };
107 };
108};
diff --git a/arch/mips/boot/dts/brcm/bcm3384_zephyr.dtsi b/arch/mips/boot/dts/brcm/bcm3384_zephyr.dtsi
new file mode 100644
index 000000000000..a7bd8564e9f6
--- /dev/null
+++ b/arch/mips/boot/dts/brcm/bcm3384_zephyr.dtsi
@@ -0,0 +1,126 @@
1/ {
2 #address-cells = <1>;
3 #size-cells = <1>;
4 compatible = "brcm,bcm3384", "brcm,bcm33843";
5
6 memory@0 {
7 device_type = "memory";
8
9 /* Typical range. The bootloader should fill this in. */
10 reg = <0x0 0x08000000>;
11 };
12
13 cpus {
14 #address-cells = <1>;
15 #size-cells = <0>;
16
17 /* On BMIPS5000 this is 1/8th of the CPU core clock */
18 mips-hpt-frequency = <100000000>;
19
20 cpu@0 {
21 compatible = "brcm,bmips5000";
22 device_type = "cpu";
23 reg = <0>;
24 };
25
26 cpu@1 {
27 compatible = "brcm,bmips5000";
28 device_type = "cpu";
29 reg = <1>;
30 };
31 };
32
33 cpu_intc: cpu_intc {
34 #address-cells = <0>;
35 compatible = "mti,cpu-interrupt-controller";
36
37 interrupt-controller;
38 #interrupt-cells = <1>;
39 };
40
41 clocks {
42 periph_clk: periph_clk {
43 compatible = "fixed-clock";
44 #clock-cells = <0>;
45 clock-frequency = <54000000>;
46 };
47 };
48
49 aliases {
50 uart0 = &uart0;
51 };
52
53 ubus {
54 #address-cells = <1>;
55 #size-cells = <1>;
56
57 compatible = "brcm,ubus", "simple-bus";
58 ranges;
59 dma-ranges = <0x00000000 0x08000000 0x08000000>,
60 <0x08000000 0x00000000 0x08000000>;
61
62 periph_intc: periph_intc@14e00038 {
63 compatible = "brcm,bcm3380-l2-intc";
64 reg = <0x14e00038 0x4 0x14e0003c 0x4>,
65 <0x14e00340 0x4 0x14e00344 0x4>;
66
67 interrupt-controller;
68 #interrupt-cells = <1>;
69
70 interrupt-parent = <&cpu_intc>;
71 interrupts = <4>;
72 };
73
74 zmips_intc: zmips_intc@104b0060 {
75 compatible = "brcm,bcm3380-l2-intc";
76 reg = <0x104b0060 0x4 0x104b0064 0x4>;
77
78 interrupt-controller;
79 #interrupt-cells = <1>;
80
81 interrupt-parent = <&periph_intc>;
82 interrupts = <29>;
83 brcm,int-map-mask = <0xffffffff>;
84 };
85
86 iop_intc: iop_intc@14e00058 {
87 compatible = "brcm,bcm3380-l2-intc";
88 reg = <0x14e00058 0x4 0x14e0005c 0x4>;
89
90 interrupt-controller;
91 #interrupt-cells = <1>;
92
93 interrupt-parent = <&cpu_intc>;
94 interrupts = <6>;
95 brcm,int-map-mask = <0xffffffff>;
96 };
97
98 uart0: serial@14e00520 {
99 compatible = "brcm,bcm6345-uart";
100 reg = <0x14e00520 0x18>;
101 interrupt-parent = <&periph_intc>;
102 interrupts = <2>;
103 clocks = <&periph_clk>;
104 status = "disabled";
105 };
106
107 ehci0: usb@15400300 {
108 compatible = "brcm,bcm3384-ehci", "generic-ehci";
109 reg = <0x15400300 0x100>;
110 big-endian;
111 interrupt-parent = <&periph_intc>;
112 interrupts = <41>;
113 status = "disabled";
114 };
115
116 ohci0: usb@15400400 {
117 compatible = "brcm,bcm3384-ohci", "generic-ohci";
118 reg = <0x15400400 0x100>;
119 big-endian;
120 no-big-frame-no;
121 interrupt-parent = <&periph_intc>;
122 interrupts = <40>;
123 status = "disabled";
124 };
125 };
126};
diff --git a/arch/mips/boot/dts/brcm/bcm6328.dtsi b/arch/mips/boot/dts/brcm/bcm6328.dtsi
new file mode 100644
index 000000000000..41891c1e58bd
--- /dev/null
+++ b/arch/mips/boot/dts/brcm/bcm6328.dtsi
@@ -0,0 +1,86 @@
1/ {
2 #address-cells = <1>;
3 #size-cells = <1>;
4 compatible = "brcm,bcm6328";
5
6 cpus {
7 #address-cells = <1>;
8 #size-cells = <0>;
9
10 mips-hpt-frequency = <160000000>;
11
12 cpu@0 {
13 compatible = "brcm,bmips4350";
14 device_type = "cpu";
15 reg = <0>;
16 };
17
18 cpu@1 {
19 compatible = "brcm,bmips4350";
20 device_type = "cpu";
21 reg = <1>;
22 };
23 };
24
25 clocks {
26 periph_clk: periph_clk {
27 compatible = "fixed-clock";
28 #clock-cells = <0>;
29 clock-frequency = <50000000>;
30 };
31 };
32
33 aliases {
34 uart0 = &uart0;
35 };
36
37 cpu_intc: cpu_intc {
38 #address-cells = <0>;
39 compatible = "mti,cpu-interrupt-controller";
40
41 interrupt-controller;
42 #interrupt-cells = <1>;
43 };
44
45 ubus {
46 #address-cells = <1>;
47 #size-cells = <1>;
48
49 compatible = "simple-bus";
50 ranges;
51
52 periph_intc: periph_intc@10000020 {
53 compatible = "brcm,bcm3380-l2-intc";
54 reg = <0x10000024 0x4 0x1000002c 0x4>,
55 <0x10000020 0x4 0x10000028 0x4>;
56
57 interrupt-controller;
58 #interrupt-cells = <1>;
59
60 interrupt-parent = <&cpu_intc>;
61 interrupts = <2>;
62 };
63
64 uart0: serial@10000100 {
65 compatible = "brcm,bcm6345-uart";
66 reg = <0x10000100 0x18>;
67 interrupt-parent = <&periph_intc>;
68 interrupts = <28>;
69 clocks = <&periph_clk>;
70 status = "disabled";
71 };
72
73 timer: timer@10000040 {
74 compatible = "syscon";
75 reg = <0x10000040 0x2c>;
76 little-endian;
77 };
78
79 reboot {
80 compatible = "syscon-reboot";
81 regmap = <&timer>;
82 offset = <0x28>;
83 mask = <0x1>;
84 };
85 };
86};
diff --git a/arch/mips/boot/dts/brcm/bcm6368.dtsi b/arch/mips/boot/dts/brcm/bcm6368.dtsi
new file mode 100644
index 000000000000..45152bc22117
--- /dev/null
+++ b/arch/mips/boot/dts/brcm/bcm6368.dtsi
@@ -0,0 +1,93 @@
1/ {
2 #address-cells = <1>;
3 #size-cells = <1>;
4 compatible = "brcm,bcm6368";
5
6 cpus {
7 #address-cells = <1>;
8 #size-cells = <0>;
9
10 mips-hpt-frequency = <200000000>;
11
12 cpu@0 {
13 compatible = "brcm,bmips4350";
14 device_type = "cpu";
15 reg = <0>;
16 };
17
18 cpu@1 {
19 compatible = "brcm,bmips4350";
20 device_type = "cpu";
21 reg = <1>;
22 };
23
24 };
25
26 clocks {
27 periph_clk: periph_clk {
28 compatible = "fixed-clock";
29 #clock-cells = <0>;
30 clock-frequency = <50000000>;
31 };
32 };
33
34 aliases {
35 uart0 = &uart0;
36 };
37
38 cpu_intc: cpu_intc {
39 #address-cells = <0>;
40 compatible = "mti,cpu-interrupt-controller";
41
42 interrupt-controller;
43 #interrupt-cells = <1>;
44 };
45
46 ubus {
47 #address-cells = <1>;
48 #size-cells = <1>;
49
50 compatible = "simple-bus";
51 ranges;
52
53 periph_intc: periph_intc@10000020 {
54 compatible = "brcm,bcm3380-l2-intc";
55 reg = <0x10000024 0x4 0x1000002c 0x4>,
56 <0x10000020 0x4 0x10000028 0x4>;
57
58 interrupt-controller;
59 #interrupt-cells = <1>;
60
61 interrupt-parent = <&cpu_intc>;
62 interrupts = <2>;
63 };
64
65 uart0: serial@10000100 {
66 compatible = "brcm,bcm6345-uart";
67 reg = <0x10000100 0x18>;
68 interrupt-parent = <&periph_intc>;
69 interrupts = <2>;
70 clocks = <&periph_clk>;
71 status = "disabled";
72 };
73
74 ehci0: usb@10001500 {
75 compatible = "brcm,bcm6368-ehci", "generic-ehci";
76 reg = <0x10001500 0x100>;
77 big-endian;
78 interrupt-parent = <&periph_intc>;
79 interrupts = <7>;
80 status = "disabled";
81 };
82
83 ohci0: usb@10001600 {
84 compatible = "brcm,bcm6368-ohci", "generic-ohci";
85 reg = <0x10001600 0x100>;
86 big-endian;
87 no-big-frame-no;
88 interrupt-parent = <&periph_intc>;
89 interrupts = <5>;
90 status = "disabled";
91 };
92 };
93};
diff --git a/arch/mips/boot/dts/brcm/bcm7125.dtsi b/arch/mips/boot/dts/brcm/bcm7125.dtsi
new file mode 100644
index 000000000000..1a7efa883c5e
--- /dev/null
+++ b/arch/mips/boot/dts/brcm/bcm7125.dtsi
@@ -0,0 +1,139 @@
1/ {
2 #address-cells = <1>;
3 #size-cells = <1>;
4 compatible = "brcm,bcm7125";
5
6 cpus {
7 #address-cells = <1>;
8 #size-cells = <0>;
9
10 mips-hpt-frequency = <202500000>;
11
12 cpu@0 {
13 compatible = "brcm,bmips4380";
14 device_type = "cpu";
15 reg = <0>;
16 };
17
18 cpu@1 {
19 compatible = "brcm,bmips4380";
20 device_type = "cpu";
21 reg = <1>;
22 };
23 };
24
25 aliases {
26 uart0 = &uart0;
27 };
28
29 cpu_intc: cpu_intc {
30 #address-cells = <0>;
31 compatible = "mti,cpu-interrupt-controller";
32
33 interrupt-controller;
34 #interrupt-cells = <1>;
35 };
36
37 clocks {
38 uart_clk: uart_clk {
39 compatible = "fixed-clock";
40 #clock-cells = <0>;
41 clock-frequency = <81000000>;
42 };
43 };
44
45 rdb {
46 #address-cells = <1>;
47 #size-cells = <1>;
48
49 compatible = "simple-bus";
50 ranges = <0 0x10000000 0x01000000>;
51
52 periph_intc: periph_intc@441400 {
53 compatible = "brcm,bcm7038-l1-intc";
54 reg = <0x441400 0x30>, <0x441600 0x30>;
55
56 interrupt-controller;
57 #interrupt-cells = <1>;
58
59 interrupt-parent = <&cpu_intc>;
60 interrupts = <2>, <3>;
61 };
62
63 sun_l2_intc: sun_l2_intc@401800 {
64 compatible = "brcm,l2-intc";
65 reg = <0x401800 0x30>;
66 interrupt-controller;
67 #interrupt-cells = <1>;
68 interrupt-parent = <&periph_intc>;
69 interrupts = <23>;
70 };
71
72 gisb-arb@400000 {
73 compatible = "brcm,bcm7400-gisb-arb";
74 reg = <0x400000 0xdc>;
75 native-endian;
76 interrupt-parent = <&sun_l2_intc>;
77 interrupts = <0>, <2>;
78 brcm,gisb-arb-master-mask = <0x2f7>;
79 brcm,gisb-arb-master-names = "ssp_0", "cpu_0", "pci_0",
80 "bsp_0", "rdc_0", "rptd_0",
81 "avd_0", "jtag_0";
82 };
83
84 upg_irq0_intc: upg_irq0_intc@406780 {
85 compatible = "brcm,bcm7120-l2-intc";
86 reg = <0x406780 0x8>;
87
88 brcm,int-map-mask = <0x44>;
89 brcm,int-fwd-mask = <0x70000>;
90
91 interrupt-controller;
92 #interrupt-cells = <1>;
93
94 interrupt-parent = <&periph_intc>;
95 interrupts = <18>;
96 };
97
98 sun_top_ctrl: syscon@404000 {
99 compatible = "brcm,bcm7125-sun-top-ctrl", "syscon";
100 reg = <0x404000 0x60c>;
101 little-endian;
102 };
103
104 reboot {
105 compatible = "brcm,bcm7038-reboot";
106 syscon = <&sun_top_ctrl 0x8 0x14>;
107 };
108
109 uart0: serial@406b00 {
110 compatible = "ns16550a";
111 reg = <0x406b00 0x20>;
112 reg-io-width = <0x4>;
113 reg-shift = <0x2>;
114 native-endian;
115 interrupt-parent = <&periph_intc>;
116 interrupts = <21>;
117 clocks = <&uart_clk>;
118 status = "disabled";
119 };
120
121 ehci0: usb@488300 {
122 compatible = "brcm,bcm7125-ehci", "generic-ehci";
123 reg = <0x488300 0x100>;
124 native-endian;
125 interrupt-parent = <&periph_intc>;
126 interrupts = <60>;
127 status = "disabled";
128 };
129
130 ohci0: usb@488400 {
131 compatible = "brcm,bcm7125-ohci", "generic-ohci";
132 reg = <0x488400 0x100>;
133 native-endian;
134 interrupt-parent = <&periph_intc>;
135 interrupts = <61>;
136 status = "disabled";
137 };
138 };
139};
diff --git a/arch/mips/boot/dts/brcm/bcm7346.dtsi b/arch/mips/boot/dts/brcm/bcm7346.dtsi
new file mode 100644
index 000000000000..1f30728a3177
--- /dev/null
+++ b/arch/mips/boot/dts/brcm/bcm7346.dtsi
@@ -0,0 +1,224 @@
1/ {
2 #address-cells = <1>;
3 #size-cells = <1>;
4 compatible = "brcm,bcm7346";
5
6 cpus {
7 #address-cells = <1>;
8 #size-cells = <0>;
9
10 mips-hpt-frequency = <163125000>;
11
12 cpu@0 {
13 compatible = "brcm,bmips5000";
14 device_type = "cpu";
15 reg = <0>;
16 };
17
18 cpu@1 {
19 compatible = "brcm,bmips5000";
20 device_type = "cpu";
21 reg = <1>;
22 };
23 };
24
25 aliases {
26 uart0 = &uart0;
27 };
28
29 cpu_intc: cpu_intc {
30 #address-cells = <0>;
31 compatible = "mti,cpu-interrupt-controller";
32
33 interrupt-controller;
34 #interrupt-cells = <1>;
35 };
36
37 clocks {
38 uart_clk: uart_clk {
39 compatible = "fixed-clock";
40 #clock-cells = <0>;
41 clock-frequency = <81000000>;
42 };
43 };
44
45 rdb {
46 #address-cells = <1>;
47 #size-cells = <1>;
48
49 compatible = "simple-bus";
50 ranges = <0 0x10000000 0x01000000>;
51
52 periph_intc: periph_intc@411400 {
53 compatible = "brcm,bcm7038-l1-intc";
54 reg = <0x411400 0x30>, <0x411600 0x30>;
55
56 interrupt-controller;
57 #interrupt-cells = <1>;
58
59 interrupt-parent = <&cpu_intc>;
60 interrupts = <2>, <3>;
61 };
62
63 sun_l2_intc: sun_l2_intc@403000 {
64 compatible = "brcm,l2-intc";
65 reg = <0x403000 0x30>;
66 interrupt-controller;
67 #interrupt-cells = <1>;
68 interrupt-parent = <&periph_intc>;
69 interrupts = <51>;
70 };
71
72 gisb-arb@400000 {
73 compatible = "brcm,bcm7400-gisb-arb";
74 reg = <0x400000 0xdc>;
75 native-endian;
76 interrupt-parent = <&sun_l2_intc>;
77 interrupts = <0>, <2>;
78 brcm,gisb-arb-master-mask = <0x673>;
79 brcm,gisb-arb-master-names = "ssp_0", "cpu_0", "bsp_0",
80 "rdc_0", "raaga_0",
81 "jtag_0", "svd_0";
82 };
83
84 upg_irq0_intc: upg_irq0_intc@406780 {
85 compatible = "brcm,bcm7120-l2-intc";
86 reg = <0x406780 0x8>;
87
88 brcm,int-map-mask = <0x44>;
89 brcm,int-fwd-mask = <0x70000>;
90
91 interrupt-controller;
92 #interrupt-cells = <1>;
93
94 interrupt-parent = <&periph_intc>;
95 interrupts = <59>;
96 };
97
98 sun_top_ctrl: syscon@404000 {
99 compatible = "brcm,bcm7346-sun-top-ctrl", "syscon";
100 reg = <0x404000 0x51c>;
101 little-endian;
102 };
103
104 reboot {
105 compatible = "brcm,brcmstb-reboot";
106 syscon = <&sun_top_ctrl 0x304 0x308>;
107 };
108
109 uart0: serial@406900 {
110 compatible = "ns16550a";
111 reg = <0x406900 0x20>;
112 reg-io-width = <0x4>;
113 reg-shift = <0x2>;
114 native-endian;
115 interrupt-parent = <&periph_intc>;
116 interrupts = <64>;
117 clocks = <&uart_clk>;
118 status = "disabled";
119 };
120
121 enet0: ethernet@430000 {
122 phy-mode = "internal";
123 phy-handle = <&phy1>;
124 mac-address = [ 00 10 18 36 23 1a ];
125 compatible = "brcm,genet-v2";
126 #address-cells = <0x1>;
127 #size-cells = <0x1>;
128 reg = <0x430000 0x4c8c>;
129 interrupts = <24>, <25>;
130 interrupt-parent = <&periph_intc>;
131 status = "disabled";
132
133 mdio@e14 {
134 compatible = "brcm,genet-mdio-v2";
135 #address-cells = <0x1>;
136 #size-cells = <0x0>;
137 reg = <0xe14 0x8>;
138
139 phy1: ethernet-phy@1 {
140 max-speed = <100>;
141 reg = <0x1>;
142 compatible = "brcm,40nm-ephy",
143 "ethernet-phy-ieee802.3-c22";
144 };
145 };
146 };
147
148 ehci0: usb@480300 {
149 compatible = "brcm,bcm7346-ehci", "generic-ehci";
150 reg = <0x480300 0x100>;
151 native-endian;
152 interrupt-parent = <&periph_intc>;
153 interrupts = <68>;
154 status = "disabled";
155 };
156
157 ohci0: usb@480400 {
158 compatible = "brcm,bcm7346-ohci", "generic-ohci";
159 reg = <0x480400 0x100>;
160 native-endian;
161 no-big-frame-no;
162 interrupt-parent = <&periph_intc>;
163 interrupts = <70>;
164 status = "disabled";
165 };
166
167 ehci1: usb@480500 {
168 compatible = "brcm,bcm7346-ehci", "generic-ehci";
169 reg = <0x480500 0x100>;
170 native-endian;
171 interrupt-parent = <&periph_intc>;
172 interrupts = <69>;
173 status = "disabled";
174 };
175
176 ohci1: usb@480600 {
177 compatible = "brcm,bcm7346-ohci", "generic-ohci";
178 reg = <0x480600 0x100>;
179 native-endian;
180 no-big-frame-no;
181 interrupt-parent = <&periph_intc>;
182 interrupts = <71>;
183 status = "disabled";
184 };
185
186 ehci2: usb@490300 {
187 compatible = "brcm,bcm7346-ehci", "generic-ehci";
188 reg = <0x490300 0x100>;
189 native-endian;
190 interrupt-parent = <&periph_intc>;
191 interrupts = <73>;
192 status = "disabled";
193 };
194
195 ohci2: usb@490400 {
196 compatible = "brcm,bcm7346-ohci", "generic-ohci";
197 reg = <0x490400 0x100>;
198 native-endian;
199 no-big-frame-no;
200 interrupt-parent = <&periph_intc>;
201 interrupts = <75>;
202 status = "disabled";
203 };
204
205 ehci3: usb@490500 {
206 compatible = "brcm,bcm7346-ehci", "generic-ehci";
207 reg = <0x490500 0x100>;
208 native-endian;
209 interrupt-parent = <&periph_intc>;
210 interrupts = <74>;
211 status = "disabled";
212 };
213
214 ohci3: usb@490600 {
215 compatible = "brcm,bcm7346-ohci", "generic-ohci";
216 reg = <0x490600 0x100>;
217 native-endian;
218 no-big-frame-no;
219 interrupt-parent = <&periph_intc>;
220 interrupts = <76>;
221 status = "disabled";
222 };
223 };
224};
diff --git a/arch/mips/boot/dts/brcm/bcm7358.dtsi b/arch/mips/boot/dts/brcm/bcm7358.dtsi
new file mode 100644
index 000000000000..2c2aa9368f76
--- /dev/null
+++ b/arch/mips/boot/dts/brcm/bcm7358.dtsi
@@ -0,0 +1,161 @@
1/ {
2 #address-cells = <1>;
3 #size-cells = <1>;
4 compatible = "brcm,bcm7358";
5
6 cpus {
7 #address-cells = <1>;
8 #size-cells = <0>;
9
10 mips-hpt-frequency = <375000000>;
11
12 cpu@0 {
13 compatible = "brcm,bmips3300";
14 device_type = "cpu";
15 reg = <0>;
16 };
17 };
18
19 aliases {
20 uart0 = &uart0;
21 };
22
23 cpu_intc: cpu_intc {
24 #address-cells = <0>;
25 compatible = "mti,cpu-interrupt-controller";
26
27 interrupt-controller;
28 #interrupt-cells = <1>;
29 };
30
31 clocks {
32 uart_clk: uart_clk {
33 compatible = "fixed-clock";
34 #clock-cells = <0>;
35 clock-frequency = <81000000>;
36 };
37 };
38
39 rdb {
40 #address-cells = <1>;
41 #size-cells = <1>;
42
43 compatible = "simple-bus";
44 ranges = <0 0x10000000 0x01000000>;
45
46 periph_intc: periph_intc@411400 {
47 compatible = "brcm,bcm7038-l1-intc";
48 reg = <0x411400 0x30>;
49
50 interrupt-controller;
51 #interrupt-cells = <1>;
52
53 interrupt-parent = <&cpu_intc>;
54 interrupts = <2>;
55 };
56
57 sun_l2_intc: sun_l2_intc@403000 {
58 compatible = "brcm,l2-intc";
59 reg = <0x403000 0x30>;
60 interrupt-controller;
61 #interrupt-cells = <1>;
62 interrupt-parent = <&periph_intc>;
63 interrupts = <48>;
64 };
65
66 gisb-arb@400000 {
67 compatible = "brcm,bcm7400-gisb-arb";
68 reg = <0x400000 0xdc>;
69 native-endian;
70 interrupt-parent = <&sun_l2_intc>;
71 interrupts = <0>, <2>;
72 brcm,gisb-arb-master-mask = <0x2f3>;
73 brcm,gisb-arb-master-names = "ssp_0", "cpu_0", "bsp_0",
74 "rdc_0", "raaga_0",
75 "avd_0", "jtag_0";
76 };
77
78 upg_irq0_intc: upg_irq0_intc@406600 {
79 compatible = "brcm,bcm7120-l2-intc";
80 reg = <0x406600 0x8>;
81
82 brcm,int-map-mask = <0x44>;
83 brcm,int-fwd-mask = <0x70000>;
84
85 interrupt-controller;
86 #interrupt-cells = <1>;
87
88 interrupt-parent = <&periph_intc>;
89 interrupts = <56>;
90 };
91
92 sun_top_ctrl: syscon@404000 {
93 compatible = "brcm,bcm7358-sun-top-ctrl", "syscon";
94 reg = <0x404000 0x51c>;
95 little-endian;
96 };
97
98 reboot {
99 compatible = "brcm,brcmstb-reboot";
100 syscon = <&sun_top_ctrl 0x304 0x308>;
101 };
102
103 uart0: serial@406800 {
104 compatible = "ns16550a";
105 reg = <0x406800 0x20>;
106 reg-io-width = <0x4>;
107 reg-shift = <0x2>;
108 native-endian;
109 interrupt-parent = <&periph_intc>;
110 interrupts = <61>;
111 clocks = <&uart_clk>;
112 status = "disabled";
113 };
114
115 enet0: ethernet@430000 {
116 phy-mode = "internal";
117 phy-handle = <&phy1>;
118 mac-address = [ 00 10 18 36 23 1a ];
119 compatible = "brcm,genet-v2";
120 #address-cells = <0x1>;
121 #size-cells = <0x1>;
122 reg = <0x430000 0x4c8c>;
123 interrupts = <24>, <25>;
124 interrupt-parent = <&periph_intc>;
125 status = "disabled";
126
127 mdio@e14 {
128 compatible = "brcm,genet-mdio-v2";
129 #address-cells = <0x1>;
130 #size-cells = <0x0>;
131 reg = <0xe14 0x8>;
132
133 phy1: ethernet-phy@1 {
134 max-speed = <100>;
135 reg = <0x1>;
136 compatible = "brcm,40nm-ephy",
137 "ethernet-phy-ieee802.3-c22";
138 };
139 };
140 };
141
142 ehci0: usb@480300 {
143 compatible = "brcm,bcm7358-ehci", "generic-ehci";
144 reg = <0x480300 0x100>;
145 native-endian;
146 interrupt-parent = <&periph_intc>;
147 interrupts = <65>;
148 status = "disabled";
149 };
150
151 ohci0: usb@480400 {
152 compatible = "brcm,bcm7358-ohci", "generic-ohci";
153 reg = <0x480400 0x100>;
154 native-endian;
155 no-big-frame-no;
156 interrupt-parent = <&periph_intc>;
157 interrupts = <66>;
158 status = "disabled";
159 };
160 };
161};
diff --git a/arch/mips/boot/dts/brcm/bcm7360.dtsi b/arch/mips/boot/dts/brcm/bcm7360.dtsi
new file mode 100644
index 000000000000..f23b0aed276f
--- /dev/null
+++ b/arch/mips/boot/dts/brcm/bcm7360.dtsi
@@ -0,0 +1,161 @@
1/ {
2 #address-cells = <1>;
3 #size-cells = <1>;
4 compatible = "brcm,bcm7360";
5
6 cpus {
7 #address-cells = <1>;
8 #size-cells = <0>;
9
10 mips-hpt-frequency = <375000000>;
11
12 cpu@0 {
13 compatible = "brcm,bmips3300";
14 device_type = "cpu";
15 reg = <0>;
16 };
17 };
18
19 aliases {
20 uart0 = &uart0;
21 };
22
23 cpu_intc: cpu_intc {
24 #address-cells = <0>;
25 compatible = "mti,cpu-interrupt-controller";
26
27 interrupt-controller;
28 #interrupt-cells = <1>;
29 };
30
31 clocks {
32 uart_clk: uart_clk {
33 compatible = "fixed-clock";
34 #clock-cells = <0>;
35 clock-frequency = <81000000>;
36 };
37 };
38
39 rdb {
40 #address-cells = <1>;
41 #size-cells = <1>;
42
43 compatible = "simple-bus";
44 ranges = <0 0x10000000 0x01000000>;
45
46 periph_intc: periph_intc@411400 {
47 compatible = "brcm,bcm7038-l1-intc";
48 reg = <0x411400 0x30>;
49
50 interrupt-controller;
51 #interrupt-cells = <1>;
52
53 interrupt-parent = <&cpu_intc>;
54 interrupts = <2>;
55 };
56
57 sun_l2_intc: sun_l2_intc@403000 {
58 compatible = "brcm,l2-intc";
59 reg = <0x403000 0x30>;
60 interrupt-controller;
61 #interrupt-cells = <1>;
62 interrupt-parent = <&periph_intc>;
63 interrupts = <48>;
64 };
65
66 gisb-arb@400000 {
67 compatible = "brcm,bcm7400-gisb-arb";
68 reg = <0x400000 0xdc>;
69 native-endian;
70 interrupt-parent = <&sun_l2_intc>;
71 interrupts = <0>, <2>;
72 brcm,gisb-arb-master-mask = <0x2f3>;
73 brcm,gisb-arb-master-names = "ssp_0", "cpu_0", "bsp_0",
74 "rdc_0", "raaga_0",
75 "avd_0", "jtag_0";
76 };
77
78 upg_irq0_intc: upg_irq0_intc@406600 {
79 compatible = "brcm,bcm7120-l2-intc";
80 reg = <0x406600 0x8>;
81
82 brcm,int-map-mask = <0x44>;
83 brcm,int-fwd-mask = <0x70000>;
84
85 interrupt-controller;
86 #interrupt-cells = <1>;
87
88 interrupt-parent = <&periph_intc>;
89 interrupts = <56>;
90 };
91
92 sun_top_ctrl: syscon@404000 {
93 compatible = "brcm,bcm7360-sun-top-ctrl", "syscon";
94 reg = <0x404000 0x51c>;
95 little-endian;
96 };
97
98 reboot {
99 compatible = "brcm,brcmstb-reboot";
100 syscon = <&sun_top_ctrl 0x304 0x308>;
101 };
102
103 uart0: serial@406800 {
104 compatible = "ns16550a";
105 reg = <0x406800 0x20>;
106 reg-io-width = <0x4>;
107 reg-shift = <0x2>;
108 native-endian;
109 interrupt-parent = <&periph_intc>;
110 interrupts = <61>;
111 clocks = <&uart_clk>;
112 status = "disabled";
113 };
114
115 enet0: ethernet@430000 {
116 phy-mode = "internal";
117 phy-handle = <&phy1>;
118 mac-address = [ 00 10 18 36 23 1a ];
119 compatible = "brcm,genet-v2";
120 #address-cells = <0x1>;
121 #size-cells = <0x1>;
122 reg = <0x430000 0x4c8c>;
123 interrupts = <24>, <25>;
124 interrupt-parent = <&periph_intc>;
125 status = "disabled";
126
127 mdio@e14 {
128 compatible = "brcm,genet-mdio-v2";
129 #address-cells = <0x1>;
130 #size-cells = <0x0>;
131 reg = <0xe14 0x8>;
132
133 phy1: ethernet-phy@1 {
134 max-speed = <100>;
135 reg = <0x1>;
136 compatible = "brcm,40nm-ephy",
137 "ethernet-phy-ieee802.3-c22";
138 };
139 };
140 };
141
142 ehci0: usb@480300 {
143 compatible = "brcm,bcm7360-ehci", "generic-ehci";
144 reg = <0x480300 0x100>;
145 native-endian;
146 interrupt-parent = <&periph_intc>;
147 interrupts = <65>;
148 status = "disabled";
149 };
150
151 ohci0: usb@480400 {
152 compatible = "brcm,bcm7360-ohci", "generic-ohci";
153 reg = <0x480400 0x100>;
154 native-endian;
155 no-big-frame-no;
156 interrupt-parent = <&periph_intc>;
157 interrupts = <66>;
158 status = "disabled";
159 };
160 };
161};
diff --git a/arch/mips/boot/dts/brcm/bcm7362.dtsi b/arch/mips/boot/dts/brcm/bcm7362.dtsi
new file mode 100644
index 000000000000..da99db665bbc
--- /dev/null
+++ b/arch/mips/boot/dts/brcm/bcm7362.dtsi
@@ -0,0 +1,167 @@
1/ {
2 #address-cells = <1>;
3 #size-cells = <1>;
4 compatible = "brcm,bcm7362";
5
6 cpus {
7 #address-cells = <1>;
8 #size-cells = <0>;
9
10 mips-hpt-frequency = <375000000>;
11
12 cpu@0 {
13 compatible = "brcm,bmips4380";
14 device_type = "cpu";
15 reg = <0>;
16 };
17
18 cpu@1 {
19 compatible = "brcm,bmips4380";
20 device_type = "cpu";
21 reg = <1>;
22 };
23 };
24
25 aliases {
26 uart0 = &uart0;
27 };
28
29 cpu_intc: cpu_intc {
30 #address-cells = <0>;
31 compatible = "mti,cpu-interrupt-controller";
32
33 interrupt-controller;
34 #interrupt-cells = <1>;
35 };
36
37 clocks {
38 uart_clk: uart_clk {
39 compatible = "fixed-clock";
40 #clock-cells = <0>;
41 clock-frequency = <81000000>;
42 };
43 };
44
45 rdb {
46 #address-cells = <1>;
47 #size-cells = <1>;
48
49 compatible = "simple-bus";
50 ranges = <0 0x10000000 0x01000000>;
51
52 periph_intc: periph_intc@411400 {
53 compatible = "brcm,bcm7038-l1-intc";
54 reg = <0x411400 0x30>, <0x411600 0x30>;
55
56 interrupt-controller;
57 #interrupt-cells = <1>;
58
59 interrupt-parent = <&cpu_intc>;
60 interrupts = <2>, <3>;
61 };
62
63 sun_l2_intc: sun_l2_intc@403000 {
64 compatible = "brcm,l2-intc";
65 reg = <0x403000 0x30>;
66 interrupt-controller;
67 #interrupt-cells = <1>;
68 interrupt-parent = <&periph_intc>;
69 interrupts = <48>;
70 };
71
72 gisb-arb@400000 {
73 compatible = "brcm,bcm7400-gisb-arb";
74 reg = <0x400000 0xdc>;
75 native-endian;
76 interrupt-parent = <&sun_l2_intc>;
77 interrupts = <0>, <2>;
78 brcm,gisb-arb-master-mask = <0x2f3>;
79 brcm,gisb-arb-master-names = "ssp_0", "cpu_0", "bsp_0",
80 "rdc_0", "raaga_0",
81 "avd_0", "jtag_0";
82 };
83
84 upg_irq0_intc: upg_irq0_intc@406600 {
85 compatible = "brcm,bcm7120-l2-intc";
86 reg = <0x406600 0x8>;
87
88 brcm,int-map-mask = <0x44>;
89 brcm,int-fwd-mask = <0x70000>;
90
91 interrupt-controller;
92 #interrupt-cells = <1>;
93
94 interrupt-parent = <&periph_intc>;
95 interrupts = <56>;
96 };
97
98 sun_top_ctrl: syscon@404000 {
99 compatible = "brcm,bcm7362-sun-top-ctrl", "syscon";
100 reg = <0x404000 0x51c>;
101 little-endian;
102 };
103
104 reboot {
105 compatible = "brcm,brcmstb-reboot";
106 syscon = <&sun_top_ctrl 0x304 0x308>;
107 };
108
109 uart0: serial@406800 {
110 compatible = "ns16550a";
111 reg = <0x406800 0x20>;
112 reg-io-width = <0x4>;
113 reg-shift = <0x2>;
114 native-endian;
115 interrupt-parent = <&periph_intc>;
116 interrupts = <61>;
117 clocks = <&uart_clk>;
118 status = "disabled";
119 };
120
121 enet0: ethernet@430000 {
122 phy-mode = "internal";
123 phy-handle = <&phy1>;
124 mac-address = [ 00 10 18 36 23 1a ];
125 compatible = "brcm,genet-v2";
126 #address-cells = <0x1>;
127 #size-cells = <0x1>;
128 reg = <0x430000 0x4c8c>;
129 interrupts = <24>, <25>;
130 interrupt-parent = <&periph_intc>;
131 status = "disabled";
132
133 mdio@e14 {
134 compatible = "brcm,genet-mdio-v2";
135 #address-cells = <0x1>;
136 #size-cells = <0x0>;
137 reg = <0xe14 0x8>;
138
139 phy1: ethernet-phy@1 {
140 max-speed = <100>;
141 reg = <0x1>;
142 compatible = "brcm,40nm-ephy",
143 "ethernet-phy-ieee802.3-c22";
144 };
145 };
146 };
147
148 ehci0: usb@480300 {
149 compatible = "brcm,bcm7362-ehci", "generic-ehci";
150 reg = <0x480300 0x100>;
151 native-endian;
152 interrupt-parent = <&periph_intc>;
153 interrupts = <65>;
154 status = "disabled";
155 };
156
157 ohci0: usb@480400 {
158 compatible = "brcm,bcm7362-ohci", "generic-ohci";
159 reg = <0x480400 0x100>;
160 native-endian;
161 no-big-frame-no;
162 interrupt-parent = <&periph_intc>;
163 interrupts = <66>;
164 status = "disabled";
165 };
166 };
167};
diff --git a/arch/mips/boot/dts/brcm/bcm7420.dtsi b/arch/mips/boot/dts/brcm/bcm7420.dtsi
new file mode 100644
index 000000000000..5f55d0a50a28
--- /dev/null
+++ b/arch/mips/boot/dts/brcm/bcm7420.dtsi
@@ -0,0 +1,184 @@
1/ {
2 #address-cells = <1>;
3 #size-cells = <1>;
4 compatible = "brcm,bcm7420";
5
6 cpus {
7 #address-cells = <1>;
8 #size-cells = <0>;
9
10 mips-hpt-frequency = <93750000>;
11
12 cpu@0 {
13 compatible = "brcm,bmips5000";
14 device_type = "cpu";
15 reg = <0>;
16 };
17
18 cpu@1 {
19 compatible = "brcm,bmips5000";
20 device_type = "cpu";
21 reg = <1>;
22 };
23 };
24
25 aliases {
26 uart0 = &uart0;
27 };
28
29 cpu_intc: cpu_intc {
30 #address-cells = <0>;
31 compatible = "mti,cpu-interrupt-controller";
32
33 interrupt-controller;
34 #interrupt-cells = <1>;
35 };
36
37 clocks {
38 uart_clk: uart_clk {
39 compatible = "fixed-clock";
40 #clock-cells = <0>;
41 clock-frequency = <81000000>;
42 };
43 };
44
45 rdb {
46 #address-cells = <1>;
47 #size-cells = <1>;
48
49 compatible = "simple-bus";
50 ranges = <0 0x10000000 0x01000000>;
51
52 periph_intc: periph_intc@441400 {
53 compatible = "brcm,bcm7038-l1-intc";
54 reg = <0x441400 0x30>, <0x441600 0x30>;
55
56 interrupt-controller;
57 #interrupt-cells = <1>;
58
59 interrupt-parent = <&cpu_intc>;
60 interrupts = <2>, <3>;
61 };
62
63 sun_l2_intc: sun_l2_intc@401800 {
64 compatible = "brcm,l2-intc";
65 reg = <0x401800 0x30>;
66 interrupt-controller;
67 #interrupt-cells = <1>;
68 interrupt-parent = <&periph_intc>;
69 interrupts = <23>;
70 };
71
72 gisb-arb@400000 {
73 compatible = "brcm,bcm7400-gisb-arb";
74 reg = <0x400000 0xdc>;
75 native-endian;
76 interrupt-parent = <&sun_l2_intc>;
77 interrupts = <0>, <2>;
78 brcm,gisb-arb-master-mask = <0x3ff>;
79 brcm,gisb-arb-master-names = "ssp_0", "cpu_0", "pci_0",
80 "pcie_0", "bsp_0", "rdc_0",
81 "rptd_0", "avd_0", "avd_1",
82 "jtag_0";
83 };
84
85 upg_irq0_intc: upg_irq0_intc@406780 {
86 compatible = "brcm,bcm7120-l2-intc";
87 reg = <0x406780 0x8>;
88
89 brcm,int-map-mask = <0x44>;
90 brcm,int-fwd-mask = <0x70000>;
91
92 interrupt-controller;
93 #interrupt-cells = <1>;
94
95 interrupt-parent = <&periph_intc>;
96 interrupts = <18>;
97 };
98
99 sun_top_ctrl: syscon@404000 {
100 compatible = "brcm,bcm7420-sun-top-ctrl", "syscon";
101 reg = <0x404000 0x60c>;
102 little-endian;
103 };
104
105 reboot {
106 compatible = "brcm,bcm7038-reboot";
107 syscon = <&sun_top_ctrl 0x8 0x14>;
108 };
109
110 uart0: serial@406b00 {
111 compatible = "ns16550a";
112 reg = <0x406b00 0x20>;
113 reg-io-width = <0x4>;
114 reg-shift = <0x2>;
115 interrupt-parent = <&periph_intc>;
116 interrupts = <21>;
117 clocks = <&uart_clk>;
118 status = "disabled";
119 };
120
121 enet0: ethernet@468000 {
122 phy-mode = "internal";
123 phy-handle = <&phy1>;
124 mac-address = [ 00 10 18 36 23 1a ];
125 compatible = "brcm,genet-v1";
126 #address-cells = <0x1>;
127 #size-cells = <0x1>;
128 reg = <0x468000 0x3c8c>;
129 interrupts = <69>, <79>;
130 interrupt-parent = <&periph_intc>;
131 status = "disabled";
132
133 mdio@e14 {
134 compatible = "brcm,genet-mdio-v1";
135 #address-cells = <0x1>;
136 #size-cells = <0x0>;
137 reg = <0xe14 0x8>;
138
139 phy1: ethernet-phy@1 {
140 max-speed = <100>;
141 reg = <0x1>;
142 compatible = "brcm,65nm-ephy",
143 "ethernet-phy-ieee802.3-c22";
144 };
145 };
146 };
147
148 ehci0: usb@488300 {
149 compatible = "brcm,bcm7420-ehci", "generic-ehci";
150 reg = <0x488300 0x100>;
151 interrupt-parent = <&periph_intc>;
152 interrupts = <60>;
153 status = "disabled";
154 };
155
156 ohci0: usb@488400 {
157 compatible = "brcm,bcm7420-ohci", "generic-ohci";
158 reg = <0x488400 0x100>;
159 native-endian;
160 no-big-frame-no;
161 interrupt-parent = <&periph_intc>;
162 interrupts = <61>;
163 status = "disabled";
164 };
165
166 ehci1: usb@488500 {
167 compatible = "brcm,bcm7420-ehci", "generic-ehci";
168 reg = <0x488500 0x100>;
169 interrupt-parent = <&periph_intc>;
170 interrupts = <55>;
171 status = "disabled";
172 };
173
174 ohci1: usb@488600 {
175 compatible = "brcm,bcm7420-ohci", "generic-ohci";
176 reg = <0x488600 0x100>;
177 native-endian;
178 no-big-frame-no;
179 interrupt-parent = <&periph_intc>;
180 interrupts = <62>;
181 status = "disabled";
182 };
183 };
184};
diff --git a/arch/mips/boot/dts/brcm/bcm7425.dtsi b/arch/mips/boot/dts/brcm/bcm7425.dtsi
new file mode 100644
index 000000000000..5b660b617ead
--- /dev/null
+++ b/arch/mips/boot/dts/brcm/bcm7425.dtsi
@@ -0,0 +1,225 @@
1/ {
2 #address-cells = <1>;
3 #size-cells = <1>;
4 compatible = "brcm,bcm7425";
5
6 cpus {
7 #address-cells = <1>;
8 #size-cells = <0>;
9
10 mips-hpt-frequency = <163125000>;
11
12 cpu@0 {
13 compatible = "brcm,bmips5000";
14 device_type = "cpu";
15 reg = <0>;
16 };
17
18 cpu@1 {
19 compatible = "brcm,bmips5000";
20 device_type = "cpu";
21 reg = <1>;
22 };
23 };
24
25 aliases {
26 uart0 = &uart0;
27 };
28
29 cpu_intc: cpu_intc {
30 #address-cells = <0>;
31 compatible = "mti,cpu-interrupt-controller";
32
33 interrupt-controller;
34 #interrupt-cells = <1>;
35 };
36
37 clocks {
38 uart_clk: uart_clk {
39 compatible = "fixed-clock";
40 #clock-cells = <0>;
41 clock-frequency = <81000000>;
42 };
43 };
44
45 rdb {
46 #address-cells = <1>;
47 #size-cells = <1>;
48
49 compatible = "simple-bus";
50 ranges = <0 0x10000000 0x01000000>;
51
52 periph_intc: periph_intc@41a400 {
53 compatible = "brcm,bcm7038-l1-intc";
54 reg = <0x41a400 0x30>, <0x41a600 0x30>;
55
56 interrupt-controller;
57 #interrupt-cells = <1>;
58
59 interrupt-parent = <&cpu_intc>;
60 interrupts = <2>, <3>;
61 };
62
63 sun_l2_intc: sun_l2_intc@403000 {
64 compatible = "brcm,l2-intc";
65 reg = <0x403000 0x30>;
66 interrupt-controller;
67 #interrupt-cells = <1>;
68 interrupt-parent = <&periph_intc>;
69 interrupts = <47>;
70 };
71
72 gisb-arb@400000 {
73 compatible = "brcm,bcm7400-gisb-arb";
74 reg = <0x400000 0xdc>;
75 native-endian;
76 interrupt-parent = <&sun_l2_intc>;
77 interrupts = <0>, <2>;
78 brcm,gisb-arb-master-mask = <0x177b>;
79 brcm,gisb-arb-master-names = "ssp_0", "cpu_0", "pcie_0",
80 "bsp_0", "rdc_0",
81 "raaga_0", "avd_1",
82 "jtag_0", "svd_0",
83 "vice_0";
84 };
85
86 upg_irq0_intc: upg_irq0_intc@406780 {
87 compatible = "brcm,bcm7120-l2-intc";
88 reg = <0x406780 0x8>;
89
90 brcm,int-map-mask = <0x44>;
91 brcm,int-fwd-mask = <0x70000>;
92
93 interrupt-controller;
94 #interrupt-cells = <1>;
95
96 interrupt-parent = <&periph_intc>;
97 interrupts = <55>;
98 };
99
100 sun_top_ctrl: syscon@404000 {
101 compatible = "brcm,bcm7425-sun-top-ctrl", "syscon";
102 reg = <0x404000 0x51c>;
103 little-endian;
104 };
105
106 reboot {
107 compatible = "brcm,brcmstb-reboot";
108 syscon = <&sun_top_ctrl 0x304 0x308>;
109 };
110
111 uart0: serial@406b00 {
112 compatible = "ns16550a";
113 reg = <0x406b00 0x20>;
114 reg-io-width = <0x4>;
115 reg-shift = <0x2>;
116 interrupt-parent = <&periph_intc>;
117 interrupts = <61>;
118 clocks = <&uart_clk>;
119 status = "disabled";
120 };
121
122 enet0: ethernet@b80000 {
123 phy-mode = "internal";
124 phy-handle = <&phy1>;
125 mac-address = [ 00 10 18 36 23 1a ];
126 compatible = "brcm,genet-v3";
127 #address-cells = <0x1>;
128 #size-cells = <0x1>;
129 reg = <0xb80000 0x11c88>;
130 interrupts = <17>, <18>;
131 interrupt-parent = <&periph_intc>;
132 status = "disabled";
133
134 mdio@e14 {
135 compatible = "brcm,genet-mdio-v3";
136 #address-cells = <0x1>;
137 #size-cells = <0x0>;
138 reg = <0xe14 0x8>;
139
140 phy1: ethernet-phy@1 {
141 max-speed = <100>;
142 reg = <0x1>;
143 compatible = "brcm,40nm-ephy",
144 "ethernet-phy-ieee802.3-c22";
145 };
146 };
147 };
148
149 ehci0: usb@480300 {
150 compatible = "brcm,bcm7425-ehci", "generic-ehci";
151 reg = <0x480300 0x100>;
152 native-endian;
153 interrupt-parent = <&periph_intc>;
154 interrupts = <65>;
155 status = "disabled";
156 };
157
158 ohci0: usb@480400 {
159 compatible = "brcm,bcm7425-ohci", "generic-ohci";
160 reg = <0x480400 0x100>;
161 native-endian;
162 no-big-frame-no;
163 interrupt-parent = <&periph_intc>;
164 interrupts = <67>;
165 status = "disabled";
166 };
167
168 ehci1: usb@480500 {
169 compatible = "brcm,bcm7425-ehci", "generic-ehci";
170 reg = <0x480500 0x100>;
171 native-endian;
172 interrupt-parent = <&periph_intc>;
173 interrupts = <66>;
174 status = "disabled";
175 };
176
177 ohci1: usb@480600 {
178 compatible = "brcm,bcm7425-ohci", "generic-ohci";
179 reg = <0x480600 0x100>;
180 native-endian;
181 no-big-frame-no;
182 interrupt-parent = <&periph_intc>;
183 interrupts = <68>;
184 status = "disabled";
185 };
186
187 ehci2: usb@490300 {
188 compatible = "brcm,bcm7425-ehci", "generic-ehci";
189 reg = <0x490300 0x100>;
190 native-endian;
191 interrupt-parent = <&periph_intc>;
192 interrupts = <70>;
193 status = "disabled";
194 };
195
196 ohci2: usb@490400 {
197 compatible = "brcm,bcm7425-ohci", "generic-ohci";
198 reg = <0x490400 0x100>;
199 native-endian;
200 no-big-frame-no;
201 interrupt-parent = <&periph_intc>;
202 interrupts = <72>;
203 status = "disabled";
204 };
205
206 ehci3: usb@490500 {
207 compatible = "brcm,bcm7425-ehci", "generic-ehci";
208 reg = <0x490500 0x100>;
209 native-endian;
210 interrupt-parent = <&periph_intc>;
211 interrupts = <71>;
212 status = "disabled";
213 };
214
215 ohci3: usb@490600 {
216 compatible = "brcm,bcm7425-ohci", "generic-ohci";
217 reg = <0x490600 0x100>;
218 native-endian;
219 no-big-frame-no;
220 interrupt-parent = <&periph_intc>;
221 interrupts = <73>;
222 status = "disabled";
223 };
224 };
225};
diff --git a/arch/mips/boot/dts/bcm93384wvg.dts b/arch/mips/boot/dts/brcm/bcm93384wvg.dts
index 831741179212..d1e44a17d41a 100644
--- a/arch/mips/boot/dts/bcm93384wvg.dts
+++ b/arch/mips/boot/dts/brcm/bcm93384wvg.dts
@@ -1,6 +1,6 @@
1/dts-v1/; 1/dts-v1/;
2 2
3/include/ "bcm3384.dtsi" 3/include/ "bcm3384_zephyr.dtsi"
4 4
5/ { 5/ {
6 compatible = "brcm,bcm93384wvg", "brcm,bcm3384"; 6 compatible = "brcm,bcm93384wvg", "brcm,bcm3384";
@@ -10,13 +10,6 @@
10 bootargs = "console=ttyS0,115200"; 10 bootargs = "console=ttyS0,115200";
11 stdout-path = &uart0; 11 stdout-path = &uart0;
12 }; 12 };
13
14 memory@0 {
15 device_type = "memory";
16 reg = <0x0 0x04000000>;
17 dma-xor-mask = <0x08000000>;
18 dma-xor-limit = <0x0fffffff>;
19 };
20}; 13};
21 14
22&uart0 { 15&uart0 {
diff --git a/arch/mips/boot/dts/brcm/bcm93384wvg_viper.dts b/arch/mips/boot/dts/brcm/bcm93384wvg_viper.dts
new file mode 100644
index 000000000000..1ecb2696aca8
--- /dev/null
+++ b/arch/mips/boot/dts/brcm/bcm93384wvg_viper.dts
@@ -0,0 +1,25 @@
1/dts-v1/;
2
3/include/ "bcm3384_viper.dtsi"
4
5/ {
6 compatible = "brcm,bcm93384wvg-viper", "brcm,bcm3384-viper";
7 model = "Broadcom BCM93384WVG-viper";
8
9 chosen {
10 bootargs = "console=ttyS0,115200";
11 stdout-path = &uart0;
12 };
13};
14
15&uart0 {
16 status = "okay";
17};
18
19&ehci0 {
20 status = "okay";
21};
22
23&ohci0 {
24 status = "okay";
25};
diff --git a/arch/mips/boot/dts/brcm/bcm96368mvwg.dts b/arch/mips/boot/dts/brcm/bcm96368mvwg.dts
new file mode 100644
index 000000000000..0e890c28fe5c
--- /dev/null
+++ b/arch/mips/boot/dts/brcm/bcm96368mvwg.dts
@@ -0,0 +1,31 @@
1/dts-v1/;
2
3/include/ "bcm6368.dtsi"
4
5/ {
6 compatible = "brcm,bcm96368mvwg", "brcm,bcm6368";
7 model = "Broadcom BCM96368MVWG";
8
9 memory@0 {
10 device_type = "memory";
11 reg = <0x00000000 0x04000000>;
12 };
13
14 chosen {
15 bootargs = "console=ttyS0,115200";
16 stdout-path = &uart0;
17 };
18};
19
20&uart0 {
21 status = "okay";
22};
23
24/* FIXME: need to set up USB_CTRL registers first */
25&ehci0 {
26 status = "disabled";
27};
28
29&ohci0 {
30 status = "disabled";
31};
diff --git a/arch/mips/boot/dts/brcm/bcm97125cbmb.dts b/arch/mips/boot/dts/brcm/bcm97125cbmb.dts
new file mode 100644
index 000000000000..e046b1109eab
--- /dev/null
+++ b/arch/mips/boot/dts/brcm/bcm97125cbmb.dts
@@ -0,0 +1,31 @@
1/dts-v1/;
2
3/include/ "bcm7125.dtsi"
4
5/ {
6 compatible = "brcm,bcm97125cbmb", "brcm,bcm7125";
7 model = "Broadcom BCM97125CBMB";
8
9 memory@0 {
10 device_type = "memory";
11 reg = <0x00000000 0x10000000>;
12 };
13
14 chosen {
15 bootargs = "console=ttyS0,115200";
16 stdout-path = &uart0;
17 };
18};
19
20&uart0 {
21 status = "okay";
22};
23
24/* FIXME: USB is wonky; disable it for now */
25&ehci0 {
26 status = "disabled";
27};
28
29&ohci0 {
30 status = "disabled";
31};
diff --git a/arch/mips/boot/dts/brcm/bcm97346dbsmb.dts b/arch/mips/boot/dts/brcm/bcm97346dbsmb.dts
new file mode 100644
index 000000000000..70f196d89d26
--- /dev/null
+++ b/arch/mips/boot/dts/brcm/bcm97346dbsmb.dts
@@ -0,0 +1,58 @@
1/dts-v1/;
2
3/include/ "bcm7346.dtsi"
4
5/ {
6 compatible = "brcm,bcm97346dbsmb", "brcm,bcm7346";
7 model = "Broadcom BCM97346DBSMB";
8
9 memory@0 {
10 device_type = "memory";
11 reg = <0x00000000 0x10000000>, <0x20000000 0x30000000>;
12 };
13
14 chosen {
15 bootargs = "console=ttyS0,115200";
16 stdout-path = &uart0;
17 };
18};
19
20&uart0 {
21 status = "okay";
22};
23
24&enet0 {
25 status = "okay";
26};
27
28&ehci0 {
29 status = "okay";
30};
31
32&ohci0 {
33 status = "okay";
34};
35
36&ehci1 {
37 status = "okay";
38};
39
40&ohci1 {
41 status = "okay";
42};
43
44&ehci2 {
45 status = "okay";
46};
47
48&ohci2 {
49 status = "okay";
50};
51
52&ehci3 {
53 status = "okay";
54};
55
56&ohci3 {
57 status = "okay";
58};
diff --git a/arch/mips/boot/dts/brcm/bcm97358svmb.dts b/arch/mips/boot/dts/brcm/bcm97358svmb.dts
new file mode 100644
index 000000000000..d18e6d947739
--- /dev/null
+++ b/arch/mips/boot/dts/brcm/bcm97358svmb.dts
@@ -0,0 +1,34 @@
1/dts-v1/;
2
3/include/ "bcm7358.dtsi"
4
5/ {
6 compatible = "brcm,bcm97358svmb", "brcm,bcm7358";
7 model = "Broadcom BCM97358SVMB";
8
9 memory@0 {
10 device_type = "memory";
11 reg = <0x00000000 0x10000000>;
12 };
13
14 chosen {
15 bootargs = "console=ttyS0,115200";
16 stdout-path = &uart0;
17 };
18};
19
20&uart0 {
21 status = "okay";
22};
23
24&enet0 {
25 status = "okay";
26};
27
28&ehci0 {
29 status = "okay";
30};
31
32&ohci0 {
33 status = "okay";
34};
diff --git a/arch/mips/boot/dts/brcm/bcm97360svmb.dts b/arch/mips/boot/dts/brcm/bcm97360svmb.dts
new file mode 100644
index 000000000000..4fe515500102
--- /dev/null
+++ b/arch/mips/boot/dts/brcm/bcm97360svmb.dts
@@ -0,0 +1,34 @@
1/dts-v1/;
2
3/include/ "bcm7360.dtsi"
4
5/ {
6 compatible = "brcm,bcm97360svmb", "brcm,bcm7360";
7 model = "Broadcom BCM97360SVMB";
8
9 memory@0 {
10 device_type = "memory";
11 reg = <0x00000000 0x10000000>;
12 };
13
14 chosen {
15 bootargs = "console=ttyS0,115200";
16 stdout-path = &uart0;
17 };
18};
19
20&uart0 {
21 status = "okay";
22};
23
24&enet0 {
25 status = "okay";
26};
27
28&ehci0 {
29 status = "okay";
30};
31
32&ohci0 {
33 status = "okay";
34};
diff --git a/arch/mips/boot/dts/brcm/bcm97362svmb.dts b/arch/mips/boot/dts/brcm/bcm97362svmb.dts
new file mode 100644
index 000000000000..b7b88e5dc9e7
--- /dev/null
+++ b/arch/mips/boot/dts/brcm/bcm97362svmb.dts
@@ -0,0 +1,34 @@
1/dts-v1/;
2
3/include/ "bcm7362.dtsi"
4
5/ {
6 compatible = "brcm,bcm97362svmb", "brcm,bcm7362";
7 model = "Broadcom BCM97362SVMB";
8
9 memory@0 {
10 device_type = "memory";
11 reg = <0x00000000 0x10000000>, <0x20000000 0x30000000>;
12 };
13
14 chosen {
15 bootargs = "console=ttyS0,115200";
16 stdout-path = &uart0;
17 };
18};
19
20&uart0 {
21 status = "okay";
22};
23
24&enet0 {
25 status = "okay";
26};
27
28&ehci0 {
29 status = "okay";
30};
31
32&ohci0 {
33 status = "okay";
34};
diff --git a/arch/mips/boot/dts/brcm/bcm97420c.dts b/arch/mips/boot/dts/brcm/bcm97420c.dts
new file mode 100644
index 000000000000..67fe1f3a3891
--- /dev/null
+++ b/arch/mips/boot/dts/brcm/bcm97420c.dts
@@ -0,0 +1,45 @@
1/dts-v1/;
2
3/include/ "bcm7420.dtsi"
4
5/ {
6 compatible = "brcm,bcm97420c", "brcm,bcm7420";
7 model = "Broadcom BCM97420C";
8
9 memory@0 {
10 device_type = "memory";
11 reg = <0x00000000 0x10000000>,
12 <0x20000000 0x30000000>,
13 <0x60000000 0x10000000>;
14 };
15
16 chosen {
17 bootargs = "console=ttyS0,115200";
18 stdout-path = &uart0;
19 };
20};
21
22&uart0 {
23 status = "okay";
24};
25
26/* FIXME: MAC driver comes up but cannot attach to PHY */
27&enet0 {
28 status = "disabled";
29};
30
31&ehci0 {
32 status = "okay";
33};
34
35&ohci0 {
36 status = "okay";
37};
38
39&ehci1 {
40 status = "okay";
41};
42
43&ohci1 {
44 status = "okay";
45};
diff --git a/arch/mips/boot/dts/brcm/bcm97425svmb.dts b/arch/mips/boot/dts/brcm/bcm97425svmb.dts
new file mode 100644
index 000000000000..689c68a4f9c8
--- /dev/null
+++ b/arch/mips/boot/dts/brcm/bcm97425svmb.dts
@@ -0,0 +1,60 @@
1/dts-v1/;
2
3/include/ "bcm7425.dtsi"
4
5/ {
6 compatible = "brcm,bcm97425svmb", "brcm,bcm7425";
7 model = "Broadcom BCM97425SVMB";
8
9 memory@0 {
10 device_type = "memory";
11 reg = <0x00000000 0x10000000>,
12 <0x20000000 0x30000000>,
13 <0x90000000 0x40000000>;
14 };
15
16 chosen {
17 bootargs = "console=ttyS0,115200";
18 stdout-path = &uart0;
19 };
20};
21
22&uart0 {
23 status = "okay";
24};
25
26&enet0 {
27 status = "okay";
28};
29
30&ehci0 {
31 status = "okay";
32};
33
34&ohci0 {
35 status = "okay";
36};
37
38&ehci1 {
39 status = "okay";
40};
41
42&ohci1 {
43 status = "okay";
44};
45
46&ehci2 {
47 status = "okay";
48};
49
50&ohci2 {
51 status = "okay";
52};
53
54&ehci3 {
55 status = "okay";
56};
57
58&ohci3 {
59 status = "okay";
60};
diff --git a/arch/mips/boot/dts/brcm/bcm9ejtagprb.dts b/arch/mips/boot/dts/brcm/bcm9ejtagprb.dts
new file mode 100644
index 000000000000..1da4608680aa
--- /dev/null
+++ b/arch/mips/boot/dts/brcm/bcm9ejtagprb.dts
@@ -0,0 +1,22 @@
1/dts-v1/;
2
3/include/ "bcm6328.dtsi"
4
5/ {
6 compatible = "brcm,bcm9ejtagprb", "brcm,bcm6328";
7 model = "Broadcom BCM9EJTAGPRB";
8
9 memory@0 {
10 device_type = "memory";
11 reg = <0x00000000 0x08000000>;
12 };
13
14 chosen {
15 bootargs = "console=ttyS0,115200";
16 stdout-path = &uart0;
17 };
18};
19
20&uart0 {
21 status = "okay";
22};
diff --git a/arch/mips/boot/dts/cavium-octeon/Makefile b/arch/mips/boot/dts/cavium-octeon/Makefile
new file mode 100644
index 000000000000..5b99c40a058f
--- /dev/null
+++ b/arch/mips/boot/dts/cavium-octeon/Makefile
@@ -0,0 +1,9 @@
1dtb-$(CONFIG_CAVIUM_OCTEON_SOC) += octeon_3xxx.dtb octeon_68xx.dtb
2
3obj-y += $(patsubst %.dtb, %.dtb.o, $(dtb-y))
4
5# Force kbuild to make empty built-in.o if necessary
6obj- += dummy.o
7
8always := $(dtb-y)
9clean-files := *.dtb *.dtb.S
diff --git a/arch/mips/boot/dts/octeon_3xxx.dts b/arch/mips/boot/dts/cavium-octeon/octeon_3xxx.dts
index fa33115bde33..9c48e0586ba7 100644
--- a/arch/mips/boot/dts/octeon_3xxx.dts
+++ b/arch/mips/boot/dts/cavium-octeon/octeon_3xxx.dts
@@ -587,4 +587,16 @@
587 usbn = &usbn; 587 usbn = &usbn;
588 led0 = &led0; 588 led0 = &led0;
589 }; 589 };
590
591 dsr1000n-leds {
592 compatible = "gpio-leds";
593 usb1 {
594 label = "usb1";
595 gpios = <&gpio 9 1>; /* Active low */
596 };
597 usb2 {
598 label = "usb2";
599 gpios = <&gpio 10 1>; /* Active low */
600 };
601 };
590 }; 602 };
diff --git a/arch/mips/boot/dts/octeon_68xx.dts b/arch/mips/boot/dts/cavium-octeon/octeon_68xx.dts
index 79b46fcb0a11..79b46fcb0a11 100644
--- a/arch/mips/boot/dts/octeon_68xx.dts
+++ b/arch/mips/boot/dts/cavium-octeon/octeon_68xx.dts
diff --git a/arch/mips/boot/dts/lantiq/Makefile b/arch/mips/boot/dts/lantiq/Makefile
new file mode 100644
index 000000000000..0906c62141b9
--- /dev/null
+++ b/arch/mips/boot/dts/lantiq/Makefile
@@ -0,0 +1,9 @@
1dtb-$(CONFIG_DT_EASY50712) += easy50712.dtb
2
3obj-y += $(patsubst %.dtb, %.dtb.o, $(dtb-y))
4
5# Force kbuild to make empty built-in.o if necessary
6obj- += dummy.o
7
8always := $(dtb-y)
9clean-files := *.dtb *.dtb.S
diff --git a/arch/mips/boot/dts/danube.dtsi b/arch/mips/boot/dts/lantiq/danube.dtsi
index d4c59e003708..d4c59e003708 100644
--- a/arch/mips/boot/dts/danube.dtsi
+++ b/arch/mips/boot/dts/lantiq/danube.dtsi
diff --git a/arch/mips/boot/dts/easy50712.dts b/arch/mips/boot/dts/lantiq/easy50712.dts
index 143b8a37b5e4..143b8a37b5e4 100644
--- a/arch/mips/boot/dts/easy50712.dts
+++ b/arch/mips/boot/dts/lantiq/easy50712.dts
diff --git a/arch/mips/boot/dts/mti/Makefile b/arch/mips/boot/dts/mti/Makefile
new file mode 100644
index 000000000000..ef1f3dbed033
--- /dev/null
+++ b/arch/mips/boot/dts/mti/Makefile
@@ -0,0 +1,9 @@
1dtb-$(CONFIG_MIPS_SEAD3) += sead3.dtb
2
3obj-y += $(patsubst %.dtb, %.dtb.o, $(dtb-y))
4
5# Force kbuild to make empty built-in.o if necessary
6obj- += dummy.o
7
8always := $(dtb-y)
9clean-files := *.dtb *.dtb.S
diff --git a/arch/mips/boot/dts/sead3.dts b/arch/mips/boot/dts/mti/sead3.dts
index e4b317d414f1..e4b317d414f1 100644
--- a/arch/mips/boot/dts/sead3.dts
+++ b/arch/mips/boot/dts/mti/sead3.dts
diff --git a/arch/mips/boot/dts/netlogic/Makefile b/arch/mips/boot/dts/netlogic/Makefile
new file mode 100644
index 000000000000..9868057140b5
--- /dev/null
+++ b/arch/mips/boot/dts/netlogic/Makefile
@@ -0,0 +1,13 @@
1dtb-$(CONFIG_DT_XLP_EVP) += xlp_evp.dtb
2dtb-$(CONFIG_DT_XLP_SVP) += xlp_svp.dtb
3dtb-$(CONFIG_DT_XLP_FVP) += xlp_fvp.dtb
4dtb-$(CONFIG_DT_XLP_GVP) += xlp_gvp.dtb
5dtb-$(CONFIG_DT_XLP_RVP) += xlp_rvp.dtb
6
7obj-y += $(patsubst %.dtb, %.dtb.o, $(dtb-y))
8
9# Force kbuild to make empty built-in.o if necessary
10obj- += dummy.o
11
12always := $(dtb-y)
13clean-files := *.dtb *.dtb.S
diff --git a/arch/mips/boot/dts/xlp_evp.dts b/arch/mips/boot/dts/netlogic/xlp_evp.dts
index 89ad04808c02..89ad04808c02 100644
--- a/arch/mips/boot/dts/xlp_evp.dts
+++ b/arch/mips/boot/dts/netlogic/xlp_evp.dts
diff --git a/arch/mips/boot/dts/xlp_fvp.dts b/arch/mips/boot/dts/netlogic/xlp_fvp.dts
index 63e62b7bd758..63e62b7bd758 100644
--- a/arch/mips/boot/dts/xlp_fvp.dts
+++ b/arch/mips/boot/dts/netlogic/xlp_fvp.dts
diff --git a/arch/mips/boot/dts/xlp_gvp.dts b/arch/mips/boot/dts/netlogic/xlp_gvp.dts
index bb4ecd1d47fc..bb4ecd1d47fc 100644
--- a/arch/mips/boot/dts/xlp_gvp.dts
+++ b/arch/mips/boot/dts/netlogic/xlp_gvp.dts
diff --git a/arch/mips/boot/dts/netlogic/xlp_rvp.dts b/arch/mips/boot/dts/netlogic/xlp_rvp.dts
new file mode 100644
index 000000000000..7188aed2ea2e
--- /dev/null
+++ b/arch/mips/boot/dts/netlogic/xlp_rvp.dts
@@ -0,0 +1,77 @@
1/*
2 * XLP5XX Device Tree Source for RVP boards
3 */
4
5/dts-v1/;
6/ {
7 model = "netlogic,XLP-RVP";
8 compatible = "netlogic,xlp";
9 #address-cells = <2>;
10 #size-cells = <2>;
11
12 soc {
13 #address-cells = <2>;
14 #size-cells = <1>;
15 compatible = "simple-bus";
16 ranges = <0 0 0 0x18000000 0x04000000 // PCIe CFG
17 1 0 0 0x16000000 0x02000000>; // GBU chipselects
18
19 serial0: serial@30000 {
20 device_type = "serial";
21 compatible = "ns16550";
22 reg = <0 0x112100 0xa00>;
23 reg-shift = <2>;
24 reg-io-width = <4>;
25 clock-frequency = <125000000>;
26 interrupt-parent = <&pic>;
27 interrupts = <17>;
28 };
29 pic: pic@110000 {
30 compatible = "netlogic,xlp-pic";
31 #address-cells = <0>;
32 #interrupt-cells = <1>;
33 reg = <0 0x110000 0x200>;
34 interrupt-controller;
35 };
36
37 nor_flash@1,0 {
38 compatible = "cfi-flash";
39 #address-cells = <1>;
40 #size-cells = <1>;
41 bank-width = <2>;
42 reg = <1 0 0x1000000>;
43
44 partition@0 {
45 label = "x-loader";
46 reg = <0x0 0x100000>; /* 1M */
47 read-only;
48 };
49
50 partition@100000 {
51 label = "u-boot";
52 reg = <0x100000 0x100000>; /* 1M */
53 };
54
55 partition@200000 {
56 label = "kernel";
57 reg = <0x200000 0x500000>; /* 5M */
58 };
59
60 partition@700000 {
61 label = "rootfs";
62 reg = <0x700000 0x800000>; /* 8M */
63 };
64
65 partition@f00000 {
66 label = "env";
67 reg = <0xf00000 0x100000>; /* 1M */
68 read-only;
69 };
70 };
71
72 };
73
74 chosen {
75 bootargs = "console=ttyS0,115200 rdinit=/sbin/init";
76 };
77};
diff --git a/arch/mips/boot/dts/xlp_svp.dts b/arch/mips/boot/dts/netlogic/xlp_svp.dts
index 1ebd00edaacc..1ebd00edaacc 100644
--- a/arch/mips/boot/dts/xlp_svp.dts
+++ b/arch/mips/boot/dts/netlogic/xlp_svp.dts
diff --git a/arch/mips/boot/dts/ralink/Makefile b/arch/mips/boot/dts/ralink/Makefile
new file mode 100644
index 000000000000..2a7225954bf6
--- /dev/null
+++ b/arch/mips/boot/dts/ralink/Makefile
@@ -0,0 +1,12 @@
1dtb-$(CONFIG_DTB_RT2880_EVAL) += rt2880_eval.dtb
2dtb-$(CONFIG_DTB_RT305X_EVAL) += rt3052_eval.dtb
3dtb-$(CONFIG_DTB_RT3883_EVAL) += rt3883_eval.dtb
4dtb-$(CONFIG_DTB_MT7620A_EVAL) += mt7620a_eval.dtb
5
6obj-y += $(patsubst %.dtb, %.dtb.o, $(dtb-y))
7
8# Force kbuild to make empty built-in.o if necessary
9obj- += dummy.o
10
11always := $(dtb-y)
12clean-files := *.dtb *.dtb.S
diff --git a/arch/mips/boot/dts/mt7620a.dtsi b/arch/mips/boot/dts/ralink/mt7620a.dtsi
index 08bf24fefe9f..08bf24fefe9f 100644
--- a/arch/mips/boot/dts/mt7620a.dtsi
+++ b/arch/mips/boot/dts/ralink/mt7620a.dtsi
diff --git a/arch/mips/boot/dts/mt7620a_eval.dts b/arch/mips/boot/dts/ralink/mt7620a_eval.dts
index 709f58132f5c..709f58132f5c 100644
--- a/arch/mips/boot/dts/mt7620a_eval.dts
+++ b/arch/mips/boot/dts/ralink/mt7620a_eval.dts
diff --git a/arch/mips/boot/dts/rt2880.dtsi b/arch/mips/boot/dts/ralink/rt2880.dtsi
index 182afde2f2e1..182afde2f2e1 100644
--- a/arch/mips/boot/dts/rt2880.dtsi
+++ b/arch/mips/boot/dts/ralink/rt2880.dtsi
diff --git a/arch/mips/boot/dts/rt2880_eval.dts b/arch/mips/boot/dts/ralink/rt2880_eval.dts
index 0a685db093d4..0a685db093d4 100644
--- a/arch/mips/boot/dts/rt2880_eval.dts
+++ b/arch/mips/boot/dts/ralink/rt2880_eval.dts
diff --git a/arch/mips/boot/dts/rt3050.dtsi b/arch/mips/boot/dts/ralink/rt3050.dtsi
index e3203d414fee..e3203d414fee 100644
--- a/arch/mips/boot/dts/rt3050.dtsi
+++ b/arch/mips/boot/dts/ralink/rt3050.dtsi
diff --git a/arch/mips/boot/dts/rt3052_eval.dts b/arch/mips/boot/dts/ralink/rt3052_eval.dts
index ec9e9a035541..ec9e9a035541 100644
--- a/arch/mips/boot/dts/rt3052_eval.dts
+++ b/arch/mips/boot/dts/ralink/rt3052_eval.dts
diff --git a/arch/mips/boot/dts/rt3883.dtsi b/arch/mips/boot/dts/ralink/rt3883.dtsi
index 3b131dd0d5ac..3b131dd0d5ac 100644
--- a/arch/mips/boot/dts/rt3883.dtsi
+++ b/arch/mips/boot/dts/ralink/rt3883.dtsi
diff --git a/arch/mips/boot/dts/rt3883_eval.dts b/arch/mips/boot/dts/ralink/rt3883_eval.dts
index e8df21a5d10d..e8df21a5d10d 100644
--- a/arch/mips/boot/dts/rt3883_eval.dts
+++ b/arch/mips/boot/dts/ralink/rt3883_eval.dts
diff --git a/arch/mips/cavium-octeon/crypto/octeon-crypto.h b/arch/mips/cavium-octeon/crypto/octeon-crypto.h
index 355072535110..7315cc307397 100644
--- a/arch/mips/cavium-octeon/crypto/octeon-crypto.h
+++ b/arch/mips/cavium-octeon/crypto/octeon-crypto.h
@@ -33,7 +33,7 @@ do { \
33 __asm__ __volatile__ ( \ 33 __asm__ __volatile__ ( \
34 "dmtc2 %[rt],0x0048+" STR(index) \ 34 "dmtc2 %[rt],0x0048+" STR(index) \
35 : \ 35 : \
36 : [rt] "d" (value)); \ 36 : [rt] "d" (cpu_to_be64(value))); \
37} while (0) 37} while (0)
38 38
39/* 39/*
@@ -48,7 +48,7 @@ do { \
48 : [rt] "=d" (__value) \ 48 : [rt] "=d" (__value) \
49 : ); \ 49 : ); \
50 \ 50 \
51 __value; \ 51 be64_to_cpu(__value); \
52}) 52})
53 53
54/* 54/*
@@ -59,7 +59,7 @@ do { \
59 __asm__ __volatile__ ( \ 59 __asm__ __volatile__ ( \
60 "dmtc2 %[rt],0x0040+" STR(index) \ 60 "dmtc2 %[rt],0x0040+" STR(index) \
61 : \ 61 : \
62 : [rt] "d" (value)); \ 62 : [rt] "d" (cpu_to_be64(value))); \
63} while (0) 63} while (0)
64 64
65/* 65/*
@@ -70,6 +70,80 @@ do { \
70 __asm__ __volatile__ ( \ 70 __asm__ __volatile__ ( \
71 "dmtc2 %[rt],0x4047" \ 71 "dmtc2 %[rt],0x4047" \
72 : \ 72 : \
73 : [rt] "d" (cpu_to_be64(value))); \
74} while (0)
75
76/*
77 * The value is the final block dword (64-bit).
78 */
79#define octeon_sha1_start(value) \
80do { \
81 __asm__ __volatile__ ( \
82 "dmtc2 %[rt],0x4057" \
83 : \
84 : [rt] "d" (value)); \
85} while (0)
86
87/*
88 * The value is the final block dword (64-bit).
89 */
90#define octeon_sha256_start(value) \
91do { \
92 __asm__ __volatile__ ( \
93 "dmtc2 %[rt],0x404f" \
94 : \
95 : [rt] "d" (value)); \
96} while (0)
97
98/*
99 * Macros needed to implement SHA512:
100 */
101
102/*
103 * The index can be 0-7.
104 */
105#define write_octeon_64bit_hash_sha512(value, index) \
106do { \
107 __asm__ __volatile__ ( \
108 "dmtc2 %[rt],0x0250+" STR(index) \
109 : \
110 : [rt] "d" (value)); \
111} while (0)
112
113/*
114 * The index can be 0-7.
115 */
116#define read_octeon_64bit_hash_sha512(index) \
117({ \
118 u64 __value; \
119 \
120 __asm__ __volatile__ ( \
121 "dmfc2 %[rt],0x0250+" STR(index) \
122 : [rt] "=d" (__value) \
123 : ); \
124 \
125 __value; \
126})
127
128/*
129 * The index can be 0-14.
130 */
131#define write_octeon_64bit_block_sha512(value, index) \
132do { \
133 __asm__ __volatile__ ( \
134 "dmtc2 %[rt],0x0240+" STR(index) \
135 : \
136 : [rt] "d" (value)); \
137} while (0)
138
139/*
140 * The value is the final block word (64-bit).
141 */
142#define octeon_sha512_start(value) \
143do { \
144 __asm__ __volatile__ ( \
145 "dmtc2 %[rt],0x424f" \
146 : \
73 : [rt] "d" (value)); \ 147 : [rt] "d" (value)); \
74} while (0) 148} while (0)
75 149
diff --git a/arch/mips/cavium-octeon/dma-octeon.c b/arch/mips/cavium-octeon/dma-octeon.c
index 7d8987818ccf..d8960d46417b 100644
--- a/arch/mips/cavium-octeon/dma-octeon.c
+++ b/arch/mips/cavium-octeon/dma-octeon.c
@@ -306,7 +306,7 @@ void __init plat_swiotlb_setup(void)
306 swiotlbsize = 64 * (1<<20); 306 swiotlbsize = 64 * (1<<20);
307 } 307 }
308#endif 308#endif
309#ifdef CONFIG_USB_OCTEON_OHCI 309#ifdef CONFIG_USB_OHCI_HCD_PLATFORM
310 /* OCTEON II ohci is only 32-bit. */ 310 /* OCTEON II ohci is only 32-bit. */
311 if (OCTEON_IS_OCTEON2() && max_addr >= 0x100000000ul) 311 if (OCTEON_IS_OCTEON2() && max_addr >= 0x100000000ul)
312 swiotlbsize = 64 * (1<<20); 312 swiotlbsize = 64 * (1<<20);
diff --git a/arch/mips/cavium-octeon/executive/cvmx-l2c.c b/arch/mips/cavium-octeon/executive/cvmx-l2c.c
index 42e38c30b540..89b5273299ab 100644
--- a/arch/mips/cavium-octeon/executive/cvmx-l2c.c
+++ b/arch/mips/cavium-octeon/executive/cvmx-l2c.c
@@ -519,44 +519,89 @@ int cvmx_l2c_unlock_mem_region(uint64_t start, uint64_t len)
519union __cvmx_l2c_tag { 519union __cvmx_l2c_tag {
520 uint64_t u64; 520 uint64_t u64;
521 struct cvmx_l2c_tag_cn50xx { 521 struct cvmx_l2c_tag_cn50xx {
522#ifdef __BIG_ENDIAN_BITFIELD
522 uint64_t reserved:40; 523 uint64_t reserved:40;
523 uint64_t V:1; /* Line valid */ 524 uint64_t V:1; /* Line valid */
524 uint64_t D:1; /* Line dirty */ 525 uint64_t D:1; /* Line dirty */
525 uint64_t L:1; /* Line locked */ 526 uint64_t L:1; /* Line locked */
526 uint64_t U:1; /* Use, LRU eviction */ 527 uint64_t U:1; /* Use, LRU eviction */
527 uint64_t addr:20; /* Phys mem addr (33..14) */ 528 uint64_t addr:20; /* Phys mem addr (33..14) */
529#else
530 uint64_t addr:20; /* Phys mem addr (33..14) */
531 uint64_t U:1; /* Use, LRU eviction */
532 uint64_t L:1; /* Line locked */
533 uint64_t D:1; /* Line dirty */
534 uint64_t V:1; /* Line valid */
535 uint64_t reserved:40;
536#endif
528 } cn50xx; 537 } cn50xx;
529 struct cvmx_l2c_tag_cn30xx { 538 struct cvmx_l2c_tag_cn30xx {
539#ifdef __BIG_ENDIAN_BITFIELD
530 uint64_t reserved:41; 540 uint64_t reserved:41;
531 uint64_t V:1; /* Line valid */ 541 uint64_t V:1; /* Line valid */
532 uint64_t D:1; /* Line dirty */ 542 uint64_t D:1; /* Line dirty */
533 uint64_t L:1; /* Line locked */ 543 uint64_t L:1; /* Line locked */
534 uint64_t U:1; /* Use, LRU eviction */ 544 uint64_t U:1; /* Use, LRU eviction */
535 uint64_t addr:19; /* Phys mem addr (33..15) */ 545 uint64_t addr:19; /* Phys mem addr (33..15) */
546#else
547 uint64_t addr:19; /* Phys mem addr (33..15) */
548 uint64_t U:1; /* Use, LRU eviction */
549 uint64_t L:1; /* Line locked */
550 uint64_t D:1; /* Line dirty */
551 uint64_t V:1; /* Line valid */
552 uint64_t reserved:41;
553#endif
536 } cn30xx; 554 } cn30xx;
537 struct cvmx_l2c_tag_cn31xx { 555 struct cvmx_l2c_tag_cn31xx {
556#ifdef __BIG_ENDIAN_BITFIELD
538 uint64_t reserved:42; 557 uint64_t reserved:42;
539 uint64_t V:1; /* Line valid */ 558 uint64_t V:1; /* Line valid */
540 uint64_t D:1; /* Line dirty */ 559 uint64_t D:1; /* Line dirty */
541 uint64_t L:1; /* Line locked */ 560 uint64_t L:1; /* Line locked */
542 uint64_t U:1; /* Use, LRU eviction */ 561 uint64_t U:1; /* Use, LRU eviction */
543 uint64_t addr:18; /* Phys mem addr (33..16) */ 562 uint64_t addr:18; /* Phys mem addr (33..16) */
563#else
564 uint64_t addr:18; /* Phys mem addr (33..16) */
565 uint64_t U:1; /* Use, LRU eviction */
566 uint64_t L:1; /* Line locked */
567 uint64_t D:1; /* Line dirty */
568 uint64_t V:1; /* Line valid */
569 uint64_t reserved:42;
570#endif
544 } cn31xx; 571 } cn31xx;
545 struct cvmx_l2c_tag_cn38xx { 572 struct cvmx_l2c_tag_cn38xx {
573#ifdef __BIG_ENDIAN_BITFIELD
546 uint64_t reserved:43; 574 uint64_t reserved:43;
547 uint64_t V:1; /* Line valid */ 575 uint64_t V:1; /* Line valid */
548 uint64_t D:1; /* Line dirty */ 576 uint64_t D:1; /* Line dirty */
549 uint64_t L:1; /* Line locked */ 577 uint64_t L:1; /* Line locked */
550 uint64_t U:1; /* Use, LRU eviction */ 578 uint64_t U:1; /* Use, LRU eviction */
551 uint64_t addr:17; /* Phys mem addr (33..17) */ 579 uint64_t addr:17; /* Phys mem addr (33..17) */
580#else
581 uint64_t addr:17; /* Phys mem addr (33..17) */
582 uint64_t U:1; /* Use, LRU eviction */
583 uint64_t L:1; /* Line locked */
584 uint64_t D:1; /* Line dirty */
585 uint64_t V:1; /* Line valid */
586 uint64_t reserved:43;
587#endif
552 } cn38xx; 588 } cn38xx;
553 struct cvmx_l2c_tag_cn58xx { 589 struct cvmx_l2c_tag_cn58xx {
590#ifdef __BIG_ENDIAN_BITFIELD
554 uint64_t reserved:44; 591 uint64_t reserved:44;
555 uint64_t V:1; /* Line valid */ 592 uint64_t V:1; /* Line valid */
556 uint64_t D:1; /* Line dirty */ 593 uint64_t D:1; /* Line dirty */
557 uint64_t L:1; /* Line locked */ 594 uint64_t L:1; /* Line locked */
558 uint64_t U:1; /* Use, LRU eviction */ 595 uint64_t U:1; /* Use, LRU eviction */
559 uint64_t addr:16; /* Phys mem addr (33..18) */ 596 uint64_t addr:16; /* Phys mem addr (33..18) */
597#else
598 uint64_t addr:16; /* Phys mem addr (33..18) */
599 uint64_t U:1; /* Use, LRU eviction */
600 uint64_t L:1; /* Line locked */
601 uint64_t D:1; /* Line dirty */
602 uint64_t V:1; /* Line valid */
603 uint64_t reserved:44;
604#endif
560 } cn58xx; 605 } cn58xx;
561 struct cvmx_l2c_tag_cn58xx cn56xx; /* 2048 sets */ 606 struct cvmx_l2c_tag_cn58xx cn56xx; /* 2048 sets */
562 struct cvmx_l2c_tag_cn31xx cn52xx; /* 512 sets */ 607 struct cvmx_l2c_tag_cn31xx cn52xx; /* 512 sets */
diff --git a/arch/mips/cavium-octeon/flash_setup.c b/arch/mips/cavium-octeon/flash_setup.c
index 237e5b1a72d8..a5e8f4a784af 100644
--- a/arch/mips/cavium-octeon/flash_setup.c
+++ b/arch/mips/cavium-octeon/flash_setup.c
@@ -8,9 +8,11 @@
8 * Copyright (C) 2007, 2008 Cavium Networks 8 * Copyright (C) 2007, 2008 Cavium Networks
9 */ 9 */
10#include <linux/kernel.h> 10#include <linux/kernel.h>
11#include <linux/export.h> 11#include <linux/module.h>
12#include <linux/semaphore.h>
12#include <linux/mtd/mtd.h> 13#include <linux/mtd/mtd.h>
13#include <linux/mtd/map.h> 14#include <linux/mtd/map.h>
15#include <linux/of_platform.h>
14#include <linux/mtd/partitions.h> 16#include <linux/mtd/partitions.h>
15 17
16#include <asm/octeon/octeon.h> 18#include <asm/octeon/octeon.h>
@@ -25,19 +27,62 @@ static const char *part_probe_types[] = {
25 NULL 27 NULL
26}; 28};
27 29
30static map_word octeon_flash_map_read(struct map_info *map, unsigned long ofs)
31{
32 map_word r;
33
34 down(&octeon_bootbus_sem);
35 r = inline_map_read(map, ofs);
36 up(&octeon_bootbus_sem);
37
38 return r;
39}
40
41static void octeon_flash_map_write(struct map_info *map, const map_word datum,
42 unsigned long ofs)
43{
44 down(&octeon_bootbus_sem);
45 inline_map_write(map, datum, ofs);
46 up(&octeon_bootbus_sem);
47}
48
49static void octeon_flash_map_copy_from(struct map_info *map, void *to,
50 unsigned long from, ssize_t len)
51{
52 down(&octeon_bootbus_sem);
53 inline_map_copy_from(map, to, from, len);
54 up(&octeon_bootbus_sem);
55}
56
57static void octeon_flash_map_copy_to(struct map_info *map, unsigned long to,
58 const void *from, ssize_t len)
59{
60 down(&octeon_bootbus_sem);
61 inline_map_copy_to(map, to, from, len);
62 up(&octeon_bootbus_sem);
63}
64
28/** 65/**
29 * Module/ driver initialization. 66 * Module/ driver initialization.
30 * 67 *
31 * Returns Zero on success 68 * Returns Zero on success
32 */ 69 */
33static int __init flash_init(void) 70static int octeon_flash_probe(struct platform_device *pdev)
34{ 71{
72 union cvmx_mio_boot_reg_cfgx region_cfg;
73 u32 cs;
74 int r;
75 struct device_node *np = pdev->dev.of_node;
76
77 r = of_property_read_u32(np, "reg", &cs);
78 if (r)
79 return r;
80
35 /* 81 /*
36 * Read the bootbus region 0 setup to determine the base 82 * Read the bootbus region 0 setup to determine the base
37 * address of the flash. 83 * address of the flash.
38 */ 84 */
39 union cvmx_mio_boot_reg_cfgx region_cfg; 85 region_cfg.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(cs));
40 region_cfg.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(0));
41 if (region_cfg.s.en) { 86 if (region_cfg.s.en) {
42 /* 87 /*
43 * The bootloader always takes the flash and sets its 88 * The bootloader always takes the flash and sets its
@@ -56,7 +101,11 @@ static int __init flash_init(void)
56 flash_map.virt = ioremap(flash_map.phys, flash_map.size); 101 flash_map.virt = ioremap(flash_map.phys, flash_map.size);
57 pr_notice("Bootbus flash: Setting flash for %luMB flash at " 102 pr_notice("Bootbus flash: Setting flash for %luMB flash at "
58 "0x%08llx\n", flash_map.size >> 20, flash_map.phys); 103 "0x%08llx\n", flash_map.size >> 20, flash_map.phys);
59 simple_map_init(&flash_map); 104 WARN_ON(!map_bankwidth_supported(flash_map.bankwidth));
105 flash_map.read = octeon_flash_map_read;
106 flash_map.write = octeon_flash_map_write;
107 flash_map.copy_from = octeon_flash_map_copy_from;
108 flash_map.copy_to = octeon_flash_map_copy_to;
60 mymtd = do_map_probe("cfi_probe", &flash_map); 109 mymtd = do_map_probe("cfi_probe", &flash_map);
61 if (mymtd) { 110 if (mymtd) {
62 mymtd->owner = THIS_MODULE; 111 mymtd->owner = THIS_MODULE;
@@ -69,4 +118,26 @@ static int __init flash_init(void)
69 return 0; 118 return 0;
70} 119}
71 120
72late_initcall(flash_init); 121static const struct of_device_id of_flash_match[] = {
122 {
123 .compatible = "cfi-flash",
124 },
125 { },
126};
127MODULE_DEVICE_TABLE(of, of_flash_match);
128
129static struct platform_driver of_flash_driver = {
130 .driver = {
131 .name = "octeon-of-flash",
132 .of_match_table = of_flash_match,
133 },
134 .probe = octeon_flash_probe,
135};
136
137static int octeon_flash_init(void)
138{
139 return platform_driver_register(&of_flash_driver);
140}
141late_initcall(octeon_flash_init);
142
143MODULE_LICENSE("GPL");
diff --git a/arch/mips/cavium-octeon/octeon-platform.c b/arch/mips/cavium-octeon/octeon-platform.c
index 12410a2788d8..d113c8ded6e2 100644
--- a/arch/mips/cavium-octeon/octeon-platform.c
+++ b/arch/mips/cavium-octeon/octeon-platform.c
@@ -325,8 +325,14 @@ static void __init octeon_ehci_hw_start(struct device *dev)
325 /* Use 64-bit addressing. */ 325 /* Use 64-bit addressing. */
326 ehci_ctl.s.ehci_64b_addr_en = 1; 326 ehci_ctl.s.ehci_64b_addr_en = 1;
327 ehci_ctl.s.l2c_addr_msb = 0; 327 ehci_ctl.s.l2c_addr_msb = 0;
328#ifdef __BIG_ENDIAN
328 ehci_ctl.s.l2c_buff_emod = 1; /* Byte swapped. */ 329 ehci_ctl.s.l2c_buff_emod = 1; /* Byte swapped. */
329 ehci_ctl.s.l2c_desc_emod = 1; /* Byte swapped. */ 330 ehci_ctl.s.l2c_desc_emod = 1; /* Byte swapped. */
331#else
332 ehci_ctl.s.l2c_buff_emod = 0; /* not swapped. */
333 ehci_ctl.s.l2c_desc_emod = 0; /* not swapped. */
334 ehci_ctl.s.inv_reg_a2 = 1;
335#endif
330 cvmx_write_csr(CVMX_UCTLX_EHCI_CTL(0), ehci_ctl.u64); 336 cvmx_write_csr(CVMX_UCTLX_EHCI_CTL(0), ehci_ctl.u64);
331 337
332 octeon2_usb_clocks_stop(); 338 octeon2_usb_clocks_stop();
@@ -381,8 +387,14 @@ static void __init octeon_ohci_hw_start(struct device *dev)
381 387
382 ohci_ctl.u64 = cvmx_read_csr(CVMX_UCTLX_OHCI_CTL(0)); 388 ohci_ctl.u64 = cvmx_read_csr(CVMX_UCTLX_OHCI_CTL(0));
383 ohci_ctl.s.l2c_addr_msb = 0; 389 ohci_ctl.s.l2c_addr_msb = 0;
390#ifdef __BIG_ENDIAN
384 ohci_ctl.s.l2c_buff_emod = 1; /* Byte swapped. */ 391 ohci_ctl.s.l2c_buff_emod = 1; /* Byte swapped. */
385 ohci_ctl.s.l2c_desc_emod = 1; /* Byte swapped. */ 392 ohci_ctl.s.l2c_desc_emod = 1; /* Byte swapped. */
393#else
394 ohci_ctl.s.l2c_buff_emod = 0; /* not swapped. */
395 ohci_ctl.s.l2c_desc_emod = 0; /* not swapped. */
396 ohci_ctl.s.inv_reg_a2 = 1;
397#endif
386 cvmx_write_csr(CVMX_UCTLX_OHCI_CTL(0), ohci_ctl.u64); 398 cvmx_write_csr(CVMX_UCTLX_OHCI_CTL(0), ohci_ctl.u64);
387 399
388 octeon2_usb_clocks_stop(); 400 octeon2_usb_clocks_stop();
@@ -958,6 +970,13 @@ end_led:
958 } 970 }
959 } 971 }
960 972
973 if (octeon_bootinfo->board_type != CVMX_BOARD_TYPE_CUST_DSR1000N) {
974 int dsr1000n_leds = fdt_path_offset(initial_boot_params,
975 "/dsr1000n-leds");
976 if (dsr1000n_leds >= 0)
977 fdt_nop_node(initial_boot_params, dsr1000n_leds);
978 }
979
961 return 0; 980 return 0;
962} 981}
963 982
diff --git a/arch/mips/cavium-octeon/octeon_boot.h b/arch/mips/cavium-octeon/octeon_boot.h
index 7b066bbca86d..a6ce7c43e0ae 100644
--- a/arch/mips/cavium-octeon/octeon_boot.h
+++ b/arch/mips/cavium-octeon/octeon_boot.h
@@ -37,11 +37,13 @@ struct boot_init_vector {
37 37
38/* similar to bootloader's linux_app_boot_info but without global data */ 38/* similar to bootloader's linux_app_boot_info but without global data */
39struct linux_app_boot_info { 39struct linux_app_boot_info {
40#ifdef __BIG_ENDIAN_BITFIELD
40 uint32_t labi_signature; 41 uint32_t labi_signature;
41 uint32_t start_core0_addr; 42 uint32_t start_core0_addr;
42 uint32_t avail_coremask; 43 uint32_t avail_coremask;
43 uint32_t pci_console_active; 44 uint32_t pci_console_active;
44 uint32_t icache_prefetch_disable; 45 uint32_t icache_prefetch_disable;
46 uint32_t padding;
45 uint64_t InitTLBStart_addr; 47 uint64_t InitTLBStart_addr;
46 uint32_t start_app_addr; 48 uint32_t start_app_addr;
47 uint32_t cur_exception_base; 49 uint32_t cur_exception_base;
@@ -49,6 +51,27 @@ struct linux_app_boot_info {
49 uint32_t compact_flash_common_base_addr; 51 uint32_t compact_flash_common_base_addr;
50 uint32_t compact_flash_attribute_base_addr; 52 uint32_t compact_flash_attribute_base_addr;
51 uint32_t led_display_base_addr; 53 uint32_t led_display_base_addr;
54#else
55 uint32_t start_core0_addr;
56 uint32_t labi_signature;
57
58 uint32_t pci_console_active;
59 uint32_t avail_coremask;
60
61 uint32_t padding;
62 uint32_t icache_prefetch_disable;
63
64 uint64_t InitTLBStart_addr;
65
66 uint32_t cur_exception_base;
67 uint32_t start_app_addr;
68
69 uint32_t compact_flash_common_base_addr;
70 uint32_t no_mark_private_data;
71
72 uint32_t led_display_base_addr;
73 uint32_t compact_flash_attribute_base_addr;
74#endif
52}; 75};
53 76
54/* If not to copy a lot of bootloader's structures 77/* If not to copy a lot of bootloader's structures
diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c
index a42110e7edbc..89a628455bc2 100644
--- a/arch/mips/cavium-octeon/setup.c
+++ b/arch/mips/cavium-octeon/setup.c
@@ -51,6 +51,9 @@ extern void pci_console_init(const char *arg);
51 51
52static unsigned long long MAX_MEMORY = 512ull << 20; 52static unsigned long long MAX_MEMORY = 512ull << 20;
53 53
54DEFINE_SEMAPHORE(octeon_bootbus_sem);
55EXPORT_SYMBOL(octeon_bootbus_sem);
56
54struct octeon_boot_descriptor *octeon_boot_desc_ptr; 57struct octeon_boot_descriptor *octeon_boot_desc_ptr;
55 58
56struct cvmx_bootinfo *octeon_bootinfo; 59struct cvmx_bootinfo *octeon_bootinfo;
@@ -413,7 +416,10 @@ static void octeon_restart(char *command)
413 416
414 mb(); 417 mb();
415 while (1) 418 while (1)
416 cvmx_write_csr(CVMX_CIU_SOFT_RST, 1); 419 if (OCTEON_IS_OCTEON3())
420 cvmx_write_csr(CVMX_RST_SOFT_RST, 1);
421 else
422 cvmx_write_csr(CVMX_CIU_SOFT_RST, 1);
417} 423}
418 424
419 425
@@ -1043,7 +1049,7 @@ int prom_putchar(char c)
1043} 1049}
1044EXPORT_SYMBOL(prom_putchar); 1050EXPORT_SYMBOL(prom_putchar);
1045 1051
1046void prom_free_prom_memory(void) 1052void __init prom_free_prom_memory(void)
1047{ 1053{
1048 if (CAVIUM_OCTEON_DCACHE_PREFETCH_WAR) { 1054 if (CAVIUM_OCTEON_DCACHE_PREFETCH_WAR) {
1049 /* Check for presence of Core-14449 fix. */ 1055 /* Check for presence of Core-14449 fix. */
diff --git a/arch/mips/configs/bcm3384_defconfig b/arch/mips/configs/bmips_be_defconfig
index 88711c28ff32..f5585c8f35ad 100644
--- a/arch/mips/configs/bcm3384_defconfig
+++ b/arch/mips/configs/bmips_be_defconfig
@@ -1,4 +1,4 @@
1CONFIG_BCM3384=y 1CONFIG_BMIPS_GENERIC=y
2CONFIG_HIGHMEM=y 2CONFIG_HIGHMEM=y
3CONFIG_SMP=y 3CONFIG_SMP=y
4CONFIG_NR_CPUS=4 4CONFIG_NR_CPUS=4
@@ -33,6 +33,7 @@ CONFIG_DEVTMPFS=y
33CONFIG_DEVTMPFS_MOUNT=y 33CONFIG_DEVTMPFS_MOUNT=y
34# CONFIG_STANDALONE is not set 34# CONFIG_STANDALONE is not set
35# CONFIG_PREVENT_FIRMWARE_BUILD is not set 35# CONFIG_PREVENT_FIRMWARE_BUILD is not set
36CONFIG_BRCMSTB_GISB_ARB=y
36CONFIG_MTD=y 37CONFIG_MTD=y
37CONFIG_MTD_CFI=y 38CONFIG_MTD_CFI=y
38CONFIG_MTD_CFI_INTELEXT=y 39CONFIG_MTD_CFI_INTELEXT=y
@@ -43,15 +44,19 @@ CONFIG_SCSI=y
43CONFIG_BLK_DEV_SD=y 44CONFIG_BLK_DEV_SD=y
44# CONFIG_SCSI_LOWLEVEL is not set 45# CONFIG_SCSI_LOWLEVEL is not set
45CONFIG_NETDEVICES=y 46CONFIG_NETDEVICES=y
47CONFIG_BCMGENET=y
46CONFIG_USB_USBNET=y 48CONFIG_USB_USBNET=y
47# CONFIG_INPUT is not set 49# CONFIG_INPUT is not set
48# CONFIG_SERIO is not set 50# CONFIG_SERIO is not set
49# CONFIG_VT is not set 51# CONFIG_VT is not set
50# CONFIG_DEVKMEM is not set 52# CONFIG_DEVKMEM is not set
51CONFIG_SERIAL_EARLYCON_FORCE=y
52CONFIG_SERIAL_BCM63XX=y 53CONFIG_SERIAL_BCM63XX=y
53CONFIG_SERIAL_BCM63XX_CONSOLE=y 54CONFIG_SERIAL_BCM63XX_CONSOLE=y
54# CONFIG_HW_RANDOM is not set 55# CONFIG_HW_RANDOM is not set
56CONFIG_POWER_SUPPLY=y
57CONFIG_POWER_RESET=y
58CONFIG_POWER_RESET_BRCMSTB=y
59CONFIG_POWER_RESET_SYSCON=y
55# CONFIG_HWMON is not set 60# CONFIG_HWMON is not set
56CONFIG_USB=y 61CONFIG_USB=y
57CONFIG_USB_EHCI_HCD=y 62CONFIG_USB_EHCI_HCD=y
@@ -75,4 +80,6 @@ CONFIG_NLS_ASCII=y
75CONFIG_NLS_ISO8859_1=y 80CONFIG_NLS_ISO8859_1=y
76CONFIG_DEBUG_FS=y 81CONFIG_DEBUG_FS=y
77CONFIG_MAGIC_SYSRQ=y 82CONFIG_MAGIC_SYSRQ=y
83CONFIG_CMDLINE_BOOL=y
84CONFIG_CMDLINE="earlycon"
78# CONFIG_CRYPTO_HW is not set 85# CONFIG_CRYPTO_HW is not set
diff --git a/arch/mips/configs/bmips_stb_defconfig b/arch/mips/configs/bmips_stb_defconfig
new file mode 100644
index 000000000000..400a47ec1ef1
--- /dev/null
+++ b/arch/mips/configs/bmips_stb_defconfig
@@ -0,0 +1,88 @@
1CONFIG_BMIPS_GENERIC=y
2CONFIG_CPU_LITTLE_ENDIAN=y
3CONFIG_HIGHMEM=y
4CONFIG_SMP=y
5CONFIG_NR_CPUS=4
6# CONFIG_SECCOMP is not set
7CONFIG_MIPS_O32_FP64_SUPPORT=y
8# CONFIG_LOCALVERSION_AUTO is not set
9# CONFIG_SWAP is not set
10CONFIG_NO_HZ=y
11CONFIG_BLK_DEV_INITRD=y
12# CONFIG_RD_GZIP is not set
13CONFIG_EXPERT=y
14# CONFIG_VM_EVENT_COUNTERS is not set
15# CONFIG_SLUB_DEBUG is not set
16# CONFIG_BLK_DEV_BSG is not set
17# CONFIG_IOSCHED_DEADLINE is not set
18# CONFIG_IOSCHED_CFQ is not set
19CONFIG_NET=y
20CONFIG_PACKET=y
21CONFIG_PACKET_DIAG=y
22CONFIG_UNIX=y
23CONFIG_INET=y
24# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
25# CONFIG_INET_XFRM_MODE_TUNNEL is not set
26# CONFIG_INET_XFRM_MODE_BEET is not set
27# CONFIG_INET_LRO is not set
28# CONFIG_INET_DIAG is not set
29CONFIG_CFG80211=y
30CONFIG_NL80211_TESTMODE=y
31CONFIG_MAC80211=y
32CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
33CONFIG_DEVTMPFS=y
34CONFIG_DEVTMPFS_MOUNT=y
35# CONFIG_STANDALONE is not set
36# CONFIG_PREVENT_FIRMWARE_BUILD is not set
37CONFIG_BRCMSTB_GISB_ARB=y
38CONFIG_MTD=y
39CONFIG_MTD_CFI=y
40CONFIG_MTD_CFI_INTELEXT=y
41CONFIG_MTD_CFI_AMDSTD=y
42CONFIG_MTD_PHYSMAP=y
43# CONFIG_BLK_DEV is not set
44CONFIG_SCSI=y
45CONFIG_BLK_DEV_SD=y
46# CONFIG_SCSI_LOWLEVEL is not set
47CONFIG_NETDEVICES=y
48CONFIG_BCMGENET=y
49CONFIG_USB_USBNET=y
50# CONFIG_INPUT is not set
51# CONFIG_SERIO is not set
52# CONFIG_VT is not set
53# CONFIG_DEVKMEM is not set
54CONFIG_SERIAL_8250=y
55# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set
56CONFIG_SERIAL_8250_CONSOLE=y
57CONFIG_SERIAL_OF_PLATFORM=y
58# CONFIG_HW_RANDOM is not set
59CONFIG_POWER_SUPPLY=y
60CONFIG_POWER_RESET=y
61CONFIG_POWER_RESET_BRCMSTB=y
62CONFIG_POWER_RESET_SYSCON=y
63# CONFIG_HWMON is not set
64CONFIG_USB=y
65CONFIG_USB_EHCI_HCD=y
66# CONFIG_USB_EHCI_TT_NEWSCHED is not set
67CONFIG_USB_EHCI_HCD_PLATFORM=y
68CONFIG_USB_OHCI_HCD=y
69CONFIG_USB_OHCI_HCD_PLATFORM=y
70CONFIG_USB_STORAGE=y
71CONFIG_EXT4_FS=y
72CONFIG_EXT4_FS_POSIX_ACL=y
73CONFIG_EXT4_FS_SECURITY=y
74# CONFIG_DNOTIFY is not set
75CONFIG_FUSE_FS=y
76CONFIG_VFAT_FS=y
77CONFIG_PROC_KCORE=y
78CONFIG_TMPFS=y
79CONFIG_NFS_FS=y
80CONFIG_CIFS=y
81CONFIG_NLS_CODEPAGE_437=y
82CONFIG_NLS_ASCII=y
83CONFIG_NLS_ISO8859_1=y
84CONFIG_DEBUG_FS=y
85CONFIG_MAGIC_SYSRQ=y
86CONFIG_CMDLINE_BOOL=y
87CONFIG_CMDLINE="earlycon"
88# CONFIG_CRYPTO_HW is not set
diff --git a/arch/mips/configs/maltaup_xpa_defconfig b/arch/mips/configs/maltaup_xpa_defconfig
new file mode 100644
index 000000000000..c388bff09148
--- /dev/null
+++ b/arch/mips/configs/maltaup_xpa_defconfig
@@ -0,0 +1,439 @@
1CONFIG_MIPS_MALTA=y
2CONFIG_CPU_LITTLE_ENDIAN=y
3CONFIG_CPU_MIPS32_R2=y
4CONFIG_CPU_MIPS32_R5_FEATURES=y
5CONFIG_CPU_MIPS32_R5_XPA=y
6CONFIG_PAGE_SIZE_16KB=y
7CONFIG_HZ_100=y
8CONFIG_SYSVIPC=y
9CONFIG_NO_HZ=y
10CONFIG_HIGH_RES_TIMERS=y
11CONFIG_IKCONFIG=y
12CONFIG_IKCONFIG_PROC=y
13CONFIG_LOG_BUF_SHIFT=15
14CONFIG_NAMESPACES=y
15CONFIG_RELAY=y
16CONFIG_EXPERT=y
17# CONFIG_COMPAT_BRK is not set
18CONFIG_SLAB=y
19CONFIG_MODULES=y
20CONFIG_MODULE_UNLOAD=y
21CONFIG_MODVERSIONS=y
22CONFIG_MODULE_SRCVERSION_ALL=y
23CONFIG_PCI=y
24CONFIG_NET=y
25CONFIG_PACKET=y
26CONFIG_UNIX=y
27CONFIG_XFRM_USER=m
28CONFIG_NET_KEY=y
29CONFIG_NET_KEY_MIGRATE=y
30CONFIG_INET=y
31CONFIG_IP_MULTICAST=y
32CONFIG_IP_ADVANCED_ROUTER=y
33CONFIG_IP_MULTIPLE_TABLES=y
34CONFIG_IP_ROUTE_MULTIPATH=y
35CONFIG_IP_ROUTE_VERBOSE=y
36CONFIG_IP_PNP=y
37CONFIG_IP_PNP_DHCP=y
38CONFIG_IP_PNP_BOOTP=y
39CONFIG_NET_IPIP=m
40CONFIG_IP_MROUTE=y
41CONFIG_IP_PIMSM_V1=y
42CONFIG_IP_PIMSM_V2=y
43CONFIG_SYN_COOKIES=y
44CONFIG_INET_AH=m
45CONFIG_INET_ESP=m
46CONFIG_INET_IPCOMP=m
47CONFIG_INET_XFRM_MODE_TRANSPORT=m
48CONFIG_INET_XFRM_MODE_TUNNEL=m
49CONFIG_TCP_MD5SIG=y
50CONFIG_IPV6_ROUTER_PREF=y
51CONFIG_IPV6_ROUTE_INFO=y
52CONFIG_IPV6_OPTIMISTIC_DAD=y
53CONFIG_INET6_AH=m
54CONFIG_INET6_ESP=m
55CONFIG_INET6_IPCOMP=m
56CONFIG_IPV6_TUNNEL=m
57CONFIG_IPV6_MROUTE=y
58CONFIG_IPV6_PIMSM_V2=y
59CONFIG_NETWORK_SECMARK=y
60CONFIG_NETFILTER=y
61CONFIG_NF_CONNTRACK=m
62CONFIG_NF_CONNTRACK_SECMARK=y
63CONFIG_NF_CONNTRACK_EVENTS=y
64CONFIG_NF_CT_PROTO_DCCP=m
65CONFIG_NF_CT_PROTO_UDPLITE=m
66CONFIG_NF_CONNTRACK_AMANDA=m
67CONFIG_NF_CONNTRACK_FTP=m
68CONFIG_NF_CONNTRACK_H323=m
69CONFIG_NF_CONNTRACK_IRC=m
70CONFIG_NF_CONNTRACK_PPTP=m
71CONFIG_NF_CONNTRACK_SANE=m
72CONFIG_NF_CONNTRACK_SIP=m
73CONFIG_NF_CONNTRACK_TFTP=m
74CONFIG_NF_CT_NETLINK=m
75CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
76CONFIG_NETFILTER_XT_TARGET_CONNMARK=m
77CONFIG_NETFILTER_XT_TARGET_MARK=m
78CONFIG_NETFILTER_XT_TARGET_NFLOG=m
79CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
80CONFIG_NETFILTER_XT_TARGET_TRACE=m
81CONFIG_NETFILTER_XT_TARGET_SECMARK=m
82CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
83CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m
84CONFIG_NETFILTER_XT_MATCH_COMMENT=m
85CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
86CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m
87CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
88CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
89CONFIG_NETFILTER_XT_MATCH_DCCP=m
90CONFIG_NETFILTER_XT_MATCH_ESP=m
91CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
92CONFIG_NETFILTER_XT_MATCH_HELPER=m
93CONFIG_NETFILTER_XT_MATCH_IPRANGE=m
94CONFIG_NETFILTER_XT_MATCH_LENGTH=m
95CONFIG_NETFILTER_XT_MATCH_LIMIT=m
96CONFIG_NETFILTER_XT_MATCH_MAC=m
97CONFIG_NETFILTER_XT_MATCH_MARK=m
98CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
99CONFIG_NETFILTER_XT_MATCH_OWNER=m
100CONFIG_NETFILTER_XT_MATCH_POLICY=m
101CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
102CONFIG_NETFILTER_XT_MATCH_QUOTA=m
103CONFIG_NETFILTER_XT_MATCH_RATEEST=m
104CONFIG_NETFILTER_XT_MATCH_REALM=m
105CONFIG_NETFILTER_XT_MATCH_RECENT=m
106CONFIG_NETFILTER_XT_MATCH_STATE=m
107CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
108CONFIG_NETFILTER_XT_MATCH_STRING=m
109CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
110CONFIG_NETFILTER_XT_MATCH_TIME=m
111CONFIG_NETFILTER_XT_MATCH_U32=m
112CONFIG_IP_VS=m
113CONFIG_IP_VS_IPV6=y
114CONFIG_IP_VS_PROTO_TCP=y
115CONFIG_IP_VS_PROTO_UDP=y
116CONFIG_IP_VS_PROTO_ESP=y
117CONFIG_IP_VS_PROTO_AH=y
118CONFIG_IP_VS_RR=m
119CONFIG_IP_VS_WRR=m
120CONFIG_IP_VS_LC=m
121CONFIG_IP_VS_WLC=m
122CONFIG_IP_VS_LBLC=m
123CONFIG_IP_VS_LBLCR=m
124CONFIG_IP_VS_DH=m
125CONFIG_IP_VS_SH=m
126CONFIG_IP_VS_SED=m
127CONFIG_IP_VS_NQ=m
128CONFIG_NF_CONNTRACK_IPV4=m
129CONFIG_IP_NF_IPTABLES=m
130CONFIG_IP_NF_MATCH_AH=m
131CONFIG_IP_NF_MATCH_ECN=m
132CONFIG_IP_NF_MATCH_TTL=m
133CONFIG_IP_NF_FILTER=m
134CONFIG_IP_NF_TARGET_REJECT=m
135CONFIG_IP_NF_MANGLE=m
136CONFIG_IP_NF_TARGET_CLUSTERIP=m
137CONFIG_IP_NF_TARGET_ECN=m
138CONFIG_IP_NF_TARGET_TTL=m
139CONFIG_IP_NF_RAW=m
140CONFIG_IP_NF_ARPTABLES=m
141CONFIG_IP_NF_ARPFILTER=m
142CONFIG_IP_NF_ARP_MANGLE=m
143CONFIG_NF_CONNTRACK_IPV6=m
144CONFIG_IP6_NF_MATCH_AH=m
145CONFIG_IP6_NF_MATCH_EUI64=m
146CONFIG_IP6_NF_MATCH_FRAG=m
147CONFIG_IP6_NF_MATCH_OPTS=m
148CONFIG_IP6_NF_MATCH_HL=m
149CONFIG_IP6_NF_MATCH_IPV6HEADER=m
150CONFIG_IP6_NF_MATCH_MH=m
151CONFIG_IP6_NF_MATCH_RT=m
152CONFIG_IP6_NF_TARGET_HL=m
153CONFIG_IP6_NF_FILTER=m
154CONFIG_IP6_NF_TARGET_REJECT=m
155CONFIG_IP6_NF_MANGLE=m
156CONFIG_IP6_NF_RAW=m
157CONFIG_BRIDGE_NF_EBTABLES=m
158CONFIG_BRIDGE_EBT_BROUTE=m
159CONFIG_BRIDGE_EBT_T_FILTER=m
160CONFIG_BRIDGE_EBT_T_NAT=m
161CONFIG_BRIDGE_EBT_802_3=m
162CONFIG_BRIDGE_EBT_AMONG=m
163CONFIG_BRIDGE_EBT_ARP=m
164CONFIG_BRIDGE_EBT_IP=m
165CONFIG_BRIDGE_EBT_IP6=m
166CONFIG_BRIDGE_EBT_LIMIT=m
167CONFIG_BRIDGE_EBT_MARK=m
168CONFIG_BRIDGE_EBT_PKTTYPE=m
169CONFIG_BRIDGE_EBT_STP=m
170CONFIG_BRIDGE_EBT_VLAN=m
171CONFIG_BRIDGE_EBT_ARPREPLY=m
172CONFIG_BRIDGE_EBT_DNAT=m
173CONFIG_BRIDGE_EBT_MARK_T=m
174CONFIG_BRIDGE_EBT_REDIRECT=m
175CONFIG_BRIDGE_EBT_SNAT=m
176CONFIG_BRIDGE_EBT_LOG=m
177CONFIG_BRIDGE_EBT_NFLOG=m
178CONFIG_IP_SCTP=m
179CONFIG_BRIDGE=m
180CONFIG_VLAN_8021Q=m
181CONFIG_VLAN_8021Q_GVRP=y
182CONFIG_ATALK=m
183CONFIG_DEV_APPLETALK=m
184CONFIG_IPDDP=m
185CONFIG_IPDDP_ENCAP=y
186CONFIG_PHONET=m
187CONFIG_NET_SCHED=y
188CONFIG_NET_SCH_CBQ=m
189CONFIG_NET_SCH_HTB=m
190CONFIG_NET_SCH_HFSC=m
191CONFIG_NET_SCH_PRIO=m
192CONFIG_NET_SCH_RED=m
193CONFIG_NET_SCH_SFQ=m
194CONFIG_NET_SCH_TEQL=m
195CONFIG_NET_SCH_TBF=m
196CONFIG_NET_SCH_GRED=m
197CONFIG_NET_SCH_DSMARK=m
198CONFIG_NET_SCH_NETEM=m
199CONFIG_NET_SCH_INGRESS=m
200CONFIG_NET_CLS_BASIC=m
201CONFIG_NET_CLS_TCINDEX=m
202CONFIG_NET_CLS_ROUTE4=m
203CONFIG_NET_CLS_FW=m
204CONFIG_NET_CLS_U32=m
205CONFIG_NET_CLS_RSVP=m
206CONFIG_NET_CLS_RSVP6=m
207CONFIG_NET_CLS_FLOW=m
208CONFIG_NET_CLS_ACT=y
209CONFIG_NET_ACT_POLICE=y
210CONFIG_NET_ACT_GACT=m
211CONFIG_GACT_PROB=y
212CONFIG_NET_ACT_MIRRED=m
213CONFIG_NET_ACT_IPT=m
214CONFIG_NET_ACT_NAT=m
215CONFIG_NET_ACT_PEDIT=m
216CONFIG_NET_ACT_SIMP=m
217CONFIG_NET_ACT_SKBEDIT=m
218CONFIG_NET_CLS_IND=y
219CONFIG_CFG80211=m
220CONFIG_MAC80211=m
221CONFIG_MAC80211_MESH=y
222CONFIG_RFKILL=m
223CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
224CONFIG_DEVTMPFS=y
225CONFIG_DEVTMPFS_MOUNT=y
226CONFIG_CONNECTOR=m
227CONFIG_MTD=y
228CONFIG_MTD_BLOCK=y
229CONFIG_MTD_OOPS=m
230CONFIG_MTD_CFI=y
231CONFIG_MTD_CFI_INTELEXT=y
232CONFIG_MTD_CFI_AMDSTD=y
233CONFIG_MTD_CFI_STAA=y
234CONFIG_MTD_PHYSMAP=y
235CONFIG_MTD_UBI=m
236CONFIG_MTD_UBI_GLUEBI=m
237CONFIG_BLK_DEV_FD=m
238CONFIG_BLK_DEV_UMEM=m
239CONFIG_BLK_DEV_LOOP=m
240CONFIG_BLK_DEV_CRYPTOLOOP=m
241CONFIG_BLK_DEV_NBD=m
242CONFIG_BLK_DEV_RAM=y
243CONFIG_CDROM_PKTCDVD=m
244CONFIG_ATA_OVER_ETH=m
245CONFIG_IDE=y
246CONFIG_BLK_DEV_IDECD=y
247CONFIG_IDE_GENERIC=y
248CONFIG_BLK_DEV_GENERIC=y
249CONFIG_BLK_DEV_PIIX=y
250CONFIG_BLK_DEV_IT8213=m
251CONFIG_BLK_DEV_TC86C001=m
252CONFIG_RAID_ATTRS=m
253CONFIG_SCSI=m
254CONFIG_BLK_DEV_SD=m
255CONFIG_CHR_DEV_ST=m
256CONFIG_CHR_DEV_OSST=m
257CONFIG_BLK_DEV_SR=m
258CONFIG_BLK_DEV_SR_VENDOR=y
259CONFIG_CHR_DEV_SG=m
260CONFIG_SCSI_CONSTANTS=y
261CONFIG_SCSI_LOGGING=y
262CONFIG_SCSI_SCAN_ASYNC=y
263CONFIG_SCSI_FC_ATTRS=m
264CONFIG_ISCSI_TCP=m
265CONFIG_BLK_DEV_3W_XXXX_RAID=m
266CONFIG_SCSI_3W_9XXX=m
267CONFIG_SCSI_ACARD=m
268CONFIG_SCSI_AACRAID=m
269CONFIG_SCSI_AIC7XXX=m
270CONFIG_AIC7XXX_RESET_DELAY_MS=15000
271# CONFIG_AIC7XXX_DEBUG_ENABLE is not set
272CONFIG_MD=y
273CONFIG_BLK_DEV_MD=m
274CONFIG_MD_LINEAR=m
275CONFIG_MD_RAID0=m
276CONFIG_MD_RAID1=m
277CONFIG_MD_RAID10=m
278CONFIG_MD_RAID456=m
279CONFIG_MD_MULTIPATH=m
280CONFIG_MD_FAULTY=m
281CONFIG_BLK_DEV_DM=m
282CONFIG_DM_CRYPT=m
283CONFIG_DM_SNAPSHOT=m
284CONFIG_DM_MIRROR=m
285CONFIG_DM_ZERO=m
286CONFIG_DM_MULTIPATH=m
287CONFIG_NETDEVICES=y
288CONFIG_BONDING=m
289CONFIG_DUMMY=m
290CONFIG_EQUALIZER=m
291CONFIG_IFB=m
292CONFIG_MACVLAN=m
293CONFIG_TUN=m
294CONFIG_VETH=m
295# CONFIG_NET_VENDOR_3COM is not set
296CONFIG_PCNET32=y
297CONFIG_CHELSIO_T3=m
298CONFIG_AX88796=m
299CONFIG_NETXEN_NIC=m
300CONFIG_TC35815=m
301CONFIG_MARVELL_PHY=m
302CONFIG_DAVICOM_PHY=m
303CONFIG_QSEMI_PHY=m
304CONFIG_LXT_PHY=m
305CONFIG_CICADA_PHY=m
306CONFIG_VITESSE_PHY=m
307CONFIG_SMSC_PHY=m
308CONFIG_BROADCOM_PHY=m
309CONFIG_ICPLUS_PHY=m
310CONFIG_REALTEK_PHY=m
311CONFIG_ATMEL=m
312CONFIG_PCI_ATMEL=m
313CONFIG_PRISM54=m
314CONFIG_HOSTAP=m
315CONFIG_HOSTAP_FIRMWARE=y
316CONFIG_HOSTAP_FIRMWARE_NVRAM=y
317CONFIG_HOSTAP_PLX=m
318CONFIG_HOSTAP_PCI=m
319CONFIG_IPW2100=m
320CONFIG_IPW2100_MONITOR=y
321CONFIG_LIBERTAS=m
322# CONFIG_INPUT_KEYBOARD is not set
323# CONFIG_INPUT_MOUSE is not set
324# CONFIG_SERIO_I8042 is not set
325CONFIG_SERIAL_8250=y
326CONFIG_SERIAL_8250_CONSOLE=y
327# CONFIG_HWMON is not set
328CONFIG_FB=y
329CONFIG_FB_CIRRUS=y
330# CONFIG_VGA_CONSOLE is not set
331CONFIG_FRAMEBUFFER_CONSOLE=y
332CONFIG_HID=m
333CONFIG_RTC_CLASS=y
334CONFIG_RTC_DRV_CMOS=y
335CONFIG_UIO=m
336CONFIG_UIO_CIF=m
337CONFIG_EXT2_FS=y
338CONFIG_EXT3_FS=y
339CONFIG_REISERFS_FS=m
340CONFIG_REISERFS_PROC_INFO=y
341CONFIG_REISERFS_FS_XATTR=y
342CONFIG_REISERFS_FS_POSIX_ACL=y
343CONFIG_REISERFS_FS_SECURITY=y
344CONFIG_JFS_FS=m
345CONFIG_JFS_POSIX_ACL=y
346CONFIG_JFS_SECURITY=y
347CONFIG_XFS_FS=m
348CONFIG_XFS_QUOTA=y
349CONFIG_XFS_POSIX_ACL=y
350CONFIG_QUOTA=y
351CONFIG_QFMT_V2=y
352CONFIG_FUSE_FS=m
353CONFIG_ISO9660_FS=m
354CONFIG_JOLIET=y
355CONFIG_ZISOFS=y
356CONFIG_UDF_FS=m
357CONFIG_MSDOS_FS=m
358CONFIG_VFAT_FS=m
359CONFIG_PROC_KCORE=y
360CONFIG_TMPFS=y
361CONFIG_AFFS_FS=m
362CONFIG_HFS_FS=m
363CONFIG_HFSPLUS_FS=m
364CONFIG_BEFS_FS=m
365CONFIG_BFS_FS=m
366CONFIG_EFS_FS=m
367CONFIG_JFFS2_FS=m
368CONFIG_JFFS2_FS_XATTR=y
369CONFIG_JFFS2_COMPRESSION_OPTIONS=y
370CONFIG_JFFS2_RUBIN=y
371CONFIG_CRAMFS=m
372CONFIG_VXFS_FS=m
373CONFIG_MINIX_FS=m
374CONFIG_ROMFS_FS=m
375CONFIG_SYSV_FS=m
376CONFIG_UFS_FS=m
377CONFIG_NFS_FS=y
378CONFIG_ROOT_NFS=y
379CONFIG_NFSD=y
380CONFIG_NFSD_V3=y
381CONFIG_NLS_CODEPAGE_437=m
382CONFIG_NLS_CODEPAGE_737=m
383CONFIG_NLS_CODEPAGE_775=m
384CONFIG_NLS_CODEPAGE_850=m
385CONFIG_NLS_CODEPAGE_852=m
386CONFIG_NLS_CODEPAGE_855=m
387CONFIG_NLS_CODEPAGE_857=m
388CONFIG_NLS_CODEPAGE_860=m
389CONFIG_NLS_CODEPAGE_861=m
390CONFIG_NLS_CODEPAGE_862=m
391CONFIG_NLS_CODEPAGE_863=m
392CONFIG_NLS_CODEPAGE_864=m
393CONFIG_NLS_CODEPAGE_865=m
394CONFIG_NLS_CODEPAGE_866=m
395CONFIG_NLS_CODEPAGE_869=m
396CONFIG_NLS_CODEPAGE_936=m
397CONFIG_NLS_CODEPAGE_950=m
398CONFIG_NLS_CODEPAGE_932=m
399CONFIG_NLS_CODEPAGE_949=m
400CONFIG_NLS_CODEPAGE_874=m
401CONFIG_NLS_ISO8859_8=m
402CONFIG_NLS_CODEPAGE_1250=m
403CONFIG_NLS_CODEPAGE_1251=m
404CONFIG_NLS_ASCII=m
405CONFIG_NLS_ISO8859_1=m
406CONFIG_NLS_ISO8859_2=m
407CONFIG_NLS_ISO8859_3=m
408CONFIG_NLS_ISO8859_4=m
409CONFIG_NLS_ISO8859_5=m
410CONFIG_NLS_ISO8859_6=m
411CONFIG_NLS_ISO8859_7=m
412CONFIG_NLS_ISO8859_9=m
413CONFIG_NLS_ISO8859_13=m
414CONFIG_NLS_ISO8859_14=m
415CONFIG_NLS_ISO8859_15=m
416CONFIG_NLS_KOI8_R=m
417CONFIG_NLS_KOI8_U=m
418CONFIG_CRYPTO_CRYPTD=m
419CONFIG_CRYPTO_LRW=m
420CONFIG_CRYPTO_PCBC=m
421CONFIG_CRYPTO_HMAC=y
422CONFIG_CRYPTO_XCBC=m
423CONFIG_CRYPTO_MD4=m
424CONFIG_CRYPTO_SHA256=m
425CONFIG_CRYPTO_SHA512=m
426CONFIG_CRYPTO_TGR192=m
427CONFIG_CRYPTO_WP512=m
428CONFIG_CRYPTO_ANUBIS=m
429CONFIG_CRYPTO_BLOWFISH=m
430CONFIG_CRYPTO_CAMELLIA=m
431CONFIG_CRYPTO_CAST5=m
432CONFIG_CRYPTO_CAST6=m
433CONFIG_CRYPTO_FCRYPT=m
434CONFIG_CRYPTO_KHAZAD=m
435CONFIG_CRYPTO_SERPENT=m
436CONFIG_CRYPTO_TEA=m
437CONFIG_CRYPTO_TWOFISH=m
438# CONFIG_CRYPTO_ANSI_CPRNG is not set
439CONFIG_CRC16=m
diff --git a/arch/mips/configs/pistachio_defconfig b/arch/mips/configs/pistachio_defconfig
new file mode 100644
index 000000000000..f22e92ee7709
--- /dev/null
+++ b/arch/mips/configs/pistachio_defconfig
@@ -0,0 +1,336 @@
1CONFIG_MACH_PISTACHIO=y
2CONFIG_MIPS_MT_SMP=y
3CONFIG_MIPS_CPS=y
4# CONFIG_COMPACTION is not set
5CONFIG_DEFAULT_MMAP_MIN_ADDR=32768
6CONFIG_ZSMALLOC=y
7CONFIG_NR_CPUS=4
8CONFIG_PREEMPT_VOLUNTARY=y
9# CONFIG_LOCALVERSION_AUTO is not set
10CONFIG_DEFAULT_HOSTNAME="localhost"
11CONFIG_SYSVIPC=y
12CONFIG_NO_HZ=y
13CONFIG_HIGH_RES_TIMERS=y
14CONFIG_IKCONFIG=m
15CONFIG_IKCONFIG_PROC=y
16CONFIG_LOG_BUF_SHIFT=18
17CONFIG_CGROUPS=y
18CONFIG_CGROUP_FREEZER=y
19CONFIG_CGROUP_SCHED=y
20CONFIG_CFS_BANDWIDTH=y
21CONFIG_NAMESPACES=y
22CONFIG_USER_NS=y
23CONFIG_BLK_DEV_INITRD=y
24# CONFIG_RD_BZIP2 is not set
25# CONFIG_RD_LZMA is not set
26# CONFIG_RD_LZO is not set
27# CONFIG_RD_LZ4 is not set
28CONFIG_CC_OPTIMIZE_FOR_SIZE=y
29CONFIG_EMBEDDED=y
30# CONFIG_COMPAT_BRK is not set
31CONFIG_PROFILING=y
32CONFIG_CC_STACKPROTECTOR_STRONG=y
33CONFIG_MODULES=y
34CONFIG_MODULE_UNLOAD=y
35CONFIG_MODULE_FORCE_UNLOAD=y
36CONFIG_PARTITION_ADVANCED=y
37CONFIG_PM_DEBUG=y
38CONFIG_PM_ADVANCED_DEBUG=y
39CONFIG_CPU_IDLE=y
40# CONFIG_MIPS_CPS_CPUIDLE is not set
41CONFIG_NET=y
42CONFIG_PACKET=y
43CONFIG_UNIX=y
44CONFIG_NET_KEY=m
45CONFIG_INET=y
46CONFIG_IP_MULTICAST=y
47CONFIG_IP_ADVANCED_ROUTER=y
48CONFIG_IP_MULTIPLE_TABLES=y
49CONFIG_IP_ROUTE_MULTIPATH=y
50CONFIG_IP_ROUTE_VERBOSE=y
51CONFIG_IP_MROUTE=y
52CONFIG_IP_PIMSM_V1=y
53CONFIG_IP_PIMSM_V2=y
54CONFIG_SYN_COOKIES=y
55CONFIG_INET_AH=m
56CONFIG_INET_ESP=m
57CONFIG_INET_IPCOMP=m
58CONFIG_INET_XFRM_MODE_TRANSPORT=m
59CONFIG_INET_XFRM_MODE_TUNNEL=m
60CONFIG_INET_XFRM_MODE_BEET=m
61# CONFIG_INET_DIAG is not set
62CONFIG_TCP_CONG_ADVANCED=y
63# CONFIG_TCP_CONG_BIC is not set
64# CONFIG_TCP_CONG_WESTWOOD is not set
65# CONFIG_TCP_CONG_HTCP is not set
66CONFIG_TCP_CONG_LP=m
67CONFIG_TCP_MD5SIG=y
68CONFIG_IPV6=y
69CONFIG_INET6_AH=m
70CONFIG_INET6_ESP=m
71CONFIG_INET6_XFRM_MODE_TRANSPORT=m
72CONFIG_INET6_XFRM_MODE_TUNNEL=m
73CONFIG_INET6_XFRM_MODE_BEET=m
74CONFIG_IPV6_SIT=m
75CONFIG_NETWORK_SECMARK=y
76CONFIG_NETFILTER=y
77# CONFIG_BRIDGE_NETFILTER is not set
78CONFIG_NF_CONNTRACK=y
79CONFIG_NF_CT_NETLINK=y
80CONFIG_NETFILTER_XT_MARK=m
81CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y
82CONFIG_NETFILTER_XT_TARGET_DSCP=y
83CONFIG_NETFILTER_XT_TARGET_NFLOG=y
84CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y
85CONFIG_NETFILTER_XT_TARGET_SECMARK=y
86CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
87CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y
88CONFIG_NETFILTER_XT_MATCH_DSCP=y
89CONFIG_NETFILTER_XT_MATCH_POLICY=y
90CONFIG_NETFILTER_XT_MATCH_STATE=y
91CONFIG_NF_CONNTRACK_IPV4=y
92CONFIG_NF_NAT_IPV4=m
93CONFIG_IP_NF_IPTABLES=y
94CONFIG_IP_NF_FILTER=y
95CONFIG_IP_NF_TARGET_REJECT=y
96CONFIG_IP_NF_MANGLE=y
97CONFIG_NF_CONNTRACK_IPV6=m
98CONFIG_NF_NAT_IPV6=m
99CONFIG_IP6_NF_IPTABLES=m
100CONFIG_IP6_NF_MATCH_IPV6HEADER=m
101CONFIG_IP6_NF_FILTER=m
102CONFIG_IP6_NF_TARGET_REJECT=m
103CONFIG_IP6_NF_MANGLE=m
104CONFIG_BRIDGE=m
105CONFIG_VLAN_8021Q=m
106CONFIG_NET_SCHED=y
107CONFIG_NET_SCH_HTB=m
108CONFIG_NET_SCH_CODEL=m
109CONFIG_NET_SCH_FQ_CODEL=m
110CONFIG_NET_CLS_U32=m
111CONFIG_CLS_U32_MARK=y
112CONFIG_BT=m
113CONFIG_BT_RFCOMM=m
114CONFIG_BT_HCIBTUSB=m
115CONFIG_BT_HCIBFUSB=m
116CONFIG_BT_HCIVHCI=m
117CONFIG_CFG80211=m
118CONFIG_NL80211_TESTMODE=y
119CONFIG_CFG80211_DEBUGFS=y
120CONFIG_CFG80211_WEXT=y
121CONFIG_MAC80211=m
122CONFIG_MAC80211_LEDS=y
123CONFIG_MAC80211_DEBUGFS=y
124CONFIG_MAC80211_DEBUG_MENU=y
125CONFIG_MAC80211_VERBOSE_DEBUG=y
126CONFIG_RFKILL=y
127CONFIG_DEVTMPFS=y
128CONFIG_DEVTMPFS_MOUNT=y
129CONFIG_DEBUG_DEVRES=y
130CONFIG_CONNECTOR=y
131CONFIG_MTD=y
132CONFIG_MTD_BLOCK=y
133CONFIG_MTD_M25P80=y
134CONFIG_MTD_SPI_NOR=y
135CONFIG_MTD_UBI=y
136CONFIG_MTD_UBI_BLOCK=y
137CONFIG_ZRAM=m
138CONFIG_BLK_DEV_LOOP=y
139CONFIG_SCSI=y
140CONFIG_BLK_DEV_SD=y
141CONFIG_BLK_DEV_SR=m
142CONFIG_SCSI_SPI_ATTRS=y
143CONFIG_MD=y
144CONFIG_BLK_DEV_DM=y
145CONFIG_DM_CRYPT=y
146CONFIG_DM_VERITY=y
147CONFIG_NETDEVICES=y
148CONFIG_TUN=m
149CONFIG_VETH=m
150# CONFIG_NET_VENDOR_MARVELL is not set
151# CONFIG_NET_VENDOR_MICREL is not set
152# CONFIG_NET_VENDOR_MICROCHIP is not set
153# CONFIG_NET_VENDOR_NATSEMI is not set
154# CONFIG_NET_VENDOR_SEEQ is not set
155# CONFIG_NET_VENDOR_SMSC is not set
156CONFIG_STMMAC_ETH=y
157# CONFIG_NET_VENDOR_VIA is not set
158CONFIG_PPP=m
159CONFIG_PPP_ASYNC=m
160CONFIG_USB_PEGASUS=m
161CONFIG_USB_RTL8150=m
162CONFIG_USB_RTL8152=m
163CONFIG_USB_NET_DM9601=m
164CONFIG_USB_NET_SMSC75XX=m
165CONFIG_USB_NET_SMSC95XX=m
166CONFIG_USB_NET_MCS7830=m
167# CONFIG_USB_NET_CDC_SUBSET is not set
168# CONFIG_USB_NET_ZAURUS is not set
169CONFIG_LIBERTAS_THINFIRM=m
170CONFIG_USB_NET_RNDIS_WLAN=m
171CONFIG_MAC80211_HWSIM=m
172CONFIG_HOSTAP=m
173CONFIG_HOSTAP_FIRMWARE=y
174CONFIG_HOSTAP_FIRMWARE_NVRAM=y
175CONFIG_RT2X00=m
176CONFIG_RT2800USB=m
177# CONFIG_INPUT_MOUSEDEV is not set
178CONFIG_INPUT_EVDEV=y
179# CONFIG_KEYBOARD_ATKBD is not set
180CONFIG_KEYBOARD_GPIO=y
181# CONFIG_INPUT_MOUSE is not set
182# CONFIG_SERIO is not set
183# CONFIG_VT is not set
184# CONFIG_LEGACY_PTYS is not set
185# CONFIG_DEVKMEM is not set
186CONFIG_SERIAL_8250=y
187# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set
188CONFIG_SERIAL_8250_CONSOLE=y
189CONFIG_SERIAL_8250_DW=y
190CONFIG_SERIAL_OF_PLATFORM=y
191CONFIG_HW_RANDOM=y
192CONFIG_TCG_TPM=y
193CONFIG_I2C=y
194CONFIG_I2C_CHARDEV=m
195CONFIG_I2C_IMG=y
196CONFIG_I2C_STUB=m
197CONFIG_SPI=y
198CONFIG_SPI_BITBANG=m
199CONFIG_SPI_IMG_SPFI=y
200CONFIG_SPI_SPIDEV=y
201CONFIG_DEBUG_GPIO=y
202CONFIG_GPIO_SYSFS=y
203CONFIG_POWER_SUPPLY=y
204CONFIG_THERMAL=y
205CONFIG_WATCHDOG=y
206CONFIG_WATCHDOG_CORE=y
207CONFIG_IMGPDC_WDT=y
208CONFIG_REGULATOR_FIXED_VOLTAGE=y
209CONFIG_REGULATOR_GPIO=y
210CONFIG_MEDIA_SUPPORT=y
211CONFIG_MEDIA_RC_SUPPORT=y
212# CONFIG_RC_DECODERS is not set
213CONFIG_RC_DEVICES=y
214CONFIG_IR_IMG=y
215CONFIG_IR_IMG_NEC=y
216CONFIG_IR_IMG_JVC=y
217CONFIG_IR_IMG_SONY=y
218CONFIG_IR_IMG_SHARP=y
219CONFIG_IR_IMG_SANYO=y
220CONFIG_IR_IMG_RC5=y
221CONFIG_IR_IMG_RC6=y
222# CONFIG_DVB_TUNER_DIB0070 is not set
223# CONFIG_DVB_TUNER_DIB0090 is not set
224CONFIG_FB=y
225CONFIG_FB_MODE_HELPERS=y
226CONFIG_BACKLIGHT_LCD_SUPPORT=y
227# CONFIG_LCD_CLASS_DEVICE is not set
228CONFIG_BACKLIGHT_CLASS_DEVICE=y
229CONFIG_SOUND=y
230CONFIG_SND=y
231CONFIG_SND_SEQUENCER=m
232CONFIG_SND_SEQ_DUMMY=m
233CONFIG_SND_HRTIMER=m
234CONFIG_SND_DYNAMIC_MINORS=y
235# CONFIG_SND_SPI is not set
236CONFIG_SND_USB_AUDIO=m
237CONFIG_USB=y
238CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
239# CONFIG_USB_DEFAULT_PERSIST is not set
240CONFIG_USB_MON=y
241CONFIG_USB_EHCI_HCD=y
242CONFIG_USB_EHCI_ROOT_HUB_TT=y
243CONFIG_USB_ACM=y
244CONFIG_USB_STORAGE=y
245CONFIG_USB_DWC2=y
246CONFIG_USB_SERIAL=y
247CONFIG_USB_SERIAL_GENERIC=y
248CONFIG_USB_SERIAL_CP210X=m
249CONFIG_USB_SERIAL_FTDI_SIO=m
250CONFIG_USB_SERIAL_KEYSPAN=m
251CONFIG_USB_SERIAL_PL2303=m
252CONFIG_USB_SERIAL_OTI6858=m
253CONFIG_USB_SERIAL_QUALCOMM=m
254CONFIG_USB_SERIAL_SIERRAWIRELESS=m
255CONFIG_USB_SERIAL_OPTION=m
256CONFIG_MMC=y
257CONFIG_MMC_BLOCK_MINORS=16
258CONFIG_MMC_TEST=m
259CONFIG_MMC_DW=y
260CONFIG_MMC_DW_IDMAC=y
261CONFIG_NEW_LEDS=y
262CONFIG_LEDS_CLASS=y
263CONFIG_RTC_CLASS=y
264CONFIG_DMADEVICES=y
265CONFIG_IMG_MDC_DMA=y
266CONFIG_STAGING=y
267CONFIG_ASHMEM=y
268# CONFIG_ANDROID_TIMED_OUTPUT is not set
269# CONFIG_IOMMU_SUPPORT is not set
270CONFIG_MEMORY=y
271CONFIG_IIO=y
272CONFIG_CC10001_ADC=y
273CONFIG_PWM=y
274CONFIG_PWM_IMG=y
275CONFIG_ANDROID=y
276CONFIG_EXT4_FS=y
277CONFIG_EXT4_FS_POSIX_ACL=y
278CONFIG_EXT4_FS_SECURITY=y
279# CONFIG_DNOTIFY is not set
280CONFIG_FUSE_FS=m
281CONFIG_ISO9660_FS=m
282CONFIG_JOLIET=y
283CONFIG_ZISOFS=y
284CONFIG_UDF_FS=m
285CONFIG_VFAT_FS=m
286CONFIG_TMPFS=y
287CONFIG_TMPFS_POSIX_ACL=y
288CONFIG_ECRYPT_FS=y
289CONFIG_HFSPLUS_FS=m
290CONFIG_UBIFS_FS=y
291CONFIG_SQUASHFS=y
292CONFIG_SQUASHFS_FILE_DIRECT=y
293CONFIG_SQUASHFS_LZO=y
294CONFIG_PSTORE=y
295CONFIG_PSTORE_CONSOLE=y
296CONFIG_PSTORE_RAM=y
297# CONFIG_NETWORK_FILESYSTEMS is not set
298CONFIG_NLS_DEFAULT="utf8"
299CONFIG_NLS_CODEPAGE_437=m
300CONFIG_NLS_ASCII=m
301CONFIG_NLS_ISO8859_1=m
302CONFIG_PRINTK_TIME=y
303CONFIG_DEBUG_INFO=y
304CONFIG_MAGIC_SYSRQ=y
305CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0
306CONFIG_LOCKUP_DETECTOR=y
307CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC=y
308CONFIG_BOOTPARAM_HUNG_TASK_PANIC=y
309# CONFIG_SCHED_DEBUG is not set
310CONFIG_SCHEDSTATS=y
311CONFIG_TIMER_STATS=y
312CONFIG_DEBUG_SPINLOCK=y
313CONFIG_DEBUG_CREDENTIALS=y
314CONFIG_FUNCTION_TRACER=y
315CONFIG_BLK_DEV_IO_TRACE=y
316CONFIG_LKDTM=y
317CONFIG_TEST_UDELAY=m
318CONFIG_KEYS=y
319CONFIG_SECURITY=y
320CONFIG_SECURITY_NETWORK=y
321CONFIG_SECURITY_YAMA=y
322CONFIG_SECURITY_YAMA_STACKED=y
323CONFIG_DEFAULT_SECURITY_DAC=y
324CONFIG_CRYPTO_AUTHENC=y
325CONFIG_CRYPTO_HMAC=y
326CONFIG_CRYPTO_SHA1=y
327CONFIG_CRYPTO_SHA256=y
328CONFIG_CRYPTO_SHA512=m
329CONFIG_CRYPTO_ARC4=y
330CONFIG_CRYPTO_DES=y
331# CONFIG_CRYPTO_ANSI_CPRNG is not set
332CONFIG_CRC_CCITT=y
333CONFIG_CRC_T10DIF=m
334CONFIG_CRC7=m
335CONFIG_LIBCRC32C=m
336# CONFIG_XZ_DEC_X86 is not set
diff --git a/arch/mips/dec/int-handler.S b/arch/mips/dec/int-handler.S
index 41a2fa1fa12e..8c6f508e59de 100644
--- a/arch/mips/dec/int-handler.S
+++ b/arch/mips/dec/int-handler.S
@@ -267,8 +267,13 @@ handle_it:
267 267
268#ifdef CONFIG_32BIT 268#ifdef CONFIG_32BIT
269fpu: 269fpu:
270 lw t0,fpu_kstat_irq
271 nop
272 lw t1,(t0)
273 nop
274 addu t1,1
270 j handle_fpe_int 275 j handle_fpe_int
271 nop 276 sw t1,(t0)
272#endif 277#endif
273 278
274spurious: 279spurious:
diff --git a/arch/mips/dec/setup.c b/arch/mips/dec/setup.c
index 41bbffd9cc0e..a0b8943c8f11 100644
--- a/arch/mips/dec/setup.c
+++ b/arch/mips/dec/setup.c
@@ -12,13 +12,15 @@
12#include <linux/init.h> 12#include <linux/init.h>
13#include <linux/interrupt.h> 13#include <linux/interrupt.h>
14#include <linux/ioport.h> 14#include <linux/ioport.h>
15#include <linux/irq.h>
16#include <linux/irqnr.h>
15#include <linux/module.h> 17#include <linux/module.h>
16#include <linux/param.h> 18#include <linux/param.h>
19#include <linux/percpu-defs.h>
17#include <linux/sched.h> 20#include <linux/sched.h>
18#include <linux/spinlock.h> 21#include <linux/spinlock.h>
19#include <linux/types.h> 22#include <linux/types.h>
20#include <linux/pm.h> 23#include <linux/pm.h>
21#include <linux/irq.h>
22 24
23#include <asm/bootinfo.h> 25#include <asm/bootinfo.h>
24#include <asm/cpu.h> 26#include <asm/cpu.h>
@@ -98,6 +100,7 @@ int_ptr asic_mask_nr_tbl[DEC_MAX_ASIC_INTS][2] = {
98 { { .i = ~0 }, { .p = asic_intr_unimplemented } }, 100 { { .i = ~0 }, { .p = asic_intr_unimplemented } },
99}; 101};
100int cpu_fpu_mask = DEC_CPU_IRQ_MASK(DEC_CPU_INR_FPU); 102int cpu_fpu_mask = DEC_CPU_IRQ_MASK(DEC_CPU_INR_FPU);
103int *fpu_kstat_irq;
101 104
102static struct irqaction ioirq = { 105static struct irqaction ioirq = {
103 .handler = no_action, 106 .handler = no_action,
@@ -755,8 +758,15 @@ void __init arch_init_irq(void)
755 dec_interrupt[DEC_IRQ_HALT] = -1; 758 dec_interrupt[DEC_IRQ_HALT] = -1;
756 759
757 /* Register board interrupts: FPU and cascade. */ 760 /* Register board interrupts: FPU and cascade. */
758 if (dec_interrupt[DEC_IRQ_FPU] >= 0) 761 if (dec_interrupt[DEC_IRQ_FPU] >= 0 && cpu_has_fpu) {
759 setup_irq(dec_interrupt[DEC_IRQ_FPU], &fpuirq); 762 struct irq_desc *desc_fpu;
763 int irq_fpu;
764
765 irq_fpu = dec_interrupt[DEC_IRQ_FPU];
766 setup_irq(irq_fpu, &fpuirq);
767 desc_fpu = irq_to_desc(irq_fpu);
768 fpu_kstat_irq = this_cpu_ptr(desc_fpu->kstat_irqs);
769 }
760 if (dec_interrupt[DEC_IRQ_CASCADE] >= 0) 770 if (dec_interrupt[DEC_IRQ_CASCADE] >= 0)
761 setup_irq(dec_interrupt[DEC_IRQ_CASCADE], &ioirq); 771 setup_irq(dec_interrupt[DEC_IRQ_CASCADE], &ioirq);
762 772
diff --git a/arch/mips/include/asm/asm-eva.h b/arch/mips/include/asm/asm-eva.h
index e41c56e375b1..1e38f0e1ea3e 100644
--- a/arch/mips/include/asm/asm-eva.h
+++ b/arch/mips/include/asm/asm-eva.h
@@ -11,6 +11,36 @@
11#define __ASM_ASM_EVA_H 11#define __ASM_ASM_EVA_H
12 12
13#ifndef __ASSEMBLY__ 13#ifndef __ASSEMBLY__
14
15/* Kernel variants */
16
17#define kernel_cache(op, base) "cache " op ", " base "\n"
18#define kernel_ll(reg, addr) "ll " reg ", " addr "\n"
19#define kernel_sc(reg, addr) "sc " reg ", " addr "\n"
20#define kernel_lw(reg, addr) "lw " reg ", " addr "\n"
21#define kernel_lwl(reg, addr) "lwl " reg ", " addr "\n"
22#define kernel_lwr(reg, addr) "lwr " reg ", " addr "\n"
23#define kernel_lh(reg, addr) "lh " reg ", " addr "\n"
24#define kernel_lb(reg, addr) "lb " reg ", " addr "\n"
25#define kernel_lbu(reg, addr) "lbu " reg ", " addr "\n"
26#define kernel_sw(reg, addr) "sw " reg ", " addr "\n"
27#define kernel_swl(reg, addr) "swl " reg ", " addr "\n"
28#define kernel_swr(reg, addr) "swr " reg ", " addr "\n"
29#define kernel_sh(reg, addr) "sh " reg ", " addr "\n"
30#define kernel_sb(reg, addr) "sb " reg ", " addr "\n"
31
32#ifdef CONFIG_32BIT
33/*
34 * No 'sd' or 'ld' instructions in 32-bit but the code will
35 * do the correct thing
36 */
37#define kernel_sd(reg, addr) user_sw(reg, addr)
38#define kernel_ld(reg, addr) user_lw(reg, addr)
39#else
40#define kernel_sd(reg, addr) "sd " reg", " addr "\n"
41#define kernel_ld(reg, addr) "ld " reg", " addr "\n"
42#endif /* CONFIG_32BIT */
43
14#ifdef CONFIG_EVA 44#ifdef CONFIG_EVA
15 45
16#define __BUILD_EVA_INSN(insn, reg, addr) \ 46#define __BUILD_EVA_INSN(insn, reg, addr) \
@@ -41,37 +71,60 @@
41 71
42#else 72#else
43 73
44#define user_cache(op, base) "cache " op ", " base "\n" 74#define user_cache(op, base) kernel_cache(op, base)
45#define user_ll(reg, addr) "ll " reg ", " addr "\n" 75#define user_ll(reg, addr) kernel_ll(reg, addr)
46#define user_sc(reg, addr) "sc " reg ", " addr "\n" 76#define user_sc(reg, addr) kernel_sc(reg, addr)
47#define user_lw(reg, addr) "lw " reg ", " addr "\n" 77#define user_lw(reg, addr) kernel_lw(reg, addr)
48#define user_lwl(reg, addr) "lwl " reg ", " addr "\n" 78#define user_lwl(reg, addr) kernel_lwl(reg, addr)
49#define user_lwr(reg, addr) "lwr " reg ", " addr "\n" 79#define user_lwr(reg, addr) kernel_lwr(reg, addr)
50#define user_lh(reg, addr) "lh " reg ", " addr "\n" 80#define user_lh(reg, addr) kernel_lh(reg, addr)
51#define user_lb(reg, addr) "lb " reg ", " addr "\n" 81#define user_lb(reg, addr) kernel_lb(reg, addr)
52#define user_lbu(reg, addr) "lbu " reg ", " addr "\n" 82#define user_lbu(reg, addr) kernel_lbu(reg, addr)
53#define user_sw(reg, addr) "sw " reg ", " addr "\n" 83#define user_sw(reg, addr) kernel_sw(reg, addr)
54#define user_swl(reg, addr) "swl " reg ", " addr "\n" 84#define user_swl(reg, addr) kernel_swl(reg, addr)
55#define user_swr(reg, addr) "swr " reg ", " addr "\n" 85#define user_swr(reg, addr) kernel_swr(reg, addr)
56#define user_sh(reg, addr) "sh " reg ", " addr "\n" 86#define user_sh(reg, addr) kernel_sh(reg, addr)
57#define user_sb(reg, addr) "sb " reg ", " addr "\n" 87#define user_sb(reg, addr) kernel_sb(reg, addr)
58 88
59#ifdef CONFIG_32BIT 89#ifdef CONFIG_32BIT
60/* 90#define user_sd(reg, addr) kernel_sw(reg, addr)
61 * No 'sd' or 'ld' instructions in 32-bit but the code will 91#define user_ld(reg, addr) kernel_lw(reg, addr)
62 * do the correct thing
63 */
64#define user_sd(reg, addr) user_sw(reg, addr)
65#define user_ld(reg, addr) user_lw(reg, addr)
66#else 92#else
67#define user_sd(reg, addr) "sd " reg", " addr "\n" 93#define user_sd(reg, addr) kernel_sd(reg, addr)
68#define user_ld(reg, addr) "ld " reg", " addr "\n" 94#define user_ld(reg, addr) kernel_ld(reg, addr)
69#endif /* CONFIG_32BIT */ 95#endif /* CONFIG_32BIT */
70 96
71#endif /* CONFIG_EVA */ 97#endif /* CONFIG_EVA */
72 98
73#else /* __ASSEMBLY__ */ 99#else /* __ASSEMBLY__ */
74 100
101#define kernel_cache(op, base) cache op, base
102#define kernel_ll(reg, addr) ll reg, addr
103#define kernel_sc(reg, addr) sc reg, addr
104#define kernel_lw(reg, addr) lw reg, addr
105#define kernel_lwl(reg, addr) lwl reg, addr
106#define kernel_lwr(reg, addr) lwr reg, addr
107#define kernel_lh(reg, addr) lh reg, addr
108#define kernel_lb(reg, addr) lb reg, addr
109#define kernel_lbu(reg, addr) lbu reg, addr
110#define kernel_sw(reg, addr) sw reg, addr
111#define kernel_swl(reg, addr) swl reg, addr
112#define kernel_swr(reg, addr) swr reg, addr
113#define kernel_sh(reg, addr) sh reg, addr
114#define kernel_sb(reg, addr) sb reg, addr
115
116#ifdef CONFIG_32BIT
117/*
118 * No 'sd' or 'ld' instructions in 32-bit but the code will
119 * do the correct thing
120 */
121#define kernel_sd(reg, addr) user_sw(reg, addr)
122#define kernel_ld(reg, addr) user_lw(reg, addr)
123#else
124#define kernel_sd(reg, addr) sd reg, addr
125#define kernel_ld(reg, addr) ld reg, addr
126#endif /* CONFIG_32BIT */
127
75#ifdef CONFIG_EVA 128#ifdef CONFIG_EVA
76 129
77#define __BUILD_EVA_INSN(insn, reg, addr) \ 130#define __BUILD_EVA_INSN(insn, reg, addr) \
@@ -101,31 +154,27 @@
101#define user_sd(reg, addr) user_sw(reg, addr) 154#define user_sd(reg, addr) user_sw(reg, addr)
102#else 155#else
103 156
104#define user_cache(op, base) cache op, base 157#define user_cache(op, base) kernel_cache(op, base)
105#define user_ll(reg, addr) ll reg, addr 158#define user_ll(reg, addr) kernel_ll(reg, addr)
106#define user_sc(reg, addr) sc reg, addr 159#define user_sc(reg, addr) kernel_sc(reg, addr)
107#define user_lw(reg, addr) lw reg, addr 160#define user_lw(reg, addr) kernel_lw(reg, addr)
108#define user_lwl(reg, addr) lwl reg, addr 161#define user_lwl(reg, addr) kernel_lwl(reg, addr)
109#define user_lwr(reg, addr) lwr reg, addr 162#define user_lwr(reg, addr) kernel_lwr(reg, addr)
110#define user_lh(reg, addr) lh reg, addr 163#define user_lh(reg, addr) kernel_lh(reg, addr)
111#define user_lb(reg, addr) lb reg, addr 164#define user_lb(reg, addr) kernel_lb(reg, addr)
112#define user_lbu(reg, addr) lbu reg, addr 165#define user_lbu(reg, addr) kernel_lbu(reg, addr)
113#define user_sw(reg, addr) sw reg, addr 166#define user_sw(reg, addr) kernel_sw(reg, addr)
114#define user_swl(reg, addr) swl reg, addr 167#define user_swl(reg, addr) kernel_swl(reg, addr)
115#define user_swr(reg, addr) swr reg, addr 168#define user_swr(reg, addr) kernel_swr(reg, addr)
116#define user_sh(reg, addr) sh reg, addr 169#define user_sh(reg, addr) kernel_sh(reg, addr)
117#define user_sb(reg, addr) sb reg, addr 170#define user_sb(reg, addr) kernel_sb(reg, addr)
118 171
119#ifdef CONFIG_32BIT 172#ifdef CONFIG_32BIT
120/* 173#define user_sd(reg, addr) kernel_sw(reg, addr)
121 * No 'sd' or 'ld' instructions in 32-bit but the code will 174#define user_ld(reg, addr) kernel_lw(reg, addr)
122 * do the correct thing
123 */
124#define user_sd(reg, addr) user_sw(reg, addr)
125#define user_ld(reg, addr) user_lw(reg, addr)
126#else 175#else
127#define user_sd(reg, addr) sd reg, addr 176#define user_sd(reg, addr) kernel_sd(reg, addr)
128#define user_ld(reg, addr) ld reg, addr 177#define user_ld(reg, addr) kernel_sd(reg, addr)
129#endif /* CONFIG_32BIT */ 178#endif /* CONFIG_32BIT */
130 179
131#endif /* CONFIG_EVA */ 180#endif /* CONFIG_EVA */
diff --git a/arch/mips/include/asm/asmmacro-32.h b/arch/mips/include/asm/asmmacro-32.h
index 80386470d3a4..0ef39ad0f2d4 100644
--- a/arch/mips/include/asm/asmmacro-32.h
+++ b/arch/mips/include/asm/asmmacro-32.h
@@ -16,38 +16,22 @@
16 .set push 16 .set push
17 SET_HARDFLOAT 17 SET_HARDFLOAT
18 cfc1 \tmp, fcr31 18 cfc1 \tmp, fcr31
19 swc1 $f0, THREAD_FPR0(\thread) 19 s.d $f0, THREAD_FPR0(\thread)
20 swc1 $f1, THREAD_FPR1(\thread) 20 s.d $f2, THREAD_FPR2(\thread)
21 swc1 $f2, THREAD_FPR2(\thread) 21 s.d $f4, THREAD_FPR4(\thread)
22 swc1 $f3, THREAD_FPR3(\thread) 22 s.d $f6, THREAD_FPR6(\thread)
23 swc1 $f4, THREAD_FPR4(\thread) 23 s.d $f8, THREAD_FPR8(\thread)
24 swc1 $f5, THREAD_FPR5(\thread) 24 s.d $f10, THREAD_FPR10(\thread)
25 swc1 $f6, THREAD_FPR6(\thread) 25 s.d $f12, THREAD_FPR12(\thread)
26 swc1 $f7, THREAD_FPR7(\thread) 26 s.d $f14, THREAD_FPR14(\thread)
27 swc1 $f8, THREAD_FPR8(\thread) 27 s.d $f16, THREAD_FPR16(\thread)
28 swc1 $f9, THREAD_FPR9(\thread) 28 s.d $f18, THREAD_FPR18(\thread)
29 swc1 $f10, THREAD_FPR10(\thread) 29 s.d $f20, THREAD_FPR20(\thread)
30 swc1 $f11, THREAD_FPR11(\thread) 30 s.d $f22, THREAD_FPR22(\thread)
31 swc1 $f12, THREAD_FPR12(\thread) 31 s.d $f24, THREAD_FPR24(\thread)
32 swc1 $f13, THREAD_FPR13(\thread) 32 s.d $f26, THREAD_FPR26(\thread)
33 swc1 $f14, THREAD_FPR14(\thread) 33 s.d $f28, THREAD_FPR28(\thread)
34 swc1 $f15, THREAD_FPR15(\thread) 34 s.d $f30, THREAD_FPR30(\thread)
35 swc1 $f16, THREAD_FPR16(\thread)
36 swc1 $f17, THREAD_FPR17(\thread)
37 swc1 $f18, THREAD_FPR18(\thread)
38 swc1 $f19, THREAD_FPR19(\thread)
39 swc1 $f20, THREAD_FPR20(\thread)
40 swc1 $f21, THREAD_FPR21(\thread)
41 swc1 $f22, THREAD_FPR22(\thread)
42 swc1 $f23, THREAD_FPR23(\thread)
43 swc1 $f24, THREAD_FPR24(\thread)
44 swc1 $f25, THREAD_FPR25(\thread)
45 swc1 $f26, THREAD_FPR26(\thread)
46 swc1 $f27, THREAD_FPR27(\thread)
47 swc1 $f28, THREAD_FPR28(\thread)
48 swc1 $f29, THREAD_FPR29(\thread)
49 swc1 $f30, THREAD_FPR30(\thread)
50 swc1 $f31, THREAD_FPR31(\thread)
51 sw \tmp, THREAD_FCR31(\thread) 35 sw \tmp, THREAD_FCR31(\thread)
52 .set pop 36 .set pop
53 .endm 37 .endm
@@ -56,38 +40,22 @@
56 .set push 40 .set push
57 SET_HARDFLOAT 41 SET_HARDFLOAT
58 lw \tmp, THREAD_FCR31(\thread) 42 lw \tmp, THREAD_FCR31(\thread)
59 lwc1 $f0, THREAD_FPR0(\thread) 43 l.d $f0, THREAD_FPR0(\thread)
60 lwc1 $f1, THREAD_FPR1(\thread) 44 l.d $f2, THREAD_FPR2(\thread)
61 lwc1 $f2, THREAD_FPR2(\thread) 45 l.d $f4, THREAD_FPR4(\thread)
62 lwc1 $f3, THREAD_FPR3(\thread) 46 l.d $f6, THREAD_FPR6(\thread)
63 lwc1 $f4, THREAD_FPR4(\thread) 47 l.d $f8, THREAD_FPR8(\thread)
64 lwc1 $f5, THREAD_FPR5(\thread) 48 l.d $f10, THREAD_FPR10(\thread)
65 lwc1 $f6, THREAD_FPR6(\thread) 49 l.d $f12, THREAD_FPR12(\thread)
66 lwc1 $f7, THREAD_FPR7(\thread) 50 l.d $f14, THREAD_FPR14(\thread)
67 lwc1 $f8, THREAD_FPR8(\thread) 51 l.d $f16, THREAD_FPR16(\thread)
68 lwc1 $f9, THREAD_FPR9(\thread) 52 l.d $f18, THREAD_FPR18(\thread)
69 lwc1 $f10, THREAD_FPR10(\thread) 53 l.d $f20, THREAD_FPR20(\thread)
70 lwc1 $f11, THREAD_FPR11(\thread) 54 l.d $f22, THREAD_FPR22(\thread)
71 lwc1 $f12, THREAD_FPR12(\thread) 55 l.d $f24, THREAD_FPR24(\thread)
72 lwc1 $f13, THREAD_FPR13(\thread) 56 l.d $f26, THREAD_FPR26(\thread)
73 lwc1 $f14, THREAD_FPR14(\thread) 57 l.d $f28, THREAD_FPR28(\thread)
74 lwc1 $f15, THREAD_FPR15(\thread) 58 l.d $f30, THREAD_FPR30(\thread)
75 lwc1 $f16, THREAD_FPR16(\thread)
76 lwc1 $f17, THREAD_FPR17(\thread)
77 lwc1 $f18, THREAD_FPR18(\thread)
78 lwc1 $f19, THREAD_FPR19(\thread)
79 lwc1 $f20, THREAD_FPR20(\thread)
80 lwc1 $f21, THREAD_FPR21(\thread)
81 lwc1 $f22, THREAD_FPR22(\thread)
82 lwc1 $f23, THREAD_FPR23(\thread)
83 lwc1 $f24, THREAD_FPR24(\thread)
84 lwc1 $f25, THREAD_FPR25(\thread)
85 lwc1 $f26, THREAD_FPR26(\thread)
86 lwc1 $f27, THREAD_FPR27(\thread)
87 lwc1 $f28, THREAD_FPR28(\thread)
88 lwc1 $f29, THREAD_FPR29(\thread)
89 lwc1 $f30, THREAD_FPR30(\thread)
90 lwc1 $f31, THREAD_FPR31(\thread)
91 ctc1 \tmp, fcr31 59 ctc1 \tmp, fcr31
92 .set pop 60 .set pop
93 .endm 61 .endm
diff --git a/arch/mips/include/asm/bitops.h b/arch/mips/include/asm/bitops.h
index 9f935f6aa996..0cf29bd5dc5c 100644
--- a/arch/mips/include/asm/bitops.h
+++ b/arch/mips/include/asm/bitops.h
@@ -481,7 +481,7 @@ static inline unsigned long __fls(unsigned long word)
481{ 481{
482 int num; 482 int num;
483 483
484 if (BITS_PER_LONG == 32 && 484 if (BITS_PER_LONG == 32 && !__builtin_constant_p(word) &&
485 __builtin_constant_p(cpu_has_clo_clz) && cpu_has_clo_clz) { 485 __builtin_constant_p(cpu_has_clo_clz) && cpu_has_clo_clz) {
486 __asm__( 486 __asm__(
487 " .set push \n" 487 " .set push \n"
@@ -494,7 +494,7 @@ static inline unsigned long __fls(unsigned long word)
494 return 31 - num; 494 return 31 - num;
495 } 495 }
496 496
497 if (BITS_PER_LONG == 64 && 497 if (BITS_PER_LONG == 64 && !__builtin_constant_p(word) &&
498 __builtin_constant_p(cpu_has_mips64) && cpu_has_mips64) { 498 __builtin_constant_p(cpu_has_mips64) && cpu_has_mips64) {
499 __asm__( 499 __asm__(
500 " .set push \n" 500 " .set push \n"
@@ -559,7 +559,8 @@ static inline int fls(int x)
559{ 559{
560 int r; 560 int r;
561 561
562 if (__builtin_constant_p(cpu_has_clo_clz) && cpu_has_clo_clz) { 562 if (!__builtin_constant_p(x) &&
563 __builtin_constant_p(cpu_has_clo_clz) && cpu_has_clo_clz) {
563 __asm__( 564 __asm__(
564 " .set push \n" 565 " .set push \n"
565 " .set "MIPS_ISA_LEVEL" \n" 566 " .set "MIPS_ISA_LEVEL" \n"
diff --git a/arch/mips/include/asm/bmips.h b/arch/mips/include/asm/bmips.h
index 30939b02e3ff..6d25ad33ec78 100644
--- a/arch/mips/include/asm/bmips.h
+++ b/arch/mips/include/asm/bmips.h
@@ -122,6 +122,22 @@ static inline void bmips_write_zscm_reg(unsigned int offset, unsigned long data)
122 barrier(); 122 barrier();
123} 123}
124 124
125static inline void bmips_post_dma_flush(struct device *dev)
126{
127 void __iomem *cbr = BMIPS_GET_CBR();
128 u32 cfg;
129
130 if (boot_cpu_type() != CPU_BMIPS3300 &&
131 boot_cpu_type() != CPU_BMIPS4350 &&
132 boot_cpu_type() != CPU_BMIPS4380)
133 return;
134
135 /* Flush stale data out of the readahead cache */
136 cfg = __raw_readl(cbr + BMIPS_RAC_CONFIG);
137 __raw_writel(cfg | 0x100, cbr + BMIPS_RAC_CONFIG);
138 __raw_readl(cbr + BMIPS_RAC_CONFIG);
139}
140
125#endif /* !defined(__ASSEMBLY__) */ 141#endif /* !defined(__ASSEMBLY__) */
126 142
127#endif /* _ASM_BMIPS_H */ 143#endif /* _ASM_BMIPS_H */
diff --git a/arch/mips/include/asm/cacheflush.h b/arch/mips/include/asm/cacheflush.h
index e08381a37f8b..723229f4cf27 100644
--- a/arch/mips/include/asm/cacheflush.h
+++ b/arch/mips/include/asm/cacheflush.h
@@ -29,6 +29,20 @@
29 * - flush_icache_all() flush the entire instruction cache 29 * - flush_icache_all() flush the entire instruction cache
30 * - flush_data_cache_page() flushes a page from the data cache 30 * - flush_data_cache_page() flushes a page from the data cache
31 */ 31 */
32
33 /*
34 * This flag is used to indicate that the page pointed to by a pte
35 * is dirty and requires cleaning before returning it to the user.
36 */
37#define PG_dcache_dirty PG_arch_1
38
39#define Page_dcache_dirty(page) \
40 test_bit(PG_dcache_dirty, &(page)->flags)
41#define SetPageDcacheDirty(page) \
42 set_bit(PG_dcache_dirty, &(page)->flags)
43#define ClearPageDcacheDirty(page) \
44 clear_bit(PG_dcache_dirty, &(page)->flags)
45
32extern void (*flush_cache_all)(void); 46extern void (*flush_cache_all)(void);
33extern void (*__flush_cache_all)(void); 47extern void (*__flush_cache_all)(void);
34extern void (*flush_cache_mm)(struct mm_struct *mm); 48extern void (*flush_cache_mm)(struct mm_struct *mm);
@@ -37,13 +51,15 @@ extern void (*flush_cache_range)(struct vm_area_struct *vma,
37 unsigned long start, unsigned long end); 51 unsigned long start, unsigned long end);
38extern void (*flush_cache_page)(struct vm_area_struct *vma, unsigned long page, unsigned long pfn); 52extern void (*flush_cache_page)(struct vm_area_struct *vma, unsigned long page, unsigned long pfn);
39extern void __flush_dcache_page(struct page *page); 53extern void __flush_dcache_page(struct page *page);
54extern void __flush_icache_page(struct vm_area_struct *vma, struct page *page);
40 55
41#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1 56#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1
42static inline void flush_dcache_page(struct page *page) 57static inline void flush_dcache_page(struct page *page)
43{ 58{
44 if (cpu_has_dc_aliases || !cpu_has_ic_fills_f_dc) 59 if (cpu_has_dc_aliases)
45 __flush_dcache_page(page); 60 __flush_dcache_page(page);
46 61 else if (!cpu_has_ic_fills_f_dc)
62 SetPageDcacheDirty(page);
47} 63}
48 64
49#define flush_dcache_mmap_lock(mapping) do { } while (0) 65#define flush_dcache_mmap_lock(mapping) do { } while (0)
@@ -61,6 +77,11 @@ static inline void flush_anon_page(struct vm_area_struct *vma,
61static inline void flush_icache_page(struct vm_area_struct *vma, 77static inline void flush_icache_page(struct vm_area_struct *vma,
62 struct page *page) 78 struct page *page)
63{ 79{
80 if (!cpu_has_ic_fills_f_dc && (vma->vm_flags & VM_EXEC) &&
81 Page_dcache_dirty(page)) {
82 __flush_icache_page(vma, page);
83 ClearPageDcacheDirty(page);
84 }
64} 85}
65 86
66extern void (*flush_icache_range)(unsigned long start, unsigned long end); 87extern void (*flush_icache_range)(unsigned long start, unsigned long end);
@@ -95,19 +116,6 @@ extern void (*flush_icache_all)(void);
95extern void (*local_flush_data_cache_page)(void * addr); 116extern void (*local_flush_data_cache_page)(void * addr);
96extern void (*flush_data_cache_page)(unsigned long addr); 117extern void (*flush_data_cache_page)(unsigned long addr);
97 118
98/*
99 * This flag is used to indicate that the page pointed to by a pte
100 * is dirty and requires cleaning before returning it to the user.
101 */
102#define PG_dcache_dirty PG_arch_1
103
104#define Page_dcache_dirty(page) \
105 test_bit(PG_dcache_dirty, &(page)->flags)
106#define SetPageDcacheDirty(page) \
107 set_bit(PG_dcache_dirty, &(page)->flags)
108#define ClearPageDcacheDirty(page) \
109 clear_bit(PG_dcache_dirty, &(page)->flags)
110
111/* Run kernel code uncached, useful for cache probing functions. */ 119/* Run kernel code uncached, useful for cache probing functions. */
112unsigned long run_uncached(void *func); 120unsigned long run_uncached(void *func);
113 121
diff --git a/arch/mips/include/asm/cdmm.h b/arch/mips/include/asm/cdmm.h
new file mode 100644
index 000000000000..16e22ce9719f
--- /dev/null
+++ b/arch/mips/include/asm/cdmm.h
@@ -0,0 +1,98 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2014 Imagination Technologies Ltd.
7 */
8#ifndef __ASM_CDMM_H
9#define __ASM_CDMM_H
10
11#include <linux/device.h>
12#include <linux/mod_devicetable.h>
13
14/**
15 * struct mips_cdmm_device - Represents a single device on a CDMM bus.
16 * @dev: Driver model device object.
17 * @cpu: CPU which can access this device.
18 * @res: MMIO resource.
19 * @type: Device type identifier.
20 * @rev: Device revision number.
21 */
22struct mips_cdmm_device {
23 struct device dev;
24 unsigned int cpu;
25 struct resource res;
26 unsigned int type;
27 unsigned int rev;
28};
29
30/**
31 * struct mips_cdmm_driver - Represents a driver for a CDMM device.
32 * @drv: Driver model driver object.
33 * @probe Callback for probing newly discovered devices.
34 * @remove: Callback to remove the device.
35 * @shutdown: Callback on system shutdown.
36 * @cpu_down: Callback when the parent CPU is going down.
37 * Any CPU pinned threads/timers should be disabled.
38 * @cpu_up: Callback when the parent CPU is coming back up again.
39 * CPU pinned threads/timers can be restarted.
40 * @id_table: Table for CDMM IDs to match against.
41 */
42struct mips_cdmm_driver {
43 struct device_driver drv;
44 int (*probe)(struct mips_cdmm_device *);
45 int (*remove)(struct mips_cdmm_device *);
46 void (*shutdown)(struct mips_cdmm_device *);
47 int (*cpu_down)(struct mips_cdmm_device *);
48 int (*cpu_up)(struct mips_cdmm_device *);
49 const struct mips_cdmm_device_id *id_table;
50};
51
52/**
53 * mips_cdmm_phys_base() - Choose a physical base address for CDMM region.
54 *
55 * Picking a suitable physical address at which to map the CDMM region is
56 * platform specific, so this weak function can be defined by platform code to
57 * pick a suitable value if none is configured by the bootloader.
58 *
59 * This address must be 32kB aligned, and the region occupies a maximum of 32kB
60 * of physical address space which must not be used for anything else.
61 *
62 * Returns: Physical base address for CDMM region, or 0 on failure.
63 */
64phys_addr_t __weak mips_cdmm_phys_base(void);
65
66extern struct bus_type mips_cdmm_bustype;
67void __iomem *mips_cdmm_early_probe(unsigned int dev_type);
68
69#define to_mips_cdmm_device(d) container_of(d, struct mips_cdmm_device, dev)
70
71#define mips_cdmm_get_drvdata(d) dev_get_drvdata(&d->dev)
72#define mips_cdmm_set_drvdata(d, p) dev_set_drvdata(&d->dev, p)
73
74int mips_cdmm_driver_register(struct mips_cdmm_driver *);
75void mips_cdmm_driver_unregister(struct mips_cdmm_driver *);
76
77/*
78 * module_mips_cdmm_driver() - Helper macro for drivers that don't do
79 * anything special in module init/exit. This eliminates a lot of
80 * boilerplate. Each module may only use this macro once, and
81 * calling it replaces module_init() and module_exit()
82 */
83#define module_mips_cdmm_driver(__mips_cdmm_driver) \
84 module_driver(__mips_cdmm_driver, mips_cdmm_driver_register, \
85 mips_cdmm_driver_unregister)
86
87/* drivers/tty/mips_ejtag_fdc.c */
88
89#ifdef CONFIG_MIPS_EJTAG_FDC_EARLYCON
90int setup_early_fdc_console(void);
91#else
92static inline int setup_early_fdc_console(void)
93{
94 return -ENODEV;
95}
96#endif
97
98#endif /* __ASM_CDMM_H */
diff --git a/arch/mips/include/asm/cevt-r4k.h b/arch/mips/include/asm/cevt-r4k.h
index 65f9bdd02f1f..f0edf6fcd002 100644
--- a/arch/mips/include/asm/cevt-r4k.h
+++ b/arch/mips/include/asm/cevt-r4k.h
@@ -27,23 +27,4 @@ irqreturn_t c0_compare_interrupt(int, void *);
27extern struct irqaction c0_compare_irqaction; 27extern struct irqaction c0_compare_irqaction;
28extern int cp0_timer_irq_installed; 28extern int cp0_timer_irq_installed;
29 29
30/*
31 * Possibly handle a performance counter interrupt.
32 * Return true if the timer interrupt should not be checked
33 */
34
35static inline int handle_perf_irq(int r2)
36{
37 /*
38 * The performance counter overflow interrupt may be shared with the
39 * timer interrupt (cp0_perfcount_irq < 0). If it is and a
40 * performance counter has overflowed (perf_irq() == IRQ_HANDLED)
41 * and we can't reliably determine if a counter interrupt has also
42 * happened (!r2) then don't check for a timer interrupt.
43 */
44 return (cp0_perfcount_irq < 0) &&
45 perf_irq() == IRQ_HANDLED &&
46 !r2;
47}
48
49#endif /* __ASM_CEVT_R4K_H */ 30#endif /* __ASM_CEVT_R4K_H */
diff --git a/arch/mips/include/asm/checksum.h b/arch/mips/include/asm/checksum.h
index 5c585c5c1c3e..3ceacde5eb6e 100644
--- a/arch/mips/include/asm/checksum.h
+++ b/arch/mips/include/asm/checksum.h
@@ -218,6 +218,8 @@ static __inline__ __sum16 csum_ipv6_magic(const struct in6_addr *saddr,
218 __u32 len, unsigned short proto, 218 __u32 len, unsigned short proto,
219 __wsum sum) 219 __wsum sum)
220{ 220{
221 __wsum tmp;
222
221 __asm__( 223 __asm__(
222 " .set push # csum_ipv6_magic\n" 224 " .set push # csum_ipv6_magic\n"
223 " .set noreorder \n" 225 " .set noreorder \n"
@@ -270,9 +272,9 @@ static __inline__ __sum16 csum_ipv6_magic(const struct in6_addr *saddr,
270 272
271 " addu %0, $1 # Add final carry\n" 273 " addu %0, $1 # Add final carry\n"
272 " .set pop" 274 " .set pop"
273 : "=r" (sum), "=r" (proto) 275 : "=&r" (sum), "=&r" (tmp)
274 : "r" (saddr), "r" (daddr), 276 : "r" (saddr), "r" (daddr),
275 "0" (htonl(len)), "1" (htonl(proto)), "r" (sum)); 277 "0" (htonl(len)), "r" (htonl(proto)), "r" (sum));
276 278
277 return csum_fold(sum); 279 return csum_fold(sum);
278} 280}
diff --git a/arch/mips/include/asm/cmpxchg.h b/arch/mips/include/asm/cmpxchg.h
index d0a2a68ca600..412f945f1f5e 100644
--- a/arch/mips/include/asm/cmpxchg.h
+++ b/arch/mips/include/asm/cmpxchg.h
@@ -229,21 +229,22 @@ extern void __cmpxchg_called_with_bad_pointer(void);
229#define cmpxchg(ptr, old, new) __cmpxchg(ptr, old, new, smp_mb__before_llsc(), smp_llsc_mb()) 229#define cmpxchg(ptr, old, new) __cmpxchg(ptr, old, new, smp_mb__before_llsc(), smp_llsc_mb())
230#define cmpxchg_local(ptr, old, new) __cmpxchg(ptr, old, new, , ) 230#define cmpxchg_local(ptr, old, new) __cmpxchg(ptr, old, new, , )
231 231
232#define cmpxchg64(ptr, o, n) \ 232#ifdef CONFIG_64BIT
233#define cmpxchg64_local(ptr, o, n) \
233 ({ \ 234 ({ \
234 BUILD_BUG_ON(sizeof(*(ptr)) != 8); \ 235 BUILD_BUG_ON(sizeof(*(ptr)) != 8); \
235 cmpxchg((ptr), (o), (n)); \ 236 cmpxchg_local((ptr), (o), (n)); \
236 }) 237 })
237 238
238#ifdef CONFIG_64BIT 239#define cmpxchg64(ptr, o, n) \
239#define cmpxchg64_local(ptr, o, n) \
240 ({ \ 240 ({ \
241 BUILD_BUG_ON(sizeof(*(ptr)) != 8); \ 241 BUILD_BUG_ON(sizeof(*(ptr)) != 8); \
242 cmpxchg_local((ptr), (o), (n)); \ 242 cmpxchg((ptr), (o), (n)); \
243 }) 243 })
244#else 244#else
245#include <asm-generic/cmpxchg-local.h> 245#include <asm-generic/cmpxchg-local.h>
246#define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n)) 246#define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n))
247#define cmpxchg64(ptr, o, n) cmpxchg64_local((ptr), (o), (n))
247#endif 248#endif
248 249
249#endif /* __ASM_CMPXCHG_H */ 250#endif /* __ASM_CMPXCHG_H */
diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h
index 0d8208de9a3f..5aeaf19c26b0 100644
--- a/arch/mips/include/asm/cpu-features.h
+++ b/arch/mips/include/asm/cpu-features.h
@@ -68,6 +68,7 @@
68#ifndef cpu_has_octeon_cache 68#ifndef cpu_has_octeon_cache
69#define cpu_has_octeon_cache 0 69#define cpu_has_octeon_cache 0
70#endif 70#endif
71/* Don't override `cpu_has_fpu' to 1 or the "nofpu" option won't work. */
71#ifndef cpu_has_fpu 72#ifndef cpu_has_fpu
72#define cpu_has_fpu (current_cpu_data.options & MIPS_CPU_FPU) 73#define cpu_has_fpu (current_cpu_data.options & MIPS_CPU_FPU)
73#define raw_cpu_has_fpu (raw_current_cpu_data.options & MIPS_CPU_FPU) 74#define raw_cpu_has_fpu (raw_current_cpu_data.options & MIPS_CPU_FPU)
@@ -139,6 +140,9 @@
139# endif 140# endif
140#endif 141#endif
141 142
143#ifndef cpu_has_xpa
144#define cpu_has_xpa (cpu_data[0].options & MIPS_CPU_XPA)
145#endif
142#ifndef cpu_has_vtag_icache 146#ifndef cpu_has_vtag_icache
143#define cpu_has_vtag_icache (cpu_data[0].icache.flags & MIPS_CACHE_VTAG) 147#define cpu_has_vtag_icache (cpu_data[0].icache.flags & MIPS_CACHE_VTAG)
144#endif 148#endif
@@ -220,8 +224,11 @@
220#define cpu_has_mips_4_5_r (cpu_has_mips_4 | cpu_has_mips_5_r) 224#define cpu_has_mips_4_5_r (cpu_has_mips_4 | cpu_has_mips_5_r)
221#define cpu_has_mips_5_r (cpu_has_mips_5 | cpu_has_mips_r) 225#define cpu_has_mips_5_r (cpu_has_mips_5 | cpu_has_mips_r)
222 226
223#define cpu_has_mips_4_5_r2_r6 (cpu_has_mips_4_5 | cpu_has_mips_r2 | \ 227#define cpu_has_mips_3_4_5_64_r2_r6 \
224 cpu_has_mips_r6) 228 (cpu_has_mips_3 | cpu_has_mips_4_5_64_r2_r6)
229#define cpu_has_mips_4_5_64_r2_r6 \
230 (cpu_has_mips_4_5 | cpu_has_mips64r1 | \
231 cpu_has_mips_r2 | cpu_has_mips_r6)
225 232
226#define cpu_has_mips32 (cpu_has_mips32r1 | cpu_has_mips32r2 | cpu_has_mips32r6) 233#define cpu_has_mips32 (cpu_has_mips32r1 | cpu_has_mips32r2 | cpu_has_mips32r6)
227#define cpu_has_mips64 (cpu_has_mips64r1 | cpu_has_mips64r2 | cpu_has_mips64r6) 234#define cpu_has_mips64 (cpu_has_mips64r1 | cpu_has_mips64r2 | cpu_has_mips64r6)
@@ -235,8 +242,39 @@
235/* MIPSR2 and MIPSR6 have a lot of similarities */ 242/* MIPSR2 and MIPSR6 have a lot of similarities */
236#define cpu_has_mips_r2_r6 (cpu_has_mips_r2 | cpu_has_mips_r6) 243#define cpu_has_mips_r2_r6 (cpu_has_mips_r2 | cpu_has_mips_r6)
237 244
245/*
246 * cpu_has_mips_r2_exec_hazard - return if IHB is required on current processor
247 *
248 * Returns non-zero value if the current processor implementation requires
249 * an IHB instruction to deal with an instruction hazard as per MIPS R2
250 * architecture specification, zero otherwise.
251 */
238#ifndef cpu_has_mips_r2_exec_hazard 252#ifndef cpu_has_mips_r2_exec_hazard
239#define cpu_has_mips_r2_exec_hazard (cpu_has_mips_r2 | cpu_has_mips_r6) 253#define cpu_has_mips_r2_exec_hazard \
254({ \
255 int __res; \
256 \
257 switch (current_cpu_type()) { \
258 case CPU_M14KC: \
259 case CPU_74K: \
260 case CPU_1074K: \
261 case CPU_PROAPTIV: \
262 case CPU_P5600: \
263 case CPU_M5150: \
264 case CPU_QEMU_GENERIC: \
265 case CPU_CAVIUM_OCTEON: \
266 case CPU_CAVIUM_OCTEON_PLUS: \
267 case CPU_CAVIUM_OCTEON2: \
268 case CPU_CAVIUM_OCTEON3: \
269 __res = 0; \
270 break; \
271 \
272 default: \
273 __res = 1; \
274 } \
275 \
276 __res; \
277})
240#endif 278#endif
241 279
242/* 280/*
@@ -366,4 +404,8 @@
366# define cpu_has_fre (cpu_data[0].options & MIPS_CPU_FRE) 404# define cpu_has_fre (cpu_data[0].options & MIPS_CPU_FRE)
367#endif 405#endif
368 406
407#ifndef cpu_has_cdmm
408# define cpu_has_cdmm (cpu_data[0].options & MIPS_CPU_CDMM)
409#endif
410
369#endif /* __ASM_CPU_FEATURES_H */ 411#endif /* __ASM_CPU_FEATURES_H */
diff --git a/arch/mips/include/asm/cpu-info.h b/arch/mips/include/asm/cpu-info.h
index c3f4f2d2e108..e7dc785a91ca 100644
--- a/arch/mips/include/asm/cpu-info.h
+++ b/arch/mips/include/asm/cpu-info.h
@@ -49,6 +49,8 @@ struct cpuinfo_mips {
49 unsigned int udelay_val; 49 unsigned int udelay_val;
50 unsigned int processor_id; 50 unsigned int processor_id;
51 unsigned int fpu_id; 51 unsigned int fpu_id;
52 unsigned int fpu_csr31;
53 unsigned int fpu_msk31;
52 unsigned int msa_id; 54 unsigned int msa_id;
53 unsigned int cputype; 55 unsigned int cputype;
54 int isa_level; 56 int isa_level;
diff --git a/arch/mips/include/asm/cpu-type.h b/arch/mips/include/asm/cpu-type.h
index 8245875f8b33..33f3cab9e689 100644
--- a/arch/mips/include/asm/cpu-type.h
+++ b/arch/mips/include/asm/cpu-type.h
@@ -157,6 +157,7 @@ static inline int __pure __get_cpu_type(const int cpu_type)
157 case CPU_R10000: 157 case CPU_R10000:
158 case CPU_R12000: 158 case CPU_R12000:
159 case CPU_R14000: 159 case CPU_R14000:
160 case CPU_R16000:
160#endif 161#endif
161#ifdef CONFIG_SYS_HAS_CPU_RM7000 162#ifdef CONFIG_SYS_HAS_CPU_RM7000
162 case CPU_RM7000: 163 case CPU_RM7000:
diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
index 15687234d70a..e3adca1d0b99 100644
--- a/arch/mips/include/asm/cpu.h
+++ b/arch/mips/include/asm/cpu.h
@@ -67,7 +67,7 @@
67#define PRID_IMP_R4300 0x0b00 67#define PRID_IMP_R4300 0x0b00
68#define PRID_IMP_VR41XX 0x0c00 68#define PRID_IMP_VR41XX 0x0c00
69#define PRID_IMP_R12000 0x0e00 69#define PRID_IMP_R12000 0x0e00
70#define PRID_IMP_R14000 0x0f00 70#define PRID_IMP_R14000 0x0f00 /* R14K && R16K */
71#define PRID_IMP_R8000 0x1000 71#define PRID_IMP_R8000 0x1000
72#define PRID_IMP_PR4450 0x1200 72#define PRID_IMP_PR4450 0x1200
73#define PRID_IMP_R4600 0x2000 73#define PRID_IMP_R4600 0x2000
@@ -284,8 +284,8 @@ enum cpu_type_enum {
284 CPU_R4000PC, CPU_R4000SC, CPU_R4000MC, CPU_R4200, CPU_R4300, CPU_R4310, 284 CPU_R4000PC, CPU_R4000SC, CPU_R4000MC, CPU_R4200, CPU_R4300, CPU_R4310,
285 CPU_R4400PC, CPU_R4400SC, CPU_R4400MC, CPU_R4600, CPU_R4640, CPU_R4650, 285 CPU_R4400PC, CPU_R4400SC, CPU_R4400MC, CPU_R4600, CPU_R4640, CPU_R4650,
286 CPU_R4700, CPU_R5000, CPU_R5500, CPU_NEVADA, CPU_R5432, CPU_R10000, 286 CPU_R4700, CPU_R5000, CPU_R5500, CPU_NEVADA, CPU_R5432, CPU_R10000,
287 CPU_R12000, CPU_R14000, CPU_VR41XX, CPU_VR4111, CPU_VR4121, CPU_VR4122, 287 CPU_R12000, CPU_R14000, CPU_R16000, CPU_VR41XX, CPU_VR4111, CPU_VR4121,
288 CPU_VR4131, CPU_VR4133, CPU_VR4181, CPU_VR4181A, CPU_RM7000, 288 CPU_VR4122, CPU_VR4131, CPU_VR4133, CPU_VR4181, CPU_VR4181A, CPU_RM7000,
289 CPU_SR71000, CPU_TX49XX, 289 CPU_SR71000, CPU_TX49XX,
290 290
291 /* 291 /*
@@ -377,6 +377,8 @@ enum cpu_type_enum {
377#define MIPS_CPU_MAAR 0x400000000ull /* MAAR(I) registers are present */ 377#define MIPS_CPU_MAAR 0x400000000ull /* MAAR(I) registers are present */
378#define MIPS_CPU_FRE 0x800000000ull /* FRE & UFE bits implemented */ 378#define MIPS_CPU_FRE 0x800000000ull /* FRE & UFE bits implemented */
379#define MIPS_CPU_RW_LLB 0x1000000000ull /* LLADDR/LLB writes are allowed */ 379#define MIPS_CPU_RW_LLB 0x1000000000ull /* LLADDR/LLB writes are allowed */
380#define MIPS_CPU_XPA 0x2000000000ull /* CPU supports Extended Physical Addressing */
381#define MIPS_CPU_CDMM 0x4000000000ull /* CPU has Common Device Memory Map */
380 382
381/* 383/*
382 * CPU ASE encodings 384 * CPU ASE encodings
diff --git a/arch/mips/include/asm/dma-mapping.h b/arch/mips/include/asm/dma-mapping.h
index 06412aa9e3fb..fd1b4a150759 100644
--- a/arch/mips/include/asm/dma-mapping.h
+++ b/arch/mips/include/asm/dma-mapping.h
@@ -23,7 +23,7 @@ static inline struct dma_map_ops *get_dma_ops(struct device *dev)
23static inline bool dma_capable(struct device *dev, dma_addr_t addr, size_t size) 23static inline bool dma_capable(struct device *dev, dma_addr_t addr, size_t size)
24{ 24{
25 if (!dev->dma_mask) 25 if (!dev->dma_mask)
26 return 0; 26 return false;
27 27
28 return addr + size <= *dev->dma_mask; 28 return addr + size <= *dev->dma_mask;
29} 29}
diff --git a/arch/mips/include/asm/elf.h b/arch/mips/include/asm/elf.h
index 31d747d46a23..a594d8ed9698 100644
--- a/arch/mips/include/asm/elf.h
+++ b/arch/mips/include/asm/elf.h
@@ -11,6 +11,9 @@
11#include <linux/fs.h> 11#include <linux/fs.h>
12#include <uapi/linux/elf.h> 12#include <uapi/linux/elf.h>
13 13
14#include <asm/cpu-info.h>
15#include <asm/current.h>
16
14/* ELF header e_flags defines. */ 17/* ELF header e_flags defines. */
15/* MIPS architecture level. */ 18/* MIPS architecture level. */
16#define EF_MIPS_ARCH_1 0x00000000 /* -mips1 code. */ 19#define EF_MIPS_ARCH_1 0x00000000 /* -mips1 code. */
@@ -294,9 +297,14 @@ do { \
294 if (personality(current->personality) != PER_LINUX) \ 297 if (personality(current->personality) != PER_LINUX) \
295 set_personality(PER_LINUX); \ 298 set_personality(PER_LINUX); \
296 \ 299 \
300 clear_thread_flag(TIF_HYBRID_FPREGS); \
301 set_thread_flag(TIF_32BIT_FPREGS); \
302 \
297 mips_set_personality_fp(state); \ 303 mips_set_personality_fp(state); \
298 \ 304 \
299 current->thread.abi = &mips_abi; \ 305 current->thread.abi = &mips_abi; \
306 \
307 current->thread.fpu.fcr31 = current_cpu_data.fpu_csr31; \
300} while (0) 308} while (0)
301 309
302#endif /* CONFIG_32BIT */ 310#endif /* CONFIG_32BIT */
@@ -319,6 +327,8 @@ do { \
319 do { \ 327 do { \
320 set_thread_flag(TIF_32BIT_REGS); \ 328 set_thread_flag(TIF_32BIT_REGS); \
321 set_thread_flag(TIF_32BIT_ADDR); \ 329 set_thread_flag(TIF_32BIT_ADDR); \
330 clear_thread_flag(TIF_HYBRID_FPREGS); \
331 set_thread_flag(TIF_32BIT_FPREGS); \
322 \ 332 \
323 mips_set_personality_fp(state); \ 333 mips_set_personality_fp(state); \
324 \ 334 \
@@ -356,6 +366,8 @@ do { \
356 else \ 366 else \
357 current->thread.abi = &mips_abi; \ 367 current->thread.abi = &mips_abi; \
358 \ 368 \
369 current->thread.fpu.fcr31 = current_cpu_data.fpu_csr31; \
370 \
359 p = personality(current->personality); \ 371 p = personality(current->personality); \
360 if (p != PER_LINUX32 && p != PER_LINUX) \ 372 if (p != PER_LINUX32 && p != PER_LINUX) \
361 set_personality(PER_LINUX); \ 373 set_personality(PER_LINUX); \
diff --git a/arch/mips/include/asm/fpu.h b/arch/mips/include/asm/fpu.h
index b104ad9d655f..084780b355aa 100644
--- a/arch/mips/include/asm/fpu.h
+++ b/arch/mips/include/asm/fpu.h
@@ -30,7 +30,7 @@
30struct sigcontext; 30struct sigcontext;
31struct sigcontext32; 31struct sigcontext32;
32 32
33extern void _init_fpu(void); 33extern void _init_fpu(unsigned int);
34extern void _save_fp(struct task_struct *); 34extern void _save_fp(struct task_struct *);
35extern void _restore_fp(struct task_struct *); 35extern void _restore_fp(struct task_struct *);
36 36
@@ -188,6 +188,7 @@ static inline void lose_fpu(int save)
188 188
189static inline int init_fpu(void) 189static inline int init_fpu(void)
190{ 190{
191 unsigned int fcr31 = current->thread.fpu.fcr31;
191 int ret = 0; 192 int ret = 0;
192 193
193 if (cpu_has_fpu) { 194 if (cpu_has_fpu) {
@@ -198,7 +199,7 @@ static inline int init_fpu(void)
198 return ret; 199 return ret;
199 200
200 if (!cpu_has_fre) { 201 if (!cpu_has_fre) {
201 _init_fpu(); 202 _init_fpu(fcr31);
202 203
203 return 0; 204 return 0;
204 } 205 }
@@ -212,7 +213,7 @@ static inline int init_fpu(void)
212 config5 = clear_c0_config5(MIPS_CONF5_FRE); 213 config5 = clear_c0_config5(MIPS_CONF5_FRE);
213 enable_fpu_hazard(); 214 enable_fpu_hazard();
214 215
215 _init_fpu(); 216 _init_fpu(fcr31);
216 217
217 /* Restore FRE */ 218 /* Restore FRE */
218 write_c0_config5(config5); 219 write_c0_config5(config5);
diff --git a/arch/mips/include/asm/fpu_emulator.h b/arch/mips/include/asm/fpu_emulator.h
index 3ee347713307..2f021cdfba4f 100644
--- a/arch/mips/include/asm/fpu_emulator.h
+++ b/arch/mips/include/asm/fpu_emulator.h
@@ -44,6 +44,7 @@ struct mips_fpu_emulator_stats {
44 unsigned long ieee754_overflow; 44 unsigned long ieee754_overflow;
45 unsigned long ieee754_zerodiv; 45 unsigned long ieee754_zerodiv;
46 unsigned long ieee754_invalidop; 46 unsigned long ieee754_invalidop;
47 unsigned long ds_emul;
47}; 48};
48 49
49DECLARE_PER_CPU(struct mips_fpu_emulator_stats, fpuemustats); 50DECLARE_PER_CPU(struct mips_fpu_emulator_stats, fpuemustats);
@@ -65,7 +66,8 @@ extern int do_dsemulret(struct pt_regs *xcp);
65extern int fpu_emulator_cop1Handler(struct pt_regs *xcp, 66extern int fpu_emulator_cop1Handler(struct pt_regs *xcp,
66 struct mips_fpu_struct *ctx, int has_fpu, 67 struct mips_fpu_struct *ctx, int has_fpu,
67 void *__user *fault_addr); 68 void *__user *fault_addr);
68int process_fpemu_return(int sig, void __user *fault_addr); 69int process_fpemu_return(int sig, void __user *fault_addr,
70 unsigned long fcr31);
69int mm_isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn, 71int mm_isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
70 unsigned long *contpc); 72 unsigned long *contpc);
71 73
@@ -86,8 +88,6 @@ static inline void fpu_emulator_init_fpu(void)
86 struct task_struct *t = current; 88 struct task_struct *t = current;
87 int i; 89 int i;
88 90
89 t->thread.fpu.fcr31 = 0;
90
91 for (i = 0; i < 32; i++) 91 for (i = 0; i < 32; i++)
92 set_fpr64(&t->thread.fpu.fpr[i], 0, SIGNALLING_NAN); 92 set_fpr64(&t->thread.fpu.fpr[i], 0, SIGNALLING_NAN);
93} 93}
diff --git a/arch/mips/include/asm/irq.h b/arch/mips/include/asm/irq.h
index 5a4e1bb8fb1b..f0db99f8defe 100644
--- a/arch/mips/include/asm/irq.h
+++ b/arch/mips/include/asm/irq.h
@@ -47,6 +47,9 @@ extern void free_irqno(unsigned int irq);
47extern int cp0_compare_irq; 47extern int cp0_compare_irq;
48extern int cp0_compare_irq_shift; 48extern int cp0_compare_irq_shift;
49extern int cp0_perfcount_irq; 49extern int cp0_perfcount_irq;
50extern int cp0_fdc_irq;
51
52extern int __weak get_c0_fdc_int(void);
50 53
51void arch_trigger_all_cpu_backtrace(bool); 54void arch_trigger_all_cpu_backtrace(bool);
52#define arch_trigger_all_cpu_backtrace arch_trigger_all_cpu_backtrace 55#define arch_trigger_all_cpu_backtrace arch_trigger_all_cpu_backtrace
diff --git a/arch/mips/include/asm/mach-ar7/war.h b/arch/mips/include/asm/mach-ar7/war.h
deleted file mode 100644
index 99071e50faab..000000000000
--- a/arch/mips/include/asm/mach-ar7/war.h
+++ /dev/null
@@ -1,24 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
7 */
8#ifndef __ASM_MIPS_MACH_AR7_WAR_H
9#define __ASM_MIPS_MACH_AR7_WAR_H
10
11#define R4600_V1_INDEX_ICACHEOP_WAR 0
12#define R4600_V1_HIT_CACHEOP_WAR 0
13#define R4600_V2_HIT_CACHEOP_WAR 0
14#define R5432_CP0_INTERRUPT_WAR 0
15#define BCM1250_M3_WAR 0
16#define SIBYTE_1956_WAR 0
17#define MIPS4K_ICACHE_REFILL_WAR 0
18#define MIPS_CACHE_SYNC_WAR 0
19#define TX49XX_ICACHE_INDEX_INV_WAR 0
20#define ICACHE_REFILLS_WORKAROUND_WAR 0
21#define R10000_LLSC_WAR 0
22#define MIPS34K_MISSED_ITLB_WAR 0
23
24#endif /* __ASM_MIPS_MACH_AR7_WAR_H */
diff --git a/arch/mips/include/asm/mach-ath25/dma-coherence.h b/arch/mips/include/asm/mach-ath25/dma-coherence.h
index d8009c93a465..d5defdde32db 100644
--- a/arch/mips/include/asm/mach-ath25/dma-coherence.h
+++ b/arch/mips/include/asm/mach-ath25/dma-coherence.h
@@ -59,16 +59,6 @@ static inline int plat_dma_supported(struct device *dev, u64 mask)
59 return 1; 59 return 1;
60} 60}
61 61
62static inline void plat_extra_sync_for_device(struct device *dev)
63{
64}
65
66static inline int plat_dma_mapping_error(struct device *dev,
67 dma_addr_t dma_addr)
68{
69 return 0;
70}
71
72static inline int plat_device_is_coherent(struct device *dev) 62static inline int plat_device_is_coherent(struct device *dev)
73{ 63{
74#ifdef CONFIG_DMA_COHERENT 64#ifdef CONFIG_DMA_COHERENT
@@ -79,4 +69,8 @@ static inline int plat_device_is_coherent(struct device *dev)
79#endif 69#endif
80} 70}
81 71
72static inline void plat_post_dma_flush(struct device *dev)
73{
74}
75
82#endif /* __ASM_MACH_ATH25_DMA_COHERENCE_H */ 76#endif /* __ASM_MACH_ATH25_DMA_COHERENCE_H */
diff --git a/arch/mips/include/asm/mach-ath25/war.h b/arch/mips/include/asm/mach-ath25/war.h
deleted file mode 100644
index e3a5250ebd67..000000000000
--- a/arch/mips/include/asm/mach-ath25/war.h
+++ /dev/null
@@ -1,25 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2008 Felix Fietkau <nbd@openwrt.org>
7 */
8#ifndef __ASM_MACH_ATH25_WAR_H
9#define __ASM_MACH_ATH25_WAR_H
10
11#define R4600_V1_INDEX_ICACHEOP_WAR 0
12#define R4600_V1_HIT_CACHEOP_WAR 0
13#define R4600_V2_HIT_CACHEOP_WAR 0
14#define R5432_CP0_INTERRUPT_WAR 0
15#define BCM1250_M3_WAR 0
16#define SIBYTE_1956_WAR 0
17#define MIPS4K_ICACHE_REFILL_WAR 0
18#define MIPS_CACHE_SYNC_WAR 0
19#define TX49XX_ICACHE_INDEX_INV_WAR 0
20#define RM9000_CDEX_SMP_WAR 0
21#define ICACHE_REFILLS_WORKAROUND_WAR 0
22#define R10000_LLSC_WAR 0
23#define MIPS34K_MISSED_ITLB_WAR 0
24
25#endif /* __ASM_MACH_ATH25_WAR_H */
diff --git a/arch/mips/include/asm/mach-au1x00/war.h b/arch/mips/include/asm/mach-au1x00/war.h
deleted file mode 100644
index 72e260d24e59..000000000000
--- a/arch/mips/include/asm/mach-au1x00/war.h
+++ /dev/null
@@ -1,24 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
7 */
8#ifndef __ASM_MIPS_MACH_AU1X00_WAR_H
9#define __ASM_MIPS_MACH_AU1X00_WAR_H
10
11#define R4600_V1_INDEX_ICACHEOP_WAR 0
12#define R4600_V1_HIT_CACHEOP_WAR 0
13#define R4600_V2_HIT_CACHEOP_WAR 0
14#define R5432_CP0_INTERRUPT_WAR 0
15#define BCM1250_M3_WAR 0
16#define SIBYTE_1956_WAR 0
17#define MIPS4K_ICACHE_REFILL_WAR 0
18#define MIPS_CACHE_SYNC_WAR 0
19#define TX49XX_ICACHE_INDEX_INV_WAR 0
20#define ICACHE_REFILLS_WORKAROUND_WAR 0
21#define R10000_LLSC_WAR 0
22#define MIPS34K_MISSED_ITLB_WAR 0
23
24#endif /* __ASM_MIPS_MACH_AU1X00_WAR_H */
diff --git a/arch/mips/include/asm/mach-bcm3384/war.h b/arch/mips/include/asm/mach-bcm3384/war.h
deleted file mode 100644
index 59d7599059b0..000000000000
--- a/arch/mips/include/asm/mach-bcm3384/war.h
+++ /dev/null
@@ -1,24 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
7 */
8#ifndef __ASM_MIPS_MACH_BCM3384_WAR_H
9#define __ASM_MIPS_MACH_BCM3384_WAR_H
10
11#define R4600_V1_INDEX_ICACHEOP_WAR 0
12#define R4600_V1_HIT_CACHEOP_WAR 0
13#define R4600_V2_HIT_CACHEOP_WAR 0
14#define R5432_CP0_INTERRUPT_WAR 0
15#define BCM1250_M3_WAR 0
16#define SIBYTE_1956_WAR 0
17#define MIPS4K_ICACHE_REFILL_WAR 0
18#define MIPS_CACHE_SYNC_WAR 0
19#define TX49XX_ICACHE_INDEX_INV_WAR 0
20#define ICACHE_REFILLS_WORKAROUND_WAR 0
21#define R10000_LLSC_WAR 0
22#define MIPS34K_MISSED_ITLB_WAR 0
23
24#endif /* __ASM_MIPS_MACH_BCM3384_WAR_H */
diff --git a/arch/mips/include/asm/mach-bcm47xx/bcm47xx.h b/arch/mips/include/asm/mach-bcm47xx/bcm47xx.h
index 7527c1d33d02..8ed77f618940 100644
--- a/arch/mips/include/asm/mach-bcm47xx/bcm47xx.h
+++ b/arch/mips/include/asm/mach-bcm47xx/bcm47xx.h
@@ -22,6 +22,7 @@
22#include <linux/ssb/ssb.h> 22#include <linux/ssb/ssb.h>
23#include <linux/bcma/bcma.h> 23#include <linux/bcma/bcma.h>
24#include <linux/bcma/bcma_soc.h> 24#include <linux/bcma/bcma_soc.h>
25#include <linux/bcm47xx_nvram.h>
25 26
26enum bcm47xx_bus_type { 27enum bcm47xx_bus_type {
27#ifdef CONFIG_BCM47XX_SSB 28#ifdef CONFIG_BCM47XX_SSB
diff --git a/arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h b/arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h
index 1f5643b89a91..c41d1dce1062 100644
--- a/arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h
+++ b/arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h
@@ -67,6 +67,7 @@ enum bcm47xx_board {
67 BCM47XX_BOARD_LINKSYS_WRT150NV11, 67 BCM47XX_BOARD_LINKSYS_WRT150NV11,
68 BCM47XX_BOARD_LINKSYS_WRT160NV1, 68 BCM47XX_BOARD_LINKSYS_WRT160NV1,
69 BCM47XX_BOARD_LINKSYS_WRT160NV3, 69 BCM47XX_BOARD_LINKSYS_WRT160NV3,
70 BCM47XX_BOARD_LINKSYS_WRT300N_V1,
70 BCM47XX_BOARD_LINKSYS_WRT300NV11, 71 BCM47XX_BOARD_LINKSYS_WRT300NV11,
71 BCM47XX_BOARD_LINKSYS_WRT310NV1, 72 BCM47XX_BOARD_LINKSYS_WRT310NV1,
72 BCM47XX_BOARD_LINKSYS_WRT310NV2, 73 BCM47XX_BOARD_LINKSYS_WRT310NV2,
@@ -74,6 +75,7 @@ enum bcm47xx_board {
74 BCM47XX_BOARD_LINKSYS_WRT54G_TYPE_0101, 75 BCM47XX_BOARD_LINKSYS_WRT54G_TYPE_0101,
75 BCM47XX_BOARD_LINKSYS_WRT54G_TYPE_0467, 76 BCM47XX_BOARD_LINKSYS_WRT54G_TYPE_0467,
76 BCM47XX_BOARD_LINKSYS_WRT54G_TYPE_0708, 77 BCM47XX_BOARD_LINKSYS_WRT54G_TYPE_0708,
78 BCM47XX_BOARD_LINKSYS_WRT600N_V11,
77 BCM47XX_BOARD_LINKSYS_WRT610NV1, 79 BCM47XX_BOARD_LINKSYS_WRT610NV1,
78 BCM47XX_BOARD_LINKSYS_WRT610NV2, 80 BCM47XX_BOARD_LINKSYS_WRT610NV2,
79 BCM47XX_BOARD_LINKSYS_WRTSL54GS, 81 BCM47XX_BOARD_LINKSYS_WRTSL54GS,
@@ -86,9 +88,11 @@ enum bcm47xx_board {
86 88
87 BCM47XX_BOARD_NETGEAR_WGR614V8, 89 BCM47XX_BOARD_NETGEAR_WGR614V8,
88 BCM47XX_BOARD_NETGEAR_WGR614V9, 90 BCM47XX_BOARD_NETGEAR_WGR614V9,
91 BCM47XX_BOARD_NETGEAR_WGR614_V10,
89 BCM47XX_BOARD_NETGEAR_WNDR3300, 92 BCM47XX_BOARD_NETGEAR_WNDR3300,
90 BCM47XX_BOARD_NETGEAR_WNDR3400V1, 93 BCM47XX_BOARD_NETGEAR_WNDR3400V1,
91 BCM47XX_BOARD_NETGEAR_WNDR3400V2, 94 BCM47XX_BOARD_NETGEAR_WNDR3400V2,
95 BCM47XX_BOARD_NETGEAR_WNDR3400_V3,
92 BCM47XX_BOARD_NETGEAR_WNDR3400VCNA, 96 BCM47XX_BOARD_NETGEAR_WNDR3400VCNA,
93 BCM47XX_BOARD_NETGEAR_WNDR3700V3, 97 BCM47XX_BOARD_NETGEAR_WNDR3700V3,
94 BCM47XX_BOARD_NETGEAR_WNDR4000, 98 BCM47XX_BOARD_NETGEAR_WNDR4000,
diff --git a/arch/mips/include/asm/mach-bcm47xx/bcm47xx_nvram.h b/arch/mips/include/asm/mach-bcm47xx/bcm47xx_nvram.h
deleted file mode 100644
index ee59ffe99922..000000000000
--- a/arch/mips/include/asm/mach-bcm47xx/bcm47xx_nvram.h
+++ /dev/null
@@ -1,21 +0,0 @@
1/*
2 * Copyright (C) 2005, Broadcom Corporation
3 * Copyright (C) 2006, Felix Fietkau <nbd@openwrt.org>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 */
10
11#ifndef __BCM47XX_NVRAM_H
12#define __BCM47XX_NVRAM_H
13
14#include <linux/types.h>
15#include <linux/kernel.h>
16
17int bcm47xx_nvram_init_from_mem(u32 base, u32 lim);
18int bcm47xx_nvram_getenv(const char *name, char *val, size_t val_len);
19int bcm47xx_nvram_gpio_pin(const char *name);
20
21#endif /* __BCM47XX_NVRAM_H */
diff --git a/arch/mips/include/asm/mach-bcm47xx/war.h b/arch/mips/include/asm/mach-bcm47xx/war.h
deleted file mode 100644
index a3d2f448b10e..000000000000
--- a/arch/mips/include/asm/mach-bcm47xx/war.h
+++ /dev/null
@@ -1,24 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
7 */
8#ifndef __ASM_MIPS_MACH_BCM47XX_WAR_H
9#define __ASM_MIPS_MACH_BCM47XX_WAR_H
10
11#define R4600_V1_INDEX_ICACHEOP_WAR 0
12#define R4600_V1_HIT_CACHEOP_WAR 0
13#define R4600_V2_HIT_CACHEOP_WAR 0
14#define R5432_CP0_INTERRUPT_WAR 0
15#define BCM1250_M3_WAR 0
16#define SIBYTE_1956_WAR 0
17#define MIPS4K_ICACHE_REFILL_WAR 0
18#define MIPS_CACHE_SYNC_WAR 0
19#define TX49XX_ICACHE_INDEX_INV_WAR 0
20#define ICACHE_REFILLS_WORKAROUND_WAR 0
21#define R10000_LLSC_WAR 0
22#define MIPS34K_MISSED_ITLB_WAR 0
23
24#endif /* __ASM_MIPS_MACH_BCM47XX_WAR_H */
diff --git a/arch/mips/include/asm/mach-bcm63xx/dma-coherence.h b/arch/mips/include/asm/mach-bcm63xx/dma-coherence.h
new file mode 100644
index 000000000000..11d3b572b1b3
--- /dev/null
+++ b/arch/mips/include/asm/mach-bcm63xx/dma-coherence.h
@@ -0,0 +1,10 @@
1#ifndef __ASM_MACH_BCM63XX_DMA_COHERENCE_H
2#define __ASM_MACH_BCM63XX_DMA_COHERENCE_H
3
4#include <asm/bmips.h>
5
6#define plat_post_dma_flush bmips_post_dma_flush
7
8#include <asm/mach-generic/dma-coherence.h>
9
10#endif /* __ASM_MACH_BCM63XX_DMA_COHERENCE_H */
diff --git a/arch/mips/include/asm/mach-bcm63xx/war.h b/arch/mips/include/asm/mach-bcm63xx/war.h
deleted file mode 100644
index 05ee8671bef1..000000000000
--- a/arch/mips/include/asm/mach-bcm63xx/war.h
+++ /dev/null
@@ -1,24 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
7 */
8#ifndef __ASM_MIPS_MACH_BCM63XX_WAR_H
9#define __ASM_MIPS_MACH_BCM63XX_WAR_H
10
11#define R4600_V1_INDEX_ICACHEOP_WAR 0
12#define R4600_V1_HIT_CACHEOP_WAR 0
13#define R4600_V2_HIT_CACHEOP_WAR 0
14#define R5432_CP0_INTERRUPT_WAR 0
15#define BCM1250_M3_WAR 0
16#define SIBYTE_1956_WAR 0
17#define MIPS4K_ICACHE_REFILL_WAR 0
18#define MIPS_CACHE_SYNC_WAR 0
19#define TX49XX_ICACHE_INDEX_INV_WAR 0
20#define ICACHE_REFILLS_WORKAROUND_WAR 0
21#define R10000_LLSC_WAR 0
22#define MIPS34K_MISSED_ITLB_WAR 0
23
24#endif /* __ASM_MIPS_MACH_BCM63XX_WAR_H */
diff --git a/arch/mips/include/asm/mach-bcm3384/dma-coherence.h b/arch/mips/include/asm/mach-bmips/dma-coherence.h
index a3be8e50e1f0..d29781f02285 100644
--- a/arch/mips/include/asm/mach-bcm3384/dma-coherence.h
+++ b/arch/mips/include/asm/mach-bmips/dma-coherence.h
@@ -12,8 +12,12 @@
12 * GNU General Public License for more details. 12 * GNU General Public License for more details.
13 */ 13 */
14 14
15#ifndef __ASM_MACH_BCM3384_DMA_COHERENCE_H 15#ifndef __ASM_MACH_BMIPS_DMA_COHERENCE_H
16#define __ASM_MACH_BCM3384_DMA_COHERENCE_H 16#define __ASM_MACH_BMIPS_DMA_COHERENCE_H
17
18#include <asm/bmips.h>
19#include <asm/cpu-type.h>
20#include <asm/cpu.h>
17 21
18struct device; 22struct device;
19 23
@@ -45,4 +49,6 @@ static inline int plat_device_is_coherent(struct device *dev)
45 return 0; 49 return 0;
46} 50}
47 51
48#endif /* __ASM_MACH_BCM3384_DMA_COHERENCE_H */ 52#define plat_post_dma_flush bmips_post_dma_flush
53
54#endif /* __ASM_MACH_BMIPS_DMA_COHERENCE_H */
diff --git a/arch/mips/include/asm/mach-bmips/spaces.h b/arch/mips/include/asm/mach-bmips/spaces.h
new file mode 100644
index 000000000000..1b05bddc8ec5
--- /dev/null
+++ b/arch/mips/include/asm/mach-bmips/spaces.h
@@ -0,0 +1,18 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1994 - 1999, 2000, 03, 04 Ralf Baechle
7 * Copyright (C) 2000, 2002 Maciej W. Rozycki
8 * Copyright (C) 1990, 1999, 2000 Silicon Graphics, Inc.
9 */
10#ifndef _ASM_BMIPS_SPACES_H
11#define _ASM_BMIPS_SPACES_H
12
13/* Avoid collisions with system base register (SBR) region on BMIPS3300 */
14#define FIXADDR_TOP ((unsigned long)(long)(int)0xff000000)
15
16#include <asm/mach-generic/spaces.h>
17
18#endif /* __ASM_BMIPS_SPACES_H */
diff --git a/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h b/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
index fa1f3cfbae8d..d68e685cde60 100644
--- a/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
@@ -50,7 +50,6 @@
50#define cpu_has_mips32r2 0 50#define cpu_has_mips32r2 0
51#define cpu_has_mips64r1 0 51#define cpu_has_mips64r1 0
52#define cpu_has_mips64r2 1 52#define cpu_has_mips64r2 1
53#define cpu_has_mips_r2_exec_hazard 0
54#define cpu_has_dsp 0 53#define cpu_has_dsp 0
55#define cpu_has_dsp2 0 54#define cpu_has_dsp2 0
56#define cpu_has_mipsmt 0 55#define cpu_has_mipsmt 0
diff --git a/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h b/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h
index f9f448650505..460042ee5d6f 100644
--- a/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h
+++ b/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h
@@ -57,6 +57,10 @@ static inline int plat_device_is_coherent(struct device *dev)
57 return 1; 57 return 1;
58} 58}
59 59
60static inline void plat_post_dma_flush(struct device *dev)
61{
62}
63
60dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr); 64dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr);
61phys_addr_t dma_to_phys(struct device *dev, dma_addr_t daddr); 65phys_addr_t dma_to_phys(struct device *dev, dma_addr_t daddr);
62 66
diff --git a/arch/mips/include/asm/mach-cavium-octeon/mangle-port.h b/arch/mips/include/asm/mach-cavium-octeon/mangle-port.h
new file mode 100644
index 000000000000..374eefafb320
--- /dev/null
+++ b/arch/mips/include/asm/mach-cavium-octeon/mangle-port.h
@@ -0,0 +1,74 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2003, 2004 Ralf Baechle
7 */
8#ifndef __ASM_MACH_GENERIC_MANGLE_PORT_H
9#define __ASM_MACH_GENERIC_MANGLE_PORT_H
10
11#include <asm/byteorder.h>
12
13#ifdef __BIG_ENDIAN
14
15# define __swizzle_addr_b(port) (port)
16# define __swizzle_addr_w(port) (port)
17# define __swizzle_addr_l(port) (port)
18# define __swizzle_addr_q(port) (port)
19
20#else /* __LITTLE_ENDIAN */
21
22static inline bool __should_swizzle_addr(unsigned long p)
23{
24 /* boot bus? */
25 return ((p >> 40) & 0xff) == 0;
26}
27
28# define __swizzle_addr_b(port) \
29 (__should_swizzle_addr(port) ? (port) ^ 7 : (port))
30# define __swizzle_addr_w(port) \
31 (__should_swizzle_addr(port) ? (port) ^ 6 : (port))
32# define __swizzle_addr_l(port) \
33 (__should_swizzle_addr(port) ? (port) ^ 4 : (port))
34# define __swizzle_addr_q(port) (port)
35
36#endif /* __BIG_ENDIAN */
37
38/*
39 * Sane hardware offers swapping of PCI/ISA I/O space accesses in hardware;
40 * less sane hardware forces software to fiddle with this...
41 *
42 * Regardless, if the host bus endianness mismatches that of PCI/ISA, then
43 * you can't have the numerical value of data and byte addresses within
44 * multibyte quantities both preserved at the same time. Hence two
45 * variations of functions: non-prefixed ones that preserve the value
46 * and prefixed ones that preserve byte addresses. The latters are
47 * typically used for moving raw data between a peripheral and memory (cf.
48 * string I/O functions), hence the "__mem_" prefix.
49 */
50#if defined(CONFIG_SWAP_IO_SPACE)
51
52# define ioswabb(a, x) (x)
53# define __mem_ioswabb(a, x) (x)
54# define ioswabw(a, x) le16_to_cpu(x)
55# define __mem_ioswabw(a, x) (x)
56# define ioswabl(a, x) le32_to_cpu(x)
57# define __mem_ioswabl(a, x) (x)
58# define ioswabq(a, x) le64_to_cpu(x)
59# define __mem_ioswabq(a, x) (x)
60
61#else
62
63# define ioswabb(a, x) (x)
64# define __mem_ioswabb(a, x) (x)
65# define ioswabw(a, x) (x)
66# define __mem_ioswabw(a, x) cpu_to_le16(x)
67# define ioswabl(a, x) (x)
68# define __mem_ioswabl(a, x) cpu_to_le32(x)
69# define ioswabq(a, x) (x)
70# define __mem_ioswabq(a, x) cpu_to_le32(x)
71
72#endif
73
74#endif /* __ASM_MACH_GENERIC_MANGLE_PORT_H */
diff --git a/arch/mips/include/asm/mach-cobalt/cpu-feature-overrides.h b/arch/mips/include/asm/mach-cobalt/cpu-feature-overrides.h
index 71d4bface1dc..30c5cd9fd973 100644
--- a/arch/mips/include/asm/mach-cobalt/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-cobalt/cpu-feature-overrides.h
@@ -14,7 +14,6 @@
14#define cpu_has_3k_cache 0 14#define cpu_has_3k_cache 0
15#define cpu_has_4k_cache 1 15#define cpu_has_4k_cache 1
16#define cpu_has_tx39_cache 0 16#define cpu_has_tx39_cache 0
17#define cpu_has_fpu 1
18#define cpu_has_32fpr 1 17#define cpu_has_32fpr 1
19#define cpu_has_counter 1 18#define cpu_has_counter 1
20#define cpu_has_watch 0 19#define cpu_has_watch 0
diff --git a/arch/mips/include/asm/mach-cobalt/war.h b/arch/mips/include/asm/mach-cobalt/war.h
deleted file mode 100644
index 34ae4046541e..000000000000
--- a/arch/mips/include/asm/mach-cobalt/war.h
+++ /dev/null
@@ -1,24 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
7 */
8#ifndef __ASM_MIPS_MACH_COBALT_WAR_H
9#define __ASM_MIPS_MACH_COBALT_WAR_H
10
11#define R4600_V1_INDEX_ICACHEOP_WAR 0
12#define R4600_V1_HIT_CACHEOP_WAR 0
13#define R4600_V2_HIT_CACHEOP_WAR 0
14#define R5432_CP0_INTERRUPT_WAR 0
15#define BCM1250_M3_WAR 0
16#define SIBYTE_1956_WAR 0
17#define MIPS4K_ICACHE_REFILL_WAR 0
18#define MIPS_CACHE_SYNC_WAR 0
19#define TX49XX_ICACHE_INDEX_INV_WAR 0
20#define ICACHE_REFILLS_WORKAROUND_WAR 0
21#define R10000_LLSC_WAR 0
22#define MIPS34K_MISSED_ITLB_WAR 0
23
24#endif /* __ASM_MIPS_MACH_COBALT_WAR_H */
diff --git a/arch/mips/include/asm/mach-dec/cpu-feature-overrides.h b/arch/mips/include/asm/mach-dec/cpu-feature-overrides.h
index acce27fd2bb8..bdf045fb00c8 100644
--- a/arch/mips/include/asm/mach-dec/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-dec/cpu-feature-overrides.h
@@ -15,7 +15,6 @@
15/* Generic ones first. */ 15/* Generic ones first. */
16#define cpu_has_tlb 1 16#define cpu_has_tlb 1
17#define cpu_has_tx39_cache 0 17#define cpu_has_tx39_cache 0
18#define cpu_has_fpu 1
19#define cpu_has_divec 0 18#define cpu_has_divec 0
20#define cpu_has_prefetch 0 19#define cpu_has_prefetch 0
21#define cpu_has_mcheck 0 20#define cpu_has_mcheck 0
diff --git a/arch/mips/include/asm/mach-dec/war.h b/arch/mips/include/asm/mach-dec/war.h
deleted file mode 100644
index d29996feb3e7..000000000000
--- a/arch/mips/include/asm/mach-dec/war.h
+++ /dev/null
@@ -1,24 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
7 */
8#ifndef __ASM_MIPS_MACH_DEC_WAR_H
9#define __ASM_MIPS_MACH_DEC_WAR_H
10
11#define R4600_V1_INDEX_ICACHEOP_WAR 0
12#define R4600_V1_HIT_CACHEOP_WAR 0
13#define R4600_V2_HIT_CACHEOP_WAR 0
14#define R5432_CP0_INTERRUPT_WAR 0
15#define BCM1250_M3_WAR 0
16#define SIBYTE_1956_WAR 0
17#define MIPS4K_ICACHE_REFILL_WAR 0
18#define MIPS_CACHE_SYNC_WAR 0
19#define TX49XX_ICACHE_INDEX_INV_WAR 0
20#define ICACHE_REFILLS_WORKAROUND_WAR 0
21#define R10000_LLSC_WAR 0
22#define MIPS34K_MISSED_ITLB_WAR 0
23
24#endif /* __ASM_MIPS_MACH_DEC_WAR_H */
diff --git a/arch/mips/include/asm/mach-emma2rh/war.h b/arch/mips/include/asm/mach-emma2rh/war.h
deleted file mode 100644
index 79ae82da3ec7..000000000000
--- a/arch/mips/include/asm/mach-emma2rh/war.h
+++ /dev/null
@@ -1,24 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
7 */
8#ifndef __ASM_MIPS_MACH_EMMA2RH_WAR_H
9#define __ASM_MIPS_MACH_EMMA2RH_WAR_H
10
11#define R4600_V1_INDEX_ICACHEOP_WAR 0
12#define R4600_V1_HIT_CACHEOP_WAR 0
13#define R4600_V2_HIT_CACHEOP_WAR 0
14#define R5432_CP0_INTERRUPT_WAR 0
15#define BCM1250_M3_WAR 0
16#define SIBYTE_1956_WAR 0
17#define MIPS4K_ICACHE_REFILL_WAR 0
18#define MIPS_CACHE_SYNC_WAR 0
19#define TX49XX_ICACHE_INDEX_INV_WAR 0
20#define ICACHE_REFILLS_WORKAROUND_WAR 0
21#define R10000_LLSC_WAR 0
22#define MIPS34K_MISSED_ITLB_WAR 0
23
24#endif /* __ASM_MIPS_MACH_EMMA2RH_WAR_H */
diff --git a/arch/mips/include/asm/mach-generic/dma-coherence.h b/arch/mips/include/asm/mach-generic/dma-coherence.h
index 7629c35986f7..0f8a354fd468 100644
--- a/arch/mips/include/asm/mach-generic/dma-coherence.h
+++ b/arch/mips/include/asm/mach-generic/dma-coherence.h
@@ -52,6 +52,12 @@ static inline int plat_device_is_coherent(struct device *dev)
52 return coherentio; 52 return coherentio;
53} 53}
54 54
55#ifndef plat_post_dma_flush
56static inline void plat_post_dma_flush(struct device *dev)
57{
58}
59#endif
60
55#ifdef CONFIG_SWIOTLB 61#ifdef CONFIG_SWIOTLB
56static inline dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr) 62static inline dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr)
57{ 63{
diff --git a/arch/mips/include/asm/mach-ath79/war.h b/arch/mips/include/asm/mach-generic/war.h
index 0bb30905fd5b..a1bc2e71f983 100644
--- a/arch/mips/include/asm/mach-ath79/war.h
+++ b/arch/mips/include/asm/mach-generic/war.h
@@ -5,8 +5,8 @@
5 * 5 *
6 * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> 6 * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
7 */ 7 */
8#ifndef __ASM_MACH_ATH79_WAR_H 8#ifndef __ASM_MACH_GENERIC_WAR_H
9#define __ASM_MACH_ATH79_WAR_H 9#define __ASM_MACH_GENERIC_WAR_H
10 10
11#define R4600_V1_INDEX_ICACHEOP_WAR 0 11#define R4600_V1_INDEX_ICACHEOP_WAR 0
12#define R4600_V1_HIT_CACHEOP_WAR 0 12#define R4600_V1_HIT_CACHEOP_WAR 0
@@ -21,4 +21,4 @@
21#define R10000_LLSC_WAR 0 21#define R10000_LLSC_WAR 0
22#define MIPS34K_MISSED_ITLB_WAR 0 22#define MIPS34K_MISSED_ITLB_WAR 0
23 23
24#endif /* __ASM_MACH_ATH79_WAR_H */ 24#endif /* __ASM_MACH_GENERIC_WAR_H */
diff --git a/arch/mips/include/asm/mach-ip22/cpu-feature-overrides.h b/arch/mips/include/asm/mach-ip22/cpu-feature-overrides.h
index 1dfe47453ea4..9b19b72dba56 100644
--- a/arch/mips/include/asm/mach-ip22/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-ip22/cpu-feature-overrides.h
@@ -16,7 +16,6 @@
16#define cpu_has_tlb 1 16#define cpu_has_tlb 1
17#define cpu_has_4kex 1 17#define cpu_has_4kex 1
18#define cpu_has_4k_cache 1 18#define cpu_has_4k_cache 1
19#define cpu_has_fpu 1
20#define cpu_has_32fpr 1 19#define cpu_has_32fpr 1
21#define cpu_has_counter 1 20#define cpu_has_counter 1
22#define cpu_has_mips16 0 21#define cpu_has_mips16 0
diff --git a/arch/mips/include/asm/mach-ip27/dma-coherence.h b/arch/mips/include/asm/mach-ip27/dma-coherence.h
index 4ffddfdb5062..1daa64412569 100644
--- a/arch/mips/include/asm/mach-ip27/dma-coherence.h
+++ b/arch/mips/include/asm/mach-ip27/dma-coherence.h
@@ -58,6 +58,10 @@ static inline int plat_dma_supported(struct device *dev, u64 mask)
58 return 1; 58 return 1;
59} 59}
60 60
61static inline void plat_post_dma_flush(struct device *dev)
62{
63}
64
61static inline int plat_device_is_coherent(struct device *dev) 65static inline int plat_device_is_coherent(struct device *dev)
62{ 66{
63 return 1; /* IP27 non-cohernet mode is unsupported */ 67 return 1; /* IP27 non-cohernet mode is unsupported */
diff --git a/arch/mips/include/asm/mach-ip32/cpu-feature-overrides.h b/arch/mips/include/asm/mach-ip32/cpu-feature-overrides.h
index 2e1ec6cfedd5..241409b78ff1 100644
--- a/arch/mips/include/asm/mach-ip32/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-ip32/cpu-feature-overrides.h
@@ -26,7 +26,6 @@
26/* Settings which are common for all ip32 CPUs */ 26/* Settings which are common for all ip32 CPUs */
27#define cpu_has_tlb 1 27#define cpu_has_tlb 1
28#define cpu_has_4kex 1 28#define cpu_has_4kex 1
29#define cpu_has_fpu 1
30#define cpu_has_32fpr 1 29#define cpu_has_32fpr 1
31#define cpu_has_counter 1 30#define cpu_has_counter 1
32#define cpu_has_mips16 0 31#define cpu_has_mips16 0
diff --git a/arch/mips/include/asm/mach-ip32/dma-coherence.h b/arch/mips/include/asm/mach-ip32/dma-coherence.h
index 104cfbc3ed63..0a0b0e2ced60 100644
--- a/arch/mips/include/asm/mach-ip32/dma-coherence.h
+++ b/arch/mips/include/asm/mach-ip32/dma-coherence.h
@@ -80,6 +80,10 @@ static inline int plat_dma_supported(struct device *dev, u64 mask)
80 return 1; 80 return 1;
81} 81}
82 82
83static inline void plat_post_dma_flush(struct device *dev)
84{
85}
86
83static inline int plat_device_is_coherent(struct device *dev) 87static inline int plat_device_is_coherent(struct device *dev)
84{ 88{
85 return 0; /* IP32 is non-cohernet */ 89 return 0; /* IP32 is non-cohernet */
diff --git a/arch/mips/include/asm/mach-jazz/dma-coherence.h b/arch/mips/include/asm/mach-jazz/dma-coherence.h
index 949003ef97b3..dc347c25c343 100644
--- a/arch/mips/include/asm/mach-jazz/dma-coherence.h
+++ b/arch/mips/include/asm/mach-jazz/dma-coherence.h
@@ -48,6 +48,10 @@ static inline int plat_dma_supported(struct device *dev, u64 mask)
48 return 1; 48 return 1;
49} 49}
50 50
51static inline void plat_post_dma_flush(struct device *dev)
52{
53}
54
51static inline int plat_device_is_coherent(struct device *dev) 55static inline int plat_device_is_coherent(struct device *dev)
52{ 56{
53 return 0; 57 return 0;
diff --git a/arch/mips/include/asm/mach-jazz/war.h b/arch/mips/include/asm/mach-jazz/war.h
deleted file mode 100644
index 5b18b9a3d0ec..000000000000
--- a/arch/mips/include/asm/mach-jazz/war.h
+++ /dev/null
@@ -1,24 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
7 */
8#ifndef __ASM_MIPS_MACH_JAZZ_WAR_H
9#define __ASM_MIPS_MACH_JAZZ_WAR_H
10
11#define R4600_V1_INDEX_ICACHEOP_WAR 0
12#define R4600_V1_HIT_CACHEOP_WAR 0
13#define R4600_V2_HIT_CACHEOP_WAR 0
14#define R5432_CP0_INTERRUPT_WAR 0
15#define BCM1250_M3_WAR 0
16#define SIBYTE_1956_WAR 0
17#define MIPS4K_ICACHE_REFILL_WAR 0
18#define MIPS_CACHE_SYNC_WAR 0
19#define TX49XX_ICACHE_INDEX_INV_WAR 0
20#define ICACHE_REFILLS_WORKAROUND_WAR 0
21#define R10000_LLSC_WAR 0
22#define MIPS34K_MISSED_ITLB_WAR 0
23
24#endif /* __ASM_MIPS_MACH_JAZZ_WAR_H */
diff --git a/arch/mips/include/asm/mach-jz4740/war.h b/arch/mips/include/asm/mach-jz4740/war.h
deleted file mode 100644
index 9b511d323838..000000000000
--- a/arch/mips/include/asm/mach-jz4740/war.h
+++ /dev/null
@@ -1,24 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
7 */
8#ifndef __ASM_MIPS_MACH_JZ4740_WAR_H
9#define __ASM_MIPS_MACH_JZ4740_WAR_H
10
11#define R4600_V1_INDEX_ICACHEOP_WAR 0
12#define R4600_V1_HIT_CACHEOP_WAR 0
13#define R4600_V2_HIT_CACHEOP_WAR 0
14#define R5432_CP0_INTERRUPT_WAR 0
15#define BCM1250_M3_WAR 0
16#define SIBYTE_1956_WAR 0
17#define MIPS4K_ICACHE_REFILL_WAR 0
18#define MIPS_CACHE_SYNC_WAR 0
19#define TX49XX_ICACHE_INDEX_INV_WAR 0
20#define ICACHE_REFILLS_WORKAROUND_WAR 0
21#define R10000_LLSC_WAR 0
22#define MIPS34K_MISSED_ITLB_WAR 0
23
24#endif /* __ASM_MIPS_MACH_JZ4740_WAR_H */
diff --git a/arch/mips/include/asm/mach-lantiq/war.h b/arch/mips/include/asm/mach-lantiq/war.h
deleted file mode 100644
index 358ca979c1bd..000000000000
--- a/arch/mips/include/asm/mach-lantiq/war.h
+++ /dev/null
@@ -1,23 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 */
7#ifndef __ASM_MIPS_MACH_LANTIQ_WAR_H
8#define __ASM_MIPS_MACH_LANTIQ_WAR_H
9
10#define R4600_V1_INDEX_ICACHEOP_WAR 0
11#define R4600_V1_HIT_CACHEOP_WAR 0
12#define R4600_V2_HIT_CACHEOP_WAR 0
13#define R5432_CP0_INTERRUPT_WAR 0
14#define BCM1250_M3_WAR 0
15#define SIBYTE_1956_WAR 0
16#define MIPS4K_ICACHE_REFILL_WAR 0
17#define MIPS_CACHE_SYNC_WAR 0
18#define TX49XX_ICACHE_INDEX_INV_WAR 0
19#define ICACHE_REFILLS_WORKAROUND_WAR 0
20#define R10000_LLSC_WAR 0
21#define MIPS34K_MISSED_ITLB_WAR 0
22
23#endif
diff --git a/arch/mips/include/asm/mach-lasat/war.h b/arch/mips/include/asm/mach-lasat/war.h
deleted file mode 100644
index 741ae724adc6..000000000000
--- a/arch/mips/include/asm/mach-lasat/war.h
+++ /dev/null
@@ -1,24 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
7 */
8#ifndef __ASM_MIPS_MACH_LASAT_WAR_H
9#define __ASM_MIPS_MACH_LASAT_WAR_H
10
11#define R4600_V1_INDEX_ICACHEOP_WAR 0
12#define R4600_V1_HIT_CACHEOP_WAR 0
13#define R4600_V2_HIT_CACHEOP_WAR 0
14#define R5432_CP0_INTERRUPT_WAR 0
15#define BCM1250_M3_WAR 0
16#define SIBYTE_1956_WAR 0
17#define MIPS4K_ICACHE_REFILL_WAR 0
18#define MIPS_CACHE_SYNC_WAR 0
19#define TX49XX_ICACHE_INDEX_INV_WAR 0
20#define ICACHE_REFILLS_WORKAROUND_WAR 0
21#define R10000_LLSC_WAR 0
22#define MIPS34K_MISSED_ITLB_WAR 0
23
24#endif /* __ASM_MIPS_MACH_LASAT_WAR_H */
diff --git a/arch/mips/include/asm/mach-loongson/cpu-feature-overrides.h b/arch/mips/include/asm/mach-loongson/cpu-feature-overrides.h
index 6d69332f21ec..acc376897e46 100644
--- a/arch/mips/include/asm/mach-loongson/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-loongson/cpu-feature-overrides.h
@@ -34,7 +34,6 @@
34#define cpu_has_dsp 0 34#define cpu_has_dsp 0
35#define cpu_has_dsp2 0 35#define cpu_has_dsp2 0
36#define cpu_has_ejtag 0 36#define cpu_has_ejtag 0
37#define cpu_has_fpu 1
38#define cpu_has_ic_fills_f_dc 0 37#define cpu_has_ic_fills_f_dc 0
39#define cpu_has_inclusive_pcaches 1 38#define cpu_has_inclusive_pcaches 1
40#define cpu_has_llsc 1 39#define cpu_has_llsc 1
diff --git a/arch/mips/include/asm/mach-loongson/dma-coherence.h b/arch/mips/include/asm/mach-loongson/dma-coherence.h
index a90534161bd2..4bf4e19f72e8 100644
--- a/arch/mips/include/asm/mach-loongson/dma-coherence.h
+++ b/arch/mips/include/asm/mach-loongson/dma-coherence.h
@@ -78,4 +78,8 @@ static inline int plat_device_is_coherent(struct device *dev)
78#endif /* CONFIG_DMA_NONCOHERENT */ 78#endif /* CONFIG_DMA_NONCOHERENT */
79} 79}
80 80
81static inline void plat_post_dma_flush(struct device *dev)
82{
83}
84
81#endif /* __ASM_MACH_LOONGSON_DMA_COHERENCE_H */ 85#endif /* __ASM_MACH_LOONGSON_DMA_COHERENCE_H */
diff --git a/arch/mips/include/asm/mach-loongson/loongson.h b/arch/mips/include/asm/mach-loongson/loongson.h
index 5459ac09679f..9783103fd6f6 100644
--- a/arch/mips/include/asm/mach-loongson/loongson.h
+++ b/arch/mips/include/asm/mach-loongson/loongson.h
@@ -255,6 +255,10 @@ static inline void do_perfcnt_IRQ(void)
255extern u64 loongson_chipcfg[MAX_PACKAGES]; 255extern u64 loongson_chipcfg[MAX_PACKAGES];
256#define LOONGSON_CHIPCFG(id) (*(volatile u32 *)(loongson_chipcfg[id])) 256#define LOONGSON_CHIPCFG(id) (*(volatile u32 *)(loongson_chipcfg[id]))
257 257
258/* Chip Temperature registor of each physical cpu package, PRid >= Loongson-3A */
259extern u64 loongson_chiptemp[MAX_PACKAGES];
260#define LOONGSON_CHIPTEMP(id) (*(volatile u32 *)(loongson_chiptemp[id]))
261
258/* Freq Control register of each physical cpu package, PRid >= Loongson-3B */ 262/* Freq Control register of each physical cpu package, PRid >= Loongson-3B */
259extern u64 loongson_freqctrl[MAX_PACKAGES]; 263extern u64 loongson_freqctrl[MAX_PACKAGES];
260#define LOONGSON_FREQCTRL(id) (*(volatile u32 *)(loongson_freqctrl[id])) 264#define LOONGSON_FREQCTRL(id) (*(volatile u32 *)(loongson_freqctrl[id]))
diff --git a/arch/mips/include/asm/mach-loongson/war.h b/arch/mips/include/asm/mach-loongson/war.h
deleted file mode 100644
index f2570df66bb5..000000000000
--- a/arch/mips/include/asm/mach-loongson/war.h
+++ /dev/null
@@ -1,24 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
7 */
8#ifndef __ASM_MACH_LOONGSON_WAR_H
9#define __ASM_MACH_LOONGSON_WAR_H
10
11#define R4600_V1_INDEX_ICACHEOP_WAR 0
12#define R4600_V1_HIT_CACHEOP_WAR 0
13#define R4600_V2_HIT_CACHEOP_WAR 0
14#define R5432_CP0_INTERRUPT_WAR 0
15#define BCM1250_M3_WAR 0
16#define SIBYTE_1956_WAR 0
17#define MIPS4K_ICACHE_REFILL_WAR 0
18#define MIPS_CACHE_SYNC_WAR 0
19#define TX49XX_ICACHE_INDEX_INV_WAR 0
20#define ICACHE_REFILLS_WORKAROUND_WAR 0
21#define R10000_LLSC_WAR 0
22#define MIPS34K_MISSED_ITLB_WAR 0
23
24#endif /* __ASM_MACH_LEMOTE_WAR_H */
diff --git a/arch/mips/include/asm/mach-loongson1/war.h b/arch/mips/include/asm/mach-loongson1/war.h
deleted file mode 100644
index 8fb50d008131..000000000000
--- a/arch/mips/include/asm/mach-loongson1/war.h
+++ /dev/null
@@ -1,24 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
7 */
8#ifndef __ASM_MACH_LOONGSON1_WAR_H
9#define __ASM_MACH_LOONGSON1_WAR_H
10
11#define R4600_V1_INDEX_ICACHEOP_WAR 0
12#define R4600_V1_HIT_CACHEOP_WAR 0
13#define R4600_V2_HIT_CACHEOP_WAR 0
14#define R5432_CP0_INTERRUPT_WAR 0
15#define BCM1250_M3_WAR 0
16#define SIBYTE_1956_WAR 0
17#define MIPS4K_ICACHE_REFILL_WAR 0
18#define MIPS_CACHE_SYNC_WAR 0
19#define TX49XX_ICACHE_INDEX_INV_WAR 0
20#define ICACHE_REFILLS_WORKAROUND_WAR 0
21#define R10000_LLSC_WAR 0
22#define MIPS34K_MISSED_ITLB_WAR 0
23
24#endif /* __ASM_MACH_LOONGSON1_WAR_H */
diff --git a/arch/mips/include/asm/mach-netlogic/multi-node.h b/arch/mips/include/asm/mach-netlogic/multi-node.h
index 9ed8dacdc37c..8bdf47e29145 100644
--- a/arch/mips/include/asm/mach-netlogic/multi-node.h
+++ b/arch/mips/include/asm/mach-netlogic/multi-node.h
@@ -48,15 +48,6 @@
48#endif 48#endif
49 49
50#define NLM_THREADS_PER_CORE 4 50#define NLM_THREADS_PER_CORE 4
51#ifdef CONFIG_CPU_XLR
52#define nlm_cores_per_node() 8
53#else
54extern unsigned int xlp_cores_per_node;
55#define nlm_cores_per_node() xlp_cores_per_node
56#endif
57
58#define nlm_threads_per_node() (nlm_cores_per_node() * NLM_THREADS_PER_CORE)
59#define nlm_cpuid_to_node(c) ((c) / nlm_threads_per_node())
60 51
61struct nlm_soc_info { 52struct nlm_soc_info {
62 unsigned long coremask; /* cores enabled on the soc */ 53 unsigned long coremask; /* cores enabled on the soc */
diff --git a/arch/mips/include/asm/mach-netlogic/topology.h b/arch/mips/include/asm/mach-netlogic/topology.h
deleted file mode 100644
index 0eb43c832b25..000000000000
--- a/arch/mips/include/asm/mach-netlogic/topology.h
+++ /dev/null
@@ -1,15 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2013 Broadcom Corporation
7 */
8#ifndef _ASM_MACH_NETLOGIC_TOPOLOGY_H
9#define _ASM_MACH_NETLOGIC_TOPOLOGY_H
10
11#include <asm/mach-netlogic/multi-node.h>
12
13#include <asm-generic/topology.h>
14
15#endif /* _ASM_MACH_NETLOGIC_TOPOLOGY_H */
diff --git a/arch/mips/include/asm/mach-netlogic/war.h b/arch/mips/include/asm/mach-netlogic/war.h
deleted file mode 100644
index 2c7216840e18..000000000000
--- a/arch/mips/include/asm/mach-netlogic/war.h
+++ /dev/null
@@ -1,25 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2011 Netlogic Microsystems.
7 * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
8 */
9#ifndef __ASM_MIPS_MACH_NLM_WAR_H
10#define __ASM_MIPS_MACH_NLM_WAR_H
11
12#define R4600_V1_INDEX_ICACHEOP_WAR 0
13#define R4600_V1_HIT_CACHEOP_WAR 0
14#define R4600_V2_HIT_CACHEOP_WAR 0
15#define R5432_CP0_INTERRUPT_WAR 0
16#define BCM1250_M3_WAR 0
17#define SIBYTE_1956_WAR 0
18#define MIPS4K_ICACHE_REFILL_WAR 0
19#define MIPS_CACHE_SYNC_WAR 0
20#define TX49XX_ICACHE_INDEX_INV_WAR 0
21#define ICACHE_REFILLS_WORKAROUND_WAR 0
22#define R10000_LLSC_WAR 0
23#define MIPS34K_MISSED_ITLB_WAR 0
24
25#endif /* __ASM_MIPS_MACH_NLM_WAR_H */
diff --git a/arch/mips/include/asm/mach-paravirt/war.h b/arch/mips/include/asm/mach-paravirt/war.h
deleted file mode 100644
index 36d3afb98451..000000000000
--- a/arch/mips/include/asm/mach-paravirt/war.h
+++ /dev/null
@@ -1,25 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
7 * Copyright (C) 2013 Cavium Networks <support@caviumnetworks.com>
8 */
9#ifndef __ASM_MIPS_MACH_PARAVIRT_WAR_H
10#define __ASM_MIPS_MACH_PARAVIRT_WAR_H
11
12#define R4600_V1_INDEX_ICACHEOP_WAR 0
13#define R4600_V1_HIT_CACHEOP_WAR 0
14#define R4600_V2_HIT_CACHEOP_WAR 0
15#define R5432_CP0_INTERRUPT_WAR 0
16#define BCM1250_M3_WAR 0
17#define SIBYTE_1956_WAR 0
18#define MIPS4K_ICACHE_REFILL_WAR 0
19#define MIPS_CACHE_SYNC_WAR 0
20#define TX49XX_ICACHE_INDEX_INV_WAR 0
21#define ICACHE_REFILLS_WORKAROUND_WAR 0
22#define R10000_LLSC_WAR 0
23#define MIPS34K_MISSED_ITLB_WAR 0
24
25#endif /* __ASM_MIPS_MACH_PARAVIRT_WAR_H */
diff --git a/arch/mips/include/asm/mach-pistachio/gpio.h b/arch/mips/include/asm/mach-pistachio/gpio.h
new file mode 100644
index 000000000000..6c1649c27b8d
--- /dev/null
+++ b/arch/mips/include/asm/mach-pistachio/gpio.h
@@ -0,0 +1,21 @@
1/*
2 * Pistachio IRQ setup
3 *
4 * Copyright (C) 2014 Google, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 */
10
11#ifndef __ASM_MACH_PISTACHIO_GPIO_H
12#define __ASM_MACH_PISTACHIO_GPIO_H
13
14#include <asm-generic/gpio.h>
15
16#define gpio_get_value __gpio_get_value
17#define gpio_set_value __gpio_set_value
18#define gpio_cansleep __gpio_cansleep
19#define gpio_to_irq __gpio_to_irq
20
21#endif /* __ASM_MACH_PISTACHIO_GPIO_H */
diff --git a/arch/mips/include/asm/mach-pistachio/irq.h b/arch/mips/include/asm/mach-pistachio/irq.h
new file mode 100644
index 000000000000..b94a09a54221
--- /dev/null
+++ b/arch/mips/include/asm/mach-pistachio/irq.h
@@ -0,0 +1,18 @@
1/*
2 * Pistachio IRQ setup
3 *
4 * Copyright (C) 2014 Google, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 */
10
11#ifndef __ASM_MACH_PISTACHIO_IRQ_H
12#define __ASM_MACH_PISTACHIO_IRQ_H
13
14#define NR_IRQS 256
15
16#include_next <irq.h>
17
18#endif /* __ASM_MACH_PISTACHIO_IRQ_H */
diff --git a/arch/mips/include/asm/mach-pnx833x/war.h b/arch/mips/include/asm/mach-pnx833x/war.h
deleted file mode 100644
index e410df4e1b3a..000000000000
--- a/arch/mips/include/asm/mach-pnx833x/war.h
+++ /dev/null
@@ -1,24 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
7 */
8#ifndef __ASM_MIPS_MACH_PNX833X_WAR_H
9#define __ASM_MIPS_MACH_PNX833X_WAR_H
10
11#define R4600_V1_INDEX_ICACHEOP_WAR 0
12#define R4600_V1_HIT_CACHEOP_WAR 0
13#define R4600_V2_HIT_CACHEOP_WAR 0
14#define R5432_CP0_INTERRUPT_WAR 0
15#define BCM1250_M3_WAR 0
16#define SIBYTE_1956_WAR 0
17#define MIPS4K_ICACHE_REFILL_WAR 0
18#define MIPS_CACHE_SYNC_WAR 0
19#define TX49XX_ICACHE_INDEX_INV_WAR 0
20#define ICACHE_REFILLS_WORKAROUND_WAR 0
21#define R10000_LLSC_WAR 0
22#define MIPS34K_MISSED_ITLB_WAR 0
23
24#endif /* __ASM_MIPS_MACH_PNX833X_WAR_H */
diff --git a/arch/mips/include/asm/mach-ralink/war.h b/arch/mips/include/asm/mach-ralink/war.h
deleted file mode 100644
index c074b5dc1f82..000000000000
--- a/arch/mips/include/asm/mach-ralink/war.h
+++ /dev/null
@@ -1,24 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
7 */
8#ifndef __ASM_MACH_RALINK_WAR_H
9#define __ASM_MACH_RALINK_WAR_H
10
11#define R4600_V1_INDEX_ICACHEOP_WAR 0
12#define R4600_V1_HIT_CACHEOP_WAR 0
13#define R4600_V2_HIT_CACHEOP_WAR 0
14#define R5432_CP0_INTERRUPT_WAR 0
15#define BCM1250_M3_WAR 0
16#define SIBYTE_1956_WAR 0
17#define MIPS4K_ICACHE_REFILL_WAR 0
18#define MIPS_CACHE_SYNC_WAR 0
19#define TX49XX_ICACHE_INDEX_INV_WAR 0
20#define ICACHE_REFILLS_WORKAROUND_WAR 0
21#define R10000_LLSC_WAR 0
22#define MIPS34K_MISSED_ITLB_WAR 0
23
24#endif /* __ASM_MACH_RALINK_WAR_H */
diff --git a/arch/mips/include/asm/mach-rm/cpu-feature-overrides.h b/arch/mips/include/asm/mach-rm/cpu-feature-overrides.h
index f095c529c48c..98cf40417c5d 100644
--- a/arch/mips/include/asm/mach-rm/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-rm/cpu-feature-overrides.h
@@ -15,7 +15,6 @@
15#define cpu_has_tlb 1 15#define cpu_has_tlb 1
16#define cpu_has_4kex 1 16#define cpu_has_4kex 1
17#define cpu_has_4k_cache 1 17#define cpu_has_4k_cache 1
18#define cpu_has_fpu 1
19#define cpu_has_32fpr 1 18#define cpu_has_32fpr 1
20#define cpu_has_counter 1 19#define cpu_has_counter 1
21#define cpu_has_watch 0 20#define cpu_has_watch 0
diff --git a/arch/mips/include/asm/mach-tx39xx/war.h b/arch/mips/include/asm/mach-tx39xx/war.h
deleted file mode 100644
index 6a52e6534776..000000000000
--- a/arch/mips/include/asm/mach-tx39xx/war.h
+++ /dev/null
@@ -1,24 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
7 */
8#ifndef __ASM_MIPS_MACH_TX39XX_WAR_H
9#define __ASM_MIPS_MACH_TX39XX_WAR_H
10
11#define R4600_V1_INDEX_ICACHEOP_WAR 0
12#define R4600_V1_HIT_CACHEOP_WAR 0
13#define R4600_V2_HIT_CACHEOP_WAR 0
14#define R5432_CP0_INTERRUPT_WAR 0
15#define BCM1250_M3_WAR 0
16#define SIBYTE_1956_WAR 0
17#define MIPS4K_ICACHE_REFILL_WAR 0
18#define MIPS_CACHE_SYNC_WAR 0
19#define TX49XX_ICACHE_INDEX_INV_WAR 0
20#define ICACHE_REFILLS_WORKAROUND_WAR 0
21#define R10000_LLSC_WAR 0
22#define MIPS34K_MISSED_ITLB_WAR 0
23
24#endif /* __ASM_MIPS_MACH_TX39XX_WAR_H */
diff --git a/arch/mips/include/asm/mach-vr41xx/war.h b/arch/mips/include/asm/mach-vr41xx/war.h
deleted file mode 100644
index ffe31e736009..000000000000
--- a/arch/mips/include/asm/mach-vr41xx/war.h
+++ /dev/null
@@ -1,24 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
7 */
8#ifndef __ASM_MIPS_MACH_VR41XX_WAR_H
9#define __ASM_MIPS_MACH_VR41XX_WAR_H
10
11#define R4600_V1_INDEX_ICACHEOP_WAR 0
12#define R4600_V1_HIT_CACHEOP_WAR 0
13#define R4600_V2_HIT_CACHEOP_WAR 0
14#define R5432_CP0_INTERRUPT_WAR 0
15#define BCM1250_M3_WAR 0
16#define SIBYTE_1956_WAR 0
17#define MIPS4K_ICACHE_REFILL_WAR 0
18#define MIPS_CACHE_SYNC_WAR 0
19#define TX49XX_ICACHE_INDEX_INV_WAR 0
20#define ICACHE_REFILLS_WORKAROUND_WAR 0
21#define R10000_LLSC_WAR 0
22#define MIPS34K_MISSED_ITLB_WAR 0
23
24#endif /* __ASM_MIPS_MACH_VR41XX_WAR_H */
diff --git a/arch/mips/include/asm/mips-boards/sead3-addr.h b/arch/mips/include/asm/mips-boards/sead3-addr.h
new file mode 100644
index 000000000000..c0db57802f7c
--- /dev/null
+++ b/arch/mips/include/asm/mips-boards/sead3-addr.h
@@ -0,0 +1,83 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2015 Imagination Technologies, Inc.
7 * written by Ralf Baechle <ralf@linux-mips.org>
8 */
9#ifndef __ASM_MIPS_BOARDS_SEAD3_ADDR_H
10#define __ASM_MIPS_BOARDS_SEAD3_ADDR_H
11
12/*
13 * Target #0 Register Decode
14 */
15#define SEAD3_SD_SPDCNF 0xbb000040
16#define SEAD3_SD_SPADDR 0xbb000048
17#define SEAD3_SD_DATA 0xbb000050
18
19/*
20 * Target #1 Register Decode
21 */
22#define SEAD3_CFG 0xbb100110
23#define SEAD3_GIC_BASE_ADDRESS 0xbb1c0000
24#define SEAD3_SHARED_SECTION 0xbb1c0000
25#define SEAD3_VPE_LOCAL_SECTION 0xbb1c8000
26#define SEAD3_VPE_OTHER_SECTION 0xbb1cc000
27#define SEAD3_USER_MODE_VISIBLE_SECTION 0xbb1d0000
28
29/*
30 * Target #3 Register Decode
31 */
32#define SEAD3_USB_HS_BASE 0xbb200000
33#define SEAD3_USB_HS_IDENTIFICATION_REGS 0xbb200000
34#define SEAD3_USB_HS_CAPABILITY_REGS 0xbb200100
35#define SEAD3_USB_HS_OPERATIONAL_REGS 0xbb200140
36#define SEAD3_RESERVED 0xbe800000
37
38/*
39 * Target #3 Register Decode
40 */
41#define SEAD3_SRAM 0xbe000000
42#define SEAD3_OPTIONAL_SRAM 0xbe400000
43#define SEAD3_FPGA 0xbf000000
44
45#define SEAD3_PI_PIC32_USB_STATUS 0xbf000060
46#define SEAD3_PI_PIC32_USB_STATUS_IO_RDY (1 << 0)
47#define SEAD3_PI_PIC32_USB_STATUS_SPL_INT (1 << 1)
48#define SEAD3_PI_PIC32_USB_STATUS_GPIOA_INT (1 << 2)
49#define SEAD3_PI_PIC32_USB_STATUS_GPIOB_INT (1 << 3)
50
51#define SEAD3_PI_SOFT_ENDIAN 0xbf000070
52
53#define SEAD3_CPLD_P_SWITCH 0xbf000200
54#define SEAD3_CPLD_F_SWITCH 0xbf000208
55#define SEAD3_CPLD_P_LED 0xbf000210
56#define SEAD3_CPLD_F_LED 0xbf000218
57#define SEAD3_NEWSC_LIVE 0xbf000220
58#define SEAD3_NEWSC_REG 0xbf000228
59#define SEAD3_NEWSC_CTRL 0xbf000230
60
61#define SEAD3_LCD_CONTROL 0xbf000400
62#define SEAD3_LCD_DATA 0xbf000408
63#define SEAD3_CPLD_LCD_STATUS 0xbf000410
64#define SEAD3_CPLD_LCD_DATA 0xbf000418
65
66#define SEAD3_CPLD_PI_DEVRST 0xbf000480
67#define SEAD3_CPLD_PI_DEVRST_IC32_RST (1 << 0)
68#define SEAD3_RESERVED_0 0xbf000500
69
70#define SEAD3_PIC32_REGISTERS 0xbf000600
71#define SEAD3_RESERVED_1 0xbf000700
72#define SEAD3_UART_CH_0 0xbf000800
73#define SEAD3_UART_CH_1 0xbf000900
74#define SEAD3_RESERVED_2 0xbf000a00
75#define SEAD3_ETHERNET 0xbf010000
76#define SEAD3_RESERVED_3 0xbf020000
77#define SEAD3_USER_EXPANSION 0xbf400000
78#define SEAD3_RESERVED_4 0xbf800000
79#define SEAD3_BOOT_FLASH_EXTENSION 0xbfa00000
80#define SEAD3_BOOT_FLASH 0xbfc00000
81#define SEAD3_REVISION_REGISTER 0xbfc00010
82
83#endif /* __ASM_MIPS_BOARDS_SEAD3_ADDR_H */
diff --git a/arch/mips/include/asm/mips-r2-to-r6-emul.h b/arch/mips/include/asm/mips-r2-to-r6-emul.h
index 60570f2c3ba2..4b89f28047f7 100644
--- a/arch/mips/include/asm/mips-r2-to-r6-emul.h
+++ b/arch/mips/include/asm/mips-r2-to-r6-emul.h
@@ -84,11 +84,16 @@ extern void do_trap_or_bp(struct pt_regs *regs, unsigned int code,
84 84
85#ifndef CONFIG_MIPSR2_TO_R6_EMULATOR 85#ifndef CONFIG_MIPSR2_TO_R6_EMULATOR
86static int mipsr2_emulation; 86static int mipsr2_emulation;
87static __maybe_unused int mipsr2_decoder(struct pt_regs *regs, u32 inst) { return 0; }; 87static inline int mipsr2_decoder(struct pt_regs *regs, u32 inst,
88 unsigned long *fcr31)
89{
90 return 0;
91};
88#else 92#else
89/* MIPS R2 Emulator ON/OFF */ 93/* MIPS R2 Emulator ON/OFF */
90extern int mipsr2_emulation; 94extern int mipsr2_emulation;
91extern int mipsr2_decoder(struct pt_regs *regs, u32 inst); 95extern int mipsr2_decoder(struct pt_regs *regs, u32 inst,
96 unsigned long *fcr31);
92#endif /* CONFIG_MIPSR2_TO_R6_EMULATOR */ 97#endif /* CONFIG_MIPSR2_TO_R6_EMULATOR */
93 98
94#define NO_R6EMU (cpu_has_mips_r6 && !mipsr2_emulation) 99#define NO_R6EMU (cpu_has_mips_r6 && !mipsr2_emulation)
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index fef004434096..764e2756b54d 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -111,70 +111,6 @@
111 */ 111 */
112#define CP0_TX39_CACHE $7 112#define CP0_TX39_CACHE $7
113 113
114/*
115 * Coprocessor 1 (FPU) register names
116 */
117#define CP1_REVISION $0
118#define CP1_STATUS $31
119
120/*
121 * FPU Status Register Values
122 */
123/*
124 * Status Register Values
125 */
126
127#define FPU_CSR_FLUSH 0x01000000 /* flush denormalised results to 0 */
128#define FPU_CSR_COND 0x00800000 /* $fcc0 */
129#define FPU_CSR_COND0 0x00800000 /* $fcc0 */
130#define FPU_CSR_COND1 0x02000000 /* $fcc1 */
131#define FPU_CSR_COND2 0x04000000 /* $fcc2 */
132#define FPU_CSR_COND3 0x08000000 /* $fcc3 */
133#define FPU_CSR_COND4 0x10000000 /* $fcc4 */
134#define FPU_CSR_COND5 0x20000000 /* $fcc5 */
135#define FPU_CSR_COND6 0x40000000 /* $fcc6 */
136#define FPU_CSR_COND7 0x80000000 /* $fcc7 */
137
138/*
139 * Bits 18 - 20 of the FPU Status Register will be read as 0,
140 * and should be written as zero.
141 */
142#define FPU_CSR_RSVD 0x001c0000
143
144/*
145 * X the exception cause indicator
146 * E the exception enable
147 * S the sticky/flag bit
148*/
149#define FPU_CSR_ALL_X 0x0003f000
150#define FPU_CSR_UNI_X 0x00020000
151#define FPU_CSR_INV_X 0x00010000
152#define FPU_CSR_DIV_X 0x00008000
153#define FPU_CSR_OVF_X 0x00004000
154#define FPU_CSR_UDF_X 0x00002000
155#define FPU_CSR_INE_X 0x00001000
156
157#define FPU_CSR_ALL_E 0x00000f80
158#define FPU_CSR_INV_E 0x00000800
159#define FPU_CSR_DIV_E 0x00000400
160#define FPU_CSR_OVF_E 0x00000200
161#define FPU_CSR_UDF_E 0x00000100
162#define FPU_CSR_INE_E 0x00000080
163
164#define FPU_CSR_ALL_S 0x0000007c
165#define FPU_CSR_INV_S 0x00000040
166#define FPU_CSR_DIV_S 0x00000020
167#define FPU_CSR_OVF_S 0x00000010
168#define FPU_CSR_UDF_S 0x00000008
169#define FPU_CSR_INE_S 0x00000004
170
171/* Bits 0 and 1 of FPU Status Register specify the rounding mode */
172#define FPU_CSR_RM 0x00000003
173#define FPU_CSR_RN 0x0 /* nearest */
174#define FPU_CSR_RZ 0x1 /* towards zero */
175#define FPU_CSR_RU 0x2 /* towards +Infinity */
176#define FPU_CSR_RD 0x3 /* towards -Infinity */
177
178 114
179/* 115/*
180 * Values for PageMask register 116 * Values for PageMask register
@@ -341,39 +277,6 @@
341#define ST0_MX 0x01000000 277#define ST0_MX 0x01000000
342 278
343/* 279/*
344 * Bitfields in the TX39 family CP0 Configuration Register 3
345 */
346#define TX39_CONF_ICS_SHIFT 19
347#define TX39_CONF_ICS_MASK 0x00380000
348#define TX39_CONF_ICS_1KB 0x00000000
349#define TX39_CONF_ICS_2KB 0x00080000
350#define TX39_CONF_ICS_4KB 0x00100000
351#define TX39_CONF_ICS_8KB 0x00180000
352#define TX39_CONF_ICS_16KB 0x00200000
353
354#define TX39_CONF_DCS_SHIFT 16
355#define TX39_CONF_DCS_MASK 0x00070000
356#define TX39_CONF_DCS_1KB 0x00000000
357#define TX39_CONF_DCS_2KB 0x00010000
358#define TX39_CONF_DCS_4KB 0x00020000
359#define TX39_CONF_DCS_8KB 0x00030000
360#define TX39_CONF_DCS_16KB 0x00040000
361
362#define TX39_CONF_CWFON 0x00004000
363#define TX39_CONF_WBON 0x00002000
364#define TX39_CONF_RF_SHIFT 10
365#define TX39_CONF_RF_MASK 0x00000c00
366#define TX39_CONF_DOZE 0x00000200
367#define TX39_CONF_HALT 0x00000100
368#define TX39_CONF_LOCK 0x00000080
369#define TX39_CONF_ICE 0x00000020
370#define TX39_CONF_DCE 0x00000010
371#define TX39_CONF_IRSIZE_SHIFT 2
372#define TX39_CONF_IRSIZE_MASK 0x0000000c
373#define TX39_CONF_DRSIZE_SHIFT 0
374#define TX39_CONF_DRSIZE_MASK 0x00000003
375
376/*
377 * Status register bits available in all MIPS CPUs. 280 * Status register bits available in all MIPS CPUs.
378 */ 281 */
379#define ST0_IM 0x0000ff00 282#define ST0_IM 0x0000ff00
@@ -425,9 +328,9 @@
425 328
426/* 329/*
427 * Bitfields and bit numbers in the coprocessor 0 IntCtl register. (MIPSR2) 330 * Bitfields and bit numbers in the coprocessor 0 IntCtl register. (MIPSR2)
428 *
429 * Refer to your MIPS R4xx0 manual, chapter 5 for explanation.
430 */ 331 */
332#define INTCTLB_IPFDC 23
333#define INTCTLF_IPFDC (_ULCAST_(7) << INTCTLB_IPFDC)
431#define INTCTLB_IPPCI 26 334#define INTCTLB_IPPCI 26
432#define INTCTLF_IPPCI (_ULCAST_(7) << INTCTLB_IPPCI) 335#define INTCTLF_IPPCI (_ULCAST_(7) << INTCTLB_IPPCI)
433#define INTCTLB_IPTI 29 336#define INTCTLB_IPTI 29
@@ -438,10 +341,10 @@
438 * 341 *
439 * Refer to your MIPS R4xx0 manual, chapter 5 for explanation. 342 * Refer to your MIPS R4xx0 manual, chapter 5 for explanation.
440 */ 343 */
441#define CAUSEB_EXCCODE 2 344#define CAUSEB_EXCCODE 2
442#define CAUSEF_EXCCODE (_ULCAST_(31) << 2) 345#define CAUSEF_EXCCODE (_ULCAST_(31) << 2)
443#define CAUSEB_IP 8 346#define CAUSEB_IP 8
444#define CAUSEF_IP (_ULCAST_(255) << 8) 347#define CAUSEF_IP (_ULCAST_(255) << 8)
445#define CAUSEB_IP0 8 348#define CAUSEB_IP0 8
446#define CAUSEF_IP0 (_ULCAST_(1) << 8) 349#define CAUSEF_IP0 (_ULCAST_(1) << 8)
447#define CAUSEB_IP1 9 350#define CAUSEB_IP1 9
@@ -458,16 +361,18 @@
458#define CAUSEF_IP6 (_ULCAST_(1) << 14) 361#define CAUSEF_IP6 (_ULCAST_(1) << 14)
459#define CAUSEB_IP7 15 362#define CAUSEB_IP7 15
460#define CAUSEF_IP7 (_ULCAST_(1) << 15) 363#define CAUSEF_IP7 (_ULCAST_(1) << 15)
461#define CAUSEB_IV 23 364#define CAUSEB_FDCI 21
462#define CAUSEF_IV (_ULCAST_(1) << 23) 365#define CAUSEF_FDCI (_ULCAST_(1) << 21)
463#define CAUSEB_PCI 26 366#define CAUSEB_IV 23
464#define CAUSEF_PCI (_ULCAST_(1) << 26) 367#define CAUSEF_IV (_ULCAST_(1) << 23)
465#define CAUSEB_CE 28 368#define CAUSEB_PCI 26
466#define CAUSEF_CE (_ULCAST_(3) << 28) 369#define CAUSEF_PCI (_ULCAST_(1) << 26)
467#define CAUSEB_TI 30 370#define CAUSEB_CE 28
468#define CAUSEF_TI (_ULCAST_(1) << 30) 371#define CAUSEF_CE (_ULCAST_(3) << 28)
469#define CAUSEB_BD 31 372#define CAUSEB_TI 30
470#define CAUSEF_BD (_ULCAST_(1) << 31) 373#define CAUSEF_TI (_ULCAST_(1) << 30)
374#define CAUSEB_BD 31
375#define CAUSEF_BD (_ULCAST_(1) << 31)
471 376
472/* 377/*
473 * Bits in the coprocessor 0 config register. 378 * Bits in the coprocessor 0 config register.
@@ -689,18 +594,6 @@
689#define MIPS_CMGCRF_BASE (~_ULCAST_((1 << MIPS_CMGCRB_BASE) - 1)) 594#define MIPS_CMGCRF_BASE (~_ULCAST_((1 << MIPS_CMGCRB_BASE) - 1))
690 595
691/* 596/*
692 * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register.
693 */
694#define MIPS_FPIR_S (_ULCAST_(1) << 16)
695#define MIPS_FPIR_D (_ULCAST_(1) << 17)
696#define MIPS_FPIR_PS (_ULCAST_(1) << 18)
697#define MIPS_FPIR_3D (_ULCAST_(1) << 19)
698#define MIPS_FPIR_W (_ULCAST_(1) << 20)
699#define MIPS_FPIR_L (_ULCAST_(1) << 21)
700#define MIPS_FPIR_F64 (_ULCAST_(1) << 22)
701#define MIPS_FPIR_FREP (_ULCAST_(1) << 29)
702
703/*
704 * Bits in the MIPS32 Memory Segmentation registers. 597 * Bits in the MIPS32 Memory Segmentation registers.
705 */ 598 */
706#define MIPS_SEGCFG_PA_SHIFT 9 599#define MIPS_SEGCFG_PA_SHIFT 9
@@ -751,6 +644,172 @@
751#define MIPS_PWCTL_PSN_SHIFT 0 644#define MIPS_PWCTL_PSN_SHIFT 0
752#define MIPS_PWCTL_PSN_MASK 0x0000003f 645#define MIPS_PWCTL_PSN_MASK 0x0000003f
753 646
647/* CDMMBase register bit definitions */
648#define MIPS_CDMMBASE_SIZE_SHIFT 0
649#define MIPS_CDMMBASE_SIZE (_ULCAST_(511) << MIPS_CDMMBASE_SIZE_SHIFT)
650#define MIPS_CDMMBASE_CI (_ULCAST_(1) << 9)
651#define MIPS_CDMMBASE_EN (_ULCAST_(1) << 10)
652#define MIPS_CDMMBASE_ADDR_SHIFT 11
653#define MIPS_CDMMBASE_ADDR_START 15
654
655/*
656 * Bitfields in the TX39 family CP0 Configuration Register 3
657 */
658#define TX39_CONF_ICS_SHIFT 19
659#define TX39_CONF_ICS_MASK 0x00380000
660#define TX39_CONF_ICS_1KB 0x00000000
661#define TX39_CONF_ICS_2KB 0x00080000
662#define TX39_CONF_ICS_4KB 0x00100000
663#define TX39_CONF_ICS_8KB 0x00180000
664#define TX39_CONF_ICS_16KB 0x00200000
665
666#define TX39_CONF_DCS_SHIFT 16
667#define TX39_CONF_DCS_MASK 0x00070000
668#define TX39_CONF_DCS_1KB 0x00000000
669#define TX39_CONF_DCS_2KB 0x00010000
670#define TX39_CONF_DCS_4KB 0x00020000
671#define TX39_CONF_DCS_8KB 0x00030000
672#define TX39_CONF_DCS_16KB 0x00040000
673
674#define TX39_CONF_CWFON 0x00004000
675#define TX39_CONF_WBON 0x00002000
676#define TX39_CONF_RF_SHIFT 10
677#define TX39_CONF_RF_MASK 0x00000c00
678#define TX39_CONF_DOZE 0x00000200
679#define TX39_CONF_HALT 0x00000100
680#define TX39_CONF_LOCK 0x00000080
681#define TX39_CONF_ICE 0x00000020
682#define TX39_CONF_DCE 0x00000010
683#define TX39_CONF_IRSIZE_SHIFT 2
684#define TX39_CONF_IRSIZE_MASK 0x0000000c
685#define TX39_CONF_DRSIZE_SHIFT 0
686#define TX39_CONF_DRSIZE_MASK 0x00000003
687
688
689/*
690 * Coprocessor 1 (FPU) register names
691 */
692#define CP1_REVISION $0
693#define CP1_UFR $1
694#define CP1_UNFR $4
695#define CP1_FCCR $25
696#define CP1_FEXR $26
697#define CP1_FENR $28
698#define CP1_STATUS $31
699
700
701/*
702 * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register.
703 */
704#define MIPS_FPIR_S (_ULCAST_(1) << 16)
705#define MIPS_FPIR_D (_ULCAST_(1) << 17)
706#define MIPS_FPIR_PS (_ULCAST_(1) << 18)
707#define MIPS_FPIR_3D (_ULCAST_(1) << 19)
708#define MIPS_FPIR_W (_ULCAST_(1) << 20)
709#define MIPS_FPIR_L (_ULCAST_(1) << 21)
710#define MIPS_FPIR_F64 (_ULCAST_(1) << 22)
711#define MIPS_FPIR_HAS2008 (_ULCAST_(1) << 23)
712#define MIPS_FPIR_UFRP (_ULCAST_(1) << 28)
713#define MIPS_FPIR_FREP (_ULCAST_(1) << 29)
714
715/*
716 * Bits in the MIPS32/64 coprocessor 1 (FPU) condition codes register.
717 */
718#define MIPS_FCCR_CONDX_S 0
719#define MIPS_FCCR_CONDX (_ULCAST_(255) << MIPS_FCCR_CONDX_S)
720#define MIPS_FCCR_COND0_S 0
721#define MIPS_FCCR_COND0 (_ULCAST_(1) << MIPS_FCCR_COND0_S)
722#define MIPS_FCCR_COND1_S 1
723#define MIPS_FCCR_COND1 (_ULCAST_(1) << MIPS_FCCR_COND1_S)
724#define MIPS_FCCR_COND2_S 2
725#define MIPS_FCCR_COND2 (_ULCAST_(1) << MIPS_FCCR_COND2_S)
726#define MIPS_FCCR_COND3_S 3
727#define MIPS_FCCR_COND3 (_ULCAST_(1) << MIPS_FCCR_COND3_S)
728#define MIPS_FCCR_COND4_S 4
729#define MIPS_FCCR_COND4 (_ULCAST_(1) << MIPS_FCCR_COND4_S)
730#define MIPS_FCCR_COND5_S 5
731#define MIPS_FCCR_COND5 (_ULCAST_(1) << MIPS_FCCR_COND5_S)
732#define MIPS_FCCR_COND6_S 6
733#define MIPS_FCCR_COND6 (_ULCAST_(1) << MIPS_FCCR_COND6_S)
734#define MIPS_FCCR_COND7_S 7
735#define MIPS_FCCR_COND7 (_ULCAST_(1) << MIPS_FCCR_COND7_S)
736
737/*
738 * Bits in the MIPS32/64 coprocessor 1 (FPU) enables register.
739 */
740#define MIPS_FENR_FS_S 2
741#define MIPS_FENR_FS (_ULCAST_(1) << MIPS_FENR_FS_S)
742
743/*
744 * FPU Status Register Values
745 */
746#define FPU_CSR_COND_S 23 /* $fcc0 */
747#define FPU_CSR_COND (_ULCAST_(1) << FPU_CSR_COND_S)
748
749#define FPU_CSR_FS_S 24 /* flush denormalised results to 0 */
750#define FPU_CSR_FS (_ULCAST_(1) << FPU_CSR_FS_S)
751
752#define FPU_CSR_CONDX_S 25 /* $fcc[7:1] */
753#define FPU_CSR_CONDX (_ULCAST_(127) << FPU_CSR_CONDX_S)
754#define FPU_CSR_COND1_S 25 /* $fcc1 */
755#define FPU_CSR_COND1 (_ULCAST_(1) << FPU_CSR_COND1_S)
756#define FPU_CSR_COND2_S 26 /* $fcc2 */
757#define FPU_CSR_COND2 (_ULCAST_(1) << FPU_CSR_COND2_S)
758#define FPU_CSR_COND3_S 27 /* $fcc3 */
759#define FPU_CSR_COND3 (_ULCAST_(1) << FPU_CSR_COND3_S)
760#define FPU_CSR_COND4_S 28 /* $fcc4 */
761#define FPU_CSR_COND4 (_ULCAST_(1) << FPU_CSR_COND4_S)
762#define FPU_CSR_COND5_S 29 /* $fcc5 */
763#define FPU_CSR_COND5 (_ULCAST_(1) << FPU_CSR_COND5_S)
764#define FPU_CSR_COND6_S 30 /* $fcc6 */
765#define FPU_CSR_COND6 (_ULCAST_(1) << FPU_CSR_COND6_S)
766#define FPU_CSR_COND7_S 31 /* $fcc7 */
767#define FPU_CSR_COND7 (_ULCAST_(1) << FPU_CSR_COND7_S)
768
769/*
770 * Bits 22:20 of the FPU Status Register will be read as 0,
771 * and should be written as zero.
772 */
773#define FPU_CSR_RSVD (_ULCAST_(7) << 20)
774
775#define FPU_CSR_ABS2008 (_ULCAST_(1) << 19)
776#define FPU_CSR_NAN2008 (_ULCAST_(1) << 18)
777
778/*
779 * X the exception cause indicator
780 * E the exception enable
781 * S the sticky/flag bit
782*/
783#define FPU_CSR_ALL_X 0x0003f000
784#define FPU_CSR_UNI_X 0x00020000
785#define FPU_CSR_INV_X 0x00010000
786#define FPU_CSR_DIV_X 0x00008000
787#define FPU_CSR_OVF_X 0x00004000
788#define FPU_CSR_UDF_X 0x00002000
789#define FPU_CSR_INE_X 0x00001000
790
791#define FPU_CSR_ALL_E 0x00000f80
792#define FPU_CSR_INV_E 0x00000800
793#define FPU_CSR_DIV_E 0x00000400
794#define FPU_CSR_OVF_E 0x00000200
795#define FPU_CSR_UDF_E 0x00000100
796#define FPU_CSR_INE_E 0x00000080
797
798#define FPU_CSR_ALL_S 0x0000007c
799#define FPU_CSR_INV_S 0x00000040
800#define FPU_CSR_DIV_S 0x00000020
801#define FPU_CSR_OVF_S 0x00000010
802#define FPU_CSR_UDF_S 0x00000008
803#define FPU_CSR_INE_S 0x00000004
804
805/* Bits 0 and 1 of FPU Status Register specify the rounding mode */
806#define FPU_CSR_RM 0x00000003
807#define FPU_CSR_RN 0x0 /* nearest */
808#define FPU_CSR_RZ 0x1 /* towards zero */
809#define FPU_CSR_RU 0x2 /* towards +Infinity */
810#define FPU_CSR_RD 0x3 /* towards -Infinity */
811
812
754#ifndef __ASSEMBLY__ 813#ifndef __ASSEMBLY__
755 814
756/* 815/*
@@ -1282,6 +1341,9 @@ do { \
1282#define read_c0_ebase() __read_32bit_c0_register($15, 1) 1341#define read_c0_ebase() __read_32bit_c0_register($15, 1)
1283#define write_c0_ebase(val) __write_32bit_c0_register($15, 1, val) 1342#define write_c0_ebase(val) __write_32bit_c0_register($15, 1, val)
1284 1343
1344#define read_c0_cdmmbase() __read_ulong_c0_register($15, 2)
1345#define write_c0_cdmmbase(val) __write_ulong_c0_register($15, 2, val)
1346
1285/* MIPSR3 */ 1347/* MIPSR3 */
1286#define read_c0_segctl0() __read_32bit_c0_register($5, 2) 1348#define read_c0_segctl0() __read_32bit_c0_register($5, 2)
1287#define write_c0_segctl0(val) __write_32bit_c0_register($5, 2, val) 1349#define write_c0_segctl0(val) __write_32bit_c0_register($5, 2, val)
diff --git a/arch/mips/include/asm/netlogic/common.h b/arch/mips/include/asm/netlogic/common.h
index c281f03eb312..2a4c128277e4 100644
--- a/arch/mips/include/asm/netlogic/common.h
+++ b/arch/mips/include/asm/netlogic/common.h
@@ -111,6 +111,25 @@ static inline int nlm_irq_to_xirq(int node, int irq)
111 return node * NR_IRQS / NLM_NR_NODES + irq; 111 return node * NR_IRQS / NLM_NR_NODES + irq;
112} 112}
113 113
114extern int nlm_cpu_ready[]; 114#ifdef CONFIG_CPU_XLR
115#define nlm_cores_per_node() 8
116#else
117static inline int nlm_cores_per_node(void)
118{
119 return ((read_c0_prid() & PRID_IMP_MASK)
120 == PRID_IMP_NETLOGIC_XLP9XX) ? 32 : 8;
121}
115#endif 122#endif
123static inline int nlm_threads_per_node(void)
124{
125 return nlm_cores_per_node() * NLM_THREADS_PER_CORE;
126}
127
128static inline int nlm_hwtid_to_node(int hwtid)
129{
130 return hwtid / nlm_threads_per_node();
131}
132
133extern int nlm_cpu_ready[];
134#endif /* __ASSEMBLY__ */
116#endif /* _NETLOGIC_COMMON_H_ */ 135#endif /* _NETLOGIC_COMMON_H_ */
diff --git a/arch/mips/include/asm/netlogic/mips-extns.h b/arch/mips/include/asm/netlogic/mips-extns.h
index 06f1f75bfa9b..788baf399e69 100644
--- a/arch/mips/include/asm/netlogic/mips-extns.h
+++ b/arch/mips/include/asm/netlogic/mips-extns.h
@@ -157,7 +157,13 @@ static inline int nlm_nodeid(void)
157 157
158static inline unsigned int nlm_core_id(void) 158static inline unsigned int nlm_core_id(void)
159{ 159{
160 return (read_c0_ebase() & 0x1c) >> 2; 160 uint32_t prid = read_c0_prid() & PRID_IMP_MASK;
161
162 if ((prid == PRID_IMP_NETLOGIC_XLP9XX) ||
163 (prid == PRID_IMP_NETLOGIC_XLP5XX))
164 return (read_c0_ebase() & 0x7c) >> 2;
165 else
166 return (read_c0_ebase() & 0x1c) >> 2;
161} 167}
162 168
163static inline unsigned int nlm_thread_id(void) 169static inline unsigned int nlm_thread_id(void)
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/cpucontrol.h b/arch/mips/include/asm/netlogic/xlp-hal/cpucontrol.h
index 6d2e58a9a542..a06b59292153 100644
--- a/arch/mips/include/asm/netlogic/xlp-hal/cpucontrol.h
+++ b/arch/mips/include/asm/netlogic/xlp-hal/cpucontrol.h
@@ -46,6 +46,8 @@
46#define CPU_BLOCKID_FPU 9 46#define CPU_BLOCKID_FPU 9
47#define CPU_BLOCKID_MAP 10 47#define CPU_BLOCKID_MAP 10
48 48
49#define IFU_BRUB_RESERVE 0x007
50
49#define ICU_DEFEATURE 0x100 51#define ICU_DEFEATURE 0x100
50 52
51#define LSU_DEFEATURE 0x304 53#define LSU_DEFEATURE 0x304
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/sys.h b/arch/mips/include/asm/netlogic/xlp-hal/sys.h
index bc7bddf25be9..6bcf3952e556 100644
--- a/arch/mips/include/asm/netlogic/xlp-hal/sys.h
+++ b/arch/mips/include/asm/netlogic/xlp-hal/sys.h
@@ -177,6 +177,9 @@
177#define SYS_9XX_CLK_DEV_DIV 0x18d 177#define SYS_9XX_CLK_DEV_DIV 0x18d
178#define SYS_9XX_CLK_DEV_CHG 0x18f 178#define SYS_9XX_CLK_DEV_CHG 0x18f
179 179
180#define SYS_9XX_CLK_DEV_SEL_REG 0x1a4
181#define SYS_9XX_CLK_DEV_DIV_REG 0x1a6
182
180/* Registers changed on 9XX */ 183/* Registers changed on 9XX */
181#define SYS_9XX_POWER_ON_RESET_CFG 0x00 184#define SYS_9XX_POWER_ON_RESET_CFG 0x00
182#define SYS_9XX_CHIP_RESET 0x01 185#define SYS_9XX_CHIP_RESET 0x01
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/xlp.h b/arch/mips/include/asm/netlogic/xlp-hal/xlp.h
index a862b93223cc..feb6ed807ec6 100644
--- a/arch/mips/include/asm/netlogic/xlp-hal/xlp.h
+++ b/arch/mips/include/asm/netlogic/xlp-hal/xlp.h
@@ -52,6 +52,7 @@
52#define PIC_2XX_XHCI_2_IRQ 25 52#define PIC_2XX_XHCI_2_IRQ 25
53#define PIC_9XX_XHCI_0_IRQ 23 53#define PIC_9XX_XHCI_0_IRQ 23
54#define PIC_9XX_XHCI_1_IRQ 24 54#define PIC_9XX_XHCI_1_IRQ 24
55#define PIC_9XX_XHCI_2_IRQ 25
55 56
56#define PIC_MMC_IRQ 29 57#define PIC_MMC_IRQ 29
57#define PIC_I2C_0_IRQ 30 58#define PIC_I2C_0_IRQ 30
@@ -89,7 +90,7 @@ void xlp_wakeup_secondary_cpus(void);
89 90
90void xlp_mmu_init(void); 91void xlp_mmu_init(void);
91void nlm_hal_init(void); 92void nlm_hal_init(void);
92int xlp_get_dram_map(int n, uint64_t *dram_map); 93int nlm_get_dram_map(int node, uint64_t *dram_map, int nentries);
93 94
94struct pci_dev; 95struct pci_dev;
95int xlp_socdev_to_node(const struct pci_dev *dev); 96int xlp_socdev_to_node(const struct pci_dev *dev);
diff --git a/arch/mips/include/asm/octeon/cvmx-address.h b/arch/mips/include/asm/octeon/cvmx-address.h
index e2d874e681f6..e4444f8c4a61 100644
--- a/arch/mips/include/asm/octeon/cvmx-address.h
+++ b/arch/mips/include/asm/octeon/cvmx-address.h
@@ -104,6 +104,7 @@ typedef enum {
104typedef union { 104typedef union {
105 105
106 uint64_t u64; 106 uint64_t u64;
107#ifdef __BIG_ENDIAN_BITFIELD
107 /* mapped or unmapped virtual address */ 108 /* mapped or unmapped virtual address */
108 struct { 109 struct {
109 uint64_t R:2; 110 uint64_t R:2;
@@ -202,6 +203,72 @@ typedef union {
202 uint64_t didspace:24; 203 uint64_t didspace:24;
203 uint64_t unused:40; 204 uint64_t unused:40;
204 } sfilldidspace; 205 } sfilldidspace;
206#else
207 struct {
208 uint64_t offset:62;
209 uint64_t R:2;
210 } sva;
211
212 struct {
213 uint64_t offset:31;
214 uint64_t zeroes:33;
215 } suseg;
216
217 struct {
218 uint64_t offset:29;
219 uint64_t sp:2;
220 uint64_t ones:33;
221 } sxkseg;
222
223 struct {
224 uint64_t pa:49;
225 uint64_t mbz:10;
226 uint64_t cca:3;
227 uint64_t R:2;
228 } sxkphys;
229
230 struct {
231 uint64_t offset:36;
232 uint64_t unaddr:4;
233 uint64_t did:8;
234 uint64_t is_io:1;
235 uint64_t mbz:15;
236 } sphys;
237
238 struct {
239 uint64_t offset:36;
240 uint64_t unaddr:4;
241 uint64_t zeroes:24;
242 } smem;
243
244 struct {
245 uint64_t offset:36;
246 uint64_t unaddr:4;
247 uint64_t did:8;
248 uint64_t is_io:1;
249 uint64_t mbz:13;
250 uint64_t mem_region:2;
251 } sio;
252
253 struct {
254 uint64_t addr:13;
255 cvmx_add_win_dec_t csrdec:2;
256 uint64_t ones:49;
257 } sscr;
258
259 struct {
260 uint64_t addr:7;
261 uint64_t type:3;
262 uint64_t unused2:3;
263 uint64_t csrdec:2;
264 uint64_t ones:49;
265 } sdma;
266
267 struct {
268 uint64_t unused:40;
269 uint64_t didspace:24;
270 } sfilldidspace;
271#endif
205 272
206} cvmx_addr_t; 273} cvmx_addr_t;
207 274
diff --git a/arch/mips/include/asm/octeon/cvmx-bootinfo.h b/arch/mips/include/asm/octeon/cvmx-bootinfo.h
index 2298199a287e..c373d95b5e2c 100644
--- a/arch/mips/include/asm/octeon/cvmx-bootinfo.h
+++ b/arch/mips/include/asm/octeon/cvmx-bootinfo.h
@@ -53,6 +53,7 @@
53 * to 0. 53 * to 0.
54 */ 54 */
55struct cvmx_bootinfo { 55struct cvmx_bootinfo {
56#ifdef __BIG_ENDIAN_BITFIELD
56 uint32_t major_version; 57 uint32_t major_version;
57 uint32_t minor_version; 58 uint32_t minor_version;
58 59
@@ -123,6 +124,60 @@ struct cvmx_bootinfo {
123 */ 124 */
124 uint64_t fdt_addr; 125 uint64_t fdt_addr;
125#endif 126#endif
127#else /* __BIG_ENDIAN */
128 /*
129 * Little-Endian: When the CPU mode is switched to
130 * little-endian, the view of the structure has some of the
131 * fields swapped.
132 */
133 uint32_t minor_version;
134 uint32_t major_version;
135
136 uint64_t stack_top;
137 uint64_t heap_base;
138 uint64_t heap_end;
139 uint64_t desc_vaddr;
140
141 uint32_t stack_size;
142 uint32_t exception_base_addr;
143
144 uint32_t core_mask;
145 uint32_t flags;
146
147 uint32_t phy_mem_desc_addr;
148 uint32_t dram_size;
149
150 uint32_t eclock_hz;
151 uint32_t debugger_flags_base_addr;
152
153 uint32_t reserved0;
154 uint32_t dclock_hz;
155
156 uint8_t reserved3;
157 uint8_t reserved2;
158 uint16_t reserved1;
159 uint8_t board_rev_minor;
160 uint8_t board_rev_major;
161 uint16_t board_type;
162
163 char board_serial_number[CVMX_BOOTINFO_OCTEON_SERIAL_LEN];
164 uint8_t mac_addr_base[6];
165 uint8_t mac_addr_count;
166 uint8_t pad[5];
167
168#if (CVMX_BOOTINFO_MIN_VER >= 1)
169 uint64_t compact_flash_common_base_addr;
170 uint64_t compact_flash_attribute_base_addr;
171 uint64_t led_display_base_addr;
172#endif
173#if (CVMX_BOOTINFO_MIN_VER >= 2)
174 uint32_t config_flags;
175 uint32_t dfa_ref_clock_hz;
176#endif
177#if (CVMX_BOOTINFO_MIN_VER >= 3)
178 uint64_t fdt_addr;
179#endif
180#endif
126}; 181};
127 182
128#define CVMX_BOOTINFO_CFG_FLAG_PCI_HOST (1ull << 0) 183#define CVMX_BOOTINFO_CFG_FLAG_PCI_HOST (1ull << 0)
diff --git a/arch/mips/include/asm/octeon/cvmx-bootmem.h b/arch/mips/include/asm/octeon/cvmx-bootmem.h
index 352f1dc2508b..374562507d0b 100644
--- a/arch/mips/include/asm/octeon/cvmx-bootmem.h
+++ b/arch/mips/include/asm/octeon/cvmx-bootmem.h
@@ -95,6 +95,7 @@ struct cvmx_bootmem_named_block_desc {
95 * positions for backwards compatibility. 95 * positions for backwards compatibility.
96 */ 96 */
97struct cvmx_bootmem_desc { 97struct cvmx_bootmem_desc {
98#if defined(__BIG_ENDIAN_BITFIELD) || defined(CVMX_BUILD_FOR_LINUX_HOST)
98 /* spinlock to control access to list */ 99 /* spinlock to control access to list */
99 uint32_t lock; 100 uint32_t lock;
100 /* flags for indicating various conditions */ 101 /* flags for indicating various conditions */
@@ -120,7 +121,20 @@ struct cvmx_bootmem_desc {
120 uint32_t named_block_name_len; 121 uint32_t named_block_name_len;
121 /* address of named memory block descriptors */ 122 /* address of named memory block descriptors */
122 uint64_t named_block_array_addr; 123 uint64_t named_block_array_addr;
124#else /* __LITTLE_ENDIAN */
125 uint32_t flags;
126 uint32_t lock;
127 uint64_t head_addr;
123 128
129 uint32_t minor_version;
130 uint32_t major_version;
131 uint64_t app_data_addr;
132 uint64_t app_data_size;
133
134 uint32_t named_block_name_len;
135 uint32_t named_block_num_blocks;
136 uint64_t named_block_array_addr;
137#endif
124}; 138};
125 139
126/** 140/**
diff --git a/arch/mips/include/asm/octeon/cvmx-fau.h b/arch/mips/include/asm/octeon/cvmx-fau.h
index ef98f7fc102f..dafeae300c97 100644
--- a/arch/mips/include/asm/octeon/cvmx-fau.h
+++ b/arch/mips/include/asm/octeon/cvmx-fau.h
@@ -105,6 +105,16 @@ typedef union {
105 } s; 105 } s;
106} cvmx_fau_async_tagwait_result_t; 106} cvmx_fau_async_tagwait_result_t;
107 107
108#ifdef __BIG_ENDIAN_BITFIELD
109#define SWIZZLE_8 0
110#define SWIZZLE_16 0
111#define SWIZZLE_32 0
112#else
113#define SWIZZLE_8 0x7
114#define SWIZZLE_16 0x6
115#define SWIZZLE_32 0x4
116#endif
117
108/** 118/**
109 * Builds a store I/O address for writing to the FAU 119 * Builds a store I/O address for writing to the FAU
110 * 120 *
@@ -175,6 +185,7 @@ static inline int64_t cvmx_fau_fetch_and_add64(cvmx_fau_reg_64_t reg,
175static inline int32_t cvmx_fau_fetch_and_add32(cvmx_fau_reg_32_t reg, 185static inline int32_t cvmx_fau_fetch_and_add32(cvmx_fau_reg_32_t reg,
176 int32_t value) 186 int32_t value)
177{ 187{
188 reg ^= SWIZZLE_32;
178 return cvmx_read64_int32(__cvmx_fau_atomic_address(0, reg, value)); 189 return cvmx_read64_int32(__cvmx_fau_atomic_address(0, reg, value));
179} 190}
180 191
@@ -189,6 +200,7 @@ static inline int32_t cvmx_fau_fetch_and_add32(cvmx_fau_reg_32_t reg,
189static inline int16_t cvmx_fau_fetch_and_add16(cvmx_fau_reg_16_t reg, 200static inline int16_t cvmx_fau_fetch_and_add16(cvmx_fau_reg_16_t reg,
190 int16_t value) 201 int16_t value)
191{ 202{
203 reg ^= SWIZZLE_16;
192 return cvmx_read64_int16(__cvmx_fau_atomic_address(0, reg, value)); 204 return cvmx_read64_int16(__cvmx_fau_atomic_address(0, reg, value));
193} 205}
194 206
@@ -201,6 +213,7 @@ static inline int16_t cvmx_fau_fetch_and_add16(cvmx_fau_reg_16_t reg,
201 */ 213 */
202static inline int8_t cvmx_fau_fetch_and_add8(cvmx_fau_reg_8_t reg, int8_t value) 214static inline int8_t cvmx_fau_fetch_and_add8(cvmx_fau_reg_8_t reg, int8_t value)
203{ 215{
216 reg ^= SWIZZLE_8;
204 return cvmx_read64_int8(__cvmx_fau_atomic_address(0, reg, value)); 217 return cvmx_read64_int8(__cvmx_fau_atomic_address(0, reg, value));
205} 218}
206 219
@@ -247,6 +260,7 @@ cvmx_fau_tagwait_fetch_and_add32(cvmx_fau_reg_32_t reg, int32_t value)
247 uint64_t i32; 260 uint64_t i32;
248 cvmx_fau_tagwait32_t t; 261 cvmx_fau_tagwait32_t t;
249 } result; 262 } result;
263 reg ^= SWIZZLE_32;
250 result.i32 = 264 result.i32 =
251 cvmx_read64_int32(__cvmx_fau_atomic_address(1, reg, value)); 265 cvmx_read64_int32(__cvmx_fau_atomic_address(1, reg, value));
252 return result.t; 266 return result.t;
@@ -270,6 +284,7 @@ cvmx_fau_tagwait_fetch_and_add16(cvmx_fau_reg_16_t reg, int16_t value)
270 uint64_t i16; 284 uint64_t i16;
271 cvmx_fau_tagwait16_t t; 285 cvmx_fau_tagwait16_t t;
272 } result; 286 } result;
287 reg ^= SWIZZLE_16;
273 result.i16 = 288 result.i16 =
274 cvmx_read64_int16(__cvmx_fau_atomic_address(1, reg, value)); 289 cvmx_read64_int16(__cvmx_fau_atomic_address(1, reg, value));
275 return result.t; 290 return result.t;
@@ -292,6 +307,7 @@ cvmx_fau_tagwait_fetch_and_add8(cvmx_fau_reg_8_t reg, int8_t value)
292 uint64_t i8; 307 uint64_t i8;
293 cvmx_fau_tagwait8_t t; 308 cvmx_fau_tagwait8_t t;
294 } result; 309 } result;
310 reg ^= SWIZZLE_8;
295 result.i8 = cvmx_read64_int8(__cvmx_fau_atomic_address(1, reg, value)); 311 result.i8 = cvmx_read64_int8(__cvmx_fau_atomic_address(1, reg, value));
296 return result.t; 312 return result.t;
297} 313}
@@ -521,6 +537,7 @@ static inline void cvmx_fau_atomic_add64(cvmx_fau_reg_64_t reg, int64_t value)
521 */ 537 */
522static inline void cvmx_fau_atomic_add32(cvmx_fau_reg_32_t reg, int32_t value) 538static inline void cvmx_fau_atomic_add32(cvmx_fau_reg_32_t reg, int32_t value)
523{ 539{
540 reg ^= SWIZZLE_32;
524 cvmx_write64_int32(__cvmx_fau_store_address(0, reg), value); 541 cvmx_write64_int32(__cvmx_fau_store_address(0, reg), value);
525} 542}
526 543
@@ -533,6 +550,7 @@ static inline void cvmx_fau_atomic_add32(cvmx_fau_reg_32_t reg, int32_t value)
533 */ 550 */
534static inline void cvmx_fau_atomic_add16(cvmx_fau_reg_16_t reg, int16_t value) 551static inline void cvmx_fau_atomic_add16(cvmx_fau_reg_16_t reg, int16_t value)
535{ 552{
553 reg ^= SWIZZLE_16;
536 cvmx_write64_int16(__cvmx_fau_store_address(0, reg), value); 554 cvmx_write64_int16(__cvmx_fau_store_address(0, reg), value);
537} 555}
538 556
@@ -544,6 +562,7 @@ static inline void cvmx_fau_atomic_add16(cvmx_fau_reg_16_t reg, int16_t value)
544 */ 562 */
545static inline void cvmx_fau_atomic_add8(cvmx_fau_reg_8_t reg, int8_t value) 563static inline void cvmx_fau_atomic_add8(cvmx_fau_reg_8_t reg, int8_t value)
546{ 564{
565 reg ^= SWIZZLE_8;
547 cvmx_write64_int8(__cvmx_fau_store_address(0, reg), value); 566 cvmx_write64_int8(__cvmx_fau_store_address(0, reg), value);
548} 567}
549 568
@@ -568,6 +587,7 @@ static inline void cvmx_fau_atomic_write64(cvmx_fau_reg_64_t reg, int64_t value)
568 */ 587 */
569static inline void cvmx_fau_atomic_write32(cvmx_fau_reg_32_t reg, int32_t value) 588static inline void cvmx_fau_atomic_write32(cvmx_fau_reg_32_t reg, int32_t value)
570{ 589{
590 reg ^= SWIZZLE_32;
571 cvmx_write64_int32(__cvmx_fau_store_address(1, reg), value); 591 cvmx_write64_int32(__cvmx_fau_store_address(1, reg), value);
572} 592}
573 593
@@ -580,6 +600,7 @@ static inline void cvmx_fau_atomic_write32(cvmx_fau_reg_32_t reg, int32_t value)
580 */ 600 */
581static inline void cvmx_fau_atomic_write16(cvmx_fau_reg_16_t reg, int16_t value) 601static inline void cvmx_fau_atomic_write16(cvmx_fau_reg_16_t reg, int16_t value)
582{ 602{
603 reg ^= SWIZZLE_16;
583 cvmx_write64_int16(__cvmx_fau_store_address(1, reg), value); 604 cvmx_write64_int16(__cvmx_fau_store_address(1, reg), value);
584} 605}
585 606
@@ -591,6 +612,7 @@ static inline void cvmx_fau_atomic_write16(cvmx_fau_reg_16_t reg, int16_t value)
591 */ 612 */
592static inline void cvmx_fau_atomic_write8(cvmx_fau_reg_8_t reg, int8_t value) 613static inline void cvmx_fau_atomic_write8(cvmx_fau_reg_8_t reg, int8_t value)
593{ 614{
615 reg ^= SWIZZLE_8;
594 cvmx_write64_int8(__cvmx_fau_store_address(1, reg), value); 616 cvmx_write64_int8(__cvmx_fau_store_address(1, reg), value);
595} 617}
596 618
diff --git a/arch/mips/include/asm/octeon/cvmx-fpa.h b/arch/mips/include/asm/octeon/cvmx-fpa.h
index aa26a2ce5a0e..c00501d0f7ae 100644
--- a/arch/mips/include/asm/octeon/cvmx-fpa.h
+++ b/arch/mips/include/asm/octeon/cvmx-fpa.h
@@ -49,6 +49,7 @@
49typedef union { 49typedef union {
50 uint64_t u64; 50 uint64_t u64;
51 struct { 51 struct {
52#ifdef __BIG_ENDIAN_BITFIELD
52 /* 53 /*
53 * the (64-bit word) location in scratchpad to write 54 * the (64-bit word) location in scratchpad to write
54 * to (if len != 0) 55 * to (if len != 0)
@@ -63,6 +64,12 @@ typedef union {
63 * the NCB bus. 64 * the NCB bus.
64 */ 65 */
65 uint64_t addr:40; 66 uint64_t addr:40;
67#else
68 uint64_t addr:40;
69 uint64_t did:8;
70 uint64_t len:8;
71 uint64_t scraddr:8;
72#endif
66 } s; 73 } s;
67} cvmx_fpa_iobdma_data_t; 74} cvmx_fpa_iobdma_data_t;
68 75
diff --git a/arch/mips/include/asm/octeon/cvmx-l2c.h b/arch/mips/include/asm/octeon/cvmx-l2c.h
index 11c0a8fa8eb5..ddb429210a0e 100644
--- a/arch/mips/include/asm/octeon/cvmx-l2c.h
+++ b/arch/mips/include/asm/octeon/cvmx-l2c.h
@@ -53,12 +53,21 @@
53union cvmx_l2c_tag { 53union cvmx_l2c_tag {
54 uint64_t u64; 54 uint64_t u64;
55 struct { 55 struct {
56#ifdef __BIG_ENDIAN_BITFIELD
56 uint64_t reserved:28; 57 uint64_t reserved:28;
57 uint64_t V:1; /* Line valid */ 58 uint64_t V:1; /* Line valid */
58 uint64_t D:1; /* Line dirty */ 59 uint64_t D:1; /* Line dirty */
59 uint64_t L:1; /* Line locked */ 60 uint64_t L:1; /* Line locked */
60 uint64_t U:1; /* Use, LRU eviction */ 61 uint64_t U:1; /* Use, LRU eviction */
61 uint64_t addr:32; /* Phys mem (not all bits valid) */ 62 uint64_t addr:32; /* Phys mem (not all bits valid) */
63#else
64 uint64_t addr:32; /* Phys mem (not all bits valid) */
65 uint64_t U:1; /* Use, LRU eviction */
66 uint64_t L:1; /* Line locked */
67 uint64_t D:1; /* Line dirty */
68 uint64_t V:1; /* Line valid */
69 uint64_t reserved:28;
70#endif
62 } s; 71 } s;
63}; 72};
64 73
diff --git a/arch/mips/include/asm/octeon/cvmx-packet.h b/arch/mips/include/asm/octeon/cvmx-packet.h
index 38aefa1bab9d..895e93d682c2 100644
--- a/arch/mips/include/asm/octeon/cvmx-packet.h
+++ b/arch/mips/include/asm/octeon/cvmx-packet.h
@@ -39,6 +39,7 @@ union cvmx_buf_ptr {
39 void *ptr; 39 void *ptr;
40 uint64_t u64; 40 uint64_t u64;
41 struct { 41 struct {
42#ifdef __BIG_ENDIAN_BITFIELD
42 /* if set, invert the "free" pick of the overall 43 /* if set, invert the "free" pick of the overall
43 * packet. HW always sets this bit to 0 on inbound 44 * packet. HW always sets this bit to 0 on inbound
44 * packet */ 45 * packet */
@@ -55,6 +56,13 @@ union cvmx_buf_ptr {
55 uint64_t size:16; 56 uint64_t size:16;
56 /* Pointer to the first byte of the data, NOT buffer */ 57 /* Pointer to the first byte of the data, NOT buffer */
57 uint64_t addr:40; 58 uint64_t addr:40;
59#else
60 uint64_t addr:40;
61 uint64_t size:16;
62 uint64_t pool:3;
63 uint64_t back:4;
64 uint64_t i:1;
65#endif
58 } s; 66 } s;
59}; 67};
60 68
diff --git a/arch/mips/include/asm/octeon/cvmx-pko.h b/arch/mips/include/asm/octeon/cvmx-pko.h
index f7d2a6718849..3da59bb8ce24 100644
--- a/arch/mips/include/asm/octeon/cvmx-pko.h
+++ b/arch/mips/include/asm/octeon/cvmx-pko.h
@@ -127,6 +127,7 @@ typedef struct {
127typedef union { 127typedef union {
128 uint64_t u64; 128 uint64_t u64;
129 struct { 129 struct {
130#ifdef __BIG_ENDIAN_BITFIELD
130 /* Must CVMX_IO_SEG */ 131 /* Must CVMX_IO_SEG */
131 uint64_t mem_space:2; 132 uint64_t mem_space:2;
132 /* Must be zero */ 133 /* Must be zero */
@@ -151,6 +152,17 @@ typedef union {
151 uint64_t queue:9; 152 uint64_t queue:9;
152 /* Must be zero */ 153 /* Must be zero */
153 uint64_t reserved4:3; 154 uint64_t reserved4:3;
155#else
156 uint64_t reserved4:3;
157 uint64_t queue:9;
158 uint64_t port:9;
159 uint64_t reserved3:15;
160 uint64_t reserved2:4;
161 uint64_t did:8;
162 uint64_t is_io:1;
163 uint64_t reserved:13;
164 uint64_t mem_space:2;
165#endif
154 } s; 166 } s;
155} cvmx_pko_doorbell_address_t; 167} cvmx_pko_doorbell_address_t;
156 168
@@ -160,6 +172,7 @@ typedef union {
160typedef union { 172typedef union {
161 uint64_t u64; 173 uint64_t u64;
162 struct { 174 struct {
175#ifdef __BIG_ENDIAN_BITFIELD
163 /* 176 /*
164 * The size of the reg1 operation - could be 8, 16, 177 * The size of the reg1 operation - could be 8, 16,
165 * 32, or 64 bits. 178 * 32, or 64 bits.
@@ -229,6 +242,24 @@ typedef union {
229 uint64_t segs:6; 242 uint64_t segs:6;
230 /* Including L2, but no trailing CRC */ 243 /* Including L2, but no trailing CRC */
231 uint64_t total_bytes:16; 244 uint64_t total_bytes:16;
245#else
246 uint64_t total_bytes:16;
247 uint64_t segs:6;
248 uint64_t dontfree:1;
249 uint64_t ignore_i:1;
250 uint64_t ipoffp1:7;
251 uint64_t gather:1;
252 uint64_t rsp:1;
253 uint64_t wqp:1;
254 uint64_t n2:1;
255 uint64_t le:1;
256 uint64_t reg0:11;
257 uint64_t subone0:1;
258 uint64_t reg1:11;
259 uint64_t subone1:1;
260 uint64_t size0:2;
261 uint64_t size1:2;
262#endif
232 } s; 263 } s;
233} cvmx_pko_command_word0_t; 264} cvmx_pko_command_word0_t;
234 265
diff --git a/arch/mips/include/asm/octeon/cvmx-pow.h b/arch/mips/include/asm/octeon/cvmx-pow.h
index 2188e65afb86..d5565d758ddd 100644
--- a/arch/mips/include/asm/octeon/cvmx-pow.h
+++ b/arch/mips/include/asm/octeon/cvmx-pow.h
@@ -178,6 +178,7 @@ typedef enum {
178typedef union { 178typedef union {
179 uint64_t u64; 179 uint64_t u64;
180 struct { 180 struct {
181#ifdef __BIG_ENDIAN_BITFIELD
181 /* 182 /*
182 * Don't reschedule this entry. no_sched is used for 183 * Don't reschedule this entry. no_sched is used for
183 * CVMX_POW_TAG_OP_SWTAG_DESCH and 184 * CVMX_POW_TAG_OP_SWTAG_DESCH and
@@ -217,6 +218,17 @@ typedef union {
217 * CVMX_POW_TAG_OP_*_NSCHED 218 * CVMX_POW_TAG_OP_*_NSCHED
218 */ 219 */
219 uint64_t tag:32; 220 uint64_t tag:32;
221#else
222 uint64_t tag:32;
223 uint64_t type:3;
224 uint64_t grp:4;
225 uint64_t qos:3;
226 uint64_t unused2:2;
227 cvmx_pow_tag_op_t op:4;
228 uint64_t index:13;
229 uint64_t unused:2;
230 uint64_t no_sched:1;
231#endif
220 } s; 232 } s;
221} cvmx_pow_tag_req_t; 233} cvmx_pow_tag_req_t;
222 234
@@ -230,6 +242,7 @@ typedef union {
230 * Address for new work request loads (did<2:0> == 0) 242 * Address for new work request loads (did<2:0> == 0)
231 */ 243 */
232 struct { 244 struct {
245#ifdef __BIG_ENDIAN_BITFIELD
233 /* Mips64 address region. Should be CVMX_IO_SEG */ 246 /* Mips64 address region. Should be CVMX_IO_SEG */
234 uint64_t mem_region:2; 247 uint64_t mem_region:2;
235 /* Must be zero */ 248 /* Must be zero */
@@ -247,12 +260,22 @@ typedef union {
247 uint64_t wait:1; 260 uint64_t wait:1;
248 /* Must be zero */ 261 /* Must be zero */
249 uint64_t reserved_0_2:3; 262 uint64_t reserved_0_2:3;
263#else
264 uint64_t reserved_0_2:3;
265 uint64_t wait:1;
266 uint64_t reserved_4_39:36;
267 uint64_t did:8;
268 uint64_t is_io:1;
269 uint64_t reserved_49_61:13;
270 uint64_t mem_region:2;
271#endif
250 } swork; 272 } swork;
251 273
252 /** 274 /**
253 * Address for loads to get POW internal status 275 * Address for loads to get POW internal status
254 */ 276 */
255 struct { 277 struct {
278#ifdef __BIG_ENDIAN_BITFIELD
256 /* Mips64 address region. Should be CVMX_IO_SEG */ 279 /* Mips64 address region. Should be CVMX_IO_SEG */
257 uint64_t mem_region:2; 280 uint64_t mem_region:2;
258 /* Must be zero */ 281 /* Must be zero */
@@ -282,12 +305,25 @@ typedef union {
282 uint64_t get_wqp:1; 305 uint64_t get_wqp:1;
283 /* Must be zero */ 306 /* Must be zero */
284 uint64_t reserved_0_2:3; 307 uint64_t reserved_0_2:3;
308#else
309 uint64_t reserved_0_2:3;
310 uint64_t get_wqp:1;
311 uint64_t get_cur:1;
312 uint64_t get_rev:1;
313 uint64_t coreid:4;
314 uint64_t reserved_10_39:30;
315 uint64_t did:8;
316 uint64_t is_io:1;
317 uint64_t reserved_49_61:13;
318 uint64_t mem_region:2;
319#endif
285 } sstatus; 320 } sstatus;
286 321
287 /** 322 /**
288 * Address for memory loads to get POW internal state 323 * Address for memory loads to get POW internal state
289 */ 324 */
290 struct { 325 struct {
326#ifdef __BIG_ENDIAN_BITFIELD
291 /* Mips64 address region. Should be CVMX_IO_SEG */ 327 /* Mips64 address region. Should be CVMX_IO_SEG */
292 uint64_t mem_region:2; 328 uint64_t mem_region:2;
293 /* Must be zero */ 329 /* Must be zero */
@@ -314,12 +350,24 @@ typedef union {
314 uint64_t get_wqp:1; 350 uint64_t get_wqp:1;
315 /* Must be zero */ 351 /* Must be zero */
316 uint64_t reserved_0_2:3; 352 uint64_t reserved_0_2:3;
353#else
354 uint64_t reserved_0_2:3;
355 uint64_t get_wqp:1;
356 uint64_t get_des:1;
357 uint64_t index:11;
358 uint64_t reserved_16_39:24;
359 uint64_t did:8;
360 uint64_t is_io:1;
361 uint64_t reserved_49_61:13;
362 uint64_t mem_region:2;
363#endif
317 } smemload; 364 } smemload;
318 365
319 /** 366 /**
320 * Address for index/pointer loads 367 * Address for index/pointer loads
321 */ 368 */
322 struct { 369 struct {
370#ifdef __BIG_ENDIAN_BITFIELD
323 /* Mips64 address region. Should be CVMX_IO_SEG */ 371 /* Mips64 address region. Should be CVMX_IO_SEG */
324 uint64_t mem_region:2; 372 uint64_t mem_region:2;
325 /* Must be zero */ 373 /* Must be zero */
@@ -366,6 +414,17 @@ typedef union {
366 uint64_t get_rmt:1; 414 uint64_t get_rmt:1;
367 /* Must be zero */ 415 /* Must be zero */
368 uint64_t reserved_0_2:3; 416 uint64_t reserved_0_2:3;
417#else
418 uint64_t reserved_0_2:3;
419 uint64_t get_rmt:1;
420 uint64_t get_des_get_tail:1;
421 uint64_t qosgrp:4;
422 uint64_t reserved_9_39:31;
423 uint64_t did:8;
424 uint64_t is_io:1;
425 uint64_t reserved_49_61:13;
426 uint64_t mem_region:2;
427#endif
369 } sindexload; 428 } sindexload;
370 429
371 /** 430 /**
@@ -377,6 +436,7 @@ typedef union {
377 * available.) 436 * available.)
378 */ 437 */
379 struct { 438 struct {
439#ifdef __BIG_ENDIAN_BITFIELD
380 /* Mips64 address region. Should be CVMX_IO_SEG */ 440 /* Mips64 address region. Should be CVMX_IO_SEG */
381 uint64_t mem_region:2; 441 uint64_t mem_region:2;
382 /* Must be zero */ 442 /* Must be zero */
@@ -387,6 +447,13 @@ typedef union {
387 uint64_t did:8; 447 uint64_t did:8;
388 /* Must be zero */ 448 /* Must be zero */
389 uint64_t reserved_0_39:40; 449 uint64_t reserved_0_39:40;
450#else
451 uint64_t reserved_0_39:40;
452 uint64_t did:8;
453 uint64_t is_io:1;
454 uint64_t reserved_49_61:13;
455 uint64_t mem_region:2;
456#endif
390 } snull_rd; 457 } snull_rd;
391} cvmx_pow_load_addr_t; 458} cvmx_pow_load_addr_t;
392 459
@@ -401,6 +468,7 @@ typedef union {
401 * Response to new work request loads 468 * Response to new work request loads
402 */ 469 */
403 struct { 470 struct {
471#ifdef __BIG_ENDIAN_BITFIELD
404 /* 472 /*
405 * Set when no new work queue entry was returned. * 473 * Set when no new work queue entry was returned. *
406 * If there was de-scheduled work, the HW will 474 * If there was de-scheduled work, the HW will
@@ -419,12 +487,18 @@ typedef union {
419 uint64_t reserved_40_62:23; 487 uint64_t reserved_40_62:23;
420 /* 36 in O1 -- the work queue pointer */ 488 /* 36 in O1 -- the work queue pointer */
421 uint64_t addr:40; 489 uint64_t addr:40;
490#else
491 uint64_t addr:40;
492 uint64_t reserved_40_62:23;
493 uint64_t no_work:1;
494#endif
422 } s_work; 495 } s_work;
423 496
424 /** 497 /**
425 * Result for a POW Status Load (when get_cur==0 and get_wqp==0) 498 * Result for a POW Status Load (when get_cur==0 and get_wqp==0)
426 */ 499 */
427 struct { 500 struct {
501#ifdef __BIG_ENDIAN_BITFIELD
428 uint64_t reserved_62_63:2; 502 uint64_t reserved_62_63:2;
429 /* Set when there is a pending non-NULL SWTAG or 503 /* Set when there is a pending non-NULL SWTAG or
430 * SWTAG_FULL, and the POW entry has not left the list 504 * SWTAG_FULL, and the POW entry has not left the list
@@ -476,12 +550,32 @@ typedef union {
476 * AND pend_desched_switch) are set. 550 * AND pend_desched_switch) are set.
477 */ 551 */
478 uint64_t pend_tag:32; 552 uint64_t pend_tag:32;
553#else
554 uint64_t pend_tag:32;
555 uint64_t pend_type:2;
556 uint64_t reserved_34_35:2;
557 uint64_t pend_grp:4;
558 uint64_t pend_index:11;
559 uint64_t reserved_51:1;
560 uint64_t pend_nosched_clr:1;
561 uint64_t pend_null_rd:1;
562 uint64_t pend_new_work_wait:1;
563 uint64_t pend_new_work:1;
564 uint64_t pend_nosched:1;
565 uint64_t pend_desched_switch:1;
566 uint64_t pend_desched:1;
567 uint64_t pend_switch_null:1;
568 uint64_t pend_switch_full:1;
569 uint64_t pend_switch:1;
570 uint64_t reserved_62_63:2;
571#endif
479 } s_sstatus0; 572 } s_sstatus0;
480 573
481 /** 574 /**
482 * Result for a POW Status Load (when get_cur==0 and get_wqp==1) 575 * Result for a POW Status Load (when get_cur==0 and get_wqp==1)
483 */ 576 */
484 struct { 577 struct {
578#ifdef __BIG_ENDIAN_BITFIELD
485 uint64_t reserved_62_63:2; 579 uint64_t reserved_62_63:2;
486 /* 580 /*
487 * Set when there is a pending non-NULL SWTAG or 581 * Set when there is a pending non-NULL SWTAG or
@@ -529,6 +623,23 @@ typedef union {
529 uint64_t pend_grp:4; 623 uint64_t pend_grp:4;
530 /* This is the wqp when pend_nosched_clr is set. */ 624 /* This is the wqp when pend_nosched_clr is set. */
531 uint64_t pend_wqp:36; 625 uint64_t pend_wqp:36;
626#else
627 uint64_t pend_wqp:36;
628 uint64_t pend_grp:4;
629 uint64_t pend_index:11;
630 uint64_t reserved_51:1;
631 uint64_t pend_nosched_clr:1;
632 uint64_t pend_null_rd:1;
633 uint64_t pend_new_work_wait:1;
634 uint64_t pend_new_work:1;
635 uint64_t pend_nosched:1;
636 uint64_t pend_desched_switch:1;
637 uint64_t pend_desched:1;
638 uint64_t pend_switch_null:1;
639 uint64_t pend_switch_full:1;
640 uint64_t pend_switch:1;
641 uint64_t reserved_62_63:2;
642#endif
532 } s_sstatus1; 643 } s_sstatus1;
533 644
534 /** 645 /**
@@ -536,6 +647,7 @@ typedef union {
536 * get_rev==0) 647 * get_rev==0)
537 */ 648 */
538 struct { 649 struct {
650#ifdef __BIG_ENDIAN_BITFIELD
539 uint64_t reserved_62_63:2; 651 uint64_t reserved_62_63:2;
540 /* 652 /*
541 * Points to the next POW entry in the tag list when 653 * Points to the next POW entry in the tag list when
@@ -573,12 +685,23 @@ typedef union {
573 * SWTAG_DESCHED). 685 * SWTAG_DESCHED).
574 */ 686 */
575 uint64_t tag:32; 687 uint64_t tag:32;
688#else
689 uint64_t tag:32;
690 uint64_t tag_type:2;
691 uint64_t tail:1;
692 uint64_t head:1;
693 uint64_t grp:4;
694 uint64_t index:11;
695 uint64_t link_index:11;
696 uint64_t reserved_62_63:2;
697#endif
576 } s_sstatus2; 698 } s_sstatus2;
577 699
578 /** 700 /**
579 * Result for a POW Status Load (when get_cur==1, get_wqp==0, and get_rev==1) 701 * Result for a POW Status Load (when get_cur==1, get_wqp==0, and get_rev==1)
580 */ 702 */
581 struct { 703 struct {
704#ifdef __BIG_ENDIAN_BITFIELD
582 uint64_t reserved_62_63:2; 705 uint64_t reserved_62_63:2;
583 /* 706 /*
584 * Points to the prior POW entry in the tag list when 707 * Points to the prior POW entry in the tag list when
@@ -617,6 +740,16 @@ typedef union {
617 * SWTAG_DESCHED). 740 * SWTAG_DESCHED).
618 */ 741 */
619 uint64_t tag:32; 742 uint64_t tag:32;
743#else
744 uint64_t tag:32;
745 uint64_t tag_type:2;
746 uint64_t tail:1;
747 uint64_t head:1;
748 uint64_t grp:4;
749 uint64_t index:11;
750 uint64_t revlink_index:11;
751 uint64_t reserved_62_63:2;
752#endif
620 } s_sstatus3; 753 } s_sstatus3;
621 754
622 /** 755 /**
@@ -624,6 +757,7 @@ typedef union {
624 * get_rev==0) 757 * get_rev==0)
625 */ 758 */
626 struct { 759 struct {
760#ifdef __BIG_ENDIAN_BITFIELD
627 uint64_t reserved_62_63:2; 761 uint64_t reserved_62_63:2;
628 /* 762 /*
629 * Points to the next POW entry in the tag list when 763 * Points to the next POW entry in the tag list when
@@ -642,6 +776,13 @@ typedef union {
642 * list entered on SWTAG_FULL). 776 * list entered on SWTAG_FULL).
643 */ 777 */
644 uint64_t wqp:36; 778 uint64_t wqp:36;
779#else
780 uint64_t wqp:36;
781 uint64_t grp:4;
782 uint64_t index:11;
783 uint64_t link_index:11;
784 uint64_t reserved_62_63:2;
785#endif
645 } s_sstatus4; 786 } s_sstatus4;
646 787
647 /** 788 /**
@@ -649,6 +790,7 @@ typedef union {
649 * get_rev==1) 790 * get_rev==1)
650 */ 791 */
651 struct { 792 struct {
793#ifdef __BIG_ENDIAN_BITFIELD
652 uint64_t reserved_62_63:2; 794 uint64_t reserved_62_63:2;
653 /* 795 /*
654 * Points to the prior POW entry in the tag list when 796 * Points to the prior POW entry in the tag list when
@@ -669,12 +811,20 @@ typedef union {
669 * list entered on SWTAG_FULL). 811 * list entered on SWTAG_FULL).
670 */ 812 */
671 uint64_t wqp:36; 813 uint64_t wqp:36;
814#else
815 uint64_t wqp:36;
816 uint64_t grp:4;
817 uint64_t index:11;
818 uint64_t revlink_index:11;
819 uint64_t reserved_62_63:2;
820#endif
672 } s_sstatus5; 821 } s_sstatus5;
673 822
674 /** 823 /**
675 * Result For POW Memory Load (get_des == 0 and get_wqp == 0) 824 * Result For POW Memory Load (get_des == 0 and get_wqp == 0)
676 */ 825 */
677 struct { 826 struct {
827#ifdef __BIG_ENDIAN_BITFIELD
678 uint64_t reserved_51_63:13; 828 uint64_t reserved_51_63:13;
679 /* 829 /*
680 * The next entry in the input, free, descheduled_head 830 * The next entry in the input, free, descheduled_head
@@ -695,12 +845,22 @@ typedef union {
695 uint64_t tag_type:2; 845 uint64_t tag_type:2;
696 /* The tag of the POW entry. */ 846 /* The tag of the POW entry. */
697 uint64_t tag:32; 847 uint64_t tag:32;
848#else
849 uint64_t tag:32;
850 uint64_t tag_type:2;
851 uint64_t tail:1;
852 uint64_t reserved_35:1;
853 uint64_t grp:4;
854 uint64_t next_index:11;
855 uint64_t reserved_51_63:13;
856#endif
698 } s_smemload0; 857 } s_smemload0;
699 858
700 /** 859 /**
701 * Result For POW Memory Load (get_des == 0 and get_wqp == 1) 860 * Result For POW Memory Load (get_des == 0 and get_wqp == 1)
702 */ 861 */
703 struct { 862 struct {
863#ifdef __BIG_ENDIAN_BITFIELD
704 uint64_t reserved_51_63:13; 864 uint64_t reserved_51_63:13;
705 /* 865 /*
706 * The next entry in the input, free, descheduled_head 866 * The next entry in the input, free, descheduled_head
@@ -712,12 +872,19 @@ typedef union {
712 uint64_t grp:4; 872 uint64_t grp:4;
713 /* The WQP held in the POW entry. */ 873 /* The WQP held in the POW entry. */
714 uint64_t wqp:36; 874 uint64_t wqp:36;
875#else
876 uint64_t wqp:36;
877 uint64_t grp:4;
878 uint64_t next_index:11;
879 uint64_t reserved_51_63:13;
880#endif
715 } s_smemload1; 881 } s_smemload1;
716 882
717 /** 883 /**
718 * Result For POW Memory Load (get_des == 1) 884 * Result For POW Memory Load (get_des == 1)
719 */ 885 */
720 struct { 886 struct {
887#ifdef __BIG_ENDIAN_BITFIELD
721 uint64_t reserved_51_63:13; 888 uint64_t reserved_51_63:13;
722 /* 889 /*
723 * The next entry in the tag list connected to the 890 * The next entry in the tag list connected to the
@@ -740,12 +907,22 @@ typedef union {
740 * is set. 907 * is set.
741 */ 908 */
742 uint64_t pend_tag:32; 909 uint64_t pend_tag:32;
910#else
911 uint64_t pend_tag:32;
912 uint64_t pend_type:2;
913 uint64_t pend_switch:1;
914 uint64_t nosched:1;
915 uint64_t grp:4;
916 uint64_t fwd_index:11;
917 uint64_t reserved_51_63:13;
918#endif
743 } s_smemload2; 919 } s_smemload2;
744 920
745 /** 921 /**
746 * Result For POW Index/Pointer Load (get_rmt == 0/get_des_get_tail == 0) 922 * Result For POW Index/Pointer Load (get_rmt == 0/get_des_get_tail == 0)
747 */ 923 */
748 struct { 924 struct {
925#ifdef __BIG_ENDIAN_BITFIELD
749 uint64_t reserved_52_63:12; 926 uint64_t reserved_52_63:12;
750 /* 927 /*
751 * set when there is one or more POW entries on the 928 * set when there is one or more POW entries on the
@@ -791,12 +968,28 @@ typedef union {
791 * the input Q list selected by qosgrp. 968 * the input Q list selected by qosgrp.
792 */ 969 */
793 uint64_t loc_tail:11; 970 uint64_t loc_tail:11;
971#else
972 uint64_t loc_tail:11;
973 uint64_t reserved_11:1;
974 uint64_t loc_head:11;
975 uint64_t reserved_23:1;
976 uint64_t loc_one:1;
977 uint64_t loc_val:1;
978 uint64_t free_tail:11;
979 uint64_t reserved_37:1;
980 uint64_t free_head:11;
981 uint64_t reserved_49:1;
982 uint64_t free_one:1;
983 uint64_t free_val:1;
984 uint64_t reserved_52_63:12;
985#endif
794 } sindexload0; 986 } sindexload0;
795 987
796 /** 988 /**
797 * Result For POW Index/Pointer Load (get_rmt == 0/get_des_get_tail == 1) 989 * Result For POW Index/Pointer Load (get_rmt == 0/get_des_get_tail == 1)
798 */ 990 */
799 struct { 991 struct {
992#ifdef __BIG_ENDIAN_BITFIELD
800 uint64_t reserved_52_63:12; 993 uint64_t reserved_52_63:12;
801 /* 994 /*
802 * set when there is one or more POW entries on the 995 * set when there is one or more POW entries on the
@@ -843,12 +1036,28 @@ typedef union {
843 * head on the descheduled list selected by qosgrp. 1036 * head on the descheduled list selected by qosgrp.
844 */ 1037 */
845 uint64_t des_tail:11; 1038 uint64_t des_tail:11;
1039#else
1040 uint64_t des_tail:11;
1041 uint64_t reserved_11:1;
1042 uint64_t des_head:11;
1043 uint64_t reserved_23:1;
1044 uint64_t des_one:1;
1045 uint64_t des_val:1;
1046 uint64_t nosched_tail:11;
1047 uint64_t reserved_37:1;
1048 uint64_t nosched_head:11;
1049 uint64_t reserved_49:1;
1050 uint64_t nosched_one:1;
1051 uint64_t nosched_val:1;
1052 uint64_t reserved_52_63:12;
1053#endif
846 } sindexload1; 1054 } sindexload1;
847 1055
848 /** 1056 /**
849 * Result For POW Index/Pointer Load (get_rmt == 1/get_des_get_tail == 0) 1057 * Result For POW Index/Pointer Load (get_rmt == 1/get_des_get_tail == 0)
850 */ 1058 */
851 struct { 1059 struct {
1060#ifdef __BIG_ENDIAN_BITFIELD
852 uint64_t reserved_39_63:25; 1061 uint64_t reserved_39_63:25;
853 /* 1062 /*
854 * Set when this DRAM list is the current head 1063 * Set when this DRAM list is the current head
@@ -877,6 +1086,13 @@ typedef union {
877 * qosgrp. 1086 * qosgrp.
878 */ 1087 */
879 uint64_t rmt_head:36; 1088 uint64_t rmt_head:36;
1089#else
1090 uint64_t rmt_head:36;
1091 uint64_t rmt_one:1;
1092 uint64_t rmt_val:1;
1093 uint64_t rmt_is_head:1;
1094 uint64_t reserved_39_63:25;
1095#endif
880 } sindexload2; 1096 } sindexload2;
881 1097
882 /** 1098 /**
@@ -884,6 +1100,7 @@ typedef union {
884 * 1/get_des_get_tail == 1) 1100 * 1/get_des_get_tail == 1)
885 */ 1101 */
886 struct { 1102 struct {
1103#ifdef __BIG_ENDIAN_BITFIELD
887 uint64_t reserved_39_63:25; 1104 uint64_t reserved_39_63:25;
888 /* 1105 /*
889 * set when this DRAM list is the current head 1106 * set when this DRAM list is the current head
@@ -912,12 +1129,20 @@ typedef union {
912 * qosgrp. 1129 * qosgrp.
913 */ 1130 */
914 uint64_t rmt_tail:36; 1131 uint64_t rmt_tail:36;
1132#else
1133 uint64_t rmt_tail:36;
1134 uint64_t rmt_one:1;
1135 uint64_t rmt_val:1;
1136 uint64_t rmt_is_head:1;
1137 uint64_t reserved_39_63:25;
1138#endif
915 } sindexload3; 1139 } sindexload3;
916 1140
917 /** 1141 /**
918 * Response to NULL_RD request loads 1142 * Response to NULL_RD request loads
919 */ 1143 */
920 struct { 1144 struct {
1145#ifdef __BIG_ENDIAN_BITFIELD
921 uint64_t unused:62; 1146 uint64_t unused:62;
922 /* of type cvmx_pow_tag_type_t. state is one of the 1147 /* of type cvmx_pow_tag_type_t. state is one of the
923 * following: 1148 * following:
@@ -928,6 +1153,10 @@ typedef union {
928 * - CVMX_POW_TAG_TYPE_NULL_NULL 1153 * - CVMX_POW_TAG_TYPE_NULL_NULL
929 */ 1154 */
930 uint64_t state:2; 1155 uint64_t state:2;
1156#else
1157 uint64_t state:2;
1158 uint64_t unused:62;
1159#endif
931 } s_null_rd; 1160 } s_null_rd;
932 1161
933} cvmx_pow_tag_load_resp_t; 1162} cvmx_pow_tag_load_resp_t;
@@ -962,6 +1191,7 @@ typedef union {
962 uint64_t u64; 1191 uint64_t u64;
963 1192
964 struct { 1193 struct {
1194#ifdef __BIG_ENDIAN_BITFIELD
965 /* Memory region. Should be CVMX_IO_SEG in most cases */ 1195 /* Memory region. Should be CVMX_IO_SEG in most cases */
966 uint64_t mem_reg:2; 1196 uint64_t mem_reg:2;
967 uint64_t reserved_49_61:13; /* Must be zero */ 1197 uint64_t reserved_49_61:13; /* Must be zero */
@@ -971,6 +1201,14 @@ typedef union {
971 uint64_t reserved_36_39:4; /* Must be zero */ 1201 uint64_t reserved_36_39:4; /* Must be zero */
972 /* Address field. addr<2:0> must be zero */ 1202 /* Address field. addr<2:0> must be zero */
973 uint64_t addr:36; 1203 uint64_t addr:36;
1204#else
1205 uint64_t addr:36;
1206 uint64_t reserved_36_39:4;
1207 uint64_t did:8;
1208 uint64_t is_io:1;
1209 uint64_t reserved_49_61:13;
1210 uint64_t mem_reg:2;
1211#endif
974 } stag; 1212 } stag;
975} cvmx_pow_tag_store_addr_t; 1213} cvmx_pow_tag_store_addr_t;
976 1214
@@ -981,6 +1219,7 @@ typedef union {
981 uint64_t u64; 1219 uint64_t u64;
982 1220
983 struct { 1221 struct {
1222#ifdef __BIG_ENDIAN_BITFIELD
984 /* 1223 /*
985 * the (64-bit word) location in scratchpad to write 1224 * the (64-bit word) location in scratchpad to write
986 * to (if len != 0) 1225 * to (if len != 0)
@@ -994,6 +1233,14 @@ typedef union {
994 /* if set, don't return load response until work is available */ 1233 /* if set, don't return load response until work is available */
995 uint64_t wait:1; 1234 uint64_t wait:1;
996 uint64_t unused2:3; 1235 uint64_t unused2:3;
1236#else
1237 uint64_t unused2:3;
1238 uint64_t wait:1;
1239 uint64_t unused:36;
1240 uint64_t did:8;
1241 uint64_t len:8;
1242 uint64_t scraddr:8;
1243#endif
997 } s; 1244 } s;
998 1245
999} cvmx_pow_iobdma_store_t; 1246} cvmx_pow_iobdma_store_t;
diff --git a/arch/mips/include/asm/octeon/cvmx-wqe.h b/arch/mips/include/asm/octeon/cvmx-wqe.h
index aa0d3d0de75c..2d6d0c7127a7 100644
--- a/arch/mips/include/asm/octeon/cvmx-wqe.h
+++ b/arch/mips/include/asm/octeon/cvmx-wqe.h
@@ -57,6 +57,7 @@ typedef union {
57 57
58 /* Use this struct if the hardware determines that the packet is IP */ 58 /* Use this struct if the hardware determines that the packet is IP */
59 struct { 59 struct {
60#ifdef __BIG_ENDIAN_BITFIELD
60 /* HW sets this to the number of buffers used by this packet */ 61 /* HW sets this to the number of buffers used by this packet */
61 uint64_t bufs:8; 62 uint64_t bufs:8;
62 /* HW sets to the number of L2 bytes prior to the IP */ 63 /* HW sets to the number of L2 bytes prior to the IP */
@@ -166,13 +167,45 @@ typedef union {
166 * the slow path */ 167 * the slow path */
167 /* type is cvmx_pip_err_t */ 168 /* type is cvmx_pip_err_t */
168 uint64_t err_code:8; 169 uint64_t err_code:8;
170#else
171 uint64_t err_code:8;
172 uint64_t rcv_error:1;
173 uint64_t not_IP:1;
174 uint64_t is_mcast:1;
175 uint64_t is_bcast:1;
176 uint64_t IP_exc:1;
177 uint64_t is_frag:1;
178 uint64_t L4_error:1;
179 uint64_t software:1;
180 uint64_t is_v6:1;
181 uint64_t dec_ipsec:1;
182 uint64_t tcp_or_udp:1;
183 uint64_t dec_ipcomp:1;
184 uint64_t unassigned2:4;
185 uint64_t unassigned2a:4;
186 uint64_t pr:4;
187 uint64_t vlan_id:12;
188 uint64_t vlan_cfi:1;
189 uint64_t unassigned:1;
190 uint64_t vlan_stacked:1;
191 uint64_t vlan_valid:1;
192 uint64_t ip_offset:8;
193 uint64_t bufs:8;
194#endif
169 } s; 195 } s;
170 196
171 /* use this to get at the 16 vlan bits */ 197 /* use this to get at the 16 vlan bits */
172 struct { 198 struct {
199#ifdef __BIG_ENDIAN_BITFIELD
173 uint64_t unused1:16; 200 uint64_t unused1:16;
174 uint64_t vlan:16; 201 uint64_t vlan:16;
175 uint64_t unused2:32; 202 uint64_t unused2:32;
203#else
204 uint64_t unused2:32;
205 uint64_t vlan:16;
206 uint64_t unused1:16;
207
208#endif
176 } svlan; 209 } svlan;
177 210
178 /* 211 /*
@@ -180,6 +213,7 @@ typedef union {
180 * the packet is ip. 213 * the packet is ip.
181 */ 214 */
182 struct { 215 struct {
216#ifdef __BIG_ENDIAN_BITFIELD
183 /* 217 /*
184 * HW sets this to the number of buffers used by this 218 * HW sets this to the number of buffers used by this
185 * packet. 219 * packet.
@@ -296,6 +330,27 @@ typedef union {
296 */ 330 */
297 /* type is cvmx_pip_err_t (union, so can't use directly */ 331 /* type is cvmx_pip_err_t (union, so can't use directly */
298 uint64_t err_code:8; 332 uint64_t err_code:8;
333#else
334 uint64_t err_code:8;
335 uint64_t rcv_error:1;
336 uint64_t not_IP:1;
337 uint64_t is_mcast:1;
338 uint64_t is_bcast:1;
339 uint64_t is_arp:1;
340 uint64_t is_rarp:1;
341 uint64_t unassigned3:1;
342 uint64_t software:1;
343 uint64_t unassigned2:4;
344 uint64_t unassigned2a:8;
345 uint64_t pr:4;
346 uint64_t vlan_id:12;
347 uint64_t vlan_cfi:1;
348 uint64_t unassigned:1;
349 uint64_t vlan_stacked:1;
350 uint64_t vlan_valid:1;
351 uint64_t unused:8;
352 uint64_t bufs:8;
353#endif
299 } snoip; 354 } snoip;
300 355
301} cvmx_pip_wqe_word2; 356} cvmx_pip_wqe_word2;
@@ -312,6 +367,7 @@ typedef struct {
312 * HW WRITE: the following 64 bits are filled by HW when a packet arrives 367 * HW WRITE: the following 64 bits are filled by HW when a packet arrives
313 */ 368 */
314 369
370#ifdef __BIG_ENDIAN_BITFIELD
315 /** 371 /**
316 * raw chksum result generated by the HW 372 * raw chksum result generated by the HW
317 */ 373 */
@@ -327,12 +383,18 @@ typedef struct {
327 * (Only 36 bits used in Octeon 1) 383 * (Only 36 bits used in Octeon 1)
328 */ 384 */
329 uint64_t next_ptr:40; 385 uint64_t next_ptr:40;
386#else
387 uint64_t next_ptr:40;
388 uint8_t unused;
389 uint16_t hw_chksum;
390#endif
330 391
331 /***************************************************************** 392 /*****************************************************************
332 * WORD 1 393 * WORD 1
333 * HW WRITE: the following 64 bits are filled by HW when a packet arrives 394 * HW WRITE: the following 64 bits are filled by HW when a packet arrives
334 */ 395 */
335 396
397#ifdef __BIG_ENDIAN_BITFIELD
336 /** 398 /**
337 * HW sets to the total number of bytes in the packet 399 * HW sets to the total number of bytes in the packet
338 */ 400 */
@@ -359,6 +421,15 @@ typedef struct {
359 * the synchronization/ordering tag 421 * the synchronization/ordering tag
360 */ 422 */
361 uint64_t tag:32; 423 uint64_t tag:32;
424#else
425 uint64_t tag:32;
426 uint64_t tag_type:2;
427 uint64_t zero_2:1;
428 uint64_t grp:4;
429 uint64_t qos:3;
430 uint64_t ipprt:6;
431 uint64_t len:16;
432#endif
362 433
363 /** 434 /**
364 * WORD 2 HW WRITE: the following 64-bits are filled in by 435 * WORD 2 HW WRITE: the following 64-bits are filled in by
diff --git a/arch/mips/include/asm/octeon/cvmx.h b/arch/mips/include/asm/octeon/cvmx.h
index 33db1c806b01..774bb45834cb 100644
--- a/arch/mips/include/asm/octeon/cvmx.h
+++ b/arch/mips/include/asm/octeon/cvmx.h
@@ -436,14 +436,6 @@ static inline uint64_t cvmx_get_cycle_global(void)
436 436
437/***************************************************************************/ 437/***************************************************************************/
438 438
439static inline void cvmx_reset_octeon(void)
440{
441 union cvmx_ciu_soft_rst ciu_soft_rst;
442 ciu_soft_rst.u64 = 0;
443 ciu_soft_rst.s.soft_rst = 1;
444 cvmx_write_csr(CVMX_CIU_SOFT_RST, ciu_soft_rst.u64);
445}
446
447/* Return the number of cores available in the chip */ 439/* Return the number of cores available in the chip */
448static inline uint32_t cvmx_octeon_num_cores(void) 440static inline uint32_t cvmx_octeon_num_cores(void)
449{ 441{
diff --git a/arch/mips/include/asm/octeon/octeon.h b/arch/mips/include/asm/octeon/octeon.h
index 041596570856..de9f74ee5dd0 100644
--- a/arch/mips/include/asm/octeon/octeon.h
+++ b/arch/mips/include/asm/octeon/octeon.h
@@ -335,4 +335,6 @@ void octeon_irq_set_ip4_handler(octeon_irq_ip4_handler_t);
335 335
336extern void octeon_fixup_irqs(void); 336extern void octeon_fixup_irqs(void);
337 337
338extern struct semaphore octeon_bootbus_sem;
339
338#endif /* __ASM_OCTEON_OCTEON_H */ 340#endif /* __ASM_OCTEON_OCTEON_H */
diff --git a/arch/mips/include/asm/octeon/pci-octeon.h b/arch/mips/include/asm/octeon/pci-octeon.h
index 64ba56a02843..1884609741a8 100644
--- a/arch/mips/include/asm/octeon/pci-octeon.h
+++ b/arch/mips/include/asm/octeon/pci-octeon.h
@@ -11,9 +11,6 @@
11 11
12#include <linux/pci.h> 12#include <linux/pci.h>
13 13
14/* Some PCI cards require delays when accessing config space. */
15#define PCI_CONFIG_SPACE_DELAY 10000
16
17/* 14/*
18 * The physical memory base mapped by BAR1. 256MB at the end of the 15 * The physical memory base mapped by BAR1. 256MB at the end of the
19 * first 4GB. 16 * first 4GB.
diff --git a/arch/mips/include/asm/page.h b/arch/mips/include/asm/page.h
index 154b70a10483..89dd7fed1a57 100644
--- a/arch/mips/include/asm/page.h
+++ b/arch/mips/include/asm/page.h
@@ -105,8 +105,6 @@ static inline void clear_user_page(void *addr, unsigned long vaddr,
105 flush_data_cache_page((unsigned long)addr); 105 flush_data_cache_page((unsigned long)addr);
106} 106}
107 107
108extern void copy_user_page(void *vto, void *vfrom, unsigned long vaddr,
109 struct page *to);
110struct vm_area_struct; 108struct vm_area_struct;
111extern void copy_user_highpage(struct page *to, struct page *from, 109extern void copy_user_highpage(struct page *to, struct page *from,
112 unsigned long vaddr, struct vm_area_struct *vma); 110 unsigned long vaddr, struct vm_area_struct *vma);
diff --git a/arch/mips/include/asm/pci.h b/arch/mips/include/asm/pci.h
index 193b4c6b7541..d9692993fc83 100644
--- a/arch/mips/include/asm/pci.h
+++ b/arch/mips/include/asm/pci.h
@@ -35,6 +35,8 @@ struct pci_controller {
35 struct resource *io_resource; 35 struct resource *io_resource;
36 unsigned long io_offset; 36 unsigned long io_offset;
37 unsigned long io_map_base; 37 unsigned long io_map_base;
38 struct resource *busn_resource;
39 unsigned long busn_offset;
38 40
39 unsigned int index; 41 unsigned int index;
40 /* For compatibility with current (as of July 2003) pciutils 42 /* For compatibility with current (as of July 2003) pciutils
diff --git a/arch/mips/include/asm/pci/bridge.h b/arch/mips/include/asm/pci/bridge.h
index af2c8a351ca7..8d7a63b52ac7 100644
--- a/arch/mips/include/asm/pci/bridge.h
+++ b/arch/mips/include/asm/pci/bridge.h
@@ -835,6 +835,7 @@ struct bridge_controller {
835 struct pci_controller pc; 835 struct pci_controller pc;
836 struct resource mem; 836 struct resource mem;
837 struct resource io; 837 struct resource io;
838 struct resource busn;
838 bridge_t *base; 839 bridge_t *base;
839 nasid_t nasid; 840 nasid_t nasid;
840 unsigned int widget_id; 841 unsigned int widget_id;
diff --git a/arch/mips/include/asm/pgtable-32.h b/arch/mips/include/asm/pgtable-32.h
index a6be006b6f75..7d56686c0e62 100644
--- a/arch/mips/include/asm/pgtable-32.h
+++ b/arch/mips/include/asm/pgtable-32.h
@@ -105,13 +105,16 @@ static inline void pmd_clear(pmd_t *pmdp)
105 105
106#if defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32) 106#if defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32)
107#define pte_page(x) pfn_to_page(pte_pfn(x)) 107#define pte_page(x) pfn_to_page(pte_pfn(x))
108#define pte_pfn(x) ((unsigned long)((x).pte_high >> 6)) 108#define pte_pfn(x) (((unsigned long)((x).pte_high >> _PFN_SHIFT)) | (unsigned long)((x).pte_low << _PAGE_PRESENT_SHIFT))
109static inline pte_t 109static inline pte_t
110pfn_pte(unsigned long pfn, pgprot_t prot) 110pfn_pte(unsigned long pfn, pgprot_t prot)
111{ 111{
112 pte_t pte; 112 pte_t pte;
113 pte.pte_high = (pfn << 6) | (pgprot_val(prot) & 0x3f); 113
114 pte.pte_low = pgprot_val(prot); 114 pte.pte_low = (pfn >> _PAGE_PRESENT_SHIFT) |
115 (pgprot_val(prot) & ~_PFNX_MASK);
116 pte.pte_high = (pfn << _PFN_SHIFT) |
117 (pgprot_val(prot) & ~_PFN_MASK);
115 return pte; 118 return pte;
116} 119}
117 120
@@ -166,9 +169,9 @@ pfn_pte(unsigned long pfn, pgprot_t prot)
166#if defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32) 169#if defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32)
167 170
168/* Swap entries must have VALID and GLOBAL bits cleared. */ 171/* Swap entries must have VALID and GLOBAL bits cleared. */
169#define __swp_type(x) (((x).val >> 2) & 0x1f) 172#define __swp_type(x) (((x).val >> 4) & 0x1f)
170#define __swp_offset(x) ((x).val >> 7) 173#define __swp_offset(x) ((x).val >> 9)
171#define __swp_entry(type,offset) ((swp_entry_t) { ((type) << 2) | ((offset) << 7) }) 174#define __swp_entry(type,offset) ((swp_entry_t) { ((type) << 4) | ((offset) << 9) })
172#define __pte_to_swp_entry(pte) ((swp_entry_t) { (pte).pte_high }) 175#define __pte_to_swp_entry(pte) ((swp_entry_t) { (pte).pte_high })
173#define __swp_entry_to_pte(x) ((pte_t) { 0, (x).val }) 176#define __swp_entry_to_pte(x) ((pte_t) { 0, (x).val })
174 177
diff --git a/arch/mips/include/asm/pgtable-64.h b/arch/mips/include/asm/pgtable-64.h
index 1659bb91ae21..cf661a2fb141 100644
--- a/arch/mips/include/asm/pgtable-64.h
+++ b/arch/mips/include/asm/pgtable-64.h
@@ -279,14 +279,14 @@ extern void pgd_init(unsigned long page);
279extern void pmd_init(unsigned long page, unsigned long pagetable); 279extern void pmd_init(unsigned long page, unsigned long pagetable);
280 280
281/* 281/*
282 * Non-present pages: high 24 bits are offset, next 8 bits type, 282 * Non-present pages: high 40 bits are offset, next 8 bits type,
283 * low 32 bits zero. 283 * low 16 bits zero.
284 */ 284 */
285static inline pte_t mk_swap_pte(unsigned long type, unsigned long offset) 285static inline pte_t mk_swap_pte(unsigned long type, unsigned long offset)
286{ pte_t pte; pte_val(pte) = (type << 32) | (offset << 40); return pte; } 286{ pte_t pte; pte_val(pte) = (type << 16) | (offset << 24); return pte; }
287 287
288#define __swp_type(x) (((x).val >> 32) & 0xff) 288#define __swp_type(x) (((x).val >> 16) & 0xff)
289#define __swp_offset(x) ((x).val >> 40) 289#define __swp_offset(x) ((x).val >> 24)
290#define __swp_entry(type, offset) ((swp_entry_t) { pte_val(mk_swap_pte((type), (offset))) }) 290#define __swp_entry(type, offset) ((swp_entry_t) { pte_val(mk_swap_pte((type), (offset))) })
291#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) 291#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
292#define __swp_entry_to_pte(x) ((pte_t) { (x).val }) 292#define __swp_entry_to_pte(x) ((pte_t) { (x).val })
diff --git a/arch/mips/include/asm/pgtable-bits.h b/arch/mips/include/asm/pgtable-bits.h
index 91747c282bb3..18ae5ddef118 100644
--- a/arch/mips/include/asm/pgtable-bits.h
+++ b/arch/mips/include/asm/pgtable-bits.h
@@ -37,7 +37,11 @@
37/* 37/*
38 * The following bits are implemented by the TLB hardware 38 * The following bits are implemented by the TLB hardware
39 */ 39 */
40#define _PAGE_GLOBAL_SHIFT 0 40#define _PAGE_NO_EXEC_SHIFT 0
41#define _PAGE_NO_EXEC (1 << _PAGE_NO_EXEC_SHIFT)
42#define _PAGE_NO_READ_SHIFT (_PAGE_NO_EXEC_SHIFT + 1)
43#define _PAGE_NO_READ (1 << _PAGE_NO_READ_SHIFT)
44#define _PAGE_GLOBAL_SHIFT (_PAGE_NO_READ_SHIFT + 1)
41#define _PAGE_GLOBAL (1 << _PAGE_GLOBAL_SHIFT) 45#define _PAGE_GLOBAL (1 << _PAGE_GLOBAL_SHIFT)
42#define _PAGE_VALID_SHIFT (_PAGE_GLOBAL_SHIFT + 1) 46#define _PAGE_VALID_SHIFT (_PAGE_GLOBAL_SHIFT + 1)
43#define _PAGE_VALID (1 << _PAGE_VALID_SHIFT) 47#define _PAGE_VALID (1 << _PAGE_VALID_SHIFT)
@@ -49,7 +53,7 @@
49/* 53/*
50 * The following bits are implemented in software 54 * The following bits are implemented in software
51 */ 55 */
52#define _PAGE_PRESENT_SHIFT (_CACHE_SHIFT + 3) 56#define _PAGE_PRESENT_SHIFT (24)
53#define _PAGE_PRESENT (1 << _PAGE_PRESENT_SHIFT) 57#define _PAGE_PRESENT (1 << _PAGE_PRESENT_SHIFT)
54#define _PAGE_READ_SHIFT (_PAGE_PRESENT_SHIFT + 1) 58#define _PAGE_READ_SHIFT (_PAGE_PRESENT_SHIFT + 1)
55#define _PAGE_READ (1 << _PAGE_READ_SHIFT) 59#define _PAGE_READ (1 << _PAGE_READ_SHIFT)
@@ -62,6 +66,11 @@
62 66
63#define _PFN_SHIFT (PAGE_SHIFT - 12 + _CACHE_SHIFT + 3) 67#define _PFN_SHIFT (PAGE_SHIFT - 12 + _CACHE_SHIFT + 3)
64 68
69/*
70 * Bits for extended EntryLo0/EntryLo1 registers
71 */
72#define _PFNX_MASK 0xffffff
73
65#elif defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) 74#elif defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
66 75
67/* 76/*
@@ -95,11 +104,7 @@
95 104
96#else 105#else
97/* 106/*
98 * When using the RI/XI bit support, we have 13 bits of flags below 107 * Below are the "Normal" R4K cases
99 * the physical address. The RI/XI bits are placed such that a SRL 5
100 * can strip off the software bits, then a ROTR 2 can move the RI/XI
101 * into bits [63:62]. This also limits physical address to 56 bits,
102 * which is more than we need right now.
103 */ 108 */
104 109
105/* 110/*
@@ -107,38 +112,59 @@
107 */ 112 */
108#define _PAGE_PRESENT_SHIFT 0 113#define _PAGE_PRESENT_SHIFT 0
109#define _PAGE_PRESENT (1 << _PAGE_PRESENT_SHIFT) 114#define _PAGE_PRESENT (1 << _PAGE_PRESENT_SHIFT)
110#define _PAGE_READ_SHIFT (cpu_has_rixi ? _PAGE_PRESENT_SHIFT : _PAGE_PRESENT_SHIFT + 1) 115/* R2 or later cores check for RI/XI support to determine _PAGE_READ */
111#define _PAGE_READ ({BUG_ON(cpu_has_rixi); 1 << _PAGE_READ_SHIFT; }) 116#ifdef CONFIG_CPU_MIPSR2
117#define _PAGE_WRITE_SHIFT (_PAGE_PRESENT_SHIFT + 1)
118#define _PAGE_WRITE (1 << _PAGE_WRITE_SHIFT)
119#else
120#define _PAGE_READ_SHIFT (_PAGE_PRESENT_SHIFT + 1)
121#define _PAGE_READ (1 << _PAGE_READ_SHIFT)
112#define _PAGE_WRITE_SHIFT (_PAGE_READ_SHIFT + 1) 122#define _PAGE_WRITE_SHIFT (_PAGE_READ_SHIFT + 1)
113#define _PAGE_WRITE (1 << _PAGE_WRITE_SHIFT) 123#define _PAGE_WRITE (1 << _PAGE_WRITE_SHIFT)
124#endif
114#define _PAGE_ACCESSED_SHIFT (_PAGE_WRITE_SHIFT + 1) 125#define _PAGE_ACCESSED_SHIFT (_PAGE_WRITE_SHIFT + 1)
115#define _PAGE_ACCESSED (1 << _PAGE_ACCESSED_SHIFT) 126#define _PAGE_ACCESSED (1 << _PAGE_ACCESSED_SHIFT)
116#define _PAGE_MODIFIED_SHIFT (_PAGE_ACCESSED_SHIFT + 1) 127#define _PAGE_MODIFIED_SHIFT (_PAGE_ACCESSED_SHIFT + 1)
117#define _PAGE_MODIFIED (1 << _PAGE_MODIFIED_SHIFT) 128#define _PAGE_MODIFIED (1 << _PAGE_MODIFIED_SHIFT)
118 129
119#ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT 130#if defined(CONFIG_64BIT) && defined(CONFIG_MIPS_HUGE_TLB_SUPPORT)
120/* huge tlb page */ 131/* Huge TLB page */
121#define _PAGE_HUGE_SHIFT (_PAGE_MODIFIED_SHIFT + 1) 132#define _PAGE_HUGE_SHIFT (_PAGE_MODIFIED_SHIFT + 1)
122#define _PAGE_HUGE (1 << _PAGE_HUGE_SHIFT) 133#define _PAGE_HUGE (1 << _PAGE_HUGE_SHIFT)
123#define _PAGE_SPLITTING_SHIFT (_PAGE_HUGE_SHIFT + 1) 134#define _PAGE_SPLITTING_SHIFT (_PAGE_HUGE_SHIFT + 1)
124#define _PAGE_SPLITTING (1 << _PAGE_SPLITTING_SHIFT) 135#define _PAGE_SPLITTING (1 << _PAGE_SPLITTING_SHIFT)
136
137/* Only R2 or newer cores have the XI bit */
138#ifdef CONFIG_CPU_MIPSR2
139#define _PAGE_NO_EXEC_SHIFT (_PAGE_SPLITTING_SHIFT + 1)
125#else 140#else
126#define _PAGE_HUGE_SHIFT (_PAGE_MODIFIED_SHIFT) 141#define _PAGE_GLOBAL_SHIFT (_PAGE_SPLITTING_SHIFT + 1)
127#define _PAGE_HUGE ({BUG(); 1; }) /* Dummy value */ 142#define _PAGE_GLOBAL (1 << _PAGE_GLOBAL_SHIFT)
128#define _PAGE_SPLITTING_SHIFT (_PAGE_HUGE_SHIFT) 143#endif /* CONFIG_CPU_MIPSR2 */
129#define _PAGE_SPLITTING ({BUG(); 1; }) /* Dummy value */
130#endif
131 144
132/* Page cannot be executed */ 145#endif /* CONFIG_64BIT && CONFIG_MIPS_HUGE_TLB_SUPPORT */
133#define _PAGE_NO_EXEC_SHIFT (cpu_has_rixi ? _PAGE_SPLITTING_SHIFT + 1 : _PAGE_SPLITTING_SHIFT)
134#define _PAGE_NO_EXEC ({BUG_ON(!cpu_has_rixi); 1 << _PAGE_NO_EXEC_SHIFT; })
135 146
136/* Page cannot be read */ 147#ifdef CONFIG_CPU_MIPSR2
137#define _PAGE_NO_READ_SHIFT (cpu_has_rixi ? _PAGE_NO_EXEC_SHIFT + 1 : _PAGE_NO_EXEC_SHIFT) 148/* XI - page cannot be executed */
138#define _PAGE_NO_READ ({BUG_ON(!cpu_has_rixi); 1 << _PAGE_NO_READ_SHIFT; }) 149#ifndef _PAGE_NO_EXEC_SHIFT
150#define _PAGE_NO_EXEC_SHIFT (_PAGE_MODIFIED_SHIFT + 1)
151#endif
152#define _PAGE_NO_EXEC (cpu_has_rixi ? (1 << _PAGE_NO_EXEC_SHIFT) : 0)
153
154/* RI - page cannot be read */
155#define _PAGE_READ_SHIFT (_PAGE_NO_EXEC_SHIFT + 1)
156#define _PAGE_READ (cpu_has_rixi ? 0 : (1 << _PAGE_READ_SHIFT))
157#define _PAGE_NO_READ_SHIFT _PAGE_READ_SHIFT
158#define _PAGE_NO_READ (cpu_has_rixi ? (1 << _PAGE_READ_SHIFT) : 0)
139 159
140#define _PAGE_GLOBAL_SHIFT (_PAGE_NO_READ_SHIFT + 1) 160#define _PAGE_GLOBAL_SHIFT (_PAGE_NO_READ_SHIFT + 1)
141#define _PAGE_GLOBAL (1 << _PAGE_GLOBAL_SHIFT) 161#define _PAGE_GLOBAL (1 << _PAGE_GLOBAL_SHIFT)
162
163#else /* !CONFIG_CPU_MIPSR2 */
164#define _PAGE_GLOBAL_SHIFT (_PAGE_MODIFIED_SHIFT + 1)
165#define _PAGE_GLOBAL (1 << _PAGE_GLOBAL_SHIFT)
166#endif /* CONFIG_CPU_MIPSR2 */
167
142#define _PAGE_VALID_SHIFT (_PAGE_GLOBAL_SHIFT + 1) 168#define _PAGE_VALID_SHIFT (_PAGE_GLOBAL_SHIFT + 1)
143#define _PAGE_VALID (1 << _PAGE_VALID_SHIFT) 169#define _PAGE_VALID (1 << _PAGE_VALID_SHIFT)
144#define _PAGE_DIRTY_SHIFT (_PAGE_VALID_SHIFT + 1) 170#define _PAGE_DIRTY_SHIFT (_PAGE_VALID_SHIFT + 1)
@@ -150,18 +176,26 @@
150 176
151#endif /* defined(CONFIG_PHYS_ADDR_T_64BIT && defined(CONFIG_CPU_MIPS32) */ 177#endif /* defined(CONFIG_PHYS_ADDR_T_64BIT && defined(CONFIG_CPU_MIPS32) */
152 178
179#ifndef _PAGE_NO_EXEC
180#define _PAGE_NO_EXEC 0
181#endif
182#ifndef _PAGE_NO_READ
183#define _PAGE_NO_READ 0
184#endif
185
153#define _PAGE_SILENT_READ _PAGE_VALID 186#define _PAGE_SILENT_READ _PAGE_VALID
154#define _PAGE_SILENT_WRITE _PAGE_DIRTY 187#define _PAGE_SILENT_WRITE _PAGE_DIRTY
155 188
156#define _PFN_MASK (~((1 << (_PFN_SHIFT)) - 1)) 189#define _PFN_MASK (~((1 << (_PFN_SHIFT)) - 1))
157 190
158#ifndef _PAGE_NO_READ 191/*
159#define _PAGE_NO_READ ({BUG(); 0; }) 192 * The final layouts of the PTE bits are:
160#define _PAGE_NO_READ_SHIFT ({BUG(); 0; }) 193 *
161#endif 194 * 64-bit, R1 or earlier: CCC D V G [S H] M A W R P
162#ifndef _PAGE_NO_EXEC 195 * 32-bit, R1 or earler: CCC D V G M A W R P
163#define _PAGE_NO_EXEC ({BUG(); 0; }) 196 * 64-bit, R2 or later: CCC D V G RI/R XI [S H] M A W P
164#endif 197 * 32-bit, R2 or later: CCC D V G RI/R XI M A W P
198 */
165 199
166 200
167#ifndef __ASSEMBLY__ 201#ifndef __ASSEMBLY__
@@ -171,6 +205,7 @@
171 */ 205 */
172static inline uint64_t pte_to_entrylo(unsigned long pte_val) 206static inline uint64_t pte_to_entrylo(unsigned long pte_val)
173{ 207{
208#ifdef CONFIG_CPU_MIPSR2
174 if (cpu_has_rixi) { 209 if (cpu_has_rixi) {
175 int sa; 210 int sa;
176#ifdef CONFIG_32BIT 211#ifdef CONFIG_32BIT
@@ -186,6 +221,7 @@ static inline uint64_t pte_to_entrylo(unsigned long pte_val)
186 return (pte_val >> _PAGE_GLOBAL_SHIFT) | 221 return (pte_val >> _PAGE_GLOBAL_SHIFT) |
187 ((pte_val & (_PAGE_NO_EXEC | _PAGE_NO_READ)) << sa); 222 ((pte_val & (_PAGE_NO_EXEC | _PAGE_NO_READ)) << sa);
188 } 223 }
224#endif
189 225
190 return pte_val >> _PAGE_GLOBAL_SHIFT; 226 return pte_val >> _PAGE_GLOBAL_SHIFT;
191} 227}
@@ -245,7 +281,7 @@ static inline uint64_t pte_to_entrylo(unsigned long pte_val)
245#define _CACHE_UNCACHED_ACCELERATED (7<<_CACHE_SHIFT) 281#define _CACHE_UNCACHED_ACCELERATED (7<<_CACHE_SHIFT)
246#endif 282#endif
247 283
248#define __READABLE (_PAGE_SILENT_READ | _PAGE_ACCESSED | (cpu_has_rixi ? 0 : _PAGE_READ)) 284#define __READABLE (_PAGE_SILENT_READ | _PAGE_READ | _PAGE_ACCESSED)
249#define __WRITEABLE (_PAGE_SILENT_WRITE | _PAGE_WRITE | _PAGE_MODIFIED) 285#define __WRITEABLE (_PAGE_SILENT_WRITE | _PAGE_WRITE | _PAGE_MODIFIED)
250 286
251#define _PAGE_CHG_MASK (_PAGE_ACCESSED | _PAGE_MODIFIED | \ 287#define _PAGE_CHG_MASK (_PAGE_ACCESSED | _PAGE_MODIFIED | \
diff --git a/arch/mips/include/asm/pgtable.h b/arch/mips/include/asm/pgtable.h
index bef782c4a44b..819af9d057a8 100644
--- a/arch/mips/include/asm/pgtable.h
+++ b/arch/mips/include/asm/pgtable.h
@@ -24,17 +24,17 @@ struct mm_struct;
24struct vm_area_struct; 24struct vm_area_struct;
25 25
26#define PAGE_NONE __pgprot(_PAGE_PRESENT | _CACHE_CACHABLE_NONCOHERENT) 26#define PAGE_NONE __pgprot(_PAGE_PRESENT | _CACHE_CACHABLE_NONCOHERENT)
27#define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_WRITE | (cpu_has_rixi ? 0 : _PAGE_READ) | \ 27#define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_WRITE | _PAGE_READ | \
28 _page_cachable_default) 28 _page_cachable_default)
29#define PAGE_COPY __pgprot(_PAGE_PRESENT | (cpu_has_rixi ? 0 : _PAGE_READ) | \ 29#define PAGE_COPY __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_NO_EXEC | \
30 (cpu_has_rixi ? _PAGE_NO_EXEC : 0) | _page_cachable_default) 30 _page_cachable_default)
31#define PAGE_READONLY __pgprot(_PAGE_PRESENT | (cpu_has_rixi ? 0 : _PAGE_READ) | \ 31#define PAGE_READONLY __pgprot(_PAGE_PRESENT | _PAGE_READ | \
32 _page_cachable_default) 32 _page_cachable_default)
33#define PAGE_KERNEL __pgprot(_PAGE_PRESENT | __READABLE | __WRITEABLE | \ 33#define PAGE_KERNEL __pgprot(_PAGE_PRESENT | __READABLE | __WRITEABLE | \
34 _PAGE_GLOBAL | _page_cachable_default) 34 _PAGE_GLOBAL | _page_cachable_default)
35#define PAGE_KERNEL_NC __pgprot(_PAGE_PRESENT | __READABLE | __WRITEABLE | \ 35#define PAGE_KERNEL_NC __pgprot(_PAGE_PRESENT | __READABLE | __WRITEABLE | \
36 _PAGE_GLOBAL | _CACHE_CACHABLE_NONCOHERENT) 36 _PAGE_GLOBAL | _CACHE_CACHABLE_NONCOHERENT)
37#define PAGE_USERIO __pgprot(_PAGE_PRESENT | (cpu_has_rixi ? 0 : _PAGE_READ) | _PAGE_WRITE | \ 37#define PAGE_USERIO __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \
38 _page_cachable_default) 38 _page_cachable_default)
39#define PAGE_KERNEL_UNCACHED __pgprot(_PAGE_PRESENT | __READABLE | \ 39#define PAGE_KERNEL_UNCACHED __pgprot(_PAGE_PRESENT | __READABLE | \
40 __WRITEABLE | _PAGE_GLOBAL | _CACHE_UNCACHED) 40 __WRITEABLE | _PAGE_GLOBAL | _CACHE_UNCACHED)
@@ -127,13 +127,9 @@ do { \
127 } \ 127 } \
128} while(0) 128} while(0)
129 129
130
131extern void set_pte_at(struct mm_struct *mm, unsigned long addr, pte_t *ptep,
132 pte_t pteval);
133
134#if defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32) 130#if defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32)
135 131
136#define pte_none(pte) (!(((pte).pte_low | (pte).pte_high) & ~_PAGE_GLOBAL)) 132#define pte_none(pte) (!(((pte).pte_high) & ~_PAGE_GLOBAL))
137#define pte_present(pte) ((pte).pte_low & _PAGE_PRESENT) 133#define pte_present(pte) ((pte).pte_low & _PAGE_PRESENT)
138 134
139static inline void set_pte(pte_t *ptep, pte_t pte) 135static inline void set_pte(pte_t *ptep, pte_t pte)
@@ -142,18 +138,17 @@ static inline void set_pte(pte_t *ptep, pte_t pte)
142 smp_wmb(); 138 smp_wmb();
143 ptep->pte_low = pte.pte_low; 139 ptep->pte_low = pte.pte_low;
144 140
145 if (pte.pte_low & _PAGE_GLOBAL) { 141 if (pte.pte_high & _PAGE_GLOBAL) {
146 pte_t *buddy = ptep_buddy(ptep); 142 pte_t *buddy = ptep_buddy(ptep);
147 /* 143 /*
148 * Make sure the buddy is global too (if it's !none, 144 * Make sure the buddy is global too (if it's !none,
149 * it better already be global) 145 * it better already be global)
150 */ 146 */
151 if (pte_none(*buddy)) { 147 if (pte_none(*buddy))
152 buddy->pte_low |= _PAGE_GLOBAL;
153 buddy->pte_high |= _PAGE_GLOBAL; 148 buddy->pte_high |= _PAGE_GLOBAL;
154 }
155 } 149 }
156} 150}
151#define set_pte_at(mm, addr, ptep, pteval) set_pte(ptep, pteval)
157 152
158static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep) 153static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
159{ 154{
@@ -161,8 +156,8 @@ static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *pt
161 156
162 htw_stop(); 157 htw_stop();
163 /* Preserve global status for the pair */ 158 /* Preserve global status for the pair */
164 if (ptep_buddy(ptep)->pte_low & _PAGE_GLOBAL) 159 if (ptep_buddy(ptep)->pte_high & _PAGE_GLOBAL)
165 null.pte_low = null.pte_high = _PAGE_GLOBAL; 160 null.pte_high = _PAGE_GLOBAL;
166 161
167 set_pte_at(mm, addr, ptep, null); 162 set_pte_at(mm, addr, ptep, null);
168 htw_start(); 163 htw_start();
@@ -192,6 +187,7 @@ static inline void set_pte(pte_t *ptep, pte_t pteval)
192 } 187 }
193#endif 188#endif
194} 189}
190#define set_pte_at(mm, addr, ptep, pteval) set_pte(ptep, pteval)
195 191
196static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep) 192static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
197{ 193{
@@ -242,21 +238,21 @@ static inline int pte_young(pte_t pte) { return pte.pte_low & _PAGE_ACCESSED; }
242 238
243static inline pte_t pte_wrprotect(pte_t pte) 239static inline pte_t pte_wrprotect(pte_t pte)
244{ 240{
245 pte.pte_low &= ~(_PAGE_WRITE | _PAGE_SILENT_WRITE); 241 pte.pte_low &= ~_PAGE_WRITE;
246 pte.pte_high &= ~_PAGE_SILENT_WRITE; 242 pte.pte_high &= ~_PAGE_SILENT_WRITE;
247 return pte; 243 return pte;
248} 244}
249 245
250static inline pte_t pte_mkclean(pte_t pte) 246static inline pte_t pte_mkclean(pte_t pte)
251{ 247{
252 pte.pte_low &= ~(_PAGE_MODIFIED | _PAGE_SILENT_WRITE); 248 pte.pte_low &= ~_PAGE_MODIFIED;
253 pte.pte_high &= ~_PAGE_SILENT_WRITE; 249 pte.pte_high &= ~_PAGE_SILENT_WRITE;
254 return pte; 250 return pte;
255} 251}
256 252
257static inline pte_t pte_mkold(pte_t pte) 253static inline pte_t pte_mkold(pte_t pte)
258{ 254{
259 pte.pte_low &= ~(_PAGE_ACCESSED | _PAGE_SILENT_READ); 255 pte.pte_low &= ~_PAGE_ACCESSED;
260 pte.pte_high &= ~_PAGE_SILENT_READ; 256 pte.pte_high &= ~_PAGE_SILENT_READ;
261 return pte; 257 return pte;
262} 258}
@@ -264,30 +260,24 @@ static inline pte_t pte_mkold(pte_t pte)
264static inline pte_t pte_mkwrite(pte_t pte) 260static inline pte_t pte_mkwrite(pte_t pte)
265{ 261{
266 pte.pte_low |= _PAGE_WRITE; 262 pte.pte_low |= _PAGE_WRITE;
267 if (pte.pte_low & _PAGE_MODIFIED) { 263 if (pte.pte_low & _PAGE_MODIFIED)
268 pte.pte_low |= _PAGE_SILENT_WRITE;
269 pte.pte_high |= _PAGE_SILENT_WRITE; 264 pte.pte_high |= _PAGE_SILENT_WRITE;
270 }
271 return pte; 265 return pte;
272} 266}
273 267
274static inline pte_t pte_mkdirty(pte_t pte) 268static inline pte_t pte_mkdirty(pte_t pte)
275{ 269{
276 pte.pte_low |= _PAGE_MODIFIED; 270 pte.pte_low |= _PAGE_MODIFIED;
277 if (pte.pte_low & _PAGE_WRITE) { 271 if (pte.pte_low & _PAGE_WRITE)
278 pte.pte_low |= _PAGE_SILENT_WRITE;
279 pte.pte_high |= _PAGE_SILENT_WRITE; 272 pte.pte_high |= _PAGE_SILENT_WRITE;
280 }
281 return pte; 273 return pte;
282} 274}
283 275
284static inline pte_t pte_mkyoung(pte_t pte) 276static inline pte_t pte_mkyoung(pte_t pte)
285{ 277{
286 pte.pte_low |= _PAGE_ACCESSED; 278 pte.pte_low |= _PAGE_ACCESSED;
287 if (pte.pte_low & _PAGE_READ) { 279 if (pte.pte_low & _PAGE_READ)
288 pte.pte_low |= _PAGE_SILENT_READ;
289 pte.pte_high |= _PAGE_SILENT_READ; 280 pte.pte_high |= _PAGE_SILENT_READ;
290 }
291 return pte; 281 return pte;
292} 282}
293#else 283#else
@@ -332,13 +322,13 @@ static inline pte_t pte_mkdirty(pte_t pte)
332static inline pte_t pte_mkyoung(pte_t pte) 322static inline pte_t pte_mkyoung(pte_t pte)
333{ 323{
334 pte_val(pte) |= _PAGE_ACCESSED; 324 pte_val(pte) |= _PAGE_ACCESSED;
335 if (cpu_has_rixi) { 325#ifdef CONFIG_CPU_MIPSR2
336 if (!(pte_val(pte) & _PAGE_NO_READ)) 326 if (!(pte_val(pte) & _PAGE_NO_READ))
337 pte_val(pte) |= _PAGE_SILENT_READ; 327 pte_val(pte) |= _PAGE_SILENT_READ;
338 } else { 328 else
339 if (pte_val(pte) & _PAGE_READ) 329#endif
340 pte_val(pte) |= _PAGE_SILENT_READ; 330 if (pte_val(pte) & _PAGE_READ)
341 } 331 pte_val(pte) |= _PAGE_SILENT_READ;
342 return pte; 332 return pte;
343} 333}
344 334
@@ -391,10 +381,10 @@ static inline pgprot_t pgprot_writecombine(pgprot_t _prot)
391#if defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32) 381#if defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32)
392static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 382static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
393{ 383{
394 pte.pte_low &= _PAGE_CHG_MASK; 384 pte.pte_low &= (_PAGE_MODIFIED | _PAGE_ACCESSED | _PFNX_MASK);
395 pte.pte_high &= (_PFN_MASK | _CACHE_MASK); 385 pte.pte_high &= (_PFN_MASK | _CACHE_MASK);
396 pte.pte_low |= pgprot_val(newprot); 386 pte.pte_low |= pgprot_val(newprot) & ~_PFNX_MASK;
397 pte.pte_high |= pgprot_val(newprot) & ~(_PFN_MASK | _CACHE_MASK); 387 pte.pte_high |= pgprot_val(newprot) & ~_PFN_MASK;
398 return pte; 388 return pte;
399} 389}
400#else 390#else
@@ -407,12 +397,15 @@ static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
407 397
408extern void __update_tlb(struct vm_area_struct *vma, unsigned long address, 398extern void __update_tlb(struct vm_area_struct *vma, unsigned long address,
409 pte_t pte); 399 pte_t pte);
400extern void __update_cache(struct vm_area_struct *vma, unsigned long address,
401 pte_t pte);
410 402
411static inline void update_mmu_cache(struct vm_area_struct *vma, 403static inline void update_mmu_cache(struct vm_area_struct *vma,
412 unsigned long address, pte_t *ptep) 404 unsigned long address, pte_t *ptep)
413{ 405{
414 pte_t pte = *ptep; 406 pte_t pte = *ptep;
415 __update_tlb(vma, address, pte); 407 __update_tlb(vma, address, pte);
408 __update_cache(vma, address, pte);
416} 409}
417 410
418static inline void update_mmu_cache_pmd(struct vm_area_struct *vma, 411static inline void update_mmu_cache_pmd(struct vm_area_struct *vma,
@@ -534,13 +527,13 @@ static inline pmd_t pmd_mkyoung(pmd_t pmd)
534{ 527{
535 pmd_val(pmd) |= _PAGE_ACCESSED; 528 pmd_val(pmd) |= _PAGE_ACCESSED;
536 529
537 if (cpu_has_rixi) { 530#ifdef CONFIG_CPU_MIPSR2
538 if (!(pmd_val(pmd) & _PAGE_NO_READ)) 531 if (!(pmd_val(pmd) & _PAGE_NO_READ))
539 pmd_val(pmd) |= _PAGE_SILENT_READ; 532 pmd_val(pmd) |= _PAGE_SILENT_READ;
540 } else { 533 else
541 if (pmd_val(pmd) & _PAGE_READ) 534#endif
542 pmd_val(pmd) |= _PAGE_SILENT_READ; 535 if (pmd_val(pmd) & _PAGE_READ)
543 } 536 pmd_val(pmd) |= _PAGE_SILENT_READ;
544 537
545 return pmd; 538 return pmd;
546} 539}
diff --git a/arch/mips/include/asm/r4kcache.h b/arch/mips/include/asm/r4kcache.h
index 1b22d2da88a1..38902bf97adc 100644
--- a/arch/mips/include/asm/r4kcache.h
+++ b/arch/mips/include/asm/r4kcache.h
@@ -12,6 +12,8 @@
12#ifndef _ASM_R4KCACHE_H 12#ifndef _ASM_R4KCACHE_H
13#define _ASM_R4KCACHE_H 13#define _ASM_R4KCACHE_H
14 14
15#include <linux/stringify.h>
16
15#include <asm/asm.h> 17#include <asm/asm.h>
16#include <asm/cacheops.h> 18#include <asm/cacheops.h>
17#include <asm/compiler.h> 19#include <asm/compiler.h>
@@ -344,7 +346,7 @@ static inline void invalidate_tcache_page(unsigned long addr)
344 " cache %1, 0x0a0(%0); cache %1, 0x0b0(%0)\n" \ 346 " cache %1, 0x0a0(%0); cache %1, 0x0b0(%0)\n" \
345 " cache %1, 0x0c0(%0); cache %1, 0x0d0(%0)\n" \ 347 " cache %1, 0x0c0(%0); cache %1, 0x0d0(%0)\n" \
346 " cache %1, 0x0e0(%0); cache %1, 0x0f0(%0)\n" \ 348 " cache %1, 0x0e0(%0); cache %1, 0x0f0(%0)\n" \
347 " addiu $1, $0, 0x100 \n" \ 349 " "__stringify(LONG_ADDIU)" $1, %0, 0x100 \n" \
348 " cache %1, 0x000($1); cache %1, 0x010($1)\n" \ 350 " cache %1, 0x000($1); cache %1, 0x010($1)\n" \
349 " cache %1, 0x020($1); cache %1, 0x030($1)\n" \ 351 " cache %1, 0x020($1); cache %1, 0x030($1)\n" \
350 " cache %1, 0x040($1); cache %1, 0x050($1)\n" \ 352 " cache %1, 0x040($1); cache %1, 0x050($1)\n" \
@@ -368,17 +370,17 @@ static inline void invalidate_tcache_page(unsigned long addr)
368 " cache %1, 0x040(%0); cache %1, 0x060(%0)\n" \ 370 " cache %1, 0x040(%0); cache %1, 0x060(%0)\n" \
369 " cache %1, 0x080(%0); cache %1, 0x0a0(%0)\n" \ 371 " cache %1, 0x080(%0); cache %1, 0x0a0(%0)\n" \
370 " cache %1, 0x0c0(%0); cache %1, 0x0e0(%0)\n" \ 372 " cache %1, 0x0c0(%0); cache %1, 0x0e0(%0)\n" \
371 " addiu $1, %0, 0x100\n" \ 373 " "__stringify(LONG_ADDIU)" $1, %0, 0x100 \n" \
372 " cache %1, 0x000($1); cache %1, 0x020($1)\n" \ 374 " cache %1, 0x000($1); cache %1, 0x020($1)\n" \
373 " cache %1, 0x040($1); cache %1, 0x060($1)\n" \ 375 " cache %1, 0x040($1); cache %1, 0x060($1)\n" \
374 " cache %1, 0x080($1); cache %1, 0x0a0($1)\n" \ 376 " cache %1, 0x080($1); cache %1, 0x0a0($1)\n" \
375 " cache %1, 0x0c0($1); cache %1, 0x0e0($1)\n" \ 377 " cache %1, 0x0c0($1); cache %1, 0x0e0($1)\n" \
376 " addiu $1, $1, 0x100\n" \ 378 " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \
377 " cache %1, 0x000($1); cache %1, 0x020($1)\n" \ 379 " cache %1, 0x000($1); cache %1, 0x020($1)\n" \
378 " cache %1, 0x040($1); cache %1, 0x060($1)\n" \ 380 " cache %1, 0x040($1); cache %1, 0x060($1)\n" \
379 " cache %1, 0x080($1); cache %1, 0x0a0($1)\n" \ 381 " cache %1, 0x080($1); cache %1, 0x0a0($1)\n" \
380 " cache %1, 0x0c0($1); cache %1, 0x0e0($1)\n" \ 382 " cache %1, 0x0c0($1); cache %1, 0x0e0($1)\n" \
381 " addiu $1, $1, 0x100\n" \ 383 " "__stringify(LONG_ADDIU)" $1, $1, 0x100\n" \
382 " cache %1, 0x000($1); cache %1, 0x020($1)\n" \ 384 " cache %1, 0x000($1); cache %1, 0x020($1)\n" \
383 " cache %1, 0x040($1); cache %1, 0x060($1)\n" \ 385 " cache %1, 0x040($1); cache %1, 0x060($1)\n" \
384 " cache %1, 0x080($1); cache %1, 0x0a0($1)\n" \ 386 " cache %1, 0x080($1); cache %1, 0x0a0($1)\n" \
@@ -396,25 +398,25 @@ static inline void invalidate_tcache_page(unsigned long addr)
396 " .set noat\n" \ 398 " .set noat\n" \
397 " cache %1, 0x000(%0); cache %1, 0x040(%0)\n" \ 399 " cache %1, 0x000(%0); cache %1, 0x040(%0)\n" \
398 " cache %1, 0x080(%0); cache %1, 0x0c0(%0)\n" \ 400 " cache %1, 0x080(%0); cache %1, 0x0c0(%0)\n" \
399 " addiu $1, %0, 0x100\n" \ 401 " "__stringify(LONG_ADDIU)" $1, %0, 0x100 \n" \
400 " cache %1, 0x000($1); cache %1, 0x040($1)\n" \ 402 " cache %1, 0x000($1); cache %1, 0x040($1)\n" \
401 " cache %1, 0x080($1); cache %1, 0x0c0($1)\n" \ 403 " cache %1, 0x080($1); cache %1, 0x0c0($1)\n" \
402 " addiu $1, %0, 0x100\n" \ 404 " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \
403 " cache %1, 0x000($1); cache %1, 0x040($1)\n" \ 405 " cache %1, 0x000($1); cache %1, 0x040($1)\n" \
404 " cache %1, 0x080($1); cache %1, 0x0c0($1)\n" \ 406 " cache %1, 0x080($1); cache %1, 0x0c0($1)\n" \
405 " addiu $1, %0, 0x100\n" \ 407 " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \
406 " cache %1, 0x000($1); cache %1, 0x040($1)\n" \ 408 " cache %1, 0x000($1); cache %1, 0x040($1)\n" \
407 " cache %1, 0x080($1); cache %1, 0x0c0($1)\n" \ 409 " cache %1, 0x080($1); cache %1, 0x0c0($1)\n" \
408 " addiu $1, %0, 0x100\n" \ 410 " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \
409 " cache %1, 0x000($1); cache %1, 0x040($1)\n" \ 411 " cache %1, 0x000($1); cache %1, 0x040($1)\n" \
410 " cache %1, 0x080($1); cache %1, 0x0c0($1)\n" \ 412 " cache %1, 0x080($1); cache %1, 0x0c0($1)\n" \
411 " addiu $1, %0, 0x100\n" \ 413 " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \
412 " cache %1, 0x000($1); cache %1, 0x040($1)\n" \ 414 " cache %1, 0x000($1); cache %1, 0x040($1)\n" \
413 " cache %1, 0x080($1); cache %1, 0x0c0($1)\n" \ 415 " cache %1, 0x080($1); cache %1, 0x0c0($1)\n" \
414 " addiu $1, %0, 0x100\n" \ 416 " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \
415 " cache %1, 0x000($1); cache %1, 0x040($1)\n" \ 417 " cache %1, 0x000($1); cache %1, 0x040($1)\n" \
416 " cache %1, 0x080($1); cache %1, 0x0c0($1)\n" \ 418 " cache %1, 0x080($1); cache %1, 0x0c0($1)\n" \
417 " addiu $1, %0, 0x100\n" \ 419 " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \
418 " cache %1, 0x000($1); cache %1, 0x040($1)\n" \ 420 " cache %1, 0x000($1); cache %1, 0x040($1)\n" \
419 " cache %1, 0x080($1); cache %1, 0x0c0($1)\n" \ 421 " cache %1, 0x080($1); cache %1, 0x0c0($1)\n" \
420 " .set pop\n" \ 422 " .set pop\n" \
@@ -429,39 +431,38 @@ static inline void invalidate_tcache_page(unsigned long addr)
429 " .set mips64r6\n" \ 431 " .set mips64r6\n" \
430 " .set noat\n" \ 432 " .set noat\n" \
431 " cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \ 433 " cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \
432 " addiu $1, %0, 0x100\n" \ 434 " "__stringify(LONG_ADDIU)" $1, %0, 0x100 \n" \
433 " cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \ 435 " cache %1, 0x000($1); cache %1, 0x080($1)\n" \
434 " addiu $1, %0, 0x100\n" \ 436 " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \
435 " cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \ 437 " cache %1, 0x000($1); cache %1, 0x080($1)\n" \
436 " addiu $1, %0, 0x100\n" \ 438 " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \
437 " cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \ 439 " cache %1, 0x000($1); cache %1, 0x080($1)\n" \
438 " addiu $1, %0, 0x100\n" \ 440 " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \
439 " cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \ 441 " cache %1, 0x000($1); cache %1, 0x080($1)\n" \
440 " addiu $1, %0, 0x100\n" \ 442 " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \
441 " cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \ 443 " cache %1, 0x000($1); cache %1, 0x080($1)\n" \
442 " addiu $1, %0, 0x100\n" \ 444 " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \
443 " cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \ 445 " cache %1, 0x000($1); cache %1, 0x080($1)\n" \
444 " addiu $1, %0, 0x100\n" \ 446 " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \
445 " cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \ 447 " cache %1, 0x000($1); cache %1, 0x080($1)\n" \
446 " addiu $1, %0, 0x100\n" \ 448 " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \
447 " cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \ 449 " cache %1, 0x000($1); cache %1, 0x080($1)\n" \
448 " addiu $1, %0, 0x100\n" \ 450 " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \
449 " cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \ 451 " cache %1, 0x000($1); cache %1, 0x080($1)\n" \
450 " addiu $1, %0, 0x100\n" \ 452 " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \
451 " cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \ 453 " cache %1, 0x000($1); cache %1, 0x080($1)\n" \
452 " addiu $1, %0, 0x100\n" \ 454 " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \
453 " cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \ 455 " cache %1, 0x000($1); cache %1, 0x080($1)\n" \
454 " addiu $1, %0, 0x100\n" \ 456 " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \
455 " cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \ 457 " cache %1, 0x000($1); cache %1, 0x080($1)\n" \
456 " addiu $1, %0, 0x100\n" \ 458 " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \
457 " cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \ 459 " cache %1, 0x000($1); cache %1, 0x080($1)\n" \
458 " addiu $1, %0, 0x100\n" \ 460 " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \
459 " cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \ 461 " cache %1, 0x000($1); cache %1, 0x080($1)\n" \
460 " addiu $1, %0, 0x100\n" \ 462 " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \
461 " cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \ 463 " cache %1, 0x000($1); cache %1, 0x080($1)\n" \
462 " addiu $1, %0, 0x100\n" \ 464 " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \
463 " cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \ 465 " cache %1, 0x000($1); cache %1, 0x080($1)\n" \
464 " addiu $1, %0, 0x100\n" \
465 " .set pop\n" \ 466 " .set pop\n" \
466 : \ 467 : \
467 : "r" (base), \ 468 : "r" (base), \
diff --git a/arch/mips/include/asm/sgi/sgi.h b/arch/mips/include/asm/sgi/sgi.h
index 645cea7c0f8e..b61557151e3f 100644
--- a/arch/mips/include/asm/sgi/sgi.h
+++ b/arch/mips/include/asm/sgi/sgi.h
@@ -22,14 +22,15 @@ enum sgi_mach {
22 ip17, /* R4K UP */ 22 ip17, /* R4K UP */
23 ip19, /* R4K MP */ 23 ip19, /* R4K MP */
24 ip20, /* R4K UP, Indigo */ 24 ip20, /* R4K UP, Indigo */
25 ip21, /* TFP MP */ 25 ip21, /* R8k/TFP MP */
26 ip22, /* R4x00 UP, Indigo2 */ 26 ip22, /* R4x00 UP, Indy, Indigo2 */
27 ip25, /* R10k MP */ 27 ip25, /* R10k MP */
28 ip26, /* TFP UP, Indigo2 */ 28 ip26, /* R8k/TFP UP, Indigo2 */
29 ip27, /* R10k MP, R12k MP, Origin */ 29 ip27, /* R10k MP, R12k MP, R14k MP, Origin 200/2k, Onyx2 */
30 ip28, /* R10k UP, Indigo2 */ 30 ip28, /* R10k UP, Indigo2 Impact R10k */
31 ip30, /* Octane */ 31 ip30, /* R10k MP, R12k MP, R14k MP, Octane */
32 ip32, /* O2 */ 32 ip32, /* R5k UP, RM5200 UP, RM7k UP, R10k UP, R12k UP, O2 */
33 ip35, /* R14k MP, R16k MP, Origin 300/3k, Onyx3, Fuel, Tezro */
33}; 34};
34 35
35extern enum sgi_mach sgimach; 36extern enum sgi_mach sgimach;
diff --git a/arch/mips/include/asm/spinlock.h b/arch/mips/include/asm/spinlock.h
index b4548690ade9..1fca2e0793dc 100644
--- a/arch/mips/include/asm/spinlock.h
+++ b/arch/mips/include/asm/spinlock.h
@@ -263,7 +263,7 @@ static inline void arch_read_unlock(arch_rwlock_t *rw)
263 if (R10000_LLSC_WAR) { 263 if (R10000_LLSC_WAR) {
264 __asm__ __volatile__( 264 __asm__ __volatile__(
265 "1: ll %1, %2 # arch_read_unlock \n" 265 "1: ll %1, %2 # arch_read_unlock \n"
266 " addiu %1, 1 \n" 266 " addiu %1, -1 \n"
267 " sc %1, %0 \n" 267 " sc %1, %0 \n"
268 " beqzl %1, 1b \n" 268 " beqzl %1, 1b \n"
269 : "=" GCC_OFF_SMALL_ASM() (rw->lock), "=&r" (tmp) 269 : "=" GCC_OFF_SMALL_ASM() (rw->lock), "=&r" (tmp)
diff --git a/arch/mips/include/asm/thread_info.h b/arch/mips/include/asm/thread_info.h
index 8408a30c47f3..9c0014e87c17 100644
--- a/arch/mips/include/asm/thread_info.h
+++ b/arch/mips/include/asm/thread_info.h
@@ -53,10 +53,10 @@ struct thread_info {
53#define init_stack (init_thread_union.stack) 53#define init_stack (init_thread_union.stack)
54 54
55/* How to get the thread information struct from C. */ 55/* How to get the thread information struct from C. */
56register struct thread_info *__current_thread_info __asm__("$28");
57
56static inline struct thread_info *current_thread_info(void) 58static inline struct thread_info *current_thread_info(void)
57{ 59{
58 register struct thread_info *__current_thread_info __asm__("$28");
59
60 return __current_thread_info; 60 return __current_thread_info;
61} 61}
62 62
diff --git a/arch/mips/jz4740/Platform b/arch/mips/jz4740/Platform
index ba91be9c21ef..c41d30080098 100644
--- a/arch/mips/jz4740/Platform
+++ b/arch/mips/jz4740/Platform
@@ -1,3 +1,4 @@
1platform-$(CONFIG_MACH_JZ4740) += jz4740/ 1platform-$(CONFIG_MACH_JZ4740) += jz4740/
2cflags-$(CONFIG_MACH_JZ4740) += -I$(srctree)/arch/mips/include/asm/mach-jz4740 2cflags-$(CONFIG_MACH_JZ4740) += -I$(srctree)/arch/mips/include/asm/mach-jz4740
3load-$(CONFIG_MACH_JZ4740) += 0xffffffff80010000 3load-$(CONFIG_MACH_JZ4740) += 0xffffffff80010000
4zload-$(CONFIG_MACH_JZ4740) += 0xffffffff80600000
diff --git a/arch/mips/jz4740/time.c b/arch/mips/jz4740/time.c
index 5e430ce9ac7e..72b0cecbc17c 100644
--- a/arch/mips/jz4740/time.c
+++ b/arch/mips/jz4740/time.c
@@ -18,6 +18,7 @@
18#include <linux/time.h> 18#include <linux/time.h>
19 19
20#include <linux/clockchips.h> 20#include <linux/clockchips.h>
21#include <linux/sched_clock.h>
21 22
22#include <asm/mach-jz4740/irq.h> 23#include <asm/mach-jz4740/irq.h>
23#include <asm/mach-jz4740/timer.h> 24#include <asm/mach-jz4740/timer.h>
@@ -43,6 +44,11 @@ static struct clocksource jz4740_clocksource = {
43 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 44 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
44}; 45};
45 46
47static u64 notrace jz4740_read_sched_clock(void)
48{
49 return jz4740_timer_get_count(TIMER_CLOCKSOURCE);
50}
51
46static irqreturn_t jz4740_clockevent_irq(int irq, void *devid) 52static irqreturn_t jz4740_clockevent_irq(int irq, void *devid)
47{ 53{
48 struct clock_event_device *cd = devid; 54 struct clock_event_device *cd = devid;
@@ -126,6 +132,8 @@ void __init plat_time_init(void)
126 if (ret) 132 if (ret)
127 printk(KERN_ERR "Failed to register clocksource: %d\n", ret); 133 printk(KERN_ERR "Failed to register clocksource: %d\n", ret);
128 134
135 sched_clock_register(jz4740_read_sched_clock, 16, clk_rate);
136
129 setup_irq(JZ4740_IRQ_TCU0, &timer_irqaction); 137 setup_irq(JZ4740_IRQ_TCU0, &timer_irqaction);
130 138
131 ctrl = JZ_TIMER_CTRL_PRESCALE_16 | JZ_TIMER_CTRL_SRC_EXT; 139 ctrl = JZ_TIMER_CTRL_PRESCALE_16 | JZ_TIMER_CTRL_SRC_EXT;
diff --git a/arch/mips/kernel/branch.c b/arch/mips/kernel/branch.c
index c2e0f45ddf6c..c0c5e5972256 100644
--- a/arch/mips/kernel/branch.c
+++ b/arch/mips/kernel/branch.c
@@ -36,8 +36,10 @@ int __isa_exception_epc(struct pt_regs *regs)
36 return epc; 36 return epc;
37 } 37 }
38 if (cpu_has_mips16) { 38 if (cpu_has_mips16) {
39 if (((union mips16e_instruction)inst).ri.opcode 39 union mips16e_instruction inst_mips16e;
40 == MIPS16e_jal_op) 40
41 inst_mips16e.full = inst;
42 if (inst_mips16e.ri.opcode == MIPS16e_jal_op)
41 epc += 4; 43 epc += 4;
42 else 44 else
43 epc += 2; 45 epc += 2;
diff --git a/arch/mips/kernel/cevt-r4k.c b/arch/mips/kernel/cevt-r4k.c
index 82bd2b278a24..d70c4d893219 100644
--- a/arch/mips/kernel/cevt-r4k.c
+++ b/arch/mips/kernel/cevt-r4k.c
@@ -37,6 +37,24 @@ void mips_set_clock_mode(enum clock_event_mode mode,
37DEFINE_PER_CPU(struct clock_event_device, mips_clockevent_device); 37DEFINE_PER_CPU(struct clock_event_device, mips_clockevent_device);
38int cp0_timer_irq_installed; 38int cp0_timer_irq_installed;
39 39
40/*
41 * Possibly handle a performance counter interrupt.
42 * Return true if the timer interrupt should not be checked
43 */
44static inline int handle_perf_irq(int r2)
45{
46 /*
47 * The performance counter overflow interrupt may be shared with the
48 * timer interrupt (cp0_perfcount_irq < 0). If it is and a
49 * performance counter has overflowed (perf_irq() == IRQ_HANDLED)
50 * and we can't reliably determine if a counter interrupt has also
51 * happened (!r2) then don't check for a timer interrupt.
52 */
53 return (cp0_perfcount_irq < 0) &&
54 perf_irq() == IRQ_HANDLED &&
55 !r2;
56}
57
40irqreturn_t c0_compare_interrupt(int irq, void *dev_id) 58irqreturn_t c0_compare_interrupt(int irq, void *dev_id)
41{ 59{
42 const int r2 = cpu_has_mips_r2_r6; 60 const int r2 = cpu_has_mips_r2_r6;
@@ -50,27 +68,32 @@ irqreturn_t c0_compare_interrupt(int irq, void *dev_id)
50 * the performance counter interrupt handler anyway. 68 * the performance counter interrupt handler anyway.
51 */ 69 */
52 if (handle_perf_irq(r2)) 70 if (handle_perf_irq(r2))
53 goto out; 71 return IRQ_HANDLED;
54 72
55 /* 73 /*
56 * The same applies to performance counter interrupts. But with the 74 * The same applies to performance counter interrupts. But with the
57 * above we now know that the reason we got here must be a timer 75 * above we now know that the reason we got here must be a timer
58 * interrupt. Being the paranoiacs we are we check anyway. 76 * interrupt. Being the paranoiacs we are we check anyway.
59 */ 77 */
60 if (!r2 || (read_c0_cause() & (1 << 30))) { 78 if (!r2 || (read_c0_cause() & CAUSEF_TI)) {
61 /* Clear Count/Compare Interrupt */ 79 /* Clear Count/Compare Interrupt */
62 write_c0_compare(read_c0_compare()); 80 write_c0_compare(read_c0_compare());
63 cd = &per_cpu(mips_clockevent_device, cpu); 81 cd = &per_cpu(mips_clockevent_device, cpu);
64 cd->event_handler(cd); 82 cd->event_handler(cd);
83
84 return IRQ_HANDLED;
65 } 85 }
66 86
67out: 87 return IRQ_NONE;
68 return IRQ_HANDLED;
69} 88}
70 89
71struct irqaction c0_compare_irqaction = { 90struct irqaction c0_compare_irqaction = {
72 .handler = c0_compare_interrupt, 91 .handler = c0_compare_interrupt,
73 .flags = IRQF_PERCPU | IRQF_TIMER, 92 /*
93 * IRQF_SHARED: The timer interrupt may be shared with other interrupts
94 * such as perf counter and FDC interrupts.
95 */
96 .flags = IRQF_PERCPU | IRQF_TIMER | IRQF_SHARED,
74 .name = "timer", 97 .name = "timer",
75}; 98};
76 99
diff --git a/arch/mips/kernel/cevt-txx9.c b/arch/mips/kernel/cevt-txx9.c
index 2ae08462e46e..723932441ecc 100644
--- a/arch/mips/kernel/cevt-txx9.c
+++ b/arch/mips/kernel/cevt-txx9.c
@@ -14,6 +14,7 @@
14#include <linux/init.h> 14#include <linux/init.h>
15#include <linux/interrupt.h> 15#include <linux/interrupt.h>
16#include <linux/irq.h> 16#include <linux/irq.h>
17#include <linux/sched_clock.h>
17#include <asm/time.h> 18#include <asm/time.h>
18#include <asm/txx9tmr.h> 19#include <asm/txx9tmr.h>
19 20
@@ -46,6 +47,11 @@ static struct txx9_clocksource txx9_clocksource = {
46 }, 47 },
47}; 48};
48 49
50static u64 notrace txx9_read_sched_clock(void)
51{
52 return __raw_readl(&txx9_clocksource.tmrptr->trr);
53}
54
49void __init txx9_clocksource_init(unsigned long baseaddr, 55void __init txx9_clocksource_init(unsigned long baseaddr,
50 unsigned int imbusclk) 56 unsigned int imbusclk)
51{ 57{
@@ -61,6 +67,9 @@ void __init txx9_clocksource_init(unsigned long baseaddr,
61 __raw_writel(1 << TXX9_CLOCKSOURCE_BITS, &tmrptr->cpra); 67 __raw_writel(1 << TXX9_CLOCKSOURCE_BITS, &tmrptr->cpra);
62 __raw_writel(TCR_BASE | TXx9_TMTCR_TCE, &tmrptr->tcr); 68 __raw_writel(TCR_BASE | TXx9_TMTCR_TCE, &tmrptr->tcr);
63 txx9_clocksource.tmrptr = tmrptr; 69 txx9_clocksource.tmrptr = tmrptr;
70
71 sched_clock_register(txx9_read_sched_clock, TXX9_CLOCKSOURCE_BITS,
72 TIMER_CLK(imbusclk));
64} 73}
65 74
66struct txx9_clock_event_device { 75struct txx9_clock_event_device {
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index 48dfb9de853d..e36515dcd3b2 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -20,6 +20,7 @@
20 20
21#include <asm/bugs.h> 21#include <asm/bugs.h>
22#include <asm/cpu.h> 22#include <asm/cpu.h>
23#include <asm/cpu-features.h>
23#include <asm/cpu-type.h> 24#include <asm/cpu-type.h>
24#include <asm/fpu.h> 25#include <asm/fpu.h>
25#include <asm/mipsregs.h> 26#include <asm/mipsregs.h>
@@ -31,11 +32,127 @@
31#include <asm/spram.h> 32#include <asm/spram.h>
32#include <asm/uaccess.h> 33#include <asm/uaccess.h>
33 34
35/*
36 * Get the FPU Implementation/Revision.
37 */
38static inline unsigned long cpu_get_fpu_id(void)
39{
40 unsigned long tmp, fpu_id;
41
42 tmp = read_c0_status();
43 __enable_fpu(FPU_AS_IS);
44 fpu_id = read_32bit_cp1_register(CP1_REVISION);
45 write_c0_status(tmp);
46 return fpu_id;
47}
48
49/*
50 * Check if the CPU has an external FPU.
51 */
52static inline int __cpu_has_fpu(void)
53{
54 return (cpu_get_fpu_id() & FPIR_IMP_MASK) != FPIR_IMP_NONE;
55}
56
57static inline unsigned long cpu_get_msa_id(void)
58{
59 unsigned long status, msa_id;
60
61 status = read_c0_status();
62 __enable_fpu(FPU_64BIT);
63 enable_msa();
64 msa_id = read_msa_ir();
65 disable_msa();
66 write_c0_status(status);
67 return msa_id;
68}
69
70/*
71 * Determine the FCSR mask for FPU hardware.
72 */
73static inline void cpu_set_fpu_fcsr_mask(struct cpuinfo_mips *c)
74{
75 unsigned long sr, mask, fcsr, fcsr0, fcsr1;
76
77 mask = FPU_CSR_ALL_X | FPU_CSR_ALL_E | FPU_CSR_ALL_S | FPU_CSR_RM;
78
79 sr = read_c0_status();
80 __enable_fpu(FPU_AS_IS);
81
82 fcsr = read_32bit_cp1_register(CP1_STATUS);
83
84 fcsr0 = fcsr & mask;
85 write_32bit_cp1_register(CP1_STATUS, fcsr0);
86 fcsr0 = read_32bit_cp1_register(CP1_STATUS);
87
88 fcsr1 = fcsr | ~mask;
89 write_32bit_cp1_register(CP1_STATUS, fcsr1);
90 fcsr1 = read_32bit_cp1_register(CP1_STATUS);
91
92 write_32bit_cp1_register(CP1_STATUS, fcsr);
93
94 write_c0_status(sr);
95
96 c->fpu_msk31 = ~(fcsr0 ^ fcsr1) & ~mask;
97}
98
99/*
100 * Set the FIR feature flags for the FPU emulator.
101 */
102static void cpu_set_nofpu_id(struct cpuinfo_mips *c)
103{
104 u32 value;
105
106 value = 0;
107 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
108 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
109 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6))
110 value |= MIPS_FPIR_D | MIPS_FPIR_S;
111 if (c->isa_level & (MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
112 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6))
113 value |= MIPS_FPIR_F64 | MIPS_FPIR_L | MIPS_FPIR_W;
114 c->fpu_id = value;
115}
116
117/* Determined FPU emulator mask to use for the boot CPU with "nofpu". */
118static unsigned int mips_nofpu_msk31;
119
120/*
121 * Set options for FPU hardware.
122 */
123static void cpu_set_fpu_opts(struct cpuinfo_mips *c)
124{
125 c->fpu_id = cpu_get_fpu_id();
126 mips_nofpu_msk31 = c->fpu_msk31;
127
128 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
129 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
130 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) {
131 if (c->fpu_id & MIPS_FPIR_3D)
132 c->ases |= MIPS_ASE_MIPS3D;
133 if (c->fpu_id & MIPS_FPIR_FREP)
134 c->options |= MIPS_CPU_FRE;
135 }
136
137 cpu_set_fpu_fcsr_mask(c);
138}
139
140/*
141 * Set options for the FPU emulator.
142 */
143static void cpu_set_nofpu_opts(struct cpuinfo_mips *c)
144{
145 c->options &= ~MIPS_CPU_FPU;
146 c->fpu_msk31 = mips_nofpu_msk31;
147
148 cpu_set_nofpu_id(c);
149}
150
34static int mips_fpu_disabled; 151static int mips_fpu_disabled;
35 152
36static int __init fpu_disable(char *s) 153static int __init fpu_disable(char *s)
37{ 154{
38 cpu_data[0].options &= ~MIPS_CPU_FPU; 155 cpu_set_nofpu_opts(&boot_cpu_data);
39 mips_fpu_disabled = 1; 156 mips_fpu_disabled = 1;
40 157
41 return 1; 158 return 1;
@@ -178,41 +295,6 @@ static inline void set_elf_platform(int cpu, const char *plat)
178 __elf_platform = plat; 295 __elf_platform = plat;
179} 296}
180 297
181/*
182 * Get the FPU Implementation/Revision.
183 */
184static inline unsigned long cpu_get_fpu_id(void)
185{
186 unsigned long tmp, fpu_id;
187
188 tmp = read_c0_status();
189 __enable_fpu(FPU_AS_IS);
190 fpu_id = read_32bit_cp1_register(CP1_REVISION);
191 write_c0_status(tmp);
192 return fpu_id;
193}
194
195/*
196 * Check the CPU has an FPU the official way.
197 */
198static inline int __cpu_has_fpu(void)
199{
200 return (cpu_get_fpu_id() & FPIR_IMP_MASK) != FPIR_IMP_NONE;
201}
202
203static inline unsigned long cpu_get_msa_id(void)
204{
205 unsigned long status, msa_id;
206
207 status = read_c0_status();
208 __enable_fpu(FPU_64BIT);
209 enable_msa();
210 msa_id = read_msa_ir();
211 disable_msa();
212 write_c0_status(status);
213 return msa_id;
214}
215
216static inline void cpu_probe_vmbits(struct cpuinfo_mips *c) 298static inline void cpu_probe_vmbits(struct cpuinfo_mips *c)
217{ 299{
218#ifdef __NEED_VMBITS_PROBE 300#ifdef __NEED_VMBITS_PROBE
@@ -441,6 +523,8 @@ static inline unsigned int decode_config3(struct cpuinfo_mips *c)
441 c->htw_seq = 0; 523 c->htw_seq = 0;
442 c->options |= MIPS_CPU_HTW; 524 c->options |= MIPS_CPU_HTW;
443 } 525 }
526 if (config3 & MIPS_CONF3_CDMM)
527 c->options |= MIPS_CPU_CDMM;
444 528
445 return config3 & MIPS_CONF_M; 529 return config3 & MIPS_CONF_M;
446} 530}
@@ -516,6 +600,10 @@ static inline unsigned int decode_config5(struct cpuinfo_mips *c)
516 c->options |= MIPS_CPU_MAAR; 600 c->options |= MIPS_CPU_MAAR;
517 if (config5 & MIPS_CONF5_LLB) 601 if (config5 & MIPS_CONF5_LLB)
518 c->options |= MIPS_CPU_RW_LLB; 602 c->options |= MIPS_CPU_RW_LLB;
603#ifdef CONFIG_XPA
604 if (config5 & MIPS_CONF5_MVH)
605 c->options |= MIPS_CPU_XPA;
606#endif
519 607
520 return config5 & MIPS_CONF_M; 608 return config5 & MIPS_CONF_M;
521} 609}
@@ -575,6 +663,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
575 case PRID_IMP_R2000: 663 case PRID_IMP_R2000:
576 c->cputype = CPU_R2000; 664 c->cputype = CPU_R2000;
577 __cpu_name[cpu] = "R2000"; 665 __cpu_name[cpu] = "R2000";
666 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
578 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE | 667 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
579 MIPS_CPU_NOFPUEX; 668 MIPS_CPU_NOFPUEX;
580 if (__cpu_has_fpu()) 669 if (__cpu_has_fpu())
@@ -594,6 +683,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
594 c->cputype = CPU_R3000; 683 c->cputype = CPU_R3000;
595 __cpu_name[cpu] = "R3000"; 684 __cpu_name[cpu] = "R3000";
596 } 685 }
686 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
597 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE | 687 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
598 MIPS_CPU_NOFPUEX; 688 MIPS_CPU_NOFPUEX;
599 if (__cpu_has_fpu()) 689 if (__cpu_has_fpu())
@@ -642,6 +732,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
642 } 732 }
643 733
644 set_isa(c, MIPS_CPU_ISA_III); 734 set_isa(c, MIPS_CPU_ISA_III);
735 c->fpu_msk31 |= FPU_CSR_CONDX;
645 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 736 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
646 MIPS_CPU_WATCH | MIPS_CPU_VCE | 737 MIPS_CPU_WATCH | MIPS_CPU_VCE |
647 MIPS_CPU_LLSC; 738 MIPS_CPU_LLSC;
@@ -649,6 +740,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
649 break; 740 break;
650 case PRID_IMP_VR41XX: 741 case PRID_IMP_VR41XX:
651 set_isa(c, MIPS_CPU_ISA_III); 742 set_isa(c, MIPS_CPU_ISA_III);
743 c->fpu_msk31 |= FPU_CSR_CONDX;
652 c->options = R4K_OPTS; 744 c->options = R4K_OPTS;
653 c->tlbsize = 32; 745 c->tlbsize = 32;
654 switch (c->processor_id & 0xf0) { 746 switch (c->processor_id & 0xf0) {
@@ -690,6 +782,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
690 c->cputype = CPU_R4300; 782 c->cputype = CPU_R4300;
691 __cpu_name[cpu] = "R4300"; 783 __cpu_name[cpu] = "R4300";
692 set_isa(c, MIPS_CPU_ISA_III); 784 set_isa(c, MIPS_CPU_ISA_III);
785 c->fpu_msk31 |= FPU_CSR_CONDX;
693 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 786 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
694 MIPS_CPU_LLSC; 787 MIPS_CPU_LLSC;
695 c->tlbsize = 32; 788 c->tlbsize = 32;
@@ -698,6 +791,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
698 c->cputype = CPU_R4600; 791 c->cputype = CPU_R4600;
699 __cpu_name[cpu] = "R4600"; 792 __cpu_name[cpu] = "R4600";
700 set_isa(c, MIPS_CPU_ISA_III); 793 set_isa(c, MIPS_CPU_ISA_III);
794 c->fpu_msk31 |= FPU_CSR_CONDX;
701 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 795 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
702 MIPS_CPU_LLSC; 796 MIPS_CPU_LLSC;
703 c->tlbsize = 48; 797 c->tlbsize = 48;
@@ -713,11 +807,13 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
713 c->cputype = CPU_R4650; 807 c->cputype = CPU_R4650;
714 __cpu_name[cpu] = "R4650"; 808 __cpu_name[cpu] = "R4650";
715 set_isa(c, MIPS_CPU_ISA_III); 809 set_isa(c, MIPS_CPU_ISA_III);
810 c->fpu_msk31 |= FPU_CSR_CONDX;
716 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC; 811 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
717 c->tlbsize = 48; 812 c->tlbsize = 48;
718 break; 813 break;
719 #endif 814 #endif
720 case PRID_IMP_TX39: 815 case PRID_IMP_TX39:
816 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
721 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE; 817 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE;
722 818
723 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) { 819 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
@@ -743,6 +839,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
743 c->cputype = CPU_R4700; 839 c->cputype = CPU_R4700;
744 __cpu_name[cpu] = "R4700"; 840 __cpu_name[cpu] = "R4700";
745 set_isa(c, MIPS_CPU_ISA_III); 841 set_isa(c, MIPS_CPU_ISA_III);
842 c->fpu_msk31 |= FPU_CSR_CONDX;
746 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 843 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
747 MIPS_CPU_LLSC; 844 MIPS_CPU_LLSC;
748 c->tlbsize = 48; 845 c->tlbsize = 48;
@@ -751,6 +848,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
751 c->cputype = CPU_TX49XX; 848 c->cputype = CPU_TX49XX;
752 __cpu_name[cpu] = "R49XX"; 849 __cpu_name[cpu] = "R49XX";
753 set_isa(c, MIPS_CPU_ISA_III); 850 set_isa(c, MIPS_CPU_ISA_III);
851 c->fpu_msk31 |= FPU_CSR_CONDX;
754 c->options = R4K_OPTS | MIPS_CPU_LLSC; 852 c->options = R4K_OPTS | MIPS_CPU_LLSC;
755 if (!(c->processor_id & 0x08)) 853 if (!(c->processor_id & 0x08))
756 c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR; 854 c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
@@ -792,6 +890,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
792 c->cputype = CPU_R6000; 890 c->cputype = CPU_R6000;
793 __cpu_name[cpu] = "R6000"; 891 __cpu_name[cpu] = "R6000";
794 set_isa(c, MIPS_CPU_ISA_II); 892 set_isa(c, MIPS_CPU_ISA_II);
893 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
795 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU | 894 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
796 MIPS_CPU_LLSC; 895 MIPS_CPU_LLSC;
797 c->tlbsize = 32; 896 c->tlbsize = 32;
@@ -800,6 +899,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
800 c->cputype = CPU_R6000A; 899 c->cputype = CPU_R6000A;
801 __cpu_name[cpu] = "R6000A"; 900 __cpu_name[cpu] = "R6000A";
802 set_isa(c, MIPS_CPU_ISA_II); 901 set_isa(c, MIPS_CPU_ISA_II);
902 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
803 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU | 903 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
804 MIPS_CPU_LLSC; 904 MIPS_CPU_LLSC;
805 c->tlbsize = 32; 905 c->tlbsize = 32;
@@ -850,8 +950,13 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
850 c->tlbsize = 64; 950 c->tlbsize = 64;
851 break; 951 break;
852 case PRID_IMP_R14000: 952 case PRID_IMP_R14000:
853 c->cputype = CPU_R14000; 953 if (((c->processor_id >> 4) & 0x0f) > 2) {
854 __cpu_name[cpu] = "R14000"; 954 c->cputype = CPU_R16000;
955 __cpu_name[cpu] = "R16000";
956 } else {
957 c->cputype = CPU_R14000;
958 __cpu_name[cpu] = "R14000";
959 }
855 set_isa(c, MIPS_CPU_ISA_IV); 960 set_isa(c, MIPS_CPU_ISA_IV);
856 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | 961 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
857 MIPS_CPU_FPU | MIPS_CPU_32FPR | 962 MIPS_CPU_FPU | MIPS_CPU_32FPR |
@@ -866,12 +971,14 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
866 __cpu_name[cpu] = "ICT Loongson-2"; 971 __cpu_name[cpu] = "ICT Loongson-2";
867 set_elf_platform(cpu, "loongson2e"); 972 set_elf_platform(cpu, "loongson2e");
868 set_isa(c, MIPS_CPU_ISA_III); 973 set_isa(c, MIPS_CPU_ISA_III);
974 c->fpu_msk31 |= FPU_CSR_CONDX;
869 break; 975 break;
870 case PRID_REV_LOONGSON2F: 976 case PRID_REV_LOONGSON2F:
871 c->cputype = CPU_LOONGSON2; 977 c->cputype = CPU_LOONGSON2;
872 __cpu_name[cpu] = "ICT Loongson-2"; 978 __cpu_name[cpu] = "ICT Loongson-2";
873 set_elf_platform(cpu, "loongson2f"); 979 set_elf_platform(cpu, "loongson2f");
874 set_isa(c, MIPS_CPU_ISA_III); 980 set_isa(c, MIPS_CPU_ISA_III);
981 c->fpu_msk31 |= FPU_CSR_CONDX;
875 break; 982 break;
876 case PRID_REV_LOONGSON3A: 983 case PRID_REV_LOONGSON3A:
877 c->cputype = CPU_LOONGSON3; 984 c->cputype = CPU_LOONGSON3;
@@ -1308,6 +1415,9 @@ void cpu_probe(void)
1308 c->cputype = CPU_UNKNOWN; 1415 c->cputype = CPU_UNKNOWN;
1309 c->writecombine = _CACHE_UNCACHED; 1416 c->writecombine = _CACHE_UNCACHED;
1310 1417
1418 c->fpu_csr31 = FPU_CSR_RN;
1419 c->fpu_msk31 = FPU_CSR_RSVD | FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
1420
1311 c->processor_id = read_c0_prid(); 1421 c->processor_id = read_c0_prid();
1312 switch (c->processor_id & PRID_COMP_MASK) { 1422 switch (c->processor_id & PRID_COMP_MASK) {
1313 case PRID_COMP_LEGACY: 1423 case PRID_COMP_LEGACY:
@@ -1364,16 +1474,10 @@ void cpu_probe(void)
1364 ~(1 << MIPS_PWCTL_PWEN_SHIFT)); 1474 ~(1 << MIPS_PWCTL_PWEN_SHIFT));
1365 } 1475 }
1366 1476
1367 if (c->options & MIPS_CPU_FPU) { 1477 if (c->options & MIPS_CPU_FPU)
1368 c->fpu_id = cpu_get_fpu_id(); 1478 cpu_set_fpu_opts(c);
1369 1479 else
1370 if (c->isa_level & cpu_has_mips_r) { 1480 cpu_set_nofpu_opts(c);
1371 if (c->fpu_id & MIPS_FPIR_3D)
1372 c->ases |= MIPS_ASE_MIPS3D;
1373 if (c->fpu_id & MIPS_FPIR_FREP)
1374 c->options |= MIPS_CPU_FRE;
1375 }
1376 }
1377 1481
1378 if (cpu_has_mips_r2_r6) { 1482 if (cpu_has_mips_r2_r6) {
1379 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1; 1483 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
diff --git a/arch/mips/kernel/csrc-bcm1480.c b/arch/mips/kernel/csrc-bcm1480.c
index 468f3eba4132..7f65b53d1b24 100644
--- a/arch/mips/kernel/csrc-bcm1480.c
+++ b/arch/mips/kernel/csrc-bcm1480.c
@@ -10,12 +10,9 @@
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details. 12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
17 */ 13 */
18#include <linux/clocksource.h> 14#include <linux/clocksource.h>
15#include <linux/sched_clock.h>
19 16
20#include <asm/addrspace.h> 17#include <asm/addrspace.h>
21#include <asm/io.h> 18#include <asm/io.h>
@@ -41,6 +38,11 @@ struct clocksource bcm1480_clocksource = {
41 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 38 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
42}; 39};
43 40
41static u64 notrace sb1480_read_sched_clock(void)
42{
43 return __raw_readq(IOADDR(A_SCD_ZBBUS_CYCLE_COUNT));
44}
45
44void __init sb1480_clocksource_init(void) 46void __init sb1480_clocksource_init(void)
45{ 47{
46 struct clocksource *cs = &bcm1480_clocksource; 48 struct clocksource *cs = &bcm1480_clocksource;
@@ -50,4 +52,6 @@ void __init sb1480_clocksource_init(void)
50 plldiv = G_BCM1480_SYS_PLL_DIV(__raw_readq(IOADDR(A_SCD_SYSTEM_CFG))); 52 plldiv = G_BCM1480_SYS_PLL_DIV(__raw_readq(IOADDR(A_SCD_SYSTEM_CFG)));
51 zbbus = ((plldiv >> 1) * 50000000) + ((plldiv & 1) * 25000000); 53 zbbus = ((plldiv >> 1) * 50000000) + ((plldiv & 1) * 25000000);
52 clocksource_register_hz(cs, zbbus); 54 clocksource_register_hz(cs, zbbus);
55
56 sched_clock_register(sb1480_read_sched_clock, 64, zbbus);
53} 57}
diff --git a/arch/mips/kernel/csrc-ioasic.c b/arch/mips/kernel/csrc-ioasic.c
index 6cbbf6e106b9..722f5589cd1d 100644
--- a/arch/mips/kernel/csrc-ioasic.c
+++ b/arch/mips/kernel/csrc-ioasic.c
@@ -12,12 +12,9 @@
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details. 14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
19 */ 15 */
20#include <linux/clocksource.h> 16#include <linux/clocksource.h>
17#include <linux/sched_clock.h>
21#include <linux/init.h> 18#include <linux/init.h>
22 19
23#include <asm/ds1287.h> 20#include <asm/ds1287.h>
@@ -37,6 +34,11 @@ static struct clocksource clocksource_dec = {
37 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 34 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
38}; 35};
39 36
37static u64 notrace dec_ioasic_read_sched_clock(void)
38{
39 return ioasic_read(IO_REG_FCTR);
40}
41
40int __init dec_ioasic_clocksource_init(void) 42int __init dec_ioasic_clocksource_init(void)
41{ 43{
42 unsigned int freq; 44 unsigned int freq;
@@ -65,5 +67,8 @@ int __init dec_ioasic_clocksource_init(void)
65 67
66 clocksource_dec.rating = 200 + freq / 10000000; 68 clocksource_dec.rating = 200 + freq / 10000000;
67 clocksource_register_hz(&clocksource_dec, freq); 69 clocksource_register_hz(&clocksource_dec, freq);
70
71 sched_clock_register(dec_ioasic_read_sched_clock, 32, freq);
72
68 return 0; 73 return 0;
69} 74}
diff --git a/arch/mips/kernel/csrc-r4k.c b/arch/mips/kernel/csrc-r4k.c
index decd1fa38d55..e5ed7ada1433 100644
--- a/arch/mips/kernel/csrc-r4k.c
+++ b/arch/mips/kernel/csrc-r4k.c
@@ -7,6 +7,7 @@
7 */ 7 */
8#include <linux/clocksource.h> 8#include <linux/clocksource.h>
9#include <linux/init.h> 9#include <linux/init.h>
10#include <linux/sched_clock.h>
10 11
11#include <asm/time.h> 12#include <asm/time.h>
12 13
@@ -22,6 +23,11 @@ static struct clocksource clocksource_mips = {
22 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 23 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
23}; 24};
24 25
26static u64 notrace r4k_read_sched_clock(void)
27{
28 return read_c0_count();
29}
30
25int __init init_r4k_clocksource(void) 31int __init init_r4k_clocksource(void)
26{ 32{
27 if (!cpu_has_counter || !mips_hpt_frequency) 33 if (!cpu_has_counter || !mips_hpt_frequency)
@@ -32,5 +38,7 @@ int __init init_r4k_clocksource(void)
32 38
33 clocksource_register_hz(&clocksource_mips, mips_hpt_frequency); 39 clocksource_register_hz(&clocksource_mips, mips_hpt_frequency);
34 40
41 sched_clock_register(r4k_read_sched_clock, 32, mips_hpt_frequency);
42
35 return 0; 43 return 0;
36} 44}
diff --git a/arch/mips/kernel/csrc-sb1250.c b/arch/mips/kernel/csrc-sb1250.c
index 6ecb77d82063..d915652b4d56 100644
--- a/arch/mips/kernel/csrc-sb1250.c
+++ b/arch/mips/kernel/csrc-sb1250.c
@@ -10,12 +10,9 @@
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details. 12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
17 */ 13 */
18#include <linux/clocksource.h> 14#include <linux/clocksource.h>
15#include <linux/sched_clock.h>
19 16
20#include <asm/addrspace.h> 17#include <asm/addrspace.h>
21#include <asm/io.h> 18#include <asm/io.h>
@@ -33,15 +30,22 @@
33 * The HPT is free running from SB1250_HPT_VALUE down to 0 then starts over 30 * The HPT is free running from SB1250_HPT_VALUE down to 0 then starts over
34 * again. 31 * again.
35 */ 32 */
36static cycle_t sb1250_hpt_read(struct clocksource *cs) 33static inline cycle_t sb1250_hpt_get_cycles(void)
37{ 34{
38 unsigned int count; 35 unsigned int count;
36 void __iomem *addr;
39 37
40 count = G_SCD_TIMER_CNT(__raw_readq(IOADDR(A_SCD_TIMER_REGISTER(SB1250_HPT_NUM, R_SCD_TIMER_CNT)))); 38 addr = IOADDR(A_SCD_TIMER_REGISTER(SB1250_HPT_NUM, R_SCD_TIMER_CNT));
39 count = G_SCD_TIMER_CNT(__raw_readq(addr));
41 40
42 return SB1250_HPT_VALUE - count; 41 return SB1250_HPT_VALUE - count;
43} 42}
44 43
44static cycle_t sb1250_hpt_read(struct clocksource *cs)
45{
46 return sb1250_hpt_get_cycles();
47}
48
45struct clocksource bcm1250_clocksource = { 49struct clocksource bcm1250_clocksource = {
46 .name = "bcm1250-counter-3", 50 .name = "bcm1250-counter-3",
47 .rating = 200, 51 .rating = 200,
@@ -50,6 +54,11 @@ struct clocksource bcm1250_clocksource = {
50 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 54 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
51}; 55};
52 56
57static u64 notrace sb1250_read_sched_clock(void)
58{
59 return sb1250_hpt_get_cycles();
60}
61
53void __init sb1250_clocksource_init(void) 62void __init sb1250_clocksource_init(void)
54{ 63{
55 struct clocksource *cs = &bcm1250_clocksource; 64 struct clocksource *cs = &bcm1250_clocksource;
@@ -66,4 +75,6 @@ void __init sb1250_clocksource_init(void)
66 R_SCD_TIMER_CFG))); 75 R_SCD_TIMER_CFG)));
67 76
68 clocksource_register_hz(cs, V_SCD_TIMER_FREQ); 77 clocksource_register_hz(cs, V_SCD_TIMER_FREQ);
78
79 sched_clock_register(sb1250_read_sched_clock, 23, V_SCD_TIMER_FREQ);
69} 80}
diff --git a/arch/mips/kernel/elf.c b/arch/mips/kernel/elf.c
index d2c09f6475c5..be4899f3c393 100644
--- a/arch/mips/kernel/elf.c
+++ b/arch/mips/kernel/elf.c
@@ -131,16 +131,6 @@ int arch_elf_pt_proc(void *_ehdr, void *_phdr, struct file *elf,
131 return 0; 131 return 0;
132} 132}
133 133
134static inline unsigned get_fp_abi(int in_abi)
135{
136 /* If the ABI requirement is provided, simply return that */
137 if (in_abi != MIPS_ABI_FP_UNKNOWN)
138 return in_abi;
139
140 /* Unknown ABI */
141 return MIPS_ABI_FP_UNKNOWN;
142}
143
144int arch_check_elf(void *_ehdr, bool has_interpreter, 134int arch_check_elf(void *_ehdr, bool has_interpreter,
145 struct arch_elf_state *state) 135 struct arch_elf_state *state)
146{ 136{
@@ -151,10 +141,10 @@ int arch_check_elf(void *_ehdr, bool has_interpreter,
151 if (!config_enabled(CONFIG_MIPS_O32_FP64_SUPPORT)) 141 if (!config_enabled(CONFIG_MIPS_O32_FP64_SUPPORT))
152 return 0; 142 return 0;
153 143
154 fp_abi = get_fp_abi(state->fp_abi); 144 fp_abi = state->fp_abi;
155 145
156 if (has_interpreter) { 146 if (has_interpreter) {
157 interp_fp_abi = get_fp_abi(state->interp_fp_abi); 147 interp_fp_abi = state->interp_fp_abi;
158 148
159 abi0 = min(fp_abi, interp_fp_abi); 149 abi0 = min(fp_abi, interp_fp_abi);
160 abi1 = max(fp_abi, interp_fp_abi); 150 abi1 = max(fp_abi, interp_fp_abi);
diff --git a/arch/mips/kernel/entry.S b/arch/mips/kernel/entry.S
index af41ba6db960..7791840cf22c 100644
--- a/arch/mips/kernel/entry.S
+++ b/arch/mips/kernel/entry.S
@@ -10,6 +10,7 @@
10 10
11#include <asm/asm.h> 11#include <asm/asm.h>
12#include <asm/asmmacro.h> 12#include <asm/asmmacro.h>
13#include <asm/compiler.h>
13#include <asm/regdef.h> 14#include <asm/regdef.h>
14#include <asm/mipsregs.h> 15#include <asm/mipsregs.h>
15#include <asm/stackframe.h> 16#include <asm/stackframe.h>
@@ -185,7 +186,7 @@ syscall_exit_work:
185 * For C code use the inline version named instruction_hazard(). 186 * For C code use the inline version named instruction_hazard().
186 */ 187 */
187LEAF(mips_ihb) 188LEAF(mips_ihb)
188 .set mips32r2 189 .set MIPS_ISA_LEVEL_RAW
189 jr.hb ra 190 jr.hb ra
190 nop 191 nop
191 END(mips_ihb) 192 END(mips_ihb)
diff --git a/arch/mips/kernel/idle.c b/arch/mips/kernel/idle.c
index 368c88b7eb6c..e4f62b7875d2 100644
--- a/arch/mips/kernel/idle.c
+++ b/arch/mips/kernel/idle.c
@@ -176,6 +176,17 @@ void __init check_wait(void)
176 cpu_wait = rm7k_wait_irqoff; 176 cpu_wait = rm7k_wait_irqoff;
177 break; 177 break;
178 178
179 case CPU_PROAPTIV:
180 case CPU_P5600:
181 /*
182 * Incoming Fast Debug Channel (FDC) data during a wait
183 * instruction causes the wait never to resume, even if an
184 * interrupt is received. Avoid using wait at all if FDC data is
185 * likely to be received.
186 */
187 if (IS_ENABLED(CONFIG_MIPS_EJTAG_FDC_TTY))
188 break;
189 /* fall through */
179 case CPU_M14KC: 190 case CPU_M14KC:
180 case CPU_M14KEC: 191 case CPU_M14KEC:
181 case CPU_24K: 192 case CPU_24K:
@@ -183,8 +194,6 @@ void __init check_wait(void)
183 case CPU_1004K: 194 case CPU_1004K:
184 case CPU_1074K: 195 case CPU_1074K:
185 case CPU_INTERAPTIV: 196 case CPU_INTERAPTIV:
186 case CPU_PROAPTIV:
187 case CPU_P5600:
188 case CPU_M5150: 197 case CPU_M5150:
189 case CPU_QEMU_GENERIC: 198 case CPU_QEMU_GENERIC:
190 cpu_wait = r4k_wait; 199 cpu_wait = r4k_wait;
diff --git a/arch/mips/kernel/mips-r2-to-r6-emul.c b/arch/mips/kernel/mips-r2-to-r6-emul.c
index 64d17e41093b..f2977f00911b 100644
--- a/arch/mips/kernel/mips-r2-to-r6-emul.c
+++ b/arch/mips/kernel/mips-r2-to-r6-emul.c
@@ -187,7 +187,7 @@ static inline int mipsr6_emul(struct pt_regs *regs, u32 ir)
187} 187}
188 188
189/** 189/**
190 * movt_func - Emulate a MOVT instruction 190 * movf_func - Emulate a MOVF instruction
191 * @regs: Process register set 191 * @regs: Process register set
192 * @ir: Instruction 192 * @ir: Instruction
193 * 193 *
@@ -200,9 +200,12 @@ static int movf_func(struct pt_regs *regs, u32 ir)
200 200
201 csr = current->thread.fpu.fcr31; 201 csr = current->thread.fpu.fcr31;
202 cond = fpucondbit[MIPSInst_RT(ir) >> 2]; 202 cond = fpucondbit[MIPSInst_RT(ir) >> 2];
203
203 if (((csr & cond) == 0) && MIPSInst_RD(ir)) 204 if (((csr & cond) == 0) && MIPSInst_RD(ir))
204 regs->regs[MIPSInst_RD(ir)] = regs->regs[MIPSInst_RS(ir)]; 205 regs->regs[MIPSInst_RD(ir)] = regs->regs[MIPSInst_RS(ir)];
206
205 MIPS_R2_STATS(movs); 207 MIPS_R2_STATS(movs);
208
206 return 0; 209 return 0;
207} 210}
208 211
@@ -895,8 +898,9 @@ static inline int mipsr2_find_op_func(struct pt_regs *regs, u32 inst,
895 * mipsr2_decoder: Decode and emulate a MIPS R2 instruction 898 * mipsr2_decoder: Decode and emulate a MIPS R2 instruction
896 * @regs: Process register set 899 * @regs: Process register set
897 * @inst: Instruction to decode and emulate 900 * @inst: Instruction to decode and emulate
901 * @fcr31: Floating Point Control and Status Register returned
898 */ 902 */
899int mipsr2_decoder(struct pt_regs *regs, u32 inst) 903int mipsr2_decoder(struct pt_regs *regs, u32 inst, unsigned long *fcr31)
900{ 904{
901 int err = 0; 905 int err = 0;
902 unsigned long vaddr; 906 unsigned long vaddr;
@@ -1165,6 +1169,13 @@ fpu_emul:
1165 1169
1166 err = fpu_emulator_cop1Handler(regs, &current->thread.fpu, 0, 1170 err = fpu_emulator_cop1Handler(regs, &current->thread.fpu, 0,
1167 &fault_addr); 1171 &fault_addr);
1172 *fcr31 = current->thread.fpu.fcr31;
1173
1174 /*
1175 * We can't allow the emulated instruction to leave any of
1176 * the cause bits set in $fcr31.
1177 */
1178 current->thread.fpu.fcr31 &= ~FPU_CSR_ALL_X;
1168 1179
1169 /* 1180 /*
1170 * this is a tricky issue - lose_fpu() uses LL/SC atomics 1181 * this is a tricky issue - lose_fpu() uses LL/SC atomics
diff --git a/arch/mips/kernel/perf_event_mipsxx.c b/arch/mips/kernel/perf_event_mipsxx.c
index 9466184d0039..cc1b6fadf089 100644
--- a/arch/mips/kernel/perf_event_mipsxx.c
+++ b/arch/mips/kernel/perf_event_mipsxx.c
@@ -558,8 +558,10 @@ static int mipspmu_get_irq(void)
558 if (mipspmu.irq >= 0) { 558 if (mipspmu.irq >= 0) {
559 /* Request my own irq handler. */ 559 /* Request my own irq handler. */
560 err = request_irq(mipspmu.irq, mipsxx_pmu_handle_irq, 560 err = request_irq(mipspmu.irq, mipsxx_pmu_handle_irq,
561 IRQF_PERCPU | IRQF_NOBALANCING | IRQF_NO_THREAD, 561 IRQF_PERCPU | IRQF_NOBALANCING |
562 "mips_perf_pmu", NULL); 562 IRQF_NO_THREAD | IRQF_NO_SUSPEND |
563 IRQF_SHARED,
564 "mips_perf_pmu", &mipspmu);
563 if (err) { 565 if (err) {
564 pr_warn("Unable to request IRQ%d for MIPS performance counters!\n", 566 pr_warn("Unable to request IRQ%d for MIPS performance counters!\n",
565 mipspmu.irq); 567 mipspmu.irq);
@@ -582,7 +584,7 @@ static int mipspmu_get_irq(void)
582static void mipspmu_free_irq(void) 584static void mipspmu_free_irq(void)
583{ 585{
584 if (mipspmu.irq >= 0) 586 if (mipspmu.irq >= 0)
585 free_irq(mipspmu.irq, NULL); 587 free_irq(mipspmu.irq, &mipspmu);
586 else if (cp0_perfcount_irq < 0) 588 else if (cp0_perfcount_irq < 0)
587 perf_irq = save_perf_irq; 589 perf_irq = save_perf_irq;
588} 590}
@@ -775,6 +777,7 @@ static int n_counters(void)
775 777
776 case CPU_R12000: 778 case CPU_R12000:
777 case CPU_R14000: 779 case CPU_R14000:
780 case CPU_R16000:
778 counters = 4; 781 counters = 4;
779 break; 782 break;
780 783
@@ -822,6 +825,13 @@ static const struct mips_perf_event mipsxxcore_event_map2
822 [PERF_COUNT_HW_BRANCH_MISSES] = { 0x27, CNTR_ODD, T }, 825 [PERF_COUNT_HW_BRANCH_MISSES] = { 0x27, CNTR_ODD, T },
823}; 826};
824 827
828static const struct mips_perf_event loongson3_event_map[PERF_COUNT_HW_MAX] = {
829 [PERF_COUNT_HW_CPU_CYCLES] = { 0x00, CNTR_EVEN },
830 [PERF_COUNT_HW_INSTRUCTIONS] = { 0x00, CNTR_ODD },
831 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x01, CNTR_EVEN },
832 [PERF_COUNT_HW_BRANCH_MISSES] = { 0x01, CNTR_ODD },
833};
834
825static const struct mips_perf_event octeon_event_map[PERF_COUNT_HW_MAX] = { 835static const struct mips_perf_event octeon_event_map[PERF_COUNT_HW_MAX] = {
826 [PERF_COUNT_HW_CPU_CYCLES] = { 0x01, CNTR_ALL }, 836 [PERF_COUNT_HW_CPU_CYCLES] = { 0x01, CNTR_ALL },
827 [PERF_COUNT_HW_INSTRUCTIONS] = { 0x03, CNTR_ALL }, 837 [PERF_COUNT_HW_INSTRUCTIONS] = { 0x03, CNTR_ALL },
@@ -1005,6 +1015,61 @@ static const struct mips_perf_event mipsxxcore_cache_map2
1005}, 1015},
1006}; 1016};
1007 1017
1018static const struct mips_perf_event loongson3_cache_map
1019 [PERF_COUNT_HW_CACHE_MAX]
1020 [PERF_COUNT_HW_CACHE_OP_MAX]
1021 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
1022[C(L1D)] = {
1023 /*
1024 * Like some other architectures (e.g. ARM), the performance
1025 * counters don't differentiate between read and write
1026 * accesses/misses, so this isn't strictly correct, but it's the
1027 * best we can do. Writes and reads get combined.
1028 */
1029 [C(OP_READ)] = {
1030 [C(RESULT_MISS)] = { 0x04, CNTR_ODD },
1031 },
1032 [C(OP_WRITE)] = {
1033 [C(RESULT_MISS)] = { 0x04, CNTR_ODD },
1034 },
1035},
1036[C(L1I)] = {
1037 [C(OP_READ)] = {
1038 [C(RESULT_MISS)] = { 0x04, CNTR_EVEN },
1039 },
1040 [C(OP_WRITE)] = {
1041 [C(RESULT_MISS)] = { 0x04, CNTR_EVEN },
1042 },
1043},
1044[C(DTLB)] = {
1045 [C(OP_READ)] = {
1046 [C(RESULT_MISS)] = { 0x09, CNTR_ODD },
1047 },
1048 [C(OP_WRITE)] = {
1049 [C(RESULT_MISS)] = { 0x09, CNTR_ODD },
1050 },
1051},
1052[C(ITLB)] = {
1053 [C(OP_READ)] = {
1054 [C(RESULT_MISS)] = { 0x0c, CNTR_ODD },
1055 },
1056 [C(OP_WRITE)] = {
1057 [C(RESULT_MISS)] = { 0x0c, CNTR_ODD },
1058 },
1059},
1060[C(BPU)] = {
1061 /* Using the same code for *HW_BRANCH* */
1062 [C(OP_READ)] = {
1063 [C(RESULT_ACCESS)] = { 0x02, CNTR_EVEN },
1064 [C(RESULT_MISS)] = { 0x02, CNTR_ODD },
1065 },
1066 [C(OP_WRITE)] = {
1067 [C(RESULT_ACCESS)] = { 0x02, CNTR_EVEN },
1068 [C(RESULT_MISS)] = { 0x02, CNTR_ODD },
1069 },
1070},
1071};
1072
1008/* BMIPS5000 */ 1073/* BMIPS5000 */
1009static const struct mips_perf_event bmips5000_cache_map 1074static const struct mips_perf_event bmips5000_cache_map
1010 [PERF_COUNT_HW_CACHE_MAX] 1075 [PERF_COUNT_HW_CACHE_MAX]
@@ -1539,6 +1604,10 @@ static const struct mips_perf_event *mipsxx_pmu_map_raw_event(u64 config)
1539 else 1604 else
1540 raw_event.cntr_mask = 1605 raw_event.cntr_mask =
1541 raw_id > 127 ? CNTR_ODD : CNTR_EVEN; 1606 raw_id > 127 ? CNTR_ODD : CNTR_EVEN;
1607 break;
1608 case CPU_LOONGSON3:
1609 raw_event.cntr_mask = raw_id > 127 ? CNTR_ODD : CNTR_EVEN;
1610 break;
1542 } 1611 }
1543 1612
1544 raw_event.event_id = base_id; 1613 raw_event.event_id = base_id;
@@ -1615,8 +1684,7 @@ init_hw_perf_events(void)
1615 1684
1616 if (get_c0_perfcount_int) 1685 if (get_c0_perfcount_int)
1617 irq = get_c0_perfcount_int(); 1686 irq = get_c0_perfcount_int();
1618 else if ((cp0_perfcount_irq >= 0) && 1687 else if (cp0_perfcount_irq >= 0)
1619 (cp0_compare_irq != cp0_perfcount_irq))
1620 irq = MIPS_CPU_IRQ_BASE + cp0_perfcount_irq; 1688 irq = MIPS_CPU_IRQ_BASE + cp0_perfcount_irq;
1621 else 1689 else
1622 irq = -1; 1690 irq = -1;
@@ -1669,6 +1737,11 @@ init_hw_perf_events(void)
1669 mipspmu.general_event_map = &mipsxxcore_event_map; 1737 mipspmu.general_event_map = &mipsxxcore_event_map;
1670 mipspmu.cache_event_map = &mipsxxcore_cache_map; 1738 mipspmu.cache_event_map = &mipsxxcore_cache_map;
1671 break; 1739 break;
1740 case CPU_LOONGSON3:
1741 mipspmu.name = "mips/loongson3";
1742 mipspmu.general_event_map = &loongson3_event_map;
1743 mipspmu.cache_event_map = &loongson3_cache_map;
1744 break;
1672 case CPU_CAVIUM_OCTEON: 1745 case CPU_CAVIUM_OCTEON:
1673 case CPU_CAVIUM_OCTEON_PLUS: 1746 case CPU_CAVIUM_OCTEON_PLUS:
1674 case CPU_CAVIUM_OCTEON2: 1747 case CPU_CAVIUM_OCTEON2:
diff --git a/arch/mips/kernel/proc.c b/arch/mips/kernel/proc.c
index 130af7d26a9c..298b2b773d12 100644
--- a/arch/mips/kernel/proc.c
+++ b/arch/mips/kernel/proc.c
@@ -120,6 +120,7 @@ static int show_cpuinfo(struct seq_file *m, void *v)
120 if (cpu_has_msa) seq_printf(m, "%s", " msa"); 120 if (cpu_has_msa) seq_printf(m, "%s", " msa");
121 if (cpu_has_eva) seq_printf(m, "%s", " eva"); 121 if (cpu_has_eva) seq_printf(m, "%s", " eva");
122 if (cpu_has_htw) seq_printf(m, "%s", " htw"); 122 if (cpu_has_htw) seq_printf(m, "%s", " htw");
123 if (cpu_has_xpa) seq_printf(m, "%s", " xpa");
123 seq_printf(m, "\n"); 124 seq_printf(m, "\n");
124 125
125 if (cpu_has_mmips) { 126 if (cpu_has_mmips) {
diff --git a/arch/mips/kernel/process.c b/arch/mips/kernel/process.c
index bf85cc180d91..d295bd1e4996 100644
--- a/arch/mips/kernel/process.c
+++ b/arch/mips/kernel/process.c
@@ -107,8 +107,11 @@ int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
107 return 0; 107 return 0;
108} 108}
109 109
110/*
111 * Copy architecture-specific thread state
112 */
110int copy_thread(unsigned long clone_flags, unsigned long usp, 113int copy_thread(unsigned long clone_flags, unsigned long usp,
111 unsigned long arg, struct task_struct *p) 114 unsigned long kthread_arg, struct task_struct *p)
112{ 115{
113 struct thread_info *ti = task_thread_info(p); 116 struct thread_info *ti = task_thread_info(p);
114 struct pt_regs *childregs, *regs = current_pt_regs(); 117 struct pt_regs *childregs, *regs = current_pt_regs();
@@ -123,11 +126,12 @@ int copy_thread(unsigned long clone_flags, unsigned long usp,
123 childksp = (unsigned long) childregs; 126 childksp = (unsigned long) childregs;
124 p->thread.cp0_status = read_c0_status() & ~(ST0_CU2|ST0_CU1); 127 p->thread.cp0_status = read_c0_status() & ~(ST0_CU2|ST0_CU1);
125 if (unlikely(p->flags & PF_KTHREAD)) { 128 if (unlikely(p->flags & PF_KTHREAD)) {
129 /* kernel thread */
126 unsigned long status = p->thread.cp0_status; 130 unsigned long status = p->thread.cp0_status;
127 memset(childregs, 0, sizeof(struct pt_regs)); 131 memset(childregs, 0, sizeof(struct pt_regs));
128 ti->addr_limit = KERNEL_DS; 132 ti->addr_limit = KERNEL_DS;
129 p->thread.reg16 = usp; /* fn */ 133 p->thread.reg16 = usp; /* fn */
130 p->thread.reg17 = arg; 134 p->thread.reg17 = kthread_arg;
131 p->thread.reg29 = childksp; 135 p->thread.reg29 = childksp;
132 p->thread.reg31 = (unsigned long) ret_from_kernel_thread; 136 p->thread.reg31 = (unsigned long) ret_from_kernel_thread;
133#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) 137#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
@@ -139,6 +143,8 @@ int copy_thread(unsigned long clone_flags, unsigned long usp,
139 childregs->cp0_status = status; 143 childregs->cp0_status = status;
140 return 0; 144 return 0;
141 } 145 }
146
147 /* user thread */
142 *childregs = *regs; 148 *childregs = *regs;
143 childregs->regs[7] = 0; /* Clear error flag */ 149 childregs->regs[7] = 0; /* Clear error flag */
144 childregs->regs[2] = 0; /* Child gets zero as return value */ 150 childregs->regs[2] = 0; /* Child gets zero as return value */
diff --git a/arch/mips/kernel/prom.c b/arch/mips/kernel/prom.c
index 452d4350ce42..e303cb1ef2f4 100644
--- a/arch/mips/kernel/prom.c
+++ b/arch/mips/kernel/prom.c
@@ -64,7 +64,10 @@ int __init __dt_register_buses(const char *bus0, const char *bus1)
64 panic("device tree not present"); 64 panic("device tree not present");
65 65
66 strlcpy(of_ids[0].compatible, bus0, sizeof(of_ids[0].compatible)); 66 strlcpy(of_ids[0].compatible, bus0, sizeof(of_ids[0].compatible));
67 strlcpy(of_ids[1].compatible, bus1, sizeof(of_ids[1].compatible)); 67 if (bus1) {
68 strlcpy(of_ids[1].compatible, bus1,
69 sizeof(of_ids[1].compatible));
70 }
68 71
69 if (of_platform_populate(NULL, of_ids, NULL, NULL)) 72 if (of_platform_populate(NULL, of_ids, NULL, NULL))
70 panic("failed to populate DT"); 73 panic("failed to populate DT");
diff --git a/arch/mips/kernel/ptrace.c b/arch/mips/kernel/ptrace.c
index 7da6e324dd35..d544e774eea6 100644
--- a/arch/mips/kernel/ptrace.c
+++ b/arch/mips/kernel/ptrace.c
@@ -32,6 +32,7 @@
32 32
33#include <asm/byteorder.h> 33#include <asm/byteorder.h>
34#include <asm/cpu.h> 34#include <asm/cpu.h>
35#include <asm/cpu-info.h>
35#include <asm/dsp.h> 36#include <asm/dsp.h>
36#include <asm/fpu.h> 37#include <asm/fpu.h>
37#include <asm/mipsregs.h> 38#include <asm/mipsregs.h>
@@ -157,6 +158,9 @@ int ptrace_setfpregs(struct task_struct *child, __u32 __user *data)
157{ 158{
158 union fpureg *fregs; 159 union fpureg *fregs;
159 u64 fpr_val; 160 u64 fpr_val;
161 u32 fcr31;
162 u32 value;
163 u32 mask;
160 int i; 164 int i;
161 165
162 if (!access_ok(VERIFY_READ, data, 33 * 8)) 166 if (!access_ok(VERIFY_READ, data, 33 * 8))
@@ -170,8 +174,10 @@ int ptrace_setfpregs(struct task_struct *child, __u32 __user *data)
170 set_fpr64(&fregs[i], 0, fpr_val); 174 set_fpr64(&fregs[i], 0, fpr_val);
171 } 175 }
172 176
173 __get_user(child->thread.fpu.fcr31, data + 64); 177 __get_user(value, data + 64);
174 child->thread.fpu.fcr31 &= ~FPU_CSR_ALL_X; 178 fcr31 = child->thread.fpu.fcr31;
179 mask = current_cpu_data.fpu_msk31;
180 child->thread.fpu.fcr31 = (value & ~mask) | (fcr31 & mask);
175 181
176 /* FIR may not be written. */ 182 /* FIR may not be written. */
177 183
diff --git a/arch/mips/kernel/r2300_switch.S b/arch/mips/kernel/r2300_switch.S
index 435ea652f5fa..5087a4b72e6b 100644
--- a/arch/mips/kernel/r2300_switch.S
+++ b/arch/mips/kernel/r2300_switch.S
@@ -115,11 +115,9 @@ LEAF(_restore_fp)
115 * the property that no matter whether considered as single or as double 115 * the property that no matter whether considered as single or as double
116 * precision represents signaling NANS. 116 * precision represents signaling NANS.
117 * 117 *
118 * We initialize fcr31 to rounding to nearest, no exceptions. 118 * The value to initialize fcr31 to comes in $a0.
119 */ 119 */
120 120
121#define FPU_DEFAULT 0x00000000
122
123 .set push 121 .set push
124 SET_HARDFLOAT 122 SET_HARDFLOAT
125 123
@@ -129,8 +127,7 @@ LEAF(_init_fpu)
129 or t0, t1 127 or t0, t1
130 mtc0 t0, CP0_STATUS 128 mtc0 t0, CP0_STATUS
131 129
132 li t1, FPU_DEFAULT 130 ctc1 a0, fcr31
133 ctc1 t1, fcr31
134 131
135 li t0, -1 132 li t0, -1
136 133
diff --git a/arch/mips/kernel/r4k_switch.S b/arch/mips/kernel/r4k_switch.S
index 3b1a36f13a7d..04cbbde3521b 100644
--- a/arch/mips/kernel/r4k_switch.S
+++ b/arch/mips/kernel/r4k_switch.S
@@ -165,11 +165,9 @@ LEAF(_init_msa_upper)
165 * the property that no matter whether considered as single or as double 165 * the property that no matter whether considered as single or as double
166 * precision represents signaling NANS. 166 * precision represents signaling NANS.
167 * 167 *
168 * We initialize fcr31 to rounding to nearest, no exceptions. 168 * The value to initialize fcr31 to comes in $a0.
169 */ 169 */
170 170
171#define FPU_DEFAULT 0x00000000
172
173 .set push 171 .set push
174 SET_HARDFLOAT 172 SET_HARDFLOAT
175 173
@@ -180,8 +178,7 @@ LEAF(_init_fpu)
180 mtc0 t0, CP0_STATUS 178 mtc0 t0, CP0_STATUS
181 enable_fpu_hazard 179 enable_fpu_hazard
182 180
183 li t1, FPU_DEFAULT 181 ctc1 a0, fcr31
184 ctc1 t1, fcr31
185 182
186 li t1, -1 # SNaN 183 li t1, -1 # SNaN
187 184
diff --git a/arch/mips/kernel/reset.c b/arch/mips/kernel/reset.c
index 07fc5244aed4..7c746d3458e7 100644
--- a/arch/mips/kernel/reset.c
+++ b/arch/mips/kernel/reset.c
@@ -11,6 +11,7 @@
11#include <linux/pm.h> 11#include <linux/pm.h>
12#include <linux/types.h> 12#include <linux/types.h>
13#include <linux/reboot.h> 13#include <linux/reboot.h>
14#include <linux/delay.h>
14 15
15#include <asm/reboot.h> 16#include <asm/reboot.h>
16 17
@@ -29,16 +30,40 @@ void machine_restart(char *command)
29{ 30{
30 if (_machine_restart) 31 if (_machine_restart)
31 _machine_restart(command); 32 _machine_restart(command);
33
34#ifdef CONFIG_SMP
35 preempt_disable();
36 smp_send_stop();
37#endif
38 do_kernel_restart(command);
39 mdelay(1000);
40 pr_emerg("Reboot failed -- System halted\n");
41 local_irq_disable();
42 while (1);
32} 43}
33 44
34void machine_halt(void) 45void machine_halt(void)
35{ 46{
36 if (_machine_halt) 47 if (_machine_halt)
37 _machine_halt(); 48 _machine_halt();
49
50#ifdef CONFIG_SMP
51 preempt_disable();
52 smp_send_stop();
53#endif
54 local_irq_disable();
55 while (1);
38} 56}
39 57
40void machine_power_off(void) 58void machine_power_off(void)
41{ 59{
42 if (pm_power_off) 60 if (pm_power_off)
43 pm_power_off(); 61 pm_power_off();
62
63#ifdef CONFIG_SMP
64 preempt_disable();
65 smp_send_stop();
66#endif
67 local_irq_disable();
68 while (1);
44} 69}
diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c
index 058929041368..be73c491182b 100644
--- a/arch/mips/kernel/setup.c
+++ b/arch/mips/kernel/setup.c
@@ -31,6 +31,7 @@
31#include <asm/bootinfo.h> 31#include <asm/bootinfo.h>
32#include <asm/bugs.h> 32#include <asm/bugs.h>
33#include <asm/cache.h> 33#include <asm/cache.h>
34#include <asm/cdmm.h>
34#include <asm/cpu.h> 35#include <asm/cpu.h>
35#include <asm/sections.h> 36#include <asm/sections.h>
36#include <asm/setup.h> 37#include <asm/setup.h>
@@ -763,6 +764,7 @@ void __init setup_arch(char **cmdline_p)
763 cpu_probe(); 764 cpu_probe();
764 prom_init(); 765 prom_init();
765 766
767 setup_early_fdc_console();
766#ifdef CONFIG_EARLY_PRINTK 768#ifdef CONFIG_EARLY_PRINTK
767 setup_early_printk(); 769 setup_early_printk();
768#endif 770#endif
diff --git a/arch/mips/kernel/smp-cps.c b/arch/mips/kernel/smp-cps.c
index bed7590e475f..d5589bedd0a4 100644
--- a/arch/mips/kernel/smp-cps.c
+++ b/arch/mips/kernel/smp-cps.c
@@ -88,6 +88,12 @@ static void __init cps_smp_setup(void)
88 88
89 /* Make core 0 coherent with everything */ 89 /* Make core 0 coherent with everything */
90 write_gcr_cl_coherence(0xff); 90 write_gcr_cl_coherence(0xff);
91
92#ifdef CONFIG_MIPS_MT_FPAFF
93 /* If we have an FPU, enroll ourselves in the FPU-full mask */
94 if (cpu_has_fpu)
95 cpu_set(0, mt_fpu_cpumask);
96#endif /* CONFIG_MIPS_MT_FPAFF */
91} 97}
92 98
93static void __init cps_prepare_cpus(unsigned int max_cpus) 99static void __init cps_prepare_cpus(unsigned int max_cpus)
diff --git a/arch/mips/kernel/smp.c b/arch/mips/kernel/smp.c
index 1c0d8c50b7e1..5b020bda3e05 100644
--- a/arch/mips/kernel/smp.c
+++ b/arch/mips/kernel/smp.c
@@ -176,10 +176,8 @@ static void stop_this_cpu(void *dummy)
176 * Remove this CPU: 176 * Remove this CPU:
177 */ 177 */
178 set_cpu_online(smp_processor_id(), false); 178 set_cpu_online(smp_processor_id(), false);
179 for (;;) { 179 local_irq_disable();
180 if (cpu_wait) 180 while (1);
181 (*cpu_wait)(); /* Wait if available. */
182 }
183} 181}
184 182
185void smp_send_stop(void) 183void smp_send_stop(void)
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index 5b4d711f878d..e334c641a81b 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -12,6 +12,7 @@
12 * Copyright (C) 2000, 2001, 2012 MIPS Technologies, Inc. All rights reserved. 12 * Copyright (C) 2000, 2001, 2012 MIPS Technologies, Inc. All rights reserved.
13 * Copyright (C) 2014, Imagination Technologies Ltd. 13 * Copyright (C) 2014, Imagination Technologies Ltd.
14 */ 14 */
15#include <linux/bitops.h>
15#include <linux/bug.h> 16#include <linux/bug.h>
16#include <linux/compiler.h> 17#include <linux/compiler.h>
17#include <linux/context_tracking.h> 18#include <linux/context_tracking.h>
@@ -699,36 +700,60 @@ asmlinkage void do_ov(struct pt_regs *regs)
699 exception_exit(prev_state); 700 exception_exit(prev_state);
700} 701}
701 702
702int process_fpemu_return(int sig, void __user *fault_addr) 703int process_fpemu_return(int sig, void __user *fault_addr, unsigned long fcr31)
703{ 704{
704 /* 705 struct siginfo si = { 0 };
705 * We can't allow the emulated instruction to leave any of the cause 706
706 * bits set in FCSR. If they were then the kernel would take an FP 707 switch (sig) {
707 * exception when restoring FP context. 708 case 0:
708 */ 709 return 0;
709 current->thread.fpu.fcr31 &= ~FPU_CSR_ALL_X;
710 710
711 if (sig == SIGSEGV || sig == SIGBUS) { 711 case SIGFPE:
712 struct siginfo si = {0};
713 si.si_addr = fault_addr; 712 si.si_addr = fault_addr;
714 si.si_signo = sig; 713 si.si_signo = sig;
715 if (sig == SIGSEGV) { 714 /*
716 down_read(&current->mm->mmap_sem); 715 * Inexact can happen together with Overflow or Underflow.
717 if (find_vma(current->mm, (unsigned long)fault_addr)) 716 * Respect the mask to deliver the correct exception.
718 si.si_code = SEGV_ACCERR; 717 */
719 else 718 fcr31 &= (fcr31 & FPU_CSR_ALL_E) <<
720 si.si_code = SEGV_MAPERR; 719 (ffs(FPU_CSR_ALL_X) - ffs(FPU_CSR_ALL_E));
721 up_read(&current->mm->mmap_sem); 720 if (fcr31 & FPU_CSR_INV_X)
722 } else { 721 si.si_code = FPE_FLTINV;
723 si.si_code = BUS_ADRERR; 722 else if (fcr31 & FPU_CSR_DIV_X)
724 } 723 si.si_code = FPE_FLTDIV;
724 else if (fcr31 & FPU_CSR_OVF_X)
725 si.si_code = FPE_FLTOVF;
726 else if (fcr31 & FPU_CSR_UDF_X)
727 si.si_code = FPE_FLTUND;
728 else if (fcr31 & FPU_CSR_INE_X)
729 si.si_code = FPE_FLTRES;
730 else
731 si.si_code = __SI_FAULT;
732 force_sig_info(sig, &si, current);
733 return 1;
734
735 case SIGBUS:
736 si.si_addr = fault_addr;
737 si.si_signo = sig;
738 si.si_code = BUS_ADRERR;
739 force_sig_info(sig, &si, current);
740 return 1;
741
742 case SIGSEGV:
743 si.si_addr = fault_addr;
744 si.si_signo = sig;
745 down_read(&current->mm->mmap_sem);
746 if (find_vma(current->mm, (unsigned long)fault_addr))
747 si.si_code = SEGV_ACCERR;
748 else
749 si.si_code = SEGV_MAPERR;
750 up_read(&current->mm->mmap_sem);
725 force_sig_info(sig, &si, current); 751 force_sig_info(sig, &si, current);
726 return 1; 752 return 1;
727 } else if (sig) { 753
754 default:
728 force_sig(sig, current); 755 force_sig(sig, current);
729 return 1; 756 return 1;
730 } else {
731 return 0;
732 } 757 }
733} 758}
734 759
@@ -736,7 +761,8 @@ static int simulate_fp(struct pt_regs *regs, unsigned int opcode,
736 unsigned long old_epc, unsigned long old_ra) 761 unsigned long old_epc, unsigned long old_ra)
737{ 762{
738 union mips_instruction inst = { .word = opcode }; 763 union mips_instruction inst = { .word = opcode };
739 void __user *fault_addr = NULL; 764 void __user *fault_addr;
765 unsigned long fcr31;
740 int sig; 766 int sig;
741 767
742 /* If it's obviously not an FP instruction, skip it */ 768 /* If it's obviously not an FP instruction, skip it */
@@ -766,13 +792,20 @@ static int simulate_fp(struct pt_regs *regs, unsigned int opcode,
766 /* Run the emulator */ 792 /* Run the emulator */
767 sig = fpu_emulator_cop1Handler(regs, &current->thread.fpu, 1, 793 sig = fpu_emulator_cop1Handler(regs, &current->thread.fpu, 1,
768 &fault_addr); 794 &fault_addr);
795 fcr31 = current->thread.fpu.fcr31;
769 796
770 /* If something went wrong, signal */ 797 /*
771 process_fpemu_return(sig, fault_addr); 798 * We can't allow the emulated instruction to leave any of
799 * the cause bits set in $fcr31.
800 */
801 current->thread.fpu.fcr31 &= ~FPU_CSR_ALL_X;
772 802
773 /* Restore the hardware register state */ 803 /* Restore the hardware register state */
774 own_fpu(1); 804 own_fpu(1);
775 805
806 /* Send a signal if required. */
807 process_fpemu_return(sig, fault_addr, fcr31);
808
776 return 0; 809 return 0;
777} 810}
778 811
@@ -782,7 +815,8 @@ static int simulate_fp(struct pt_regs *regs, unsigned int opcode,
782asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31) 815asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31)
783{ 816{
784 enum ctx_state prev_state; 817 enum ctx_state prev_state;
785 siginfo_t info = {0}; 818 void __user *fault_addr;
819 int sig;
786 820
787 prev_state = exception_enter(); 821 prev_state = exception_enter();
788 if (notify_die(DIE_FP, "FP exception", regs, 0, regs_to_trapnr(regs), 822 if (notify_die(DIE_FP, "FP exception", regs, 0, regs_to_trapnr(regs),
@@ -796,9 +830,6 @@ asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31)
796 die_if_kernel("FP exception in kernel code", regs); 830 die_if_kernel("FP exception in kernel code", regs);
797 831
798 if (fcr31 & FPU_CSR_UNI_X) { 832 if (fcr31 & FPU_CSR_UNI_X) {
799 int sig;
800 void __user *fault_addr = NULL;
801
802 /* 833 /*
803 * Unimplemented operation exception. If we've got the full 834 * Unimplemented operation exception. If we've got the full
804 * software emulator on-board, let's use it... 835 * software emulator on-board, let's use it...
@@ -815,30 +846,23 @@ asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31)
815 /* Run the emulator */ 846 /* Run the emulator */
816 sig = fpu_emulator_cop1Handler(regs, &current->thread.fpu, 1, 847 sig = fpu_emulator_cop1Handler(regs, &current->thread.fpu, 1,
817 &fault_addr); 848 &fault_addr);
849 fcr31 = current->thread.fpu.fcr31;
818 850
819 /* If something went wrong, signal */ 851 /*
820 process_fpemu_return(sig, fault_addr); 852 * We can't allow the emulated instruction to leave any of
853 * the cause bits set in $fcr31.
854 */
855 current->thread.fpu.fcr31 &= ~FPU_CSR_ALL_X;
821 856
822 /* Restore the hardware register state */ 857 /* Restore the hardware register state */
823 own_fpu(1); /* Using the FPU again. */ 858 own_fpu(1); /* Using the FPU again. */
859 } else {
860 sig = SIGFPE;
861 fault_addr = (void __user *) regs->cp0_epc;
862 }
824 863
825 goto out; 864 /* Send a signal if required. */
826 } else if (fcr31 & FPU_CSR_INV_X) 865 process_fpemu_return(sig, fault_addr, fcr31);
827 info.si_code = FPE_FLTINV;
828 else if (fcr31 & FPU_CSR_DIV_X)
829 info.si_code = FPE_FLTDIV;
830 else if (fcr31 & FPU_CSR_OVF_X)
831 info.si_code = FPE_FLTOVF;
832 else if (fcr31 & FPU_CSR_UDF_X)
833 info.si_code = FPE_FLTUND;
834 else if (fcr31 & FPU_CSR_INE_X)
835 info.si_code = FPE_FLTRES;
836 else
837 info.si_code = __SI_FAULT;
838 info.si_signo = SIGFPE;
839 info.si_errno = 0;
840 info.si_addr = (void __user *) regs->cp0_epc;
841 force_sig_info(SIGFPE, &info, current);
842 866
843out: 867out:
844 exception_exit(prev_state); 868 exception_exit(prev_state);
@@ -885,9 +909,9 @@ void do_trap_or_bp(struct pt_regs *regs, unsigned int code,
885 break; 909 break;
886 case BRK_MEMU: 910 case BRK_MEMU:
887 /* 911 /*
888 * Address errors may be deliberately induced by the FPU 912 * This breakpoint code is used by the FPU emulator to retake
889 * emulator to retake control of the CPU after executing the 913 * control of the CPU after executing the instruction from the
890 * instruction in the delay slot of an emulated branch. 914 * delay slot of an emulated branch.
891 * 915 *
892 * Terminate if exception was recognized as a delay slot return 916 * Terminate if exception was recognized as a delay slot return
893 * otherwise handle as normal. 917 * otherwise handle as normal.
@@ -907,10 +931,9 @@ void do_trap_or_bp(struct pt_regs *regs, unsigned int code,
907 931
908asmlinkage void do_bp(struct pt_regs *regs) 932asmlinkage void do_bp(struct pt_regs *regs)
909{ 933{
934 unsigned long epc = msk_isa16_mode(exception_epc(regs));
910 unsigned int opcode, bcode; 935 unsigned int opcode, bcode;
911 enum ctx_state prev_state; 936 enum ctx_state prev_state;
912 unsigned long epc;
913 u16 instr[2];
914 mm_segment_t seg; 937 mm_segment_t seg;
915 938
916 seg = get_fs(); 939 seg = get_fs();
@@ -919,26 +942,28 @@ asmlinkage void do_bp(struct pt_regs *regs)
919 942
920 prev_state = exception_enter(); 943 prev_state = exception_enter();
921 if (get_isa16_mode(regs->cp0_epc)) { 944 if (get_isa16_mode(regs->cp0_epc)) {
922 /* Calculate EPC. */ 945 u16 instr[2];
923 epc = exception_epc(regs); 946
924 if (cpu_has_mmips) { 947 if (__get_user(instr[0], (u16 __user *)epc))
925 if ((__get_user(instr[0], (u16 __user *)msk_isa16_mode(epc)) || 948 goto out_sigsegv;
926 (__get_user(instr[1], (u16 __user *)msk_isa16_mode(epc + 2))))) 949
927 goto out_sigsegv; 950 if (!cpu_has_mmips) {
928 opcode = (instr[0] << 16) | instr[1];
929 } else {
930 /* MIPS16e mode */ 951 /* MIPS16e mode */
931 if (__get_user(instr[0], 952 bcode = (instr[0] >> 5) & 0x3f;
932 (u16 __user *)msk_isa16_mode(epc))) 953 } else if (mm_insn_16bit(instr[0])) {
954 /* 16-bit microMIPS BREAK */
955 bcode = instr[0] & 0xf;
956 } else {
957 /* 32-bit microMIPS BREAK */
958 if (__get_user(instr[1], (u16 __user *)(epc + 2)))
933 goto out_sigsegv; 959 goto out_sigsegv;
934 bcode = (instr[0] >> 6) & 0x3f; 960 opcode = (instr[0] << 16) | instr[1];
935 do_trap_or_bp(regs, bcode, "Break"); 961 bcode = (opcode >> 6) & ((1 << 20) - 1);
936 goto out;
937 } 962 }
938 } else { 963 } else {
939 if (__get_user(opcode, 964 if (__get_user(opcode, (unsigned int __user *)epc))
940 (unsigned int __user *) exception_epc(regs)))
941 goto out_sigsegv; 965 goto out_sigsegv;
966 bcode = (opcode >> 6) & ((1 << 20) - 1);
942 } 967 }
943 968
944 /* 969 /*
@@ -947,9 +972,8 @@ asmlinkage void do_bp(struct pt_regs *regs)
947 * Gas is bug-compatible, but not always, grrr... 972 * Gas is bug-compatible, but not always, grrr...
948 * We handle both cases with a simple heuristics. --macro 973 * We handle both cases with a simple heuristics. --macro
949 */ 974 */
950 bcode = ((opcode >> 6) & ((1 << 20) - 1));
951 if (bcode >= (1 << 10)) 975 if (bcode >= (1 << 10))
952 bcode >>= 10; 976 bcode = ((bcode & ((1 << 10) - 1)) << 10) | (bcode >> 10);
953 977
954 /* 978 /*
955 * notify the kprobe handlers, if instruction is likely to 979 * notify the kprobe handlers, if instruction is likely to
@@ -1039,22 +1063,24 @@ asmlinkage void do_ri(struct pt_regs *regs)
1039 * as quickly as possible. 1063 * as quickly as possible.
1040 */ 1064 */
1041 if (mipsr2_emulation && cpu_has_mips_r6 && 1065 if (mipsr2_emulation && cpu_has_mips_r6 &&
1042 likely(user_mode(regs))) { 1066 likely(user_mode(regs)) &&
1043 if (likely(get_user(opcode, epc) >= 0)) { 1067 likely(get_user(opcode, epc) >= 0)) {
1044 status = mipsr2_decoder(regs, opcode); 1068 unsigned long fcr31 = 0;
1045 switch (status) { 1069
1046 case 0: 1070 status = mipsr2_decoder(regs, opcode, &fcr31);
1047 case SIGEMT: 1071 switch (status) {
1048 task_thread_info(current)->r2_emul_return = 1; 1072 case 0:
1049 return; 1073 case SIGEMT:
1050 case SIGILL: 1074 task_thread_info(current)->r2_emul_return = 1;
1051 goto no_r2_instr; 1075 return;
1052 default: 1076 case SIGILL:
1053 process_fpemu_return(status, 1077 goto no_r2_instr;
1054 &current->thread.cp0_baduaddr); 1078 default:
1055 task_thread_info(current)->r2_emul_return = 1; 1079 process_fpemu_return(status,
1056 return; 1080 &current->thread.cp0_baduaddr,
1057 } 1081 fcr31);
1082 task_thread_info(current)->r2_emul_return = 1;
1083 return;
1058 } 1084 }
1059 } 1085 }
1060 1086
@@ -1299,10 +1325,13 @@ asmlinkage void do_cpu(struct pt_regs *regs)
1299 enum ctx_state prev_state; 1325 enum ctx_state prev_state;
1300 unsigned int __user *epc; 1326 unsigned int __user *epc;
1301 unsigned long old_epc, old31; 1327 unsigned long old_epc, old31;
1328 void __user *fault_addr;
1302 unsigned int opcode; 1329 unsigned int opcode;
1330 unsigned long fcr31;
1303 unsigned int cpid; 1331 unsigned int cpid;
1304 int status, err; 1332 int status, err;
1305 unsigned long __maybe_unused flags; 1333 unsigned long __maybe_unused flags;
1334 int sig;
1306 1335
1307 prev_state = exception_enter(); 1336 prev_state = exception_enter();
1308 cpid = (regs->cp0_cause >> CAUSEB_CE) & 3; 1337 cpid = (regs->cp0_cause >> CAUSEB_CE) & 3;
@@ -1319,7 +1348,7 @@ asmlinkage void do_cpu(struct pt_regs *regs)
1319 status = -1; 1348 status = -1;
1320 1349
1321 if (unlikely(compute_return_epc(regs) < 0)) 1350 if (unlikely(compute_return_epc(regs) < 0))
1322 goto out; 1351 break;
1323 1352
1324 if (get_isa16_mode(regs->cp0_epc)) { 1353 if (get_isa16_mode(regs->cp0_epc)) {
1325 unsigned short mmop[2] = { 0 }; 1354 unsigned short mmop[2] = { 0 };
@@ -1352,49 +1381,54 @@ asmlinkage void do_cpu(struct pt_regs *regs)
1352 force_sig(status, current); 1381 force_sig(status, current);
1353 } 1382 }
1354 1383
1355 goto out; 1384 break;
1356 1385
1357 case 3: 1386 case 3:
1358 /* 1387 /*
1359 * Old (MIPS I and MIPS II) processors will set this code 1388 * The COP3 opcode space and consequently the CP0.Status.CU3
1360 * for COP1X opcode instructions that replaced the original 1389 * bit and the CP0.Cause.CE=3 encoding have been removed as
1361 * COP3 space. We don't limit COP1 space instructions in 1390 * of the MIPS III ISA. From the MIPS IV and MIPS32r2 ISAs
1362 * the emulator according to the CPU ISA, so we want to 1391 * up the space has been reused for COP1X instructions, that
1363 * treat COP1X instructions consistently regardless of which 1392 * are enabled by the CP0.Status.CU1 bit and consequently
1364 * code the CPU chose. Therefore we redirect this trap to 1393 * use the CP0.Cause.CE=1 encoding for Coprocessor Unusable
1365 * the FP emulator too. 1394 * exceptions. Some FPU-less processors that implement one
1366 * 1395 * of these ISAs however use this code erroneously for COP1X
1367 * Then some newer FPU-less processors use this code 1396 * instructions. Therefore we redirect this trap to the FP
1368 * erroneously too, so they are covered by this choice 1397 * emulator too.
1369 * as well.
1370 */ 1398 */
1371 if (raw_cpu_has_fpu) 1399 if (raw_cpu_has_fpu || !cpu_has_mips_4_5_64_r2_r6) {
1400 force_sig(SIGILL, current);
1372 break; 1401 break;
1402 }
1373 /* Fall through. */ 1403 /* Fall through. */
1374 1404
1375 case 1: 1405 case 1:
1376 err = enable_restore_fp_context(0); 1406 err = enable_restore_fp_context(0);
1377 1407
1378 if (!raw_cpu_has_fpu || err) { 1408 if (raw_cpu_has_fpu && !err)
1379 int sig; 1409 break;
1380 void __user *fault_addr = NULL;
1381 sig = fpu_emulator_cop1Handler(regs,
1382 &current->thread.fpu,
1383 0, &fault_addr);
1384 if (!process_fpemu_return(sig, fault_addr) && !err)
1385 mt_ase_fp_affinity();
1386 }
1387 1410
1388 goto out; 1411 sig = fpu_emulator_cop1Handler(regs, &current->thread.fpu, 0,
1412 &fault_addr);
1413 fcr31 = current->thread.fpu.fcr31;
1414
1415 /*
1416 * We can't allow the emulated instruction to leave
1417 * any of the cause bits set in $fcr31.
1418 */
1419 current->thread.fpu.fcr31 &= ~FPU_CSR_ALL_X;
1420
1421 /* Send a signal if required. */
1422 if (!process_fpemu_return(sig, fault_addr, fcr31) && !err)
1423 mt_ase_fp_affinity();
1424
1425 break;
1389 1426
1390 case 2: 1427 case 2:
1391 raw_notifier_call_chain(&cu2_chain, CU2_EXCEPTION, regs); 1428 raw_notifier_call_chain(&cu2_chain, CU2_EXCEPTION, regs);
1392 goto out; 1429 break;
1393 } 1430 }
1394 1431
1395 force_sig(SIGILL, current);
1396
1397out:
1398 exception_exit(prev_state); 1432 exception_exit(prev_state);
1399} 1433}
1400 1434
@@ -1984,6 +2018,12 @@ int cp0_compare_irq_shift;
1984int cp0_perfcount_irq; 2018int cp0_perfcount_irq;
1985EXPORT_SYMBOL_GPL(cp0_perfcount_irq); 2019EXPORT_SYMBOL_GPL(cp0_perfcount_irq);
1986 2020
2021/*
2022 * Fast debug channel IRQ or -1 if not present
2023 */
2024int cp0_fdc_irq;
2025EXPORT_SYMBOL_GPL(cp0_fdc_irq);
2026
1987static int noulri; 2027static int noulri;
1988 2028
1989static int __init ulri_disable(char *s) 2029static int __init ulri_disable(char *s)
@@ -2065,17 +2105,21 @@ void per_cpu_trap_init(bool is_boot_cpu)
2065 * 2105 *
2066 * o read IntCtl.IPTI to determine the timer interrupt 2106 * o read IntCtl.IPTI to determine the timer interrupt
2067 * o read IntCtl.IPPCI to determine the performance counter interrupt 2107 * o read IntCtl.IPPCI to determine the performance counter interrupt
2108 * o read IntCtl.IPFDC to determine the fast debug channel interrupt
2068 */ 2109 */
2069 if (cpu_has_mips_r2_r6) { 2110 if (cpu_has_mips_r2_r6) {
2070 cp0_compare_irq_shift = CAUSEB_TI - CAUSEB_IP; 2111 cp0_compare_irq_shift = CAUSEB_TI - CAUSEB_IP;
2071 cp0_compare_irq = (read_c0_intctl() >> INTCTLB_IPTI) & 7; 2112 cp0_compare_irq = (read_c0_intctl() >> INTCTLB_IPTI) & 7;
2072 cp0_perfcount_irq = (read_c0_intctl() >> INTCTLB_IPPCI) & 7; 2113 cp0_perfcount_irq = (read_c0_intctl() >> INTCTLB_IPPCI) & 7;
2073 if (cp0_perfcount_irq == cp0_compare_irq) 2114 cp0_fdc_irq = (read_c0_intctl() >> INTCTLB_IPFDC) & 7;
2074 cp0_perfcount_irq = -1; 2115 if (!cp0_fdc_irq)
2116 cp0_fdc_irq = -1;
2117
2075 } else { 2118 } else {
2076 cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ; 2119 cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ;
2077 cp0_compare_irq_shift = CP0_LEGACY_PERFCNT_IRQ; 2120 cp0_compare_irq_shift = CP0_LEGACY_PERFCNT_IRQ;
2078 cp0_perfcount_irq = -1; 2121 cp0_perfcount_irq = -1;
2122 cp0_fdc_irq = -1;
2079 } 2123 }
2080 2124
2081 if (!cpu_data[cpu].asid_cache) 2125 if (!cpu_data[cpu].asid_cache)
diff --git a/arch/mips/kernel/unaligned.c b/arch/mips/kernel/unaligned.c
index bbb69695a0a1..af84bef0c90d 100644
--- a/arch/mips/kernel/unaligned.c
+++ b/arch/mips/kernel/unaligned.c
@@ -89,8 +89,6 @@
89#include <asm/fpu_emulator.h> 89#include <asm/fpu_emulator.h>
90#include <asm/inst.h> 90#include <asm/inst.h>
91#include <asm/uaccess.h> 91#include <asm/uaccess.h>
92#include <asm/fpu.h>
93#include <asm/fpu_emulator.h>
94 92
95#define STR(x) __STR(x) 93#define STR(x) __STR(x)
96#define __STR(x) #x 94#define __STR(x) #x
@@ -109,10 +107,11 @@ static u32 unaligned_action;
109extern void show_registers(struct pt_regs *regs); 107extern void show_registers(struct pt_regs *regs);
110 108
111#ifdef __BIG_ENDIAN 109#ifdef __BIG_ENDIAN
112#define LoadHW(addr, value, res) \ 110#define _LoadHW(addr, value, res, type) \
111do { \
113 __asm__ __volatile__ (".set\tnoat\n" \ 112 __asm__ __volatile__ (".set\tnoat\n" \
114 "1:\t"user_lb("%0", "0(%2)")"\n" \ 113 "1:\t"type##_lb("%0", "0(%2)")"\n" \
115 "2:\t"user_lbu("$1", "1(%2)")"\n\t" \ 114 "2:\t"type##_lbu("$1", "1(%2)")"\n\t"\
116 "sll\t%0, 0x8\n\t" \ 115 "sll\t%0, 0x8\n\t" \
117 "or\t%0, $1\n\t" \ 116 "or\t%0, $1\n\t" \
118 "li\t%1, 0\n" \ 117 "li\t%1, 0\n" \
@@ -127,13 +126,15 @@ extern void show_registers(struct pt_regs *regs);
127 STR(PTR)"\t2b, 4b\n\t" \ 126 STR(PTR)"\t2b, 4b\n\t" \
128 ".previous" \ 127 ".previous" \
129 : "=&r" (value), "=r" (res) \ 128 : "=&r" (value), "=r" (res) \
130 : "r" (addr), "i" (-EFAULT)); 129 : "r" (addr), "i" (-EFAULT)); \
130} while(0)
131 131
132#ifndef CONFIG_CPU_MIPSR6 132#ifndef CONFIG_CPU_MIPSR6
133#define LoadW(addr, value, res) \ 133#define _LoadW(addr, value, res, type) \
134do { \
134 __asm__ __volatile__ ( \ 135 __asm__ __volatile__ ( \
135 "1:\t"user_lwl("%0", "(%2)")"\n" \ 136 "1:\t"type##_lwl("%0", "(%2)")"\n" \
136 "2:\t"user_lwr("%0", "3(%2)")"\n\t" \ 137 "2:\t"type##_lwr("%0", "3(%2)")"\n\t"\
137 "li\t%1, 0\n" \ 138 "li\t%1, 0\n" \
138 "3:\n\t" \ 139 "3:\n\t" \
139 ".insn\n\t" \ 140 ".insn\n\t" \
@@ -146,21 +147,24 @@ extern void show_registers(struct pt_regs *regs);
146 STR(PTR)"\t2b, 4b\n\t" \ 147 STR(PTR)"\t2b, 4b\n\t" \
147 ".previous" \ 148 ".previous" \
148 : "=&r" (value), "=r" (res) \ 149 : "=&r" (value), "=r" (res) \
149 : "r" (addr), "i" (-EFAULT)); 150 : "r" (addr), "i" (-EFAULT)); \
151} while(0)
152
150#else 153#else
151/* MIPSR6 has no lwl instruction */ 154/* MIPSR6 has no lwl instruction */
152#define LoadW(addr, value, res) \ 155#define _LoadW(addr, value, res, type) \
156do { \
153 __asm__ __volatile__ ( \ 157 __asm__ __volatile__ ( \
154 ".set\tpush\n" \ 158 ".set\tpush\n" \
155 ".set\tnoat\n\t" \ 159 ".set\tnoat\n\t" \
156 "1:"user_lb("%0", "0(%2)")"\n\t" \ 160 "1:"type##_lb("%0", "0(%2)")"\n\t" \
157 "2:"user_lbu("$1", "1(%2)")"\n\t" \ 161 "2:"type##_lbu("$1", "1(%2)")"\n\t" \
158 "sll\t%0, 0x8\n\t" \ 162 "sll\t%0, 0x8\n\t" \
159 "or\t%0, $1\n\t" \ 163 "or\t%0, $1\n\t" \
160 "3:"user_lbu("$1", "2(%2)")"\n\t" \ 164 "3:"type##_lbu("$1", "2(%2)")"\n\t" \
161 "sll\t%0, 0x8\n\t" \ 165 "sll\t%0, 0x8\n\t" \
162 "or\t%0, $1\n\t" \ 166 "or\t%0, $1\n\t" \
163 "4:"user_lbu("$1", "3(%2)")"\n\t" \ 167 "4:"type##_lbu("$1", "3(%2)")"\n\t" \
164 "sll\t%0, 0x8\n\t" \ 168 "sll\t%0, 0x8\n\t" \
165 "or\t%0, $1\n\t" \ 169 "or\t%0, $1\n\t" \
166 "li\t%1, 0\n" \ 170 "li\t%1, 0\n" \
@@ -178,14 +182,17 @@ extern void show_registers(struct pt_regs *regs);
178 STR(PTR)"\t4b, 11b\n\t" \ 182 STR(PTR)"\t4b, 11b\n\t" \
179 ".previous" \ 183 ".previous" \
180 : "=&r" (value), "=r" (res) \ 184 : "=&r" (value), "=r" (res) \
181 : "r" (addr), "i" (-EFAULT)); 185 : "r" (addr), "i" (-EFAULT)); \
186} while(0)
187
182#endif /* CONFIG_CPU_MIPSR6 */ 188#endif /* CONFIG_CPU_MIPSR6 */
183 189
184#define LoadHWU(addr, value, res) \ 190#define _LoadHWU(addr, value, res, type) \
191do { \
185 __asm__ __volatile__ ( \ 192 __asm__ __volatile__ ( \
186 ".set\tnoat\n" \ 193 ".set\tnoat\n" \
187 "1:\t"user_lbu("%0", "0(%2)")"\n" \ 194 "1:\t"type##_lbu("%0", "0(%2)")"\n" \
188 "2:\t"user_lbu("$1", "1(%2)")"\n\t" \ 195 "2:\t"type##_lbu("$1", "1(%2)")"\n\t"\
189 "sll\t%0, 0x8\n\t" \ 196 "sll\t%0, 0x8\n\t" \
190 "or\t%0, $1\n\t" \ 197 "or\t%0, $1\n\t" \
191 "li\t%1, 0\n" \ 198 "li\t%1, 0\n" \
@@ -201,13 +208,15 @@ extern void show_registers(struct pt_regs *regs);
201 STR(PTR)"\t2b, 4b\n\t" \ 208 STR(PTR)"\t2b, 4b\n\t" \
202 ".previous" \ 209 ".previous" \
203 : "=&r" (value), "=r" (res) \ 210 : "=&r" (value), "=r" (res) \
204 : "r" (addr), "i" (-EFAULT)); 211 : "r" (addr), "i" (-EFAULT)); \
212} while(0)
205 213
206#ifndef CONFIG_CPU_MIPSR6 214#ifndef CONFIG_CPU_MIPSR6
207#define LoadWU(addr, value, res) \ 215#define _LoadWU(addr, value, res, type) \
216do { \
208 __asm__ __volatile__ ( \ 217 __asm__ __volatile__ ( \
209 "1:\t"user_lwl("%0", "(%2)")"\n" \ 218 "1:\t"type##_lwl("%0", "(%2)")"\n" \
210 "2:\t"user_lwr("%0", "3(%2)")"\n\t" \ 219 "2:\t"type##_lwr("%0", "3(%2)")"\n\t"\
211 "dsll\t%0, %0, 32\n\t" \ 220 "dsll\t%0, %0, 32\n\t" \
212 "dsrl\t%0, %0, 32\n\t" \ 221 "dsrl\t%0, %0, 32\n\t" \
213 "li\t%1, 0\n" \ 222 "li\t%1, 0\n" \
@@ -222,9 +231,11 @@ extern void show_registers(struct pt_regs *regs);
222 STR(PTR)"\t2b, 4b\n\t" \ 231 STR(PTR)"\t2b, 4b\n\t" \
223 ".previous" \ 232 ".previous" \
224 : "=&r" (value), "=r" (res) \ 233 : "=&r" (value), "=r" (res) \
225 : "r" (addr), "i" (-EFAULT)); 234 : "r" (addr), "i" (-EFAULT)); \
235} while(0)
226 236
227#define LoadDW(addr, value, res) \ 237#define _LoadDW(addr, value, res) \
238do { \
228 __asm__ __volatile__ ( \ 239 __asm__ __volatile__ ( \
229 "1:\tldl\t%0, (%2)\n" \ 240 "1:\tldl\t%0, (%2)\n" \
230 "2:\tldr\t%0, 7(%2)\n\t" \ 241 "2:\tldr\t%0, 7(%2)\n\t" \
@@ -240,21 +251,24 @@ extern void show_registers(struct pt_regs *regs);
240 STR(PTR)"\t2b, 4b\n\t" \ 251 STR(PTR)"\t2b, 4b\n\t" \
241 ".previous" \ 252 ".previous" \
242 : "=&r" (value), "=r" (res) \ 253 : "=&r" (value), "=r" (res) \
243 : "r" (addr), "i" (-EFAULT)); 254 : "r" (addr), "i" (-EFAULT)); \
255} while(0)
256
244#else 257#else
245/* MIPSR6 has not lwl and ldl instructions */ 258/* MIPSR6 has not lwl and ldl instructions */
246#define LoadWU(addr, value, res) \ 259#define _LoadWU(addr, value, res, type) \
260do { \
247 __asm__ __volatile__ ( \ 261 __asm__ __volatile__ ( \
248 ".set\tpush\n\t" \ 262 ".set\tpush\n\t" \
249 ".set\tnoat\n\t" \ 263 ".set\tnoat\n\t" \
250 "1:"user_lbu("%0", "0(%2)")"\n\t" \ 264 "1:"type##_lbu("%0", "0(%2)")"\n\t" \
251 "2:"user_lbu("$1", "1(%2)")"\n\t" \ 265 "2:"type##_lbu("$1", "1(%2)")"\n\t" \
252 "sll\t%0, 0x8\n\t" \ 266 "sll\t%0, 0x8\n\t" \
253 "or\t%0, $1\n\t" \ 267 "or\t%0, $1\n\t" \
254 "3:"user_lbu("$1", "2(%2)")"\n\t" \ 268 "3:"type##_lbu("$1", "2(%2)")"\n\t" \
255 "sll\t%0, 0x8\n\t" \ 269 "sll\t%0, 0x8\n\t" \
256 "or\t%0, $1\n\t" \ 270 "or\t%0, $1\n\t" \
257 "4:"user_lbu("$1", "3(%2)")"\n\t" \ 271 "4:"type##_lbu("$1", "3(%2)")"\n\t" \
258 "sll\t%0, 0x8\n\t" \ 272 "sll\t%0, 0x8\n\t" \
259 "or\t%0, $1\n\t" \ 273 "or\t%0, $1\n\t" \
260 "li\t%1, 0\n" \ 274 "li\t%1, 0\n" \
@@ -272,9 +286,11 @@ extern void show_registers(struct pt_regs *regs);
272 STR(PTR)"\t4b, 11b\n\t" \ 286 STR(PTR)"\t4b, 11b\n\t" \
273 ".previous" \ 287 ".previous" \
274 : "=&r" (value), "=r" (res) \ 288 : "=&r" (value), "=r" (res) \
275 : "r" (addr), "i" (-EFAULT)); 289 : "r" (addr), "i" (-EFAULT)); \
290} while(0)
276 291
277#define LoadDW(addr, value, res) \ 292#define _LoadDW(addr, value, res) \
293do { \
278 __asm__ __volatile__ ( \ 294 __asm__ __volatile__ ( \
279 ".set\tpush\n\t" \ 295 ".set\tpush\n\t" \
280 ".set\tnoat\n\t" \ 296 ".set\tnoat\n\t" \
@@ -319,16 +335,19 @@ extern void show_registers(struct pt_regs *regs);
319 STR(PTR)"\t8b, 11b\n\t" \ 335 STR(PTR)"\t8b, 11b\n\t" \
320 ".previous" \ 336 ".previous" \
321 : "=&r" (value), "=r" (res) \ 337 : "=&r" (value), "=r" (res) \
322 : "r" (addr), "i" (-EFAULT)); 338 : "r" (addr), "i" (-EFAULT)); \
339} while(0)
340
323#endif /* CONFIG_CPU_MIPSR6 */ 341#endif /* CONFIG_CPU_MIPSR6 */
324 342
325 343
326#define StoreHW(addr, value, res) \ 344#define _StoreHW(addr, value, res, type) \
345do { \
327 __asm__ __volatile__ ( \ 346 __asm__ __volatile__ ( \
328 ".set\tnoat\n" \ 347 ".set\tnoat\n" \
329 "1:\t"user_sb("%1", "1(%2)")"\n" \ 348 "1:\t"type##_sb("%1", "1(%2)")"\n" \
330 "srl\t$1, %1, 0x8\n" \ 349 "srl\t$1, %1, 0x8\n" \
331 "2:\t"user_sb("$1", "0(%2)")"\n" \ 350 "2:\t"type##_sb("$1", "0(%2)")"\n" \
332 ".set\tat\n\t" \ 351 ".set\tat\n\t" \
333 "li\t%0, 0\n" \ 352 "li\t%0, 0\n" \
334 "3:\n\t" \ 353 "3:\n\t" \
@@ -342,13 +361,15 @@ extern void show_registers(struct pt_regs *regs);
342 STR(PTR)"\t2b, 4b\n\t" \ 361 STR(PTR)"\t2b, 4b\n\t" \
343 ".previous" \ 362 ".previous" \
344 : "=r" (res) \ 363 : "=r" (res) \
345 : "r" (value), "r" (addr), "i" (-EFAULT)); 364 : "r" (value), "r" (addr), "i" (-EFAULT));\
365} while(0)
346 366
347#ifndef CONFIG_CPU_MIPSR6 367#ifndef CONFIG_CPU_MIPSR6
348#define StoreW(addr, value, res) \ 368#define _StoreW(addr, value, res, type) \
369do { \
349 __asm__ __volatile__ ( \ 370 __asm__ __volatile__ ( \
350 "1:\t"user_swl("%1", "(%2)")"\n" \ 371 "1:\t"type##_swl("%1", "(%2)")"\n" \
351 "2:\t"user_swr("%1", "3(%2)")"\n\t" \ 372 "2:\t"type##_swr("%1", "3(%2)")"\n\t"\
352 "li\t%0, 0\n" \ 373 "li\t%0, 0\n" \
353 "3:\n\t" \ 374 "3:\n\t" \
354 ".insn\n\t" \ 375 ".insn\n\t" \
@@ -361,9 +382,11 @@ extern void show_registers(struct pt_regs *regs);
361 STR(PTR)"\t2b, 4b\n\t" \ 382 STR(PTR)"\t2b, 4b\n\t" \
362 ".previous" \ 383 ".previous" \
363 : "=r" (res) \ 384 : "=r" (res) \
364 : "r" (value), "r" (addr), "i" (-EFAULT)); 385 : "r" (value), "r" (addr), "i" (-EFAULT)); \
386} while(0)
365 387
366#define StoreDW(addr, value, res) \ 388#define _StoreDW(addr, value, res) \
389do { \
367 __asm__ __volatile__ ( \ 390 __asm__ __volatile__ ( \
368 "1:\tsdl\t%1,(%2)\n" \ 391 "1:\tsdl\t%1,(%2)\n" \
369 "2:\tsdr\t%1, 7(%2)\n\t" \ 392 "2:\tsdr\t%1, 7(%2)\n\t" \
@@ -379,20 +402,23 @@ extern void show_registers(struct pt_regs *regs);
379 STR(PTR)"\t2b, 4b\n\t" \ 402 STR(PTR)"\t2b, 4b\n\t" \
380 ".previous" \ 403 ".previous" \
381 : "=r" (res) \ 404 : "=r" (res) \
382 : "r" (value), "r" (addr), "i" (-EFAULT)); 405 : "r" (value), "r" (addr), "i" (-EFAULT)); \
406} while(0)
407
383#else 408#else
384/* MIPSR6 has no swl and sdl instructions */ 409/* MIPSR6 has no swl and sdl instructions */
385#define StoreW(addr, value, res) \ 410#define _StoreW(addr, value, res, type) \
411do { \
386 __asm__ __volatile__ ( \ 412 __asm__ __volatile__ ( \
387 ".set\tpush\n\t" \ 413 ".set\tpush\n\t" \
388 ".set\tnoat\n\t" \ 414 ".set\tnoat\n\t" \
389 "1:"user_sb("%1", "3(%2)")"\n\t" \ 415 "1:"type##_sb("%1", "3(%2)")"\n\t" \
390 "srl\t$1, %1, 0x8\n\t" \ 416 "srl\t$1, %1, 0x8\n\t" \
391 "2:"user_sb("$1", "2(%2)")"\n\t" \ 417 "2:"type##_sb("$1", "2(%2)")"\n\t" \
392 "srl\t$1, $1, 0x8\n\t" \ 418 "srl\t$1, $1, 0x8\n\t" \
393 "3:"user_sb("$1", "1(%2)")"\n\t" \ 419 "3:"type##_sb("$1", "1(%2)")"\n\t" \
394 "srl\t$1, $1, 0x8\n\t" \ 420 "srl\t$1, $1, 0x8\n\t" \
395 "4:"user_sb("$1", "0(%2)")"\n\t" \ 421 "4:"type##_sb("$1", "0(%2)")"\n\t" \
396 ".set\tpop\n\t" \ 422 ".set\tpop\n\t" \
397 "li\t%0, 0\n" \ 423 "li\t%0, 0\n" \
398 "10:\n\t" \ 424 "10:\n\t" \
@@ -409,9 +435,11 @@ extern void show_registers(struct pt_regs *regs);
409 ".previous" \ 435 ".previous" \
410 : "=&r" (res) \ 436 : "=&r" (res) \
411 : "r" (value), "r" (addr), "i" (-EFAULT) \ 437 : "r" (value), "r" (addr), "i" (-EFAULT) \
412 : "memory"); 438 : "memory"); \
439} while(0)
413 440
414#define StoreDW(addr, value, res) \ 441#define StoreDW(addr, value, res) \
442do { \
415 __asm__ __volatile__ ( \ 443 __asm__ __volatile__ ( \
416 ".set\tpush\n\t" \ 444 ".set\tpush\n\t" \
417 ".set\tnoat\n\t" \ 445 ".set\tnoat\n\t" \
@@ -451,15 +479,18 @@ extern void show_registers(struct pt_regs *regs);
451 ".previous" \ 479 ".previous" \
452 : "=&r" (res) \ 480 : "=&r" (res) \
453 : "r" (value), "r" (addr), "i" (-EFAULT) \ 481 : "r" (value), "r" (addr), "i" (-EFAULT) \
454 : "memory"); 482 : "memory"); \
483} while(0)
484
455#endif /* CONFIG_CPU_MIPSR6 */ 485#endif /* CONFIG_CPU_MIPSR6 */
456 486
457#else /* __BIG_ENDIAN */ 487#else /* __BIG_ENDIAN */
458 488
459#define LoadHW(addr, value, res) \ 489#define _LoadHW(addr, value, res, type) \
490do { \
460 __asm__ __volatile__ (".set\tnoat\n" \ 491 __asm__ __volatile__ (".set\tnoat\n" \
461 "1:\t"user_lb("%0", "1(%2)")"\n" \ 492 "1:\t"type##_lb("%0", "1(%2)")"\n" \
462 "2:\t"user_lbu("$1", "0(%2)")"\n\t" \ 493 "2:\t"type##_lbu("$1", "0(%2)")"\n\t"\
463 "sll\t%0, 0x8\n\t" \ 494 "sll\t%0, 0x8\n\t" \
464 "or\t%0, $1\n\t" \ 495 "or\t%0, $1\n\t" \
465 "li\t%1, 0\n" \ 496 "li\t%1, 0\n" \
@@ -474,13 +505,15 @@ extern void show_registers(struct pt_regs *regs);
474 STR(PTR)"\t2b, 4b\n\t" \ 505 STR(PTR)"\t2b, 4b\n\t" \
475 ".previous" \ 506 ".previous" \
476 : "=&r" (value), "=r" (res) \ 507 : "=&r" (value), "=r" (res) \
477 : "r" (addr), "i" (-EFAULT)); 508 : "r" (addr), "i" (-EFAULT)); \
509} while(0)
478 510
479#ifndef CONFIG_CPU_MIPSR6 511#ifndef CONFIG_CPU_MIPSR6
480#define LoadW(addr, value, res) \ 512#define _LoadW(addr, value, res, type) \
513do { \
481 __asm__ __volatile__ ( \ 514 __asm__ __volatile__ ( \
482 "1:\t"user_lwl("%0", "3(%2)")"\n" \ 515 "1:\t"type##_lwl("%0", "3(%2)")"\n" \
483 "2:\t"user_lwr("%0", "(%2)")"\n\t" \ 516 "2:\t"type##_lwr("%0", "(%2)")"\n\t"\
484 "li\t%1, 0\n" \ 517 "li\t%1, 0\n" \
485 "3:\n\t" \ 518 "3:\n\t" \
486 ".insn\n\t" \ 519 ".insn\n\t" \
@@ -493,21 +526,24 @@ extern void show_registers(struct pt_regs *regs);
493 STR(PTR)"\t2b, 4b\n\t" \ 526 STR(PTR)"\t2b, 4b\n\t" \
494 ".previous" \ 527 ".previous" \
495 : "=&r" (value), "=r" (res) \ 528 : "=&r" (value), "=r" (res) \
496 : "r" (addr), "i" (-EFAULT)); 529 : "r" (addr), "i" (-EFAULT)); \
530} while(0)
531
497#else 532#else
498/* MIPSR6 has no lwl instruction */ 533/* MIPSR6 has no lwl instruction */
499#define LoadW(addr, value, res) \ 534#define _LoadW(addr, value, res, type) \
535do { \
500 __asm__ __volatile__ ( \ 536 __asm__ __volatile__ ( \
501 ".set\tpush\n" \ 537 ".set\tpush\n" \
502 ".set\tnoat\n\t" \ 538 ".set\tnoat\n\t" \
503 "1:"user_lb("%0", "3(%2)")"\n\t" \ 539 "1:"type##_lb("%0", "3(%2)")"\n\t" \
504 "2:"user_lbu("$1", "2(%2)")"\n\t" \ 540 "2:"type##_lbu("$1", "2(%2)")"\n\t" \
505 "sll\t%0, 0x8\n\t" \ 541 "sll\t%0, 0x8\n\t" \
506 "or\t%0, $1\n\t" \ 542 "or\t%0, $1\n\t" \
507 "3:"user_lbu("$1", "1(%2)")"\n\t" \ 543 "3:"type##_lbu("$1", "1(%2)")"\n\t" \
508 "sll\t%0, 0x8\n\t" \ 544 "sll\t%0, 0x8\n\t" \
509 "or\t%0, $1\n\t" \ 545 "or\t%0, $1\n\t" \
510 "4:"user_lbu("$1", "0(%2)")"\n\t" \ 546 "4:"type##_lbu("$1", "0(%2)")"\n\t" \
511 "sll\t%0, 0x8\n\t" \ 547 "sll\t%0, 0x8\n\t" \
512 "or\t%0, $1\n\t" \ 548 "or\t%0, $1\n\t" \
513 "li\t%1, 0\n" \ 549 "li\t%1, 0\n" \
@@ -525,15 +561,18 @@ extern void show_registers(struct pt_regs *regs);
525 STR(PTR)"\t4b, 11b\n\t" \ 561 STR(PTR)"\t4b, 11b\n\t" \
526 ".previous" \ 562 ".previous" \
527 : "=&r" (value), "=r" (res) \ 563 : "=&r" (value), "=r" (res) \
528 : "r" (addr), "i" (-EFAULT)); 564 : "r" (addr), "i" (-EFAULT)); \
565} while(0)
566
529#endif /* CONFIG_CPU_MIPSR6 */ 567#endif /* CONFIG_CPU_MIPSR6 */
530 568
531 569
532#define LoadHWU(addr, value, res) \ 570#define _LoadHWU(addr, value, res, type) \
571do { \
533 __asm__ __volatile__ ( \ 572 __asm__ __volatile__ ( \
534 ".set\tnoat\n" \ 573 ".set\tnoat\n" \
535 "1:\t"user_lbu("%0", "1(%2)")"\n" \ 574 "1:\t"type##_lbu("%0", "1(%2)")"\n" \
536 "2:\t"user_lbu("$1", "0(%2)")"\n\t" \ 575 "2:\t"type##_lbu("$1", "0(%2)")"\n\t"\
537 "sll\t%0, 0x8\n\t" \ 576 "sll\t%0, 0x8\n\t" \
538 "or\t%0, $1\n\t" \ 577 "or\t%0, $1\n\t" \
539 "li\t%1, 0\n" \ 578 "li\t%1, 0\n" \
@@ -549,13 +588,15 @@ extern void show_registers(struct pt_regs *regs);
549 STR(PTR)"\t2b, 4b\n\t" \ 588 STR(PTR)"\t2b, 4b\n\t" \
550 ".previous" \ 589 ".previous" \
551 : "=&r" (value), "=r" (res) \ 590 : "=&r" (value), "=r" (res) \
552 : "r" (addr), "i" (-EFAULT)); 591 : "r" (addr), "i" (-EFAULT)); \
592} while(0)
553 593
554#ifndef CONFIG_CPU_MIPSR6 594#ifndef CONFIG_CPU_MIPSR6
555#define LoadWU(addr, value, res) \ 595#define _LoadWU(addr, value, res, type) \
596do { \
556 __asm__ __volatile__ ( \ 597 __asm__ __volatile__ ( \
557 "1:\t"user_lwl("%0", "3(%2)")"\n" \ 598 "1:\t"type##_lwl("%0", "3(%2)")"\n" \
558 "2:\t"user_lwr("%0", "(%2)")"\n\t" \ 599 "2:\t"type##_lwr("%0", "(%2)")"\n\t"\
559 "dsll\t%0, %0, 32\n\t" \ 600 "dsll\t%0, %0, 32\n\t" \
560 "dsrl\t%0, %0, 32\n\t" \ 601 "dsrl\t%0, %0, 32\n\t" \
561 "li\t%1, 0\n" \ 602 "li\t%1, 0\n" \
@@ -570,9 +611,11 @@ extern void show_registers(struct pt_regs *regs);
570 STR(PTR)"\t2b, 4b\n\t" \ 611 STR(PTR)"\t2b, 4b\n\t" \
571 ".previous" \ 612 ".previous" \
572 : "=&r" (value), "=r" (res) \ 613 : "=&r" (value), "=r" (res) \
573 : "r" (addr), "i" (-EFAULT)); 614 : "r" (addr), "i" (-EFAULT)); \
615} while(0)
574 616
575#define LoadDW(addr, value, res) \ 617#define _LoadDW(addr, value, res) \
618do { \
576 __asm__ __volatile__ ( \ 619 __asm__ __volatile__ ( \
577 "1:\tldl\t%0, 7(%2)\n" \ 620 "1:\tldl\t%0, 7(%2)\n" \
578 "2:\tldr\t%0, (%2)\n\t" \ 621 "2:\tldr\t%0, (%2)\n\t" \
@@ -588,21 +631,24 @@ extern void show_registers(struct pt_regs *regs);
588 STR(PTR)"\t2b, 4b\n\t" \ 631 STR(PTR)"\t2b, 4b\n\t" \
589 ".previous" \ 632 ".previous" \
590 : "=&r" (value), "=r" (res) \ 633 : "=&r" (value), "=r" (res) \
591 : "r" (addr), "i" (-EFAULT)); 634 : "r" (addr), "i" (-EFAULT)); \
635} while(0)
636
592#else 637#else
593/* MIPSR6 has not lwl and ldl instructions */ 638/* MIPSR6 has not lwl and ldl instructions */
594#define LoadWU(addr, value, res) \ 639#define _LoadWU(addr, value, res, type) \
640do { \
595 __asm__ __volatile__ ( \ 641 __asm__ __volatile__ ( \
596 ".set\tpush\n\t" \ 642 ".set\tpush\n\t" \
597 ".set\tnoat\n\t" \ 643 ".set\tnoat\n\t" \
598 "1:"user_lbu("%0", "3(%2)")"\n\t" \ 644 "1:"type##_lbu("%0", "3(%2)")"\n\t" \
599 "2:"user_lbu("$1", "2(%2)")"\n\t" \ 645 "2:"type##_lbu("$1", "2(%2)")"\n\t" \
600 "sll\t%0, 0x8\n\t" \ 646 "sll\t%0, 0x8\n\t" \
601 "or\t%0, $1\n\t" \ 647 "or\t%0, $1\n\t" \
602 "3:"user_lbu("$1", "1(%2)")"\n\t" \ 648 "3:"type##_lbu("$1", "1(%2)")"\n\t" \
603 "sll\t%0, 0x8\n\t" \ 649 "sll\t%0, 0x8\n\t" \
604 "or\t%0, $1\n\t" \ 650 "or\t%0, $1\n\t" \
605 "4:"user_lbu("$1", "0(%2)")"\n\t" \ 651 "4:"type##_lbu("$1", "0(%2)")"\n\t" \
606 "sll\t%0, 0x8\n\t" \ 652 "sll\t%0, 0x8\n\t" \
607 "or\t%0, $1\n\t" \ 653 "or\t%0, $1\n\t" \
608 "li\t%1, 0\n" \ 654 "li\t%1, 0\n" \
@@ -620,9 +666,11 @@ extern void show_registers(struct pt_regs *regs);
620 STR(PTR)"\t4b, 11b\n\t" \ 666 STR(PTR)"\t4b, 11b\n\t" \
621 ".previous" \ 667 ".previous" \
622 : "=&r" (value), "=r" (res) \ 668 : "=&r" (value), "=r" (res) \
623 : "r" (addr), "i" (-EFAULT)); 669 : "r" (addr), "i" (-EFAULT)); \
670} while(0)
624 671
625#define LoadDW(addr, value, res) \ 672#define _LoadDW(addr, value, res) \
673do { \
626 __asm__ __volatile__ ( \ 674 __asm__ __volatile__ ( \
627 ".set\tpush\n\t" \ 675 ".set\tpush\n\t" \
628 ".set\tnoat\n\t" \ 676 ".set\tnoat\n\t" \
@@ -667,15 +715,17 @@ extern void show_registers(struct pt_regs *regs);
667 STR(PTR)"\t8b, 11b\n\t" \ 715 STR(PTR)"\t8b, 11b\n\t" \
668 ".previous" \ 716 ".previous" \
669 : "=&r" (value), "=r" (res) \ 717 : "=&r" (value), "=r" (res) \
670 : "r" (addr), "i" (-EFAULT)); 718 : "r" (addr), "i" (-EFAULT)); \
719} while(0)
671#endif /* CONFIG_CPU_MIPSR6 */ 720#endif /* CONFIG_CPU_MIPSR6 */
672 721
673#define StoreHW(addr, value, res) \ 722#define _StoreHW(addr, value, res, type) \
723do { \
674 __asm__ __volatile__ ( \ 724 __asm__ __volatile__ ( \
675 ".set\tnoat\n" \ 725 ".set\tnoat\n" \
676 "1:\t"user_sb("%1", "0(%2)")"\n" \ 726 "1:\t"type##_sb("%1", "0(%2)")"\n" \
677 "srl\t$1,%1, 0x8\n" \ 727 "srl\t$1,%1, 0x8\n" \
678 "2:\t"user_sb("$1", "1(%2)")"\n" \ 728 "2:\t"type##_sb("$1", "1(%2)")"\n" \
679 ".set\tat\n\t" \ 729 ".set\tat\n\t" \
680 "li\t%0, 0\n" \ 730 "li\t%0, 0\n" \
681 "3:\n\t" \ 731 "3:\n\t" \
@@ -689,12 +739,15 @@ extern void show_registers(struct pt_regs *regs);
689 STR(PTR)"\t2b, 4b\n\t" \ 739 STR(PTR)"\t2b, 4b\n\t" \
690 ".previous" \ 740 ".previous" \
691 : "=r" (res) \ 741 : "=r" (res) \
692 : "r" (value), "r" (addr), "i" (-EFAULT)); 742 : "r" (value), "r" (addr), "i" (-EFAULT));\
743} while(0)
744
693#ifndef CONFIG_CPU_MIPSR6 745#ifndef CONFIG_CPU_MIPSR6
694#define StoreW(addr, value, res) \ 746#define _StoreW(addr, value, res, type) \
747do { \
695 __asm__ __volatile__ ( \ 748 __asm__ __volatile__ ( \
696 "1:\t"user_swl("%1", "3(%2)")"\n" \ 749 "1:\t"type##_swl("%1", "3(%2)")"\n" \
697 "2:\t"user_swr("%1", "(%2)")"\n\t" \ 750 "2:\t"type##_swr("%1", "(%2)")"\n\t"\
698 "li\t%0, 0\n" \ 751 "li\t%0, 0\n" \
699 "3:\n\t" \ 752 "3:\n\t" \
700 ".insn\n\t" \ 753 ".insn\n\t" \
@@ -707,9 +760,11 @@ extern void show_registers(struct pt_regs *regs);
707 STR(PTR)"\t2b, 4b\n\t" \ 760 STR(PTR)"\t2b, 4b\n\t" \
708 ".previous" \ 761 ".previous" \
709 : "=r" (res) \ 762 : "=r" (res) \
710 : "r" (value), "r" (addr), "i" (-EFAULT)); 763 : "r" (value), "r" (addr), "i" (-EFAULT)); \
764} while(0)
711 765
712#define StoreDW(addr, value, res) \ 766#define _StoreDW(addr, value, res) \
767do { \
713 __asm__ __volatile__ ( \ 768 __asm__ __volatile__ ( \
714 "1:\tsdl\t%1, 7(%2)\n" \ 769 "1:\tsdl\t%1, 7(%2)\n" \
715 "2:\tsdr\t%1, (%2)\n\t" \ 770 "2:\tsdr\t%1, (%2)\n\t" \
@@ -725,20 +780,23 @@ extern void show_registers(struct pt_regs *regs);
725 STR(PTR)"\t2b, 4b\n\t" \ 780 STR(PTR)"\t2b, 4b\n\t" \
726 ".previous" \ 781 ".previous" \
727 : "=r" (res) \ 782 : "=r" (res) \
728 : "r" (value), "r" (addr), "i" (-EFAULT)); 783 : "r" (value), "r" (addr), "i" (-EFAULT)); \
784} while(0)
785
729#else 786#else
730/* MIPSR6 has no swl and sdl instructions */ 787/* MIPSR6 has no swl and sdl instructions */
731#define StoreW(addr, value, res) \ 788#define _StoreW(addr, value, res, type) \
789do { \
732 __asm__ __volatile__ ( \ 790 __asm__ __volatile__ ( \
733 ".set\tpush\n\t" \ 791 ".set\tpush\n\t" \
734 ".set\tnoat\n\t" \ 792 ".set\tnoat\n\t" \
735 "1:"user_sb("%1", "0(%2)")"\n\t" \ 793 "1:"type##_sb("%1", "0(%2)")"\n\t" \
736 "srl\t$1, %1, 0x8\n\t" \ 794 "srl\t$1, %1, 0x8\n\t" \
737 "2:"user_sb("$1", "1(%2)")"\n\t" \ 795 "2:"type##_sb("$1", "1(%2)")"\n\t" \
738 "srl\t$1, $1, 0x8\n\t" \ 796 "srl\t$1, $1, 0x8\n\t" \
739 "3:"user_sb("$1", "2(%2)")"\n\t" \ 797 "3:"type##_sb("$1", "2(%2)")"\n\t" \
740 "srl\t$1, $1, 0x8\n\t" \ 798 "srl\t$1, $1, 0x8\n\t" \
741 "4:"user_sb("$1", "3(%2)")"\n\t" \ 799 "4:"type##_sb("$1", "3(%2)")"\n\t" \
742 ".set\tpop\n\t" \ 800 ".set\tpop\n\t" \
743 "li\t%0, 0\n" \ 801 "li\t%0, 0\n" \
744 "10:\n\t" \ 802 "10:\n\t" \
@@ -755,9 +813,11 @@ extern void show_registers(struct pt_regs *regs);
755 ".previous" \ 813 ".previous" \
756 : "=&r" (res) \ 814 : "=&r" (res) \
757 : "r" (value), "r" (addr), "i" (-EFAULT) \ 815 : "r" (value), "r" (addr), "i" (-EFAULT) \
758 : "memory"); 816 : "memory"); \
817} while(0)
759 818
760#define StoreDW(addr, value, res) \ 819#define _StoreDW(addr, value, res) \
820do { \
761 __asm__ __volatile__ ( \ 821 __asm__ __volatile__ ( \
762 ".set\tpush\n\t" \ 822 ".set\tpush\n\t" \
763 ".set\tnoat\n\t" \ 823 ".set\tnoat\n\t" \
@@ -797,10 +857,28 @@ extern void show_registers(struct pt_regs *regs);
797 ".previous" \ 857 ".previous" \
798 : "=&r" (res) \ 858 : "=&r" (res) \
799 : "r" (value), "r" (addr), "i" (-EFAULT) \ 859 : "r" (value), "r" (addr), "i" (-EFAULT) \
800 : "memory"); 860 : "memory"); \
861} while(0)
862
801#endif /* CONFIG_CPU_MIPSR6 */ 863#endif /* CONFIG_CPU_MIPSR6 */
802#endif 864#endif
803 865
866#define LoadHWU(addr, value, res) _LoadHWU(addr, value, res, kernel)
867#define LoadHWUE(addr, value, res) _LoadHWU(addr, value, res, user)
868#define LoadWU(addr, value, res) _LoadWU(addr, value, res, kernel)
869#define LoadWUE(addr, value, res) _LoadWU(addr, value, res, user)
870#define LoadHW(addr, value, res) _LoadHW(addr, value, res, kernel)
871#define LoadHWE(addr, value, res) _LoadHW(addr, value, res, user)
872#define LoadW(addr, value, res) _LoadW(addr, value, res, kernel)
873#define LoadWE(addr, value, res) _LoadW(addr, value, res, user)
874#define LoadDW(addr, value, res) _LoadDW(addr, value, res)
875
876#define StoreHW(addr, value, res) _StoreHW(addr, value, res, kernel)
877#define StoreHWE(addr, value, res) _StoreHW(addr, value, res, user)
878#define StoreW(addr, value, res) _StoreW(addr, value, res, kernel)
879#define StoreWE(addr, value, res) _StoreW(addr, value, res, user)
880#define StoreDW(addr, value, res) _StoreDW(addr, value, res)
881
804static void emulate_load_store_insn(struct pt_regs *regs, 882static void emulate_load_store_insn(struct pt_regs *regs,
805 void __user *addr, unsigned int __user *pc) 883 void __user *addr, unsigned int __user *pc)
806{ 884{
@@ -872,7 +950,7 @@ static void emulate_load_store_insn(struct pt_regs *regs,
872 set_fs(seg); 950 set_fs(seg);
873 goto sigbus; 951 goto sigbus;
874 } 952 }
875 LoadHW(addr, value, res); 953 LoadHWE(addr, value, res);
876 if (res) { 954 if (res) {
877 set_fs(seg); 955 set_fs(seg);
878 goto fault; 956 goto fault;
@@ -885,7 +963,7 @@ static void emulate_load_store_insn(struct pt_regs *regs,
885 set_fs(seg); 963 set_fs(seg);
886 goto sigbus; 964 goto sigbus;
887 } 965 }
888 LoadW(addr, value, res); 966 LoadWE(addr, value, res);
889 if (res) { 967 if (res) {
890 set_fs(seg); 968 set_fs(seg);
891 goto fault; 969 goto fault;
@@ -898,7 +976,7 @@ static void emulate_load_store_insn(struct pt_regs *regs,
898 set_fs(seg); 976 set_fs(seg);
899 goto sigbus; 977 goto sigbus;
900 } 978 }
901 LoadHWU(addr, value, res); 979 LoadHWUE(addr, value, res);
902 if (res) { 980 if (res) {
903 set_fs(seg); 981 set_fs(seg);
904 goto fault; 982 goto fault;
@@ -913,7 +991,7 @@ static void emulate_load_store_insn(struct pt_regs *regs,
913 } 991 }
914 compute_return_epc(regs); 992 compute_return_epc(regs);
915 value = regs->regs[insn.spec3_format.rt]; 993 value = regs->regs[insn.spec3_format.rt];
916 StoreHW(addr, value, res); 994 StoreHWE(addr, value, res);
917 if (res) { 995 if (res) {
918 set_fs(seg); 996 set_fs(seg);
919 goto fault; 997 goto fault;
@@ -926,7 +1004,7 @@ static void emulate_load_store_insn(struct pt_regs *regs,
926 } 1004 }
927 compute_return_epc(regs); 1005 compute_return_epc(regs);
928 value = regs->regs[insn.spec3_format.rt]; 1006 value = regs->regs[insn.spec3_format.rt];
929 StoreW(addr, value, res); 1007 StoreWE(addr, value, res);
930 if (res) { 1008 if (res) {
931 set_fs(seg); 1009 set_fs(seg);
932 goto fault; 1010 goto fault;
@@ -943,7 +1021,15 @@ static void emulate_load_store_insn(struct pt_regs *regs,
943 if (!access_ok(VERIFY_READ, addr, 2)) 1021 if (!access_ok(VERIFY_READ, addr, 2))
944 goto sigbus; 1022 goto sigbus;
945 1023
946 LoadHW(addr, value, res); 1024 if (config_enabled(CONFIG_EVA)) {
1025 if (segment_eq(get_fs(), get_ds()))
1026 LoadHW(addr, value, res);
1027 else
1028 LoadHWE(addr, value, res);
1029 } else {
1030 LoadHW(addr, value, res);
1031 }
1032
947 if (res) 1033 if (res)
948 goto fault; 1034 goto fault;
949 compute_return_epc(regs); 1035 compute_return_epc(regs);
@@ -954,7 +1040,15 @@ static void emulate_load_store_insn(struct pt_regs *regs,
954 if (!access_ok(VERIFY_READ, addr, 4)) 1040 if (!access_ok(VERIFY_READ, addr, 4))
955 goto sigbus; 1041 goto sigbus;
956 1042
957 LoadW(addr, value, res); 1043 if (config_enabled(CONFIG_EVA)) {
1044 if (segment_eq(get_fs(), get_ds()))
1045 LoadW(addr, value, res);
1046 else
1047 LoadWE(addr, value, res);
1048 } else {
1049 LoadW(addr, value, res);
1050 }
1051
958 if (res) 1052 if (res)
959 goto fault; 1053 goto fault;
960 compute_return_epc(regs); 1054 compute_return_epc(regs);
@@ -965,7 +1059,15 @@ static void emulate_load_store_insn(struct pt_regs *regs,
965 if (!access_ok(VERIFY_READ, addr, 2)) 1059 if (!access_ok(VERIFY_READ, addr, 2))
966 goto sigbus; 1060 goto sigbus;
967 1061
968 LoadHWU(addr, value, res); 1062 if (config_enabled(CONFIG_EVA)) {
1063 if (segment_eq(get_fs(), get_ds()))
1064 LoadHWU(addr, value, res);
1065 else
1066 LoadHWUE(addr, value, res);
1067 } else {
1068 LoadHWU(addr, value, res);
1069 }
1070
969 if (res) 1071 if (res)
970 goto fault; 1072 goto fault;
971 compute_return_epc(regs); 1073 compute_return_epc(regs);
@@ -1024,7 +1126,16 @@ static void emulate_load_store_insn(struct pt_regs *regs,
1024 1126
1025 compute_return_epc(regs); 1127 compute_return_epc(regs);
1026 value = regs->regs[insn.i_format.rt]; 1128 value = regs->regs[insn.i_format.rt];
1027 StoreHW(addr, value, res); 1129
1130 if (config_enabled(CONFIG_EVA)) {
1131 if (segment_eq(get_fs(), get_ds()))
1132 StoreHW(addr, value, res);
1133 else
1134 StoreHWE(addr, value, res);
1135 } else {
1136 StoreHW(addr, value, res);
1137 }
1138
1028 if (res) 1139 if (res)
1029 goto fault; 1140 goto fault;
1030 break; 1141 break;
@@ -1035,7 +1146,16 @@ static void emulate_load_store_insn(struct pt_regs *regs,
1035 1146
1036 compute_return_epc(regs); 1147 compute_return_epc(regs);
1037 value = regs->regs[insn.i_format.rt]; 1148 value = regs->regs[insn.i_format.rt];
1038 StoreW(addr, value, res); 1149
1150 if (config_enabled(CONFIG_EVA)) {
1151 if (segment_eq(get_fs(), get_ds()))
1152 StoreW(addr, value, res);
1153 else
1154 StoreWE(addr, value, res);
1155 } else {
1156 StoreW(addr, value, res);
1157 }
1158
1039 if (res) 1159 if (res)
1040 goto fault; 1160 goto fault;
1041 break; 1161 break;
@@ -1076,7 +1196,7 @@ static void emulate_load_store_insn(struct pt_regs *regs,
1076 own_fpu(1); /* Restore FPU state. */ 1196 own_fpu(1); /* Restore FPU state. */
1077 1197
1078 /* Signal if something went wrong. */ 1198 /* Signal if something went wrong. */
1079 process_fpemu_return(res, fault_addr); 1199 process_fpemu_return(res, fault_addr, 0);
1080 1200
1081 if (res == 0) 1201 if (res == 0)
1082 break; 1202 break;
@@ -1511,7 +1631,7 @@ fpu_emul:
1511 own_fpu(1); /* restore FPU state */ 1631 own_fpu(1); /* restore FPU state */
1512 1632
1513 /* If something went wrong, signal */ 1633 /* If something went wrong, signal */
1514 process_fpemu_return(res, fault_addr); 1634 process_fpemu_return(res, fault_addr, 0);
1515 1635
1516 if (res == 0) 1636 if (res == 0)
1517 goto success; 1637 goto success;
diff --git a/arch/mips/lantiq/prom.c b/arch/mips/lantiq/prom.c
index 39ab3e786e59..0db099ecc016 100644
--- a/arch/mips/lantiq/prom.c
+++ b/arch/mips/lantiq/prom.c
@@ -41,7 +41,7 @@ int ltq_soc_type(void)
41 return soc_info.type; 41 return soc_info.type;
42} 42}
43 43
44void prom_free_prom_memory(void) 44void __init prom_free_prom_memory(void)
45{ 45{
46} 46}
47 47
diff --git a/arch/mips/lantiq/xway/vmmc.c b/arch/mips/lantiq/xway/vmmc.c
index 696cd57f6f13..d001bc38908a 100644
--- a/arch/mips/lantiq/xway/vmmc.c
+++ b/arch/mips/lantiq/xway/vmmc.c
@@ -61,7 +61,6 @@ static struct platform_driver vmmc_driver = {
61 .probe = vmmc_probe, 61 .probe = vmmc_probe,
62 .driver = { 62 .driver = {
63 .name = "lantiq,vmmc", 63 .name = "lantiq,vmmc",
64 .owner = THIS_MODULE,
65 .of_match_table = vmmc_match, 64 .of_match_table = vmmc_match,
66 }, 65 },
67}; 66};
diff --git a/arch/mips/lasat/sysctl.c b/arch/mips/lasat/sysctl.c
index cf9b4633257e..a57959e648a6 100644
--- a/arch/mips/lasat/sysctl.c
+++ b/arch/mips/lasat/sysctl.c
@@ -53,21 +53,6 @@ int proc_dolasatstring(struct ctl_table *table, int write,
53 return 0; 53 return 0;
54} 54}
55 55
56/* proc function to write EEPROM after changing int entry */
57int proc_dolasatint(struct ctl_table *table, int write,
58 void *buffer, size_t *lenp, loff_t *ppos)
59{
60 int r;
61
62 r = proc_dointvec(table, write, buffer, lenp, ppos);
63 if ((!write) || r)
64 return r;
65
66 lasat_write_eeprom_info();
67
68 return 0;
69}
70
71#ifdef CONFIG_DS1603 56#ifdef CONFIG_DS1603
72static int rtctmp; 57static int rtctmp;
73 58
diff --git a/arch/mips/lib/csum_partial.S b/arch/mips/lib/csum_partial.S
index 4c721e247ac9..ed88647b57e2 100644
--- a/arch/mips/lib/csum_partial.S
+++ b/arch/mips/lib/csum_partial.S
@@ -76,10 +76,10 @@
76 LOAD _t1, (offset + UNIT(1))(src); \ 76 LOAD _t1, (offset + UNIT(1))(src); \
77 LOAD _t2, (offset + UNIT(2))(src); \ 77 LOAD _t2, (offset + UNIT(2))(src); \
78 LOAD _t3, (offset + UNIT(3))(src); \ 78 LOAD _t3, (offset + UNIT(3))(src); \
79 ADDC(_t0, _t1); \
80 ADDC(_t2, _t3); \
79 ADDC(sum, _t0); \ 81 ADDC(sum, _t0); \
80 ADDC(sum, _t1); \ 82 ADDC(sum, _t2)
81 ADDC(sum, _t2); \
82 ADDC(sum, _t3)
83 83
84#ifdef USE_DOUBLE 84#ifdef USE_DOUBLE
85#define CSUM_BIGCHUNK(src, offset, sum, _t0, _t1, _t2, _t3) \ 85#define CSUM_BIGCHUNK(src, offset, sum, _t0, _t1, _t2, _t3) \
@@ -504,21 +504,21 @@ LEAF(csum_partial)
504 SUB len, len, 8*NBYTES 504 SUB len, len, 8*NBYTES
505 ADD src, src, 8*NBYTES 505 ADD src, src, 8*NBYTES
506 STORE(t0, UNIT(0)(dst), .Ls_exc\@) 506 STORE(t0, UNIT(0)(dst), .Ls_exc\@)
507 ADDC(sum, t0) 507 ADDC(t0, t1)
508 STORE(t1, UNIT(1)(dst), .Ls_exc\@) 508 STORE(t1, UNIT(1)(dst), .Ls_exc\@)
509 ADDC(sum, t1) 509 ADDC(sum, t0)
510 STORE(t2, UNIT(2)(dst), .Ls_exc\@) 510 STORE(t2, UNIT(2)(dst), .Ls_exc\@)
511 ADDC(sum, t2) 511 ADDC(t2, t3)
512 STORE(t3, UNIT(3)(dst), .Ls_exc\@) 512 STORE(t3, UNIT(3)(dst), .Ls_exc\@)
513 ADDC(sum, t3) 513 ADDC(sum, t2)
514 STORE(t4, UNIT(4)(dst), .Ls_exc\@) 514 STORE(t4, UNIT(4)(dst), .Ls_exc\@)
515 ADDC(sum, t4) 515 ADDC(t4, t5)
516 STORE(t5, UNIT(5)(dst), .Ls_exc\@) 516 STORE(t5, UNIT(5)(dst), .Ls_exc\@)
517 ADDC(sum, t5) 517 ADDC(sum, t4)
518 STORE(t6, UNIT(6)(dst), .Ls_exc\@) 518 STORE(t6, UNIT(6)(dst), .Ls_exc\@)
519 ADDC(sum, t6) 519 ADDC(t6, t7)
520 STORE(t7, UNIT(7)(dst), .Ls_exc\@) 520 STORE(t7, UNIT(7)(dst), .Ls_exc\@)
521 ADDC(sum, t7) 521 ADDC(sum, t6)
522 .set reorder /* DADDI_WAR */ 522 .set reorder /* DADDI_WAR */
523 ADD dst, dst, 8*NBYTES 523 ADD dst, dst, 8*NBYTES
524 bgez len, 1b 524 bgez len, 1b
@@ -544,13 +544,13 @@ LEAF(csum_partial)
544 SUB len, len, 4*NBYTES 544 SUB len, len, 4*NBYTES
545 ADD src, src, 4*NBYTES 545 ADD src, src, 4*NBYTES
546 STORE(t0, UNIT(0)(dst), .Ls_exc\@) 546 STORE(t0, UNIT(0)(dst), .Ls_exc\@)
547 ADDC(sum, t0) 547 ADDC(t0, t1)
548 STORE(t1, UNIT(1)(dst), .Ls_exc\@) 548 STORE(t1, UNIT(1)(dst), .Ls_exc\@)
549 ADDC(sum, t1) 549 ADDC(sum, t0)
550 STORE(t2, UNIT(2)(dst), .Ls_exc\@) 550 STORE(t2, UNIT(2)(dst), .Ls_exc\@)
551 ADDC(sum, t2) 551 ADDC(t2, t3)
552 STORE(t3, UNIT(3)(dst), .Ls_exc\@) 552 STORE(t3, UNIT(3)(dst), .Ls_exc\@)
553 ADDC(sum, t3) 553 ADDC(sum, t2)
554 .set reorder /* DADDI_WAR */ 554 .set reorder /* DADDI_WAR */
555 ADD dst, dst, 4*NBYTES 555 ADD dst, dst, 4*NBYTES
556 beqz len, .Ldone\@ 556 beqz len, .Ldone\@
@@ -649,13 +649,13 @@ LEAF(csum_partial)
649 nop # improves slotting 649 nop # improves slotting
650#endif 650#endif
651 STORE(t0, UNIT(0)(dst), .Ls_exc\@) 651 STORE(t0, UNIT(0)(dst), .Ls_exc\@)
652 ADDC(sum, t0) 652 ADDC(t0, t1)
653 STORE(t1, UNIT(1)(dst), .Ls_exc\@) 653 STORE(t1, UNIT(1)(dst), .Ls_exc\@)
654 ADDC(sum, t1) 654 ADDC(sum, t0)
655 STORE(t2, UNIT(2)(dst), .Ls_exc\@) 655 STORE(t2, UNIT(2)(dst), .Ls_exc\@)
656 ADDC(sum, t2) 656 ADDC(t2, t3)
657 STORE(t3, UNIT(3)(dst), .Ls_exc\@) 657 STORE(t3, UNIT(3)(dst), .Ls_exc\@)
658 ADDC(sum, t3) 658 ADDC(sum, t2)
659 .set reorder /* DADDI_WAR */ 659 .set reorder /* DADDI_WAR */
660 ADD dst, dst, 4*NBYTES 660 ADD dst, dst, 4*NBYTES
661 bne len, rem, 1b 661 bne len, rem, 1b
diff --git a/arch/mips/loongson/common/env.c b/arch/mips/loongson/common/env.c
index 045ea3d47c87..22f04ca2ff3e 100644
--- a/arch/mips/loongson/common/env.c
+++ b/arch/mips/loongson/common/env.c
@@ -29,6 +29,7 @@ struct efi_memory_map_loongson *loongson_memmap;
29struct loongson_system_configuration loongson_sysconf; 29struct loongson_system_configuration loongson_sysconf;
30 30
31u64 loongson_chipcfg[MAX_PACKAGES] = {0xffffffffbfc00180}; 31u64 loongson_chipcfg[MAX_PACKAGES] = {0xffffffffbfc00180};
32u64 loongson_chiptemp[MAX_PACKAGES];
32u64 loongson_freqctrl[MAX_PACKAGES]; 33u64 loongson_freqctrl[MAX_PACKAGES];
33 34
34unsigned long long smp_group[4]; 35unsigned long long smp_group[4];
@@ -97,6 +98,10 @@ void __init prom_init_env(void)
97 loongson_chipcfg[1] = 0x900010001fe00180; 98 loongson_chipcfg[1] = 0x900010001fe00180;
98 loongson_chipcfg[2] = 0x900020001fe00180; 99 loongson_chipcfg[2] = 0x900020001fe00180;
99 loongson_chipcfg[3] = 0x900030001fe00180; 100 loongson_chipcfg[3] = 0x900030001fe00180;
101 loongson_chiptemp[0] = 0x900000001fe0019c;
102 loongson_chiptemp[1] = 0x900010001fe0019c;
103 loongson_chiptemp[2] = 0x900020001fe0019c;
104 loongson_chiptemp[3] = 0x900030001fe0019c;
100 loongson_sysconf.ht_control_base = 0x90000EFDFB000000; 105 loongson_sysconf.ht_control_base = 0x90000EFDFB000000;
101 loongson_sysconf.workarounds = WORKAROUND_CPUFREQ; 106 loongson_sysconf.workarounds = WORKAROUND_CPUFREQ;
102 } else if (ecpu->cputype == Loongson_3B) { 107 } else if (ecpu->cputype == Loongson_3B) {
@@ -110,6 +115,10 @@ void __init prom_init_env(void)
110 loongson_chipcfg[1] = 0x900020001fe00180; 115 loongson_chipcfg[1] = 0x900020001fe00180;
111 loongson_chipcfg[2] = 0x900040001fe00180; 116 loongson_chipcfg[2] = 0x900040001fe00180;
112 loongson_chipcfg[3] = 0x900060001fe00180; 117 loongson_chipcfg[3] = 0x900060001fe00180;
118 loongson_chiptemp[0] = 0x900000001fe0019c;
119 loongson_chiptemp[1] = 0x900020001fe0019c;
120 loongson_chiptemp[2] = 0x900040001fe0019c;
121 loongson_chiptemp[3] = 0x900060001fe0019c;
113 loongson_freqctrl[0] = 0x900000001fe001d0; 122 loongson_freqctrl[0] = 0x900000001fe001d0;
114 loongson_freqctrl[1] = 0x900020001fe001d0; 123 loongson_freqctrl[1] = 0x900020001fe001d0;
115 loongson_freqctrl[2] = 0x900040001fe001d0; 124 loongson_freqctrl[2] = 0x900040001fe001d0;
diff --git a/arch/mips/loongson/common/pci.c b/arch/mips/loongson/common/pci.c
index 003ab4e618b3..4e2575643781 100644
--- a/arch/mips/loongson/common/pci.c
+++ b/arch/mips/loongson/common/pci.c
@@ -78,6 +78,8 @@ static void __init setup_pcimap(void)
78#endif 78#endif
79} 79}
80 80
81extern int sbx00_acpi_init(void);
82
81static int __init pcibios_init(void) 83static int __init pcibios_init(void)
82{ 84{
83 setup_pcimap(); 85 setup_pcimap();
@@ -89,6 +91,10 @@ static int __init pcibios_init(void)
89#endif 91#endif
90 register_pci_controller(&loongson_pci_controller); 92 register_pci_controller(&loongson_pci_controller);
91 93
94#ifdef CONFIG_CPU_LOONGSON3
95 sbx00_acpi_init();
96#endif
97
92 return 0; 98 return 0;
93} 99}
94 100
diff --git a/arch/mips/loongson/loongson-3/cop2-ex.c b/arch/mips/loongson/loongson-3/cop2-ex.c
index b03e37d2071a..ea13764d0a03 100644
--- a/arch/mips/loongson/loongson-3/cop2-ex.c
+++ b/arch/mips/loongson/loongson-3/cop2-ex.c
@@ -43,7 +43,7 @@ static int loongson_cu2_call(struct notifier_block *nfb, unsigned long action,
43 if (!fpu_owned) { 43 if (!fpu_owned) {
44 set_thread_flag(TIF_USEDFPU); 44 set_thread_flag(TIF_USEDFPU);
45 if (!used_math()) { 45 if (!used_math()) {
46 _init_fpu(); 46 _init_fpu(current->thread.fpu.fcr31);
47 set_used_math(); 47 set_used_math();
48 } else 48 } else
49 _restore_fp(current); 49 _restore_fp(current);
diff --git a/arch/mips/loongson/loongson-3/irq.c b/arch/mips/loongson/loongson-3/irq.c
index 21221edda7a9..0f75b6b3d218 100644
--- a/arch/mips/loongson/loongson-3/irq.c
+++ b/arch/mips/loongson/loongson-3/irq.c
@@ -44,6 +44,7 @@ void mach_irq_dispatch(unsigned int pending)
44 44
45static struct irqaction cascade_irqaction = { 45static struct irqaction cascade_irqaction = {
46 .handler = no_action, 46 .handler = no_action,
47 .flags = IRQF_NO_SUSPEND,
47 .name = "cascade", 48 .name = "cascade",
48}; 49};
49 50
diff --git a/arch/mips/math-emu/Makefile b/arch/mips/math-emu/Makefile
index 619cfc1a2442..2e5f96275c38 100644
--- a/arch/mips/math-emu/Makefile
+++ b/arch/mips/math-emu/Makefile
@@ -2,12 +2,15 @@
2# Makefile for the Linux/MIPS kernel FPU emulation. 2# Makefile for the Linux/MIPS kernel FPU emulation.
3# 3#
4 4
5obj-y += cp1emu.o ieee754dp.o ieee754sp.o ieee754.o dp_div.o dp_mul.o \ 5obj-y += cp1emu.o ieee754dp.o ieee754sp.o ieee754.o \
6 dp_sub.o dp_add.o dp_fsp.o dp_cmp.o dp_simple.o dp_tint.o \ 6 dp_div.o dp_mul.o dp_sub.o dp_add.o dp_fsp.o dp_cmp.o dp_simple.o \
7 dp_fint.o dp_tlong.o dp_flong.o sp_div.o sp_mul.o sp_sub.o \ 7 dp_tint.o dp_fint.o \
8 sp_add.o sp_fdp.o sp_cmp.o sp_simple.o sp_tint.o sp_fint.o \ 8 sp_div.o sp_mul.o sp_sub.o sp_add.o sp_fdp.o sp_cmp.o sp_simple.o \
9 sp_tlong.o sp_flong.o dsemul.o 9 sp_tint.o sp_fint.o \
10 dsemul.o
10 11
11lib-y += ieee754d.o dp_sqrt.o sp_sqrt.o 12lib-y += ieee754d.o \
13 dp_tlong.o dp_flong.o dp_sqrt.o \
14 sp_tlong.o sp_flong.o sp_sqrt.o
12 15
13obj-$(CONFIG_DEBUG_FS) += me-debugfs.o 16obj-$(CONFIG_DEBUG_FS) += me-debugfs.o
diff --git a/arch/mips/math-emu/cp1emu.c b/arch/mips/math-emu/cp1emu.c
index b30bf65c7d7d..d31c537ace1d 100644
--- a/arch/mips/math-emu/cp1emu.c
+++ b/arch/mips/math-emu/cp1emu.c
@@ -45,6 +45,7 @@
45#include <asm/signal.h> 45#include <asm/signal.h>
46#include <asm/uaccess.h> 46#include <asm/uaccess.h>
47 47
48#include <asm/cpu-info.h>
48#include <asm/processor.h> 49#include <asm/processor.h>
49#include <asm/fpu_emulator.h> 50#include <asm/fpu_emulator.h>
50#include <asm/fpu.h> 51#include <asm/fpu.h>
@@ -63,14 +64,14 @@ static int fpux_emu(struct pt_regs *,
63/* Control registers */ 64/* Control registers */
64 65
65#define FPCREG_RID 0 /* $0 = revision id */ 66#define FPCREG_RID 0 /* $0 = revision id */
67#define FPCREG_FCCR 25 /* $25 = fccr */
68#define FPCREG_FEXR 26 /* $26 = fexr */
69#define FPCREG_FENR 28 /* $28 = fenr */
66#define FPCREG_CSR 31 /* $31 = csr */ 70#define FPCREG_CSR 31 /* $31 = csr */
67 71
68/* Determine rounding mode from the RM bits of the FCSR */
69#define modeindex(v) ((v) & FPU_CSR_RM)
70
71/* convert condition code register number to csr bit */ 72/* convert condition code register number to csr bit */
72const unsigned int fpucondbit[8] = { 73const unsigned int fpucondbit[8] = {
73 FPU_CSR_COND0, 74 FPU_CSR_COND,
74 FPU_CSR_COND1, 75 FPU_CSR_COND1,
75 FPU_CSR_COND2, 76 FPU_CSR_COND2,
76 FPU_CSR_COND3, 77 FPU_CSR_COND3,
@@ -843,6 +844,127 @@ do { \
843#define DPTOREG(dp, x) DITOREG((dp).bits, x) 844#define DPTOREG(dp, x) DITOREG((dp).bits, x)
844 845
845/* 846/*
847 * Emulate a CFC1 instruction.
848 */
849static inline void cop1_cfc(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
850 mips_instruction ir)
851{
852 u32 fcr31 = ctx->fcr31;
853 u32 value = 0;
854
855 switch (MIPSInst_RD(ir)) {
856 case FPCREG_CSR:
857 value = fcr31;
858 pr_debug("%p gpr[%d]<-csr=%08x\n",
859 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
860 break;
861
862 case FPCREG_FENR:
863 if (!cpu_has_mips_r)
864 break;
865 value = (fcr31 >> (FPU_CSR_FS_S - MIPS_FENR_FS_S)) &
866 MIPS_FENR_FS;
867 value |= fcr31 & (FPU_CSR_ALL_E | FPU_CSR_RM);
868 pr_debug("%p gpr[%d]<-enr=%08x\n",
869 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
870 break;
871
872 case FPCREG_FEXR:
873 if (!cpu_has_mips_r)
874 break;
875 value = fcr31 & (FPU_CSR_ALL_X | FPU_CSR_ALL_S);
876 pr_debug("%p gpr[%d]<-exr=%08x\n",
877 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
878 break;
879
880 case FPCREG_FCCR:
881 if (!cpu_has_mips_r)
882 break;
883 value = (fcr31 >> (FPU_CSR_COND_S - MIPS_FCCR_COND0_S)) &
884 MIPS_FCCR_COND0;
885 value |= (fcr31 >> (FPU_CSR_COND1_S - MIPS_FCCR_COND1_S)) &
886 (MIPS_FCCR_CONDX & ~MIPS_FCCR_COND0);
887 pr_debug("%p gpr[%d]<-ccr=%08x\n",
888 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
889 break;
890
891 case FPCREG_RID:
892 value = current_cpu_data.fpu_id;
893 break;
894
895 default:
896 break;
897 }
898
899 if (MIPSInst_RT(ir))
900 xcp->regs[MIPSInst_RT(ir)] = value;
901}
902
903/*
904 * Emulate a CTC1 instruction.
905 */
906static inline void cop1_ctc(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
907 mips_instruction ir)
908{
909 u32 fcr31 = ctx->fcr31;
910 u32 value;
911 u32 mask;
912
913 if (MIPSInst_RT(ir) == 0)
914 value = 0;
915 else
916 value = xcp->regs[MIPSInst_RT(ir)];
917
918 switch (MIPSInst_RD(ir)) {
919 case FPCREG_CSR:
920 pr_debug("%p gpr[%d]->csr=%08x\n",
921 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
922
923 /* Preserve read-only bits. */
924 mask = current_cpu_data.fpu_msk31;
925 fcr31 = (value & ~mask) | (fcr31 & mask);
926 break;
927
928 case FPCREG_FENR:
929 if (!cpu_has_mips_r)
930 break;
931 pr_debug("%p gpr[%d]->enr=%08x\n",
932 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
933 fcr31 &= ~(FPU_CSR_FS | FPU_CSR_ALL_E | FPU_CSR_RM);
934 fcr31 |= (value << (FPU_CSR_FS_S - MIPS_FENR_FS_S)) &
935 FPU_CSR_FS;
936 fcr31 |= value & (FPU_CSR_ALL_E | FPU_CSR_RM);
937 break;
938
939 case FPCREG_FEXR:
940 if (!cpu_has_mips_r)
941 break;
942 pr_debug("%p gpr[%d]->exr=%08x\n",
943 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
944 fcr31 &= ~(FPU_CSR_ALL_X | FPU_CSR_ALL_S);
945 fcr31 |= value & (FPU_CSR_ALL_X | FPU_CSR_ALL_S);
946 break;
947
948 case FPCREG_FCCR:
949 if (!cpu_has_mips_r)
950 break;
951 pr_debug("%p gpr[%d]->ccr=%08x\n",
952 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
953 fcr31 &= ~(FPU_CSR_CONDX | FPU_CSR_COND);
954 fcr31 |= (value << (FPU_CSR_COND_S - MIPS_FCCR_COND0_S)) &
955 FPU_CSR_COND;
956 fcr31 |= (value << (FPU_CSR_COND1_S - MIPS_FCCR_COND1_S)) &
957 FPU_CSR_CONDX;
958 break;
959
960 default:
961 break;
962 }
963
964 ctx->fcr31 = fcr31;
965}
966
967/*
846 * Emulate the single floating point instruction pointed at by EPC. 968 * Emulate the single floating point instruction pointed at by EPC.
847 * Two instructions if the instruction is in a branch delay slot. 969 * Two instructions if the instruction is in a branch delay slot.
848 */ 970 */
@@ -856,7 +978,6 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
856 int likely, pc_inc; 978 int likely, pc_inc;
857 u32 __user *wva; 979 u32 __user *wva;
858 u64 __user *dva; 980 u64 __user *dva;
859 u32 value;
860 u32 wval; 981 u32 wval;
861 u64 dval; 982 u64 dval;
862 int sig; 983 int sig;
@@ -1049,42 +1170,12 @@ emul:
1049 1170
1050 case cfc_op: 1171 case cfc_op:
1051 /* cop control register rd -> gpr[rt] */ 1172 /* cop control register rd -> gpr[rt] */
1052 if (MIPSInst_RD(ir) == FPCREG_CSR) { 1173 cop1_cfc(xcp, ctx, ir);
1053 value = ctx->fcr31;
1054 value = (value & ~FPU_CSR_RM) | modeindex(value);
1055 pr_debug("%p gpr[%d]<-csr=%08x\n",
1056 (void *) (xcp->cp0_epc),
1057 MIPSInst_RT(ir), value);
1058 }
1059 else if (MIPSInst_RD(ir) == FPCREG_RID)
1060 value = 0;
1061 else
1062 value = 0;
1063 if (MIPSInst_RT(ir))
1064 xcp->regs[MIPSInst_RT(ir)] = value;
1065 break; 1174 break;
1066 1175
1067 case ctc_op: 1176 case ctc_op:
1068 /* copregister rd <- rt */ 1177 /* copregister rd <- rt */
1069 if (MIPSInst_RT(ir) == 0) 1178 cop1_ctc(xcp, ctx, ir);
1070 value = 0;
1071 else
1072 value = xcp->regs[MIPSInst_RT(ir)];
1073
1074 /* we only have one writable control reg
1075 */
1076 if (MIPSInst_RD(ir) == FPCREG_CSR) {
1077 pr_debug("%p gpr[%d]->csr=%08x\n",
1078 (void *) (xcp->cp0_epc),
1079 MIPSInst_RT(ir), value);
1080
1081 /*
1082 * Don't write reserved bits,
1083 * and convert to ieee library modes
1084 */
1085 ctx->fcr31 = (value & ~(FPU_CSR_RSVD | FPU_CSR_RM)) |
1086 modeindex(value);
1087 }
1088 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) { 1179 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
1089 return SIGFPE; 1180 return SIGFPE;
1090 } 1181 }
@@ -1103,17 +1194,18 @@ emul:
1103 likely = 0; 1194 likely = 0;
1104 switch (MIPSInst_RT(ir) & 3) { 1195 switch (MIPSInst_RT(ir) & 3) {
1105 case bcfl_op: 1196 case bcfl_op:
1106 likely = 1; 1197 if (cpu_has_mips_2_3_4_5_r)
1198 likely = 1;
1199 /* Fall through */
1107 case bcf_op: 1200 case bcf_op:
1108 cond = !cond; 1201 cond = !cond;
1109 break; 1202 break;
1110 case bctl_op: 1203 case bctl_op:
1111 likely = 1; 1204 if (cpu_has_mips_2_3_4_5_r)
1205 likely = 1;
1206 /* Fall through */
1112 case bct_op: 1207 case bct_op:
1113 break; 1208 break;
1114 default:
1115 /* thats an illegal instruction */
1116 return SIGILL;
1117 } 1209 }
1118 1210
1119 set_delay_slot(xcp); 1211 set_delay_slot(xcp);
@@ -1121,6 +1213,14 @@ emul:
1121 /* 1213 /*
1122 * Branch taken: emulate dslot instruction 1214 * Branch taken: emulate dslot instruction
1123 */ 1215 */
1216 unsigned long bcpc;
1217
1218 /*
1219 * Remember EPC at the branch to point back
1220 * at so that any delay-slot instruction
1221 * signal is not silently ignored.
1222 */
1223 bcpc = xcp->cp0_epc;
1124 xcp->cp0_epc += dec_insn.pc_inc; 1224 xcp->cp0_epc += dec_insn.pc_inc;
1125 1225
1126 contpc = MIPSInst_SIMM(ir); 1226 contpc = MIPSInst_SIMM(ir);
@@ -1146,63 +1246,77 @@ emul:
1146 * Single step the non-CP1 1246 * Single step the non-CP1
1147 * instruction in the dslot. 1247 * instruction in the dslot.
1148 */ 1248 */
1149 return mips_dsemul(xcp, ir, contpc); 1249 sig = mips_dsemul(xcp, ir,
1250 contpc);
1251 if (sig)
1252 xcp->cp0_epc = bcpc;
1253 /*
1254 * SIGILL forces out of
1255 * the emulation loop.
1256 */
1257 return sig ? sig : SIGILL;
1150 } 1258 }
1151 } else 1259 } else
1152 contpc = (xcp->cp0_epc + (contpc << 2)); 1260 contpc = (xcp->cp0_epc + (contpc << 2));
1153 1261
1154 switch (MIPSInst_OPCODE(ir)) { 1262 switch (MIPSInst_OPCODE(ir)) {
1155 case lwc1_op: 1263 case lwc1_op:
1156 goto emul;
1157
1158 case swc1_op: 1264 case swc1_op:
1159 goto emul; 1265 goto emul;
1160 1266
1161 case ldc1_op: 1267 case ldc1_op:
1162 case sdc1_op: 1268 case sdc1_op:
1163 if (cpu_has_mips_2_3_4_5 || 1269 if (cpu_has_mips_2_3_4_5_r)
1164 cpu_has_mips64)
1165 goto emul; 1270 goto emul;
1166 1271
1167 return SIGILL; 1272 goto bc_sigill;
1168 goto emul;
1169 1273
1170 case cop1_op: 1274 case cop1_op:
1171 goto emul; 1275 goto emul;
1172 1276
1173 case cop1x_op: 1277 case cop1x_op:
1174 if (cpu_has_mips_4_5 || cpu_has_mips64 || cpu_has_mips32r2) 1278 if (cpu_has_mips_4_5_64_r2_r6)
1175 /* its one of ours */ 1279 /* its one of ours */
1176 goto emul; 1280 goto emul;
1177 1281
1178 return SIGILL; 1282 goto bc_sigill;
1179 1283
1180 case spec_op: 1284 case spec_op:
1181 if (!cpu_has_mips_4_5_r) 1285 switch (MIPSInst_FUNC(ir)) {
1182 return SIGILL; 1286 case movc_op:
1287 if (cpu_has_mips_4_5_r)
1288 goto emul;
1183 1289
1184 if (MIPSInst_FUNC(ir) == movc_op) 1290 goto bc_sigill;
1185 goto emul; 1291 }
1186 break; 1292 break;
1293
1294 bc_sigill:
1295 xcp->cp0_epc = bcpc;
1296 return SIGILL;
1187 } 1297 }
1188 1298
1189 /* 1299 /*
1190 * Single step the non-cp1 1300 * Single step the non-cp1
1191 * instruction in the dslot 1301 * instruction in the dslot
1192 */ 1302 */
1193 return mips_dsemul(xcp, ir, contpc); 1303 sig = mips_dsemul(xcp, ir, contpc);
1304 if (sig)
1305 xcp->cp0_epc = bcpc;
1306 /* SIGILL forces out of the emulation loop. */
1307 return sig ? sig : SIGILL;
1194 } else if (likely) { /* branch not taken */ 1308 } else if (likely) { /* branch not taken */
1195 /* 1309 /*
1196 * branch likely nullifies 1310 * branch likely nullifies
1197 * dslot if not taken 1311 * dslot if not taken
1198 */ 1312 */
1199 xcp->cp0_epc += dec_insn.pc_inc; 1313 xcp->cp0_epc += dec_insn.pc_inc;
1200 contpc += dec_insn.pc_inc; 1314 contpc += dec_insn.pc_inc;
1201 /* 1315 /*
1202 * else continue & execute 1316 * else continue & execute
1203 * dslot as normal insn 1317 * dslot as normal insn
1204 */ 1318 */
1205 } 1319 }
1206 break; 1320 break;
1207 1321
1208 default: 1322 default:
@@ -1216,7 +1330,7 @@ emul:
1216 break; 1330 break;
1217 1331
1218 case cop1x_op: 1332 case cop1x_op:
1219 if (!cpu_has_mips_4_5 && !cpu_has_mips64 && !cpu_has_mips32r2) 1333 if (!cpu_has_mips_4_5_64_r2_r6)
1220 return SIGILL; 1334 return SIGILL;
1221 1335
1222 sig = fpux_emu(xcp, ctx, ir, fault_addr); 1336 sig = fpux_emu(xcp, ctx, ir, fault_addr);
@@ -1549,7 +1663,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
1549 1663
1550 /* unary ops */ 1664 /* unary ops */
1551 case fsqrt_op: 1665 case fsqrt_op:
1552 if (!cpu_has_mips_4_5_r) 1666 if (!cpu_has_mips_2_3_4_5_r)
1553 return SIGILL; 1667 return SIGILL;
1554 1668
1555 handler.u = ieee754sp_sqrt; 1669 handler.u = ieee754sp_sqrt;
@@ -1561,14 +1675,14 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
1561 * achieve full IEEE-754 accuracy - however this emulator does. 1675 * achieve full IEEE-754 accuracy - however this emulator does.
1562 */ 1676 */
1563 case frsqrt_op: 1677 case frsqrt_op:
1564 if (!cpu_has_mips_4_5_r2_r6) 1678 if (!cpu_has_mips_4_5_64_r2_r6)
1565 return SIGILL; 1679 return SIGILL;
1566 1680
1567 handler.u = fpemu_sp_rsqrt; 1681 handler.u = fpemu_sp_rsqrt;
1568 goto scopuop; 1682 goto scopuop;
1569 1683
1570 case frecip_op: 1684 case frecip_op:
1571 if (!cpu_has_mips_4_5_r2_r6) 1685 if (!cpu_has_mips_4_5_64_r2_r6)
1572 return SIGILL; 1686 return SIGILL;
1573 1687
1574 handler.u = fpemu_sp_recip; 1688 handler.u = fpemu_sp_recip;
@@ -1670,19 +1784,19 @@ copcsr:
1670 case ftrunc_op: 1784 case ftrunc_op:
1671 case fceil_op: 1785 case fceil_op:
1672 case ffloor_op: 1786 case ffloor_op:
1673 if (!cpu_has_mips_2_3_4_5 && !cpu_has_mips64) 1787 if (!cpu_has_mips_2_3_4_5_r)
1674 return SIGILL; 1788 return SIGILL;
1675 1789
1676 oldrm = ieee754_csr.rm; 1790 oldrm = ieee754_csr.rm;
1677 SPFROMREG(fs, MIPSInst_FS(ir)); 1791 SPFROMREG(fs, MIPSInst_FS(ir));
1678 ieee754_csr.rm = modeindex(MIPSInst_FUNC(ir)); 1792 ieee754_csr.rm = MIPSInst_FUNC(ir);
1679 rv.w = ieee754sp_tint(fs); 1793 rv.w = ieee754sp_tint(fs);
1680 ieee754_csr.rm = oldrm; 1794 ieee754_csr.rm = oldrm;
1681 rfmt = w_fmt; 1795 rfmt = w_fmt;
1682 goto copcsr; 1796 goto copcsr;
1683 1797
1684 case fcvtl_op: 1798 case fcvtl_op:
1685 if (!cpu_has_mips_3_4_5 && !cpu_has_mips64) 1799 if (!cpu_has_mips_3_4_5_64_r2_r6)
1686 return SIGILL; 1800 return SIGILL;
1687 1801
1688 SPFROMREG(fs, MIPSInst_FS(ir)); 1802 SPFROMREG(fs, MIPSInst_FS(ir));
@@ -1694,12 +1808,12 @@ copcsr:
1694 case ftruncl_op: 1808 case ftruncl_op:
1695 case fceill_op: 1809 case fceill_op:
1696 case ffloorl_op: 1810 case ffloorl_op:
1697 if (!cpu_has_mips_3_4_5 && !cpu_has_mips64) 1811 if (!cpu_has_mips_3_4_5_64_r2_r6)
1698 return SIGILL; 1812 return SIGILL;
1699 1813
1700 oldrm = ieee754_csr.rm; 1814 oldrm = ieee754_csr.rm;
1701 SPFROMREG(fs, MIPSInst_FS(ir)); 1815 SPFROMREG(fs, MIPSInst_FS(ir));
1702 ieee754_csr.rm = modeindex(MIPSInst_FUNC(ir)); 1816 ieee754_csr.rm = MIPSInst_FUNC(ir);
1703 rv.l = ieee754sp_tlong(fs); 1817 rv.l = ieee754sp_tlong(fs);
1704 ieee754_csr.rm = oldrm; 1818 ieee754_csr.rm = oldrm;
1705 rfmt = l_fmt; 1819 rfmt = l_fmt;
@@ -1763,13 +1877,13 @@ copcsr:
1763 * achieve full IEEE-754 accuracy - however this emulator does. 1877 * achieve full IEEE-754 accuracy - however this emulator does.
1764 */ 1878 */
1765 case frsqrt_op: 1879 case frsqrt_op:
1766 if (!cpu_has_mips_4_5_r2_r6) 1880 if (!cpu_has_mips_4_5_64_r2_r6)
1767 return SIGILL; 1881 return SIGILL;
1768 1882
1769 handler.u = fpemu_dp_rsqrt; 1883 handler.u = fpemu_dp_rsqrt;
1770 goto dcopuop; 1884 goto dcopuop;
1771 case frecip_op: 1885 case frecip_op:
1772 if (!cpu_has_mips_4_5_r2_r6) 1886 if (!cpu_has_mips_4_5_64_r2_r6)
1773 return SIGILL; 1887 return SIGILL;
1774 1888
1775 handler.u = fpemu_dp_recip; 1889 handler.u = fpemu_dp_recip;
@@ -1852,14 +1966,14 @@ dcopuop:
1852 1966
1853 oldrm = ieee754_csr.rm; 1967 oldrm = ieee754_csr.rm;
1854 DPFROMREG(fs, MIPSInst_FS(ir)); 1968 DPFROMREG(fs, MIPSInst_FS(ir));
1855 ieee754_csr.rm = modeindex(MIPSInst_FUNC(ir)); 1969 ieee754_csr.rm = MIPSInst_FUNC(ir);
1856 rv.w = ieee754dp_tint(fs); 1970 rv.w = ieee754dp_tint(fs);
1857 ieee754_csr.rm = oldrm; 1971 ieee754_csr.rm = oldrm;
1858 rfmt = w_fmt; 1972 rfmt = w_fmt;
1859 goto copcsr; 1973 goto copcsr;
1860 1974
1861 case fcvtl_op: 1975 case fcvtl_op:
1862 if (!cpu_has_mips_3_4_5 && !cpu_has_mips64) 1976 if (!cpu_has_mips_3_4_5_64_r2_r6)
1863 return SIGILL; 1977 return SIGILL;
1864 1978
1865 DPFROMREG(fs, MIPSInst_FS(ir)); 1979 DPFROMREG(fs, MIPSInst_FS(ir));
@@ -1871,12 +1985,12 @@ dcopuop:
1871 case ftruncl_op: 1985 case ftruncl_op:
1872 case fceill_op: 1986 case fceill_op:
1873 case ffloorl_op: 1987 case ffloorl_op:
1874 if (!cpu_has_mips_3_4_5 && !cpu_has_mips64) 1988 if (!cpu_has_mips_3_4_5_64_r2_r6)
1875 return SIGILL; 1989 return SIGILL;
1876 1990
1877 oldrm = ieee754_csr.rm; 1991 oldrm = ieee754_csr.rm;
1878 DPFROMREG(fs, MIPSInst_FS(ir)); 1992 DPFROMREG(fs, MIPSInst_FS(ir));
1879 ieee754_csr.rm = modeindex(MIPSInst_FUNC(ir)); 1993 ieee754_csr.rm = MIPSInst_FUNC(ir);
1880 rv.l = ieee754dp_tlong(fs); 1994 rv.l = ieee754dp_tlong(fs);
1881 ieee754_csr.rm = oldrm; 1995 ieee754_csr.rm = oldrm;
1882 rfmt = l_fmt; 1996 rfmt = l_fmt;
@@ -1930,7 +2044,7 @@ dcopuop:
1930 2044
1931 case l_fmt: 2045 case l_fmt:
1932 2046
1933 if (!cpu_has_mips_3_4_5 && !cpu_has_mips64) 2047 if (!cpu_has_mips_3_4_5_64_r2_r6)
1934 return SIGILL; 2048 return SIGILL;
1935 2049
1936 DIFROMREG(bits, MIPSInst_FS(ir)); 2050 DIFROMREG(bits, MIPSInst_FS(ir));
@@ -1994,7 +2108,7 @@ dcopuop:
1994 SITOREG(rv.w, MIPSInst_FD(ir)); 2108 SITOREG(rv.w, MIPSInst_FD(ir));
1995 break; 2109 break;
1996 case l_fmt: 2110 case l_fmt:
1997 if (!cpu_has_mips_3_4_5 && !cpu_has_mips64) 2111 if (!cpu_has_mips_3_4_5_64_r2_r6)
1998 return SIGILL; 2112 return SIGILL;
1999 2113
2000 DITOREG(rv.l, MIPSInst_FD(ir)); 2114 DITOREG(rv.l, MIPSInst_FD(ir));
@@ -2081,10 +2195,8 @@ int fpu_emulator_cop1Handler(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
2081 xcp->cp0_epc += dec_insn.pc_inc; /* Skip NOPs */ 2195 xcp->cp0_epc += dec_insn.pc_inc; /* Skip NOPs */
2082 else { 2196 else {
2083 /* 2197 /*
2084 * The 'ieee754_csr' is an alias of 2198 * The 'ieee754_csr' is an alias of ctx->fcr31.
2085 * ctx->fcr31. No need to copy ctx->fcr31 to 2199 * No need to copy ctx->fcr31 to ieee754_csr.
2086 * ieee754_csr. But ieee754_csr.rm is ieee
2087 * library modes. (not mips rounding mode)
2088 */ 2200 */
2089 sig = cop1Emulate(xcp, ctx, dec_insn, fault_addr); 2201 sig = cop1Emulate(xcp, ctx, dec_insn, fault_addr);
2090 } 2202 }
diff --git a/arch/mips/math-emu/dp_add.c b/arch/mips/math-emu/dp_add.c
index 7f64577df984..8954ef031f84 100644
--- a/arch/mips/math-emu/dp_add.c
+++ b/arch/mips/math-emu/dp_add.c
@@ -37,19 +37,20 @@ union ieee754dp ieee754dp_add(union ieee754dp x, union ieee754dp y)
37 FLUSHYDP; 37 FLUSHYDP;
38 38
39 switch (CLPAIR(xc, yc)) { 39 switch (CLPAIR(xc, yc)) {
40 case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_QNAN):
41 case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_SNAN): 40 case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_SNAN):
42 case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_SNAN):
43 case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_SNAN): 41 case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_SNAN):
44 case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_SNAN): 42 case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_SNAN):
45 case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_SNAN): 43 case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_SNAN):
46 case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_SNAN): 44 case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_SNAN):
45 return ieee754dp_nanxcpt(y);
46
47 case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_SNAN):
48 case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_QNAN):
47 case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_ZERO): 49 case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_ZERO):
48 case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_NORM): 50 case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_NORM):
49 case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_DNORM): 51 case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_DNORM):
50 case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_INF): 52 case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_INF):
51 ieee754_setcx(IEEE754_INVALID_OPERATION); 53 return ieee754dp_nanxcpt(x);
52 return ieee754dp_nanxcpt(ieee754dp_indef());
53 54
54 case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_QNAN): 55 case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_QNAN):
55 case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_QNAN): 56 case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_QNAN):
@@ -150,8 +151,6 @@ union ieee754dp ieee754dp_add(union ieee754dp x, union ieee754dp y)
150 * leaving result in xm, xs and xe. 151 * leaving result in xm, xs and xe.
151 */ 152 */
152 xm = xm + ym; 153 xm = xm + ym;
153 xe = xe;
154 xs = xs;
155 154
156 if (xm >> (DP_FBITS + 1 + 3)) { /* carry out */ 155 if (xm >> (DP_FBITS + 1 + 3)) { /* carry out */
157 xm = XDPSRS1(xm); 156 xm = XDPSRS1(xm);
@@ -160,11 +159,8 @@ union ieee754dp ieee754dp_add(union ieee754dp x, union ieee754dp y)
160 } else { 159 } else {
161 if (xm >= ym) { 160 if (xm >= ym) {
162 xm = xm - ym; 161 xm = xm - ym;
163 xe = xe;
164 xs = xs;
165 } else { 162 } else {
166 xm = ym - xm; 163 xm = ym - xm;
167 xe = xe;
168 xs = ys; 164 xs = ys;
169 } 165 }
170 if (xm == 0) 166 if (xm == 0)
diff --git a/arch/mips/math-emu/dp_cmp.c b/arch/mips/math-emu/dp_cmp.c
index 30f95f6e9ac4..a29880e29ae4 100644
--- a/arch/mips/math-emu/dp_cmp.c
+++ b/arch/mips/math-emu/dp_cmp.c
@@ -35,16 +35,11 @@ int ieee754dp_cmp(union ieee754dp x, union ieee754dp y, int cmp, int sig)
35 FLUSHYDP; 35 FLUSHYDP;
36 ieee754_clearcx(); /* Even clear inexact flag here */ 36 ieee754_clearcx(); /* Even clear inexact flag here */
37 37
38 if (ieee754dp_isnan(x) || ieee754dp_isnan(y)) { 38 if (ieee754_class_nan(xc) || ieee754_class_nan(yc)) {
39 if (sig || xc == IEEE754_CLASS_SNAN || yc == IEEE754_CLASS_SNAN) 39 if (sig ||
40 xc == IEEE754_CLASS_SNAN || yc == IEEE754_CLASS_SNAN)
40 ieee754_setcx(IEEE754_INVALID_OPERATION); 41 ieee754_setcx(IEEE754_INVALID_OPERATION);
41 if (cmp & IEEE754_CUN) 42 return (cmp & IEEE754_CUN) != 0;
42 return 1;
43 if (cmp & (IEEE754_CLT | IEEE754_CGT)) {
44 if (sig && ieee754_setandtestcx(IEEE754_INVALID_OPERATION))
45 return 0;
46 }
47 return 0;
48 } else { 43 } else {
49 vx = x.bits; 44 vx = x.bits;
50 vy = y.bits; 45 vy = y.bits;
diff --git a/arch/mips/math-emu/dp_div.c b/arch/mips/math-emu/dp_div.c
index bef0e55e5938..f4746f7c5f63 100644
--- a/arch/mips/math-emu/dp_div.c
+++ b/arch/mips/math-emu/dp_div.c
@@ -39,19 +39,20 @@ union ieee754dp ieee754dp_div(union ieee754dp x, union ieee754dp y)
39 FLUSHYDP; 39 FLUSHYDP;
40 40
41 switch (CLPAIR(xc, yc)) { 41 switch (CLPAIR(xc, yc)) {
42 case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_QNAN):
43 case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_SNAN): 42 case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_SNAN):
44 case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_SNAN):
45 case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_SNAN): 43 case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_SNAN):
46 case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_SNAN): 44 case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_SNAN):
47 case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_SNAN): 45 case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_SNAN):
48 case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_SNAN): 46 case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_SNAN):
47 return ieee754dp_nanxcpt(y);
48
49 case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_SNAN):
50 case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_QNAN):
49 case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_ZERO): 51 case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_ZERO):
50 case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_NORM): 52 case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_NORM):
51 case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_DNORM): 53 case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_DNORM):
52 case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_INF): 54 case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_INF):
53 ieee754_setcx(IEEE754_INVALID_OPERATION); 55 return ieee754dp_nanxcpt(x);
54 return ieee754dp_nanxcpt(ieee754dp_indef());
55 56
56 case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_QNAN): 57 case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_QNAN):
57 case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_QNAN): 58 case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_QNAN):
diff --git a/arch/mips/math-emu/dp_fsp.c b/arch/mips/math-emu/dp_fsp.c
index ffb69c5830b0..57d09ca5403a 100644
--- a/arch/mips/math-emu/dp_fsp.c
+++ b/arch/mips/math-emu/dp_fsp.c
@@ -22,6 +22,12 @@
22#include "ieee754sp.h" 22#include "ieee754sp.h"
23#include "ieee754dp.h" 23#include "ieee754dp.h"
24 24
25static inline union ieee754dp ieee754dp_nan_fsp(int xs, u64 xm)
26{
27 return builddp(xs, DP_EMAX + 1 + DP_EBIAS,
28 xm << (DP_FBITS - SP_FBITS));
29}
30
25union ieee754dp ieee754dp_fsp(union ieee754sp x) 31union ieee754dp ieee754dp_fsp(union ieee754sp x)
26{ 32{
27 COMPXSP; 33 COMPXSP;
@@ -34,15 +40,11 @@ union ieee754dp ieee754dp_fsp(union ieee754sp x)
34 40
35 switch (xc) { 41 switch (xc) {
36 case IEEE754_CLASS_SNAN: 42 case IEEE754_CLASS_SNAN:
37 ieee754_setcx(IEEE754_INVALID_OPERATION); 43 return ieee754dp_nanxcpt(ieee754dp_nan_fsp(xs, xm));
38 return ieee754dp_nanxcpt(ieee754dp_indef());
39 44
40 case IEEE754_CLASS_QNAN: 45 case IEEE754_CLASS_QNAN:
41 return ieee754dp_nanxcpt(builddp(xs, 46 return ieee754dp_nan_fsp(xs, xm);
42 DP_EMAX + 1 + DP_EBIAS, 47
43 ((u64) xm
44 << (DP_FBITS -
45 SP_FBITS))));
46 case IEEE754_CLASS_INF: 48 case IEEE754_CLASS_INF:
47 return ieee754dp_inf(xs); 49 return ieee754dp_inf(xs);
48 50
diff --git a/arch/mips/math-emu/dp_mul.c b/arch/mips/math-emu/dp_mul.c
index d3acdedb5b9d..d0901f03fa19 100644
--- a/arch/mips/math-emu/dp_mul.c
+++ b/arch/mips/math-emu/dp_mul.c
@@ -47,19 +47,20 @@ union ieee754dp ieee754dp_mul(union ieee754dp x, union ieee754dp y)
47 FLUSHYDP; 47 FLUSHYDP;
48 48
49 switch (CLPAIR(xc, yc)) { 49 switch (CLPAIR(xc, yc)) {
50 case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_QNAN):
51 case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_SNAN): 50 case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_SNAN):
52 case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_SNAN):
53 case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_SNAN): 51 case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_SNAN):
54 case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_SNAN): 52 case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_SNAN):
55 case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_SNAN): 53 case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_SNAN):
56 case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_SNAN): 54 case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_SNAN):
55 return ieee754dp_nanxcpt(y);
56
57 case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_SNAN):
58 case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_QNAN):
57 case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_ZERO): 59 case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_ZERO):
58 case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_NORM): 60 case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_NORM):
59 case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_DNORM): 61 case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_DNORM):
60 case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_INF): 62 case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_INF):
61 ieee754_setcx(IEEE754_INVALID_OPERATION); 63 return ieee754dp_nanxcpt(x);
62 return ieee754dp_nanxcpt(ieee754dp_indef());
63 64
64 case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_QNAN): 65 case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_QNAN):
65 case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_QNAN): 66 case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_QNAN):
diff --git a/arch/mips/math-emu/dp_simple.c b/arch/mips/math-emu/dp_simple.c
index bccbe90efceb..926d56bf37f2 100644
--- a/arch/mips/math-emu/dp_simple.c
+++ b/arch/mips/math-emu/dp_simple.c
@@ -23,44 +23,27 @@
23 23
24union ieee754dp ieee754dp_neg(union ieee754dp x) 24union ieee754dp ieee754dp_neg(union ieee754dp x)
25{ 25{
26 COMPXDP; 26 unsigned int oldrm;
27 27 union ieee754dp y;
28 EXPLODEXDP; 28
29 ieee754_clearcx(); 29 oldrm = ieee754_csr.rm;
30 FLUSHXDP; 30 ieee754_csr.rm = FPU_CSR_RD;
31 31 y = ieee754dp_sub(ieee754dp_zero(0), x);
32 /* 32 ieee754_csr.rm = oldrm;
33 * Invert the sign ALWAYS to prevent an endless recursion on 33 return y;
34 * pow() in libc.
35 */
36 /* quick fix up */
37 DPSIGN(x) ^= 1;
38
39 if (xc == IEEE754_CLASS_SNAN) {
40 union ieee754dp y = ieee754dp_indef();
41 ieee754_setcx(IEEE754_INVALID_OPERATION);
42 DPSIGN(y) = DPSIGN(x);
43 return ieee754dp_nanxcpt(y);
44 }
45
46 return x;
47} 34}
48 35
49union ieee754dp ieee754dp_abs(union ieee754dp x) 36union ieee754dp ieee754dp_abs(union ieee754dp x)
50{ 37{
51 COMPXDP; 38 unsigned int oldrm;
52 39 union ieee754dp y;
53 EXPLODEXDP; 40
54 ieee754_clearcx(); 41 oldrm = ieee754_csr.rm;
55 FLUSHXDP; 42 ieee754_csr.rm = FPU_CSR_RD;
56 43 if (DPSIGN(x))
57 /* Clear sign ALWAYS, irrespective of NaN */ 44 y = ieee754dp_sub(ieee754dp_zero(0), x);
58 DPSIGN(x) = 0; 45 else
59 46 y = ieee754dp_add(ieee754dp_zero(0), x);
60 if (xc == IEEE754_CLASS_SNAN) { 47 ieee754_csr.rm = oldrm;
61 ieee754_setcx(IEEE754_INVALID_OPERATION); 48 return y;
62 return ieee754dp_nanxcpt(ieee754dp_indef());
63 }
64
65 return x;
66} 49}
diff --git a/arch/mips/math-emu/dp_sqrt.c b/arch/mips/math-emu/dp_sqrt.c
index 041bbb6124bb..cd5bc083001e 100644
--- a/arch/mips/math-emu/dp_sqrt.c
+++ b/arch/mips/math-emu/dp_sqrt.c
@@ -42,13 +42,12 @@ union ieee754dp ieee754dp_sqrt(union ieee754dp x)
42 42
43 /* x == INF or NAN? */ 43 /* x == INF or NAN? */
44 switch (xc) { 44 switch (xc) {
45 case IEEE754_CLASS_QNAN: 45 case IEEE754_CLASS_SNAN:
46 /* sqrt(Nan) = Nan */
47 return ieee754dp_nanxcpt(x); 46 return ieee754dp_nanxcpt(x);
48 47
49 case IEEE754_CLASS_SNAN: 48 case IEEE754_CLASS_QNAN:
50 ieee754_setcx(IEEE754_INVALID_OPERATION); 49 /* sqrt(Nan) = Nan */
51 return ieee754dp_nanxcpt(ieee754dp_indef()); 50 return x;
52 51
53 case IEEE754_CLASS_ZERO: 52 case IEEE754_CLASS_ZERO:
54 /* sqrt(0) = 0 */ 53 /* sqrt(0) = 0 */
@@ -58,7 +57,7 @@ union ieee754dp ieee754dp_sqrt(union ieee754dp x)
58 if (xs) { 57 if (xs) {
59 /* sqrt(-Inf) = Nan */ 58 /* sqrt(-Inf) = Nan */
60 ieee754_setcx(IEEE754_INVALID_OPERATION); 59 ieee754_setcx(IEEE754_INVALID_OPERATION);
61 return ieee754dp_nanxcpt(ieee754dp_indef()); 60 return ieee754dp_indef();
62 } 61 }
63 /* sqrt(+Inf) = Inf */ 62 /* sqrt(+Inf) = Inf */
64 return x; 63 return x;
@@ -71,7 +70,7 @@ union ieee754dp ieee754dp_sqrt(union ieee754dp x)
71 if (xs) { 70 if (xs) {
72 /* sqrt(-x) = Nan */ 71 /* sqrt(-x) = Nan */
73 ieee754_setcx(IEEE754_INVALID_OPERATION); 72 ieee754_setcx(IEEE754_INVALID_OPERATION);
74 return ieee754dp_nanxcpt(ieee754dp_indef()); 73 return ieee754dp_indef();
75 } 74 }
76 break; 75 break;
77 } 76 }
diff --git a/arch/mips/math-emu/dp_sub.c b/arch/mips/math-emu/dp_sub.c
index 7a174029043a..fc17a781b9ae 100644
--- a/arch/mips/math-emu/dp_sub.c
+++ b/arch/mips/math-emu/dp_sub.c
@@ -37,19 +37,20 @@ union ieee754dp ieee754dp_sub(union ieee754dp x, union ieee754dp y)
37 FLUSHYDP; 37 FLUSHYDP;
38 38
39 switch (CLPAIR(xc, yc)) { 39 switch (CLPAIR(xc, yc)) {
40 case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_QNAN):
41 case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_SNAN): 40 case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_SNAN):
42 case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_SNAN):
43 case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_SNAN): 41 case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_SNAN):
44 case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_SNAN): 42 case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_SNAN):
45 case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_SNAN): 43 case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_SNAN):
46 case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_SNAN): 44 case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_SNAN):
45 return ieee754dp_nanxcpt(y);
46
47 case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_SNAN):
48 case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_QNAN):
47 case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_ZERO): 49 case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_ZERO):
48 case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_NORM): 50 case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_NORM):
49 case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_DNORM): 51 case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_DNORM):
50 case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_INF): 52 case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_INF):
51 ieee754_setcx(IEEE754_INVALID_OPERATION); 53 return ieee754dp_nanxcpt(x);
52 return ieee754dp_nanxcpt(ieee754dp_indef());
53 54
54 case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_QNAN): 55 case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_QNAN):
55 case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_QNAN): 56 case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_QNAN):
@@ -153,8 +154,6 @@ union ieee754dp ieee754dp_sub(union ieee754dp x, union ieee754dp y)
153 /* generate 28 bit result of adding two 27 bit numbers 154 /* generate 28 bit result of adding two 27 bit numbers
154 */ 155 */
155 xm = xm + ym; 156 xm = xm + ym;
156 xe = xe;
157 xs = xs;
158 157
159 if (xm >> (DP_FBITS + 1 + 3)) { /* carry out */ 158 if (xm >> (DP_FBITS + 1 + 3)) { /* carry out */
160 xm = XDPSRS1(xm); /* shift preserving sticky */ 159 xm = XDPSRS1(xm); /* shift preserving sticky */
@@ -163,11 +162,8 @@ union ieee754dp ieee754dp_sub(union ieee754dp x, union ieee754dp y)
163 } else { 162 } else {
164 if (xm >= ym) { 163 if (xm >= ym) {
165 xm = xm - ym; 164 xm = xm - ym;
166 xe = xe;
167 xs = xs;
168 } else { 165 } else {
169 xm = ym - xm; 166 xm = ym - xm;
170 xe = xe;
171 xs = ys; 167 xs = ys;
172 } 168 }
173 if (xm == 0) { 169 if (xm == 0) {
diff --git a/arch/mips/math-emu/dsemul.c b/arch/mips/math-emu/dsemul.c
index 4f514f3724cb..e0b5cc27d78b 100644
--- a/arch/mips/math-emu/dsemul.c
+++ b/arch/mips/math-emu/dsemul.c
@@ -94,9 +94,9 @@ int mips_dsemul(struct pt_regs *regs, mips_instruction ir, unsigned long cpc)
94 regs->cp0_epc = ((unsigned long) &fr->emul) | 94 regs->cp0_epc = ((unsigned long) &fr->emul) |
95 get_isa16_mode(regs->cp0_epc); 95 get_isa16_mode(regs->cp0_epc);
96 96
97 flush_cache_sigtramp((unsigned long)&fr->badinst); 97 flush_cache_sigtramp((unsigned long)&fr->emul);
98 98
99 return SIGILL; /* force out of emulation loop */ 99 return 0;
100} 100}
101 101
102int do_dsemulret(struct pt_regs *xcp) 102int do_dsemulret(struct pt_regs *xcp)
@@ -158,6 +158,6 @@ int do_dsemulret(struct pt_regs *xcp)
158 158
159 /* Set EPC to return to post-branch instruction */ 159 /* Set EPC to return to post-branch instruction */
160 xcp->cp0_epc = epc; 160 xcp->cp0_epc = epc;
161 161 MIPS_FPU_EMU_INC_STATS(ds_emul);
162 return 1; 162 return 1;
163} 163}
diff --git a/arch/mips/math-emu/ieee754.h b/arch/mips/math-emu/ieee754.h
index 43c4fb522ac2..a5ca108ce467 100644
--- a/arch/mips/math-emu/ieee754.h
+++ b/arch/mips/math-emu/ieee754.h
@@ -126,84 +126,21 @@ enum {
126#define IEEE754_CGT 0x04 126#define IEEE754_CGT 0x04
127#define IEEE754_CUN 0x08 127#define IEEE754_CUN 0x08
128 128
129/* "normal" comparisons
130*/
131static inline int ieee754sp_eq(union ieee754sp x, union ieee754sp y)
132{
133 return ieee754sp_cmp(x, y, IEEE754_CEQ, 0);
134}
135
136static inline int ieee754sp_ne(union ieee754sp x, union ieee754sp y)
137{
138 return ieee754sp_cmp(x, y,
139 IEEE754_CLT | IEEE754_CGT | IEEE754_CUN, 0);
140}
141
142static inline int ieee754sp_lt(union ieee754sp x, union ieee754sp y)
143{
144 return ieee754sp_cmp(x, y, IEEE754_CLT, 0);
145}
146
147static inline int ieee754sp_le(union ieee754sp x, union ieee754sp y)
148{
149 return ieee754sp_cmp(x, y, IEEE754_CLT | IEEE754_CEQ, 0);
150}
151
152static inline int ieee754sp_gt(union ieee754sp x, union ieee754sp y)
153{
154 return ieee754sp_cmp(x, y, IEEE754_CGT, 0);
155}
156
157
158static inline int ieee754sp_ge(union ieee754sp x, union ieee754sp y)
159{
160 return ieee754sp_cmp(x, y, IEEE754_CGT | IEEE754_CEQ, 0);
161}
162
163static inline int ieee754dp_eq(union ieee754dp x, union ieee754dp y)
164{
165 return ieee754dp_cmp(x, y, IEEE754_CEQ, 0);
166}
167
168static inline int ieee754dp_ne(union ieee754dp x, union ieee754dp y)
169{
170 return ieee754dp_cmp(x, y,
171 IEEE754_CLT | IEEE754_CGT | IEEE754_CUN, 0);
172}
173
174static inline int ieee754dp_lt(union ieee754dp x, union ieee754dp y)
175{
176 return ieee754dp_cmp(x, y, IEEE754_CLT, 0);
177}
178
179static inline int ieee754dp_le(union ieee754dp x, union ieee754dp y)
180{
181 return ieee754dp_cmp(x, y, IEEE754_CLT | IEEE754_CEQ, 0);
182}
183
184static inline int ieee754dp_gt(union ieee754dp x, union ieee754dp y)
185{
186 return ieee754dp_cmp(x, y, IEEE754_CGT, 0);
187}
188
189static inline int ieee754dp_ge(union ieee754dp x, union ieee754dp y)
190{
191 return ieee754dp_cmp(x, y, IEEE754_CGT | IEEE754_CEQ, 0);
192}
193
194/* 129/*
195 * The control status register 130 * The control status register
196 */ 131 */
197struct _ieee754_csr { 132struct _ieee754_csr {
198 __BITFIELD_FIELD(unsigned pad0:7, 133 __BITFIELD_FIELD(unsigned fcc:7, /* condition[7:1] */
199 __BITFIELD_FIELD(unsigned nod:1, /* set 1 for no denormalised numbers */ 134 __BITFIELD_FIELD(unsigned nod:1, /* set 1 for no denormals */
200 __BITFIELD_FIELD(unsigned c:1, /* condition */ 135 __BITFIELD_FIELD(unsigned c:1, /* condition[0] */
201 __BITFIELD_FIELD(unsigned pad1:5, 136 __BITFIELD_FIELD(unsigned pad0:3,
137 __BITFIELD_FIELD(unsigned abs2008:1, /* IEEE 754-2008 ABS/NEG.fmt */
138 __BITFIELD_FIELD(unsigned nan2008:1, /* IEEE 754-2008 NaN mode */
202 __BITFIELD_FIELD(unsigned cx:6, /* exceptions this operation */ 139 __BITFIELD_FIELD(unsigned cx:6, /* exceptions this operation */
203 __BITFIELD_FIELD(unsigned mx:5, /* exception enable mask */ 140 __BITFIELD_FIELD(unsigned mx:5, /* exception enable mask */
204 __BITFIELD_FIELD(unsigned sx:5, /* exceptions total */ 141 __BITFIELD_FIELD(unsigned sx:5, /* exceptions total */
205 __BITFIELD_FIELD(unsigned rm:2, /* current rounding mode */ 142 __BITFIELD_FIELD(unsigned rm:2, /* current rounding mode */
206 ;)))))))) 143 ;))))))))))
207}; 144};
208#define ieee754_csr (*(struct _ieee754_csr *)(&current->thread.fpu.fcr31)) 145#define ieee754_csr (*(struct _ieee754_csr *)(&current->thread.fpu.fcr31))
209 146
@@ -257,23 +194,23 @@ static inline int ieee754_sxtest(unsigned n)
257union ieee754sp ieee754sp_dump(char *s, union ieee754sp x); 194union ieee754sp ieee754sp_dump(char *s, union ieee754sp x);
258union ieee754dp ieee754dp_dump(char *s, union ieee754dp x); 195union ieee754dp ieee754dp_dump(char *s, union ieee754dp x);
259 196
260#define IEEE754_SPCVAL_PZERO 0 197#define IEEE754_SPCVAL_PZERO 0 /* +0.0 */
261#define IEEE754_SPCVAL_NZERO 1 198#define IEEE754_SPCVAL_NZERO 1 /* -0.0 */
262#define IEEE754_SPCVAL_PONE 2 199#define IEEE754_SPCVAL_PONE 2 /* +1.0 */
263#define IEEE754_SPCVAL_NONE 3 200#define IEEE754_SPCVAL_NONE 3 /* -1.0 */
264#define IEEE754_SPCVAL_PTEN 4 201#define IEEE754_SPCVAL_PTEN 4 /* +10.0 */
265#define IEEE754_SPCVAL_NTEN 5 202#define IEEE754_SPCVAL_NTEN 5 /* -10.0 */
266#define IEEE754_SPCVAL_PINFINITY 6 203#define IEEE754_SPCVAL_PINFINITY 6 /* +inf */
267#define IEEE754_SPCVAL_NINFINITY 7 204#define IEEE754_SPCVAL_NINFINITY 7 /* -inf */
268#define IEEE754_SPCVAL_INDEF 8 205#define IEEE754_SPCVAL_INDEF 8 /* quiet NaN */
269#define IEEE754_SPCVAL_PMAX 9 /* +max norm */ 206#define IEEE754_SPCVAL_PMAX 9 /* +max norm */
270#define IEEE754_SPCVAL_NMAX 10 /* -max norm */ 207#define IEEE754_SPCVAL_NMAX 10 /* -max norm */
271#define IEEE754_SPCVAL_PMIN 11 /* +min norm */ 208#define IEEE754_SPCVAL_PMIN 11 /* +min norm */
272#define IEEE754_SPCVAL_NMIN 12 /* +min norm */ 209#define IEEE754_SPCVAL_NMIN 12 /* -min norm */
273#define IEEE754_SPCVAL_PMIND 13 /* +min denorm */ 210#define IEEE754_SPCVAL_PMIND 13 /* +min denorm */
274#define IEEE754_SPCVAL_NMIND 14 /* +min denorm */ 211#define IEEE754_SPCVAL_NMIND 14 /* -min denorm */
275#define IEEE754_SPCVAL_P1E31 15 /* + 1.0e31 */ 212#define IEEE754_SPCVAL_P1E31 15 /* + 1.0e31 */
276#define IEEE754_SPCVAL_P1E63 16 /* + 1.0e63 */ 213#define IEEE754_SPCVAL_P1E63 16 /* + 1.0e63 */
277 214
278extern const union ieee754dp __ieee754dp_spcvals[]; 215extern const union ieee754dp __ieee754dp_spcvals[];
279extern const union ieee754sp __ieee754sp_spcvals[]; 216extern const union ieee754sp __ieee754sp_spcvals[];
diff --git a/arch/mips/math-emu/ieee754dp.c b/arch/mips/math-emu/ieee754dp.c
index 068f45a415fc..522d843f2ffd 100644
--- a/arch/mips/math-emu/ieee754dp.c
+++ b/arch/mips/math-emu/ieee754dp.c
@@ -30,9 +30,9 @@ int ieee754dp_class(union ieee754dp x)
30 return xc; 30 return xc;
31} 31}
32 32
33int ieee754dp_isnan(union ieee754dp x) 33static inline int ieee754dp_isnan(union ieee754dp x)
34{ 34{
35 return ieee754dp_class(x) >= IEEE754_CLASS_SNAN; 35 return ieee754_class_nan(ieee754dp_class(x));
36} 36}
37 37
38static inline int ieee754dp_issnan(union ieee754dp x) 38static inline int ieee754dp_issnan(union ieee754dp x)
@@ -42,23 +42,16 @@ static inline int ieee754dp_issnan(union ieee754dp x)
42} 42}
43 43
44 44
45/*
46 * Raise the Invalid Operation IEEE 754 exception
47 * and convert the signaling NaN supplied to a quiet NaN.
48 */
45union ieee754dp __cold ieee754dp_nanxcpt(union ieee754dp r) 49union ieee754dp __cold ieee754dp_nanxcpt(union ieee754dp r)
46{ 50{
47 assert(ieee754dp_isnan(r)); 51 assert(ieee754dp_issnan(r));
48
49 if (!ieee754dp_issnan(r)) /* QNAN does not cause invalid op !! */
50 return r;
51
52 if (!ieee754_setandtestcx(IEEE754_INVALID_OPERATION)) {
53 /* not enabled convert to a quiet NaN */
54 DPMANT(r) &= (~DP_MBIT(DP_FBITS-1));
55 if (ieee754dp_isnan(r))
56 return r;
57 else
58 return ieee754dp_indef();
59 }
60 52
61 return r; 53 ieee754_setcx(IEEE754_INVALID_OPERATION);
54 return ieee754dp_indef();
62} 55}
63 56
64static u64 ieee754dp_get_rounding(int sn, u64 xm) 57static u64 ieee754dp_get_rounding(int sn, u64 xm)
diff --git a/arch/mips/math-emu/ieee754dp.h b/arch/mips/math-emu/ieee754dp.h
index 61fd6fd31350..e2babd98fee3 100644
--- a/arch/mips/math-emu/ieee754dp.h
+++ b/arch/mips/math-emu/ieee754dp.h
@@ -77,6 +77,5 @@ static inline union ieee754dp builddp(int s, int bx, u64 m)
77 return r; 77 return r;
78} 78}
79 79
80extern int ieee754dp_isnan(union ieee754dp);
81extern union ieee754dp __cold ieee754dp_nanxcpt(union ieee754dp); 80extern union ieee754dp __cold ieee754dp_nanxcpt(union ieee754dp);
82extern union ieee754dp ieee754dp_format(int, int, u64); 81extern union ieee754dp ieee754dp_format(int, int, u64);
diff --git a/arch/mips/math-emu/ieee754int.h b/arch/mips/math-emu/ieee754int.h
index f0365bb86747..05389d5e3a93 100644
--- a/arch/mips/math-emu/ieee754int.h
+++ b/arch/mips/math-emu/ieee754int.h
@@ -44,6 +44,11 @@ static inline int ieee754_setandtestcx(const unsigned int x)
44 return ieee754_csr.mx & x; 44 return ieee754_csr.mx & x;
45} 45}
46 46
47static inline int ieee754_class_nan(int xc)
48{
49 return xc >= IEEE754_CLASS_SNAN;
50}
51
47#define COMPXSP \ 52#define COMPXSP \
48 unsigned xm; int xe; int xs __maybe_unused; int xc 53 unsigned xm; int xe; int xs __maybe_unused; int xc
49 54
diff --git a/arch/mips/math-emu/ieee754sp.c b/arch/mips/math-emu/ieee754sp.c
index ba88301579c2..ca8e35e33bf7 100644
--- a/arch/mips/math-emu/ieee754sp.c
+++ b/arch/mips/math-emu/ieee754sp.c
@@ -30,9 +30,9 @@ int ieee754sp_class(union ieee754sp x)
30 return xc; 30 return xc;
31} 31}
32 32
33int ieee754sp_isnan(union ieee754sp x) 33static inline int ieee754sp_isnan(union ieee754sp x)
34{ 34{
35 return ieee754sp_class(x) >= IEEE754_CLASS_SNAN; 35 return ieee754_class_nan(ieee754sp_class(x));
36} 36}
37 37
38static inline int ieee754sp_issnan(union ieee754sp x) 38static inline int ieee754sp_issnan(union ieee754sp x)
@@ -42,23 +42,16 @@ static inline int ieee754sp_issnan(union ieee754sp x)
42} 42}
43 43
44 44
45/*
46 * Raise the Invalid Operation IEEE 754 exception
47 * and convert the signaling NaN supplied to a quiet NaN.
48 */
45union ieee754sp __cold ieee754sp_nanxcpt(union ieee754sp r) 49union ieee754sp __cold ieee754sp_nanxcpt(union ieee754sp r)
46{ 50{
47 assert(ieee754sp_isnan(r)); 51 assert(ieee754sp_issnan(r));
48
49 if (!ieee754sp_issnan(r)) /* QNAN does not cause invalid op !! */
50 return r;
51
52 if (!ieee754_setandtestcx(IEEE754_INVALID_OPERATION)) {
53 /* not enabled convert to a quiet NaN */
54 SPMANT(r) &= (~SP_MBIT(SP_FBITS-1));
55 if (ieee754sp_isnan(r))
56 return r;
57 else
58 return ieee754sp_indef();
59 }
60 52
61 return r; 53 ieee754_setcx(IEEE754_INVALID_OPERATION);
54 return ieee754sp_indef();
62} 55}
63 56
64static unsigned ieee754sp_get_rounding(int sn, unsigned xm) 57static unsigned ieee754sp_get_rounding(int sn, unsigned xm)
diff --git a/arch/mips/math-emu/ieee754sp.h b/arch/mips/math-emu/ieee754sp.h
index ad268e332318..374a3f00a589 100644
--- a/arch/mips/math-emu/ieee754sp.h
+++ b/arch/mips/math-emu/ieee754sp.h
@@ -82,6 +82,5 @@ static inline union ieee754sp buildsp(int s, int bx, unsigned m)
82 return r; 82 return r;
83} 83}
84 84
85extern int ieee754sp_isnan(union ieee754sp);
86extern union ieee754sp __cold ieee754sp_nanxcpt(union ieee754sp); 85extern union ieee754sp __cold ieee754sp_nanxcpt(union ieee754sp);
87extern union ieee754sp ieee754sp_format(int, int, unsigned); 86extern union ieee754sp ieee754sp_format(int, int, unsigned);
diff --git a/arch/mips/math-emu/me-debugfs.c b/arch/mips/math-emu/me-debugfs.c
index becdd63e14a9..f308e0f05fc5 100644
--- a/arch/mips/math-emu/me-debugfs.c
+++ b/arch/mips/math-emu/me-debugfs.c
@@ -61,6 +61,7 @@ do { \
61 FPU_STAT_CREATE(ieee754_overflow); 61 FPU_STAT_CREATE(ieee754_overflow);
62 FPU_STAT_CREATE(ieee754_zerodiv); 62 FPU_STAT_CREATE(ieee754_zerodiv);
63 FPU_STAT_CREATE(ieee754_invalidop); 63 FPU_STAT_CREATE(ieee754_invalidop);
64 FPU_STAT_CREATE(ds_emul);
64 65
65 return 0; 66 return 0;
66} 67}
diff --git a/arch/mips/math-emu/sp_add.c b/arch/mips/math-emu/sp_add.c
index 2d84d460cb67..f1c87b07d3b4 100644
--- a/arch/mips/math-emu/sp_add.c
+++ b/arch/mips/math-emu/sp_add.c
@@ -37,19 +37,20 @@ union ieee754sp ieee754sp_add(union ieee754sp x, union ieee754sp y)
37 FLUSHYSP; 37 FLUSHYSP;
38 38
39 switch (CLPAIR(xc, yc)) { 39 switch (CLPAIR(xc, yc)) {
40 case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_QNAN):
41 case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_SNAN): 40 case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_SNAN):
42 case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_SNAN):
43 case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_SNAN): 41 case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_SNAN):
44 case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_SNAN): 42 case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_SNAN):
45 case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_SNAN): 43 case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_SNAN):
46 case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_SNAN): 44 case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_SNAN):
45 return ieee754sp_nanxcpt(y);
46
47 case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_SNAN):
48 case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_QNAN):
47 case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_ZERO): 49 case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_ZERO):
48 case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_NORM): 50 case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_NORM):
49 case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_DNORM): 51 case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_DNORM):
50 case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_INF): 52 case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_INF):
51 ieee754_setcx(IEEE754_INVALID_OPERATION); 53 return ieee754sp_nanxcpt(x);
52 return ieee754sp_nanxcpt(ieee754sp_indef());
53 54
54 case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_QNAN): 55 case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_QNAN):
55 case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_QNAN): 56 case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_QNAN):
@@ -148,8 +149,6 @@ union ieee754sp ieee754sp_add(union ieee754sp x, union ieee754sp y)
148 * leaving result in xm, xs and xe. 149 * leaving result in xm, xs and xe.
149 */ 150 */
150 xm = xm + ym; 151 xm = xm + ym;
151 xe = xe;
152 xs = xs;
153 152
154 if (xm >> (SP_FBITS + 1 + 3)) { /* carry out */ 153 if (xm >> (SP_FBITS + 1 + 3)) { /* carry out */
155 SPXSRSX1(); 154 SPXSRSX1();
@@ -157,11 +156,8 @@ union ieee754sp ieee754sp_add(union ieee754sp x, union ieee754sp y)
157 } else { 156 } else {
158 if (xm >= ym) { 157 if (xm >= ym) {
159 xm = xm - ym; 158 xm = xm - ym;
160 xe = xe;
161 xs = xs;
162 } else { 159 } else {
163 xm = ym - xm; 160 xm = ym - xm;
164 xe = xe;
165 xs = ys; 161 xs = ys;
166 } 162 }
167 if (xm == 0) 163 if (xm == 0)
diff --git a/arch/mips/math-emu/sp_cmp.c b/arch/mips/math-emu/sp_cmp.c
index addbccb2f556..67b82f1e2c4a 100644
--- a/arch/mips/math-emu/sp_cmp.c
+++ b/arch/mips/math-emu/sp_cmp.c
@@ -35,16 +35,11 @@ int ieee754sp_cmp(union ieee754sp x, union ieee754sp y, int cmp, int sig)
35 FLUSHYSP; 35 FLUSHYSP;
36 ieee754_clearcx(); /* Even clear inexact flag here */ 36 ieee754_clearcx(); /* Even clear inexact flag here */
37 37
38 if (ieee754sp_isnan(x) || ieee754sp_isnan(y)) { 38 if (ieee754_class_nan(xc) || ieee754_class_nan(yc)) {
39 if (sig || xc == IEEE754_CLASS_SNAN || yc == IEEE754_CLASS_SNAN) 39 if (sig ||
40 xc == IEEE754_CLASS_SNAN || yc == IEEE754_CLASS_SNAN)
40 ieee754_setcx(IEEE754_INVALID_OPERATION); 41 ieee754_setcx(IEEE754_INVALID_OPERATION);
41 if (cmp & IEEE754_CUN) 42 return (cmp & IEEE754_CUN) != 0;
42 return 1;
43 if (cmp & (IEEE754_CLT | IEEE754_CGT)) {
44 if (sig && ieee754_setandtestcx(IEEE754_INVALID_OPERATION))
45 return 0;
46 }
47 return 0;
48 } else { 43 } else {
49 vx = x.bits; 44 vx = x.bits;
50 vy = y.bits; 45 vy = y.bits;
diff --git a/arch/mips/math-emu/sp_div.c b/arch/mips/math-emu/sp_div.c
index 721f317aa877..27f6db3a0a4c 100644
--- a/arch/mips/math-emu/sp_div.c
+++ b/arch/mips/math-emu/sp_div.c
@@ -39,19 +39,20 @@ union ieee754sp ieee754sp_div(union ieee754sp x, union ieee754sp y)
39 FLUSHYSP; 39 FLUSHYSP;
40 40
41 switch (CLPAIR(xc, yc)) { 41 switch (CLPAIR(xc, yc)) {
42 case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_QNAN):
43 case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_SNAN): 42 case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_SNAN):
44 case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_SNAN):
45 case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_SNAN): 43 case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_SNAN):
46 case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_SNAN): 44 case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_SNAN):
47 case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_SNAN): 45 case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_SNAN):
48 case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_SNAN): 46 case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_SNAN):
47 return ieee754sp_nanxcpt(y);
48
49 case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_SNAN):
50 case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_QNAN):
49 case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_ZERO): 51 case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_ZERO):
50 case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_NORM): 52 case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_NORM):
51 case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_DNORM): 53 case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_DNORM):
52 case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_INF): 54 case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_INF):
53 ieee754_setcx(IEEE754_INVALID_OPERATION); 55 return ieee754sp_nanxcpt(x);
54 return ieee754sp_nanxcpt(ieee754sp_indef());
55 56
56 case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_QNAN): 57 case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_QNAN):
57 case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_QNAN): 58 case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_QNAN):
diff --git a/arch/mips/math-emu/sp_fdp.c b/arch/mips/math-emu/sp_fdp.c
index 1b266fb16973..3797148893ad 100644
--- a/arch/mips/math-emu/sp_fdp.c
+++ b/arch/mips/math-emu/sp_fdp.c
@@ -22,12 +22,19 @@
22#include "ieee754sp.h" 22#include "ieee754sp.h"
23#include "ieee754dp.h" 23#include "ieee754dp.h"
24 24
25static inline union ieee754sp ieee754sp_nan_fdp(int xs, u64 xm)
26{
27 return buildsp(xs, SP_EMAX + 1 + SP_EBIAS,
28 xm >> (DP_FBITS - SP_FBITS));
29}
30
25union ieee754sp ieee754sp_fdp(union ieee754dp x) 31union ieee754sp ieee754sp_fdp(union ieee754dp x)
26{ 32{
33 union ieee754sp y;
27 u32 rm; 34 u32 rm;
28 35
29 COMPXDP; 36 COMPXDP;
30 union ieee754sp nan; 37 COMPYSP;
31 38
32 EXPLODEXDP; 39 EXPLODEXDP;
33 40
@@ -37,15 +44,14 @@ union ieee754sp ieee754sp_fdp(union ieee754dp x)
37 44
38 switch (xc) { 45 switch (xc) {
39 case IEEE754_CLASS_SNAN: 46 case IEEE754_CLASS_SNAN:
40 ieee754_setcx(IEEE754_INVALID_OPERATION); 47 return ieee754sp_nanxcpt(ieee754sp_nan_fdp(xs, xm));
41 return ieee754sp_nanxcpt(ieee754sp_indef());
42 48
43 case IEEE754_CLASS_QNAN: 49 case IEEE754_CLASS_QNAN:
44 nan = buildsp(xs, SP_EMAX + 1 + SP_EBIAS, (u32) 50 y = ieee754sp_nan_fdp(xs, xm);
45 (xm >> (DP_FBITS - SP_FBITS))); 51 EXPLODEYSP;
46 if (!ieee754sp_isnan(nan)) 52 if (!ieee754_class_nan(yc))
47 nan = ieee754sp_indef(); 53 y = ieee754sp_indef();
48 return ieee754sp_nanxcpt(nan); 54 return y;
49 55
50 case IEEE754_CLASS_INF: 56 case IEEE754_CLASS_INF:
51 return ieee754sp_inf(xs); 57 return ieee754sp_inf(xs);
diff --git a/arch/mips/math-emu/sp_mul.c b/arch/mips/math-emu/sp_mul.c
index 890c13a2965e..d910c43a6f30 100644
--- a/arch/mips/math-emu/sp_mul.c
+++ b/arch/mips/math-emu/sp_mul.c
@@ -47,19 +47,20 @@ union ieee754sp ieee754sp_mul(union ieee754sp x, union ieee754sp y)
47 FLUSHYSP; 47 FLUSHYSP;
48 48
49 switch (CLPAIR(xc, yc)) { 49 switch (CLPAIR(xc, yc)) {
50 case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_QNAN):
51 case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_SNAN): 50 case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_SNAN):
52 case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_SNAN):
53 case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_SNAN): 51 case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_SNAN):
54 case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_SNAN): 52 case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_SNAN):
55 case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_SNAN): 53 case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_SNAN):
56 case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_SNAN): 54 case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_SNAN):
55 return ieee754sp_nanxcpt(y);
56
57 case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_SNAN):
58 case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_QNAN):
57 case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_ZERO): 59 case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_ZERO):
58 case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_NORM): 60 case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_NORM):
59 case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_DNORM): 61 case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_DNORM):
60 case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_INF): 62 case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_INF):
61 ieee754_setcx(IEEE754_INVALID_OPERATION); 63 return ieee754sp_nanxcpt(x);
62 return ieee754sp_nanxcpt(ieee754sp_indef());
63 64
64 case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_QNAN): 65 case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_QNAN):
65 case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_QNAN): 66 case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_QNAN):
diff --git a/arch/mips/math-emu/sp_simple.c b/arch/mips/math-emu/sp_simple.c
index f1ffaa9a17e0..c50e9451f2d2 100644
--- a/arch/mips/math-emu/sp_simple.c
+++ b/arch/mips/math-emu/sp_simple.c
@@ -23,44 +23,27 @@
23 23
24union ieee754sp ieee754sp_neg(union ieee754sp x) 24union ieee754sp ieee754sp_neg(union ieee754sp x)
25{ 25{
26 COMPXSP; 26 unsigned int oldrm;
27 27 union ieee754sp y;
28 EXPLODEXSP; 28
29 ieee754_clearcx(); 29 oldrm = ieee754_csr.rm;
30 FLUSHXSP; 30 ieee754_csr.rm = FPU_CSR_RD;
31 31 y = ieee754sp_sub(ieee754sp_zero(0), x);
32 /* 32 ieee754_csr.rm = oldrm;
33 * Invert the sign ALWAYS to prevent an endless recursion on 33 return y;
34 * pow() in libc.
35 */
36 /* quick fix up */
37 SPSIGN(x) ^= 1;
38
39 if (xc == IEEE754_CLASS_SNAN) {
40 union ieee754sp y = ieee754sp_indef();
41 ieee754_setcx(IEEE754_INVALID_OPERATION);
42 SPSIGN(y) = SPSIGN(x);
43 return ieee754sp_nanxcpt(y);
44 }
45
46 return x;
47} 34}
48 35
49union ieee754sp ieee754sp_abs(union ieee754sp x) 36union ieee754sp ieee754sp_abs(union ieee754sp x)
50{ 37{
51 COMPXSP; 38 unsigned int oldrm;
52 39 union ieee754sp y;
53 EXPLODEXSP; 40
54 ieee754_clearcx(); 41 oldrm = ieee754_csr.rm;
55 FLUSHXSP; 42 ieee754_csr.rm = FPU_CSR_RD;
56 43 if (SPSIGN(x))
57 /* Clear sign ALWAYS, irrespective of NaN */ 44 y = ieee754sp_sub(ieee754sp_zero(0), x);
58 SPSIGN(x) = 0; 45 else
59 46 y = ieee754sp_add(ieee754sp_zero(0), x);
60 if (xc == IEEE754_CLASS_SNAN) { 47 ieee754_csr.rm = oldrm;
61 ieee754_setcx(IEEE754_INVALID_OPERATION); 48 return y;
62 return ieee754sp_nanxcpt(ieee754sp_indef());
63 }
64
65 return x;
66} 49}
diff --git a/arch/mips/math-emu/sp_sqrt.c b/arch/mips/math-emu/sp_sqrt.c
index b7c098a86f95..67059c33a250 100644
--- a/arch/mips/math-emu/sp_sqrt.c
+++ b/arch/mips/math-emu/sp_sqrt.c
@@ -35,13 +35,12 @@ union ieee754sp ieee754sp_sqrt(union ieee754sp x)
35 35
36 /* x == INF or NAN? */ 36 /* x == INF or NAN? */
37 switch (xc) { 37 switch (xc) {
38 case IEEE754_CLASS_QNAN: 38 case IEEE754_CLASS_SNAN:
39 /* sqrt(Nan) = Nan */
40 return ieee754sp_nanxcpt(x); 39 return ieee754sp_nanxcpt(x);
41 40
42 case IEEE754_CLASS_SNAN: 41 case IEEE754_CLASS_QNAN:
43 ieee754_setcx(IEEE754_INVALID_OPERATION); 42 /* sqrt(Nan) = Nan */
44 return ieee754sp_nanxcpt(ieee754sp_indef()); 43 return x;
45 44
46 case IEEE754_CLASS_ZERO: 45 case IEEE754_CLASS_ZERO:
47 /* sqrt(0) = 0 */ 46 /* sqrt(0) = 0 */
@@ -51,7 +50,7 @@ union ieee754sp ieee754sp_sqrt(union ieee754sp x)
51 if (xs) { 50 if (xs) {
52 /* sqrt(-Inf) = Nan */ 51 /* sqrt(-Inf) = Nan */
53 ieee754_setcx(IEEE754_INVALID_OPERATION); 52 ieee754_setcx(IEEE754_INVALID_OPERATION);
54 return ieee754sp_nanxcpt(ieee754sp_indef()); 53 return ieee754sp_indef();
55 } 54 }
56 /* sqrt(+Inf) = Inf */ 55 /* sqrt(+Inf) = Inf */
57 return x; 56 return x;
@@ -61,7 +60,7 @@ union ieee754sp ieee754sp_sqrt(union ieee754sp x)
61 if (xs) { 60 if (xs) {
62 /* sqrt(-x) = Nan */ 61 /* sqrt(-x) = Nan */
63 ieee754_setcx(IEEE754_INVALID_OPERATION); 62 ieee754_setcx(IEEE754_INVALID_OPERATION);
64 return ieee754sp_nanxcpt(ieee754sp_indef()); 63 return ieee754sp_indef();
65 } 64 }
66 break; 65 break;
67 } 66 }
diff --git a/arch/mips/math-emu/sp_sub.c b/arch/mips/math-emu/sp_sub.c
index 8592e49032b8..ec5f937a8b3e 100644
--- a/arch/mips/math-emu/sp_sub.c
+++ b/arch/mips/math-emu/sp_sub.c
@@ -37,19 +37,20 @@ union ieee754sp ieee754sp_sub(union ieee754sp x, union ieee754sp y)
37 FLUSHYSP; 37 FLUSHYSP;
38 38
39 switch (CLPAIR(xc, yc)) { 39 switch (CLPAIR(xc, yc)) {
40 case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_QNAN):
41 case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_SNAN): 40 case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_SNAN):
42 case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_SNAN):
43 case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_SNAN): 41 case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_SNAN):
44 case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_SNAN): 42 case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_SNAN):
45 case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_SNAN): 43 case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_SNAN):
46 case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_SNAN): 44 case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_SNAN):
45 return ieee754sp_nanxcpt(y);
46
47 case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_SNAN):
48 case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_QNAN):
47 case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_ZERO): 49 case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_ZERO):
48 case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_NORM): 50 case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_NORM):
49 case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_DNORM): 51 case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_DNORM):
50 case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_INF): 52 case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_INF):
51 ieee754_setcx(IEEE754_INVALID_OPERATION); 53 return ieee754sp_nanxcpt(x);
52 return ieee754sp_nanxcpt(ieee754sp_indef());
53 54
54 case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_QNAN): 55 case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_QNAN):
55 case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_QNAN): 56 case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_QNAN):
@@ -148,8 +149,6 @@ union ieee754sp ieee754sp_sub(union ieee754sp x, union ieee754sp y)
148 /* generate 28 bit result of adding two 27 bit numbers 149 /* generate 28 bit result of adding two 27 bit numbers
149 */ 150 */
150 xm = xm + ym; 151 xm = xm + ym;
151 xe = xe;
152 xs = xs;
153 152
154 if (xm >> (SP_FBITS + 1 + 3)) { /* carry out */ 153 if (xm >> (SP_FBITS + 1 + 3)) { /* carry out */
155 SPXSRSX1(); /* shift preserving sticky */ 154 SPXSRSX1(); /* shift preserving sticky */
@@ -157,11 +156,8 @@ union ieee754sp ieee754sp_sub(union ieee754sp x, union ieee754sp y)
157 } else { 156 } else {
158 if (xm >= ym) { 157 if (xm >= ym) {
159 xm = xm - ym; 158 xm = xm - ym;
160 xe = xe;
161 xs = xs;
162 } else { 159 } else {
163 xm = ym - xm; 160 xm = ym - xm;
164 xe = xe;
165 xs = ys; 161 xs = ys;
166 } 162 }
167 if (xm == 0) { 163 if (xm == 0) {
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index 3f8059602765..0dbb65a51ce5 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -430,6 +430,7 @@ static inline void local_r4k___flush_cache_all(void * args)
430 case CPU_R10000: 430 case CPU_R10000:
431 case CPU_R12000: 431 case CPU_R12000:
432 case CPU_R14000: 432 case CPU_R14000:
433 case CPU_R16000:
433 /* 434 /*
434 * These caches are inclusive caches, that is, if something 435 * These caches are inclusive caches, that is, if something
435 * is not cached in the S-cache, we know it also won't be 436 * is not cached in the S-cache, we know it also won't be
@@ -506,7 +507,7 @@ static inline void local_r4k_flush_cache_mm(void * args)
506 507
507 /* 508 /*
508 * Kludge alert. For obscure reasons R4000SC and R4400SC go nuts if we 509 * Kludge alert. For obscure reasons R4000SC and R4400SC go nuts if we
509 * only flush the primary caches but R10000 and R12000 behave sane ... 510 * only flush the primary caches but R1x000 behave sane ...
510 * R4000SC and R4400SC indexed S-cache ops also invalidate primary 511 * R4000SC and R4400SC indexed S-cache ops also invalidate primary
511 * caches, so we can bail out early. 512 * caches, so we can bail out early.
512 */ 513 */
@@ -888,33 +889,39 @@ static inline void rm7k_erratum31(void)
888 } 889 }
889} 890}
890 891
891static inline void alias_74k_erratum(struct cpuinfo_mips *c) 892static inline int alias_74k_erratum(struct cpuinfo_mips *c)
892{ 893{
893 unsigned int imp = c->processor_id & PRID_IMP_MASK; 894 unsigned int imp = c->processor_id & PRID_IMP_MASK;
894 unsigned int rev = c->processor_id & PRID_REV_MASK; 895 unsigned int rev = c->processor_id & PRID_REV_MASK;
896 int present = 0;
895 897
896 /* 898 /*
897 * Early versions of the 74K do not update the cache tags on a 899 * Early versions of the 74K do not update the cache tags on a
898 * vtag miss/ptag hit which can occur in the case of KSEG0/KUSEG 900 * vtag miss/ptag hit which can occur in the case of KSEG0/KUSEG
899 * aliases. In this case it is better to treat the cache as always 901 * aliases. In this case it is better to treat the cache as always
900 * having aliases. 902 * having aliases. Also disable the synonym tag update feature
903 * where available. In this case no opportunistic tag update will
904 * happen where a load causes a virtual address miss but a physical
905 * address hit during a D-cache look-up.
901 */ 906 */
902 switch (imp) { 907 switch (imp) {
903 case PRID_IMP_74K: 908 case PRID_IMP_74K:
904 if (rev <= PRID_REV_ENCODE_332(2, 4, 0)) 909 if (rev <= PRID_REV_ENCODE_332(2, 4, 0))
905 c->dcache.flags |= MIPS_CACHE_VTAG; 910 present = 1;
906 if (rev == PRID_REV_ENCODE_332(2, 4, 0)) 911 if (rev == PRID_REV_ENCODE_332(2, 4, 0))
907 write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND); 912 write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND);
908 break; 913 break;
909 case PRID_IMP_1074K: 914 case PRID_IMP_1074K:
910 if (rev <= PRID_REV_ENCODE_332(1, 1, 0)) { 915 if (rev <= PRID_REV_ENCODE_332(1, 1, 0)) {
911 c->dcache.flags |= MIPS_CACHE_VTAG; 916 present = 1;
912 write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND); 917 write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND);
913 } 918 }
914 break; 919 break;
915 default: 920 default:
916 BUG(); 921 BUG();
917 } 922 }
923
924 return present;
918} 925}
919 926
920static void b5k_instruction_hazard(void) 927static void b5k_instruction_hazard(void)
@@ -938,6 +945,7 @@ static void probe_pcache(void)
938 struct cpuinfo_mips *c = &current_cpu_data; 945 struct cpuinfo_mips *c = &current_cpu_data;
939 unsigned int config = read_c0_config(); 946 unsigned int config = read_c0_config();
940 unsigned int prid = read_c0_prid(); 947 unsigned int prid = read_c0_prid();
948 int has_74k_erratum = 0;
941 unsigned long config1; 949 unsigned long config1;
942 unsigned int lsize; 950 unsigned int lsize;
943 951
@@ -1012,6 +1020,7 @@ static void probe_pcache(void)
1012 case CPU_R10000: 1020 case CPU_R10000:
1013 case CPU_R12000: 1021 case CPU_R12000:
1014 case CPU_R14000: 1022 case CPU_R14000:
1023 case CPU_R16000:
1015 icache_size = 1 << (12 + ((config & R10K_CONF_IC) >> 29)); 1024 icache_size = 1 << (12 + ((config & R10K_CONF_IC) >> 29));
1016 c->icache.linesz = 64; 1025 c->icache.linesz = 64;
1017 c->icache.ways = 2; 1026 c->icache.ways = 2;
@@ -1223,8 +1232,8 @@ static void probe_pcache(void)
1223 dcache_size / (c->dcache.linesz * c->dcache.ways) : 0; 1232 dcache_size / (c->dcache.linesz * c->dcache.ways) : 0;
1224 1233
1225 /* 1234 /*
1226 * R10000 and R12000 P-caches are odd in a positive way. They're 32kB 1235 * R1x000 P-caches are odd in a positive way. They're 32kB 2-way
1227 * 2-way virtually indexed so normally would suffer from aliases. So 1236 * virtually indexed so normally would suffer from aliases. So
1228 * normally they'd suffer from aliases but magic in the hardware deals 1237 * normally they'd suffer from aliases but magic in the hardware deals
1229 * with that for us so we don't need to take care ourselves. 1238 * with that for us so we don't need to take care ourselves.
1230 */ 1239 */
@@ -1240,11 +1249,12 @@ static void probe_pcache(void)
1240 case CPU_R10000: 1249 case CPU_R10000:
1241 case CPU_R12000: 1250 case CPU_R12000:
1242 case CPU_R14000: 1251 case CPU_R14000:
1252 case CPU_R16000:
1243 break; 1253 break;
1244 1254
1245 case CPU_74K: 1255 case CPU_74K:
1246 case CPU_1074K: 1256 case CPU_1074K:
1247 alias_74k_erratum(c); 1257 has_74k_erratum = alias_74k_erratum(c);
1248 /* Fall through. */ 1258 /* Fall through. */
1249 case CPU_M14KC: 1259 case CPU_M14KC:
1250 case CPU_M14KEC: 1260 case CPU_M14KEC:
@@ -1259,7 +1269,7 @@ static void probe_pcache(void)
1259 if (!(read_c0_config7() & MIPS_CONF7_IAR) && 1269 if (!(read_c0_config7() & MIPS_CONF7_IAR) &&
1260 (c->icache.waysize > PAGE_SIZE)) 1270 (c->icache.waysize > PAGE_SIZE))
1261 c->icache.flags |= MIPS_CACHE_ALIASES; 1271 c->icache.flags |= MIPS_CACHE_ALIASES;
1262 if (read_c0_config7() & MIPS_CONF7_AR) { 1272 if (!has_74k_erratum && (read_c0_config7() & MIPS_CONF7_AR)) {
1263 /* 1273 /*
1264 * Effectively physically indexed dcache, 1274 * Effectively physically indexed dcache,
1265 * thus no virtual aliases. 1275 * thus no virtual aliases.
@@ -1268,7 +1278,7 @@ static void probe_pcache(void)
1268 break; 1278 break;
1269 } 1279 }
1270 default: 1280 default:
1271 if (c->dcache.waysize > PAGE_SIZE) 1281 if (has_74k_erratum || c->dcache.waysize > PAGE_SIZE)
1272 c->dcache.flags |= MIPS_CACHE_ALIASES; 1282 c->dcache.flags |= MIPS_CACHE_ALIASES;
1273 } 1283 }
1274 1284
@@ -1438,6 +1448,7 @@ static void setup_scache(void)
1438 case CPU_R10000: 1448 case CPU_R10000:
1439 case CPU_R12000: 1449 case CPU_R12000:
1440 case CPU_R14000: 1450 case CPU_R14000:
1451 case CPU_R16000:
1441 scache_size = 0x80000 << ((config & R10K_CONF_SS) >> 16); 1452 scache_size = 0x80000 << ((config & R10K_CONF_SS) >> 16);
1442 c->scache.linesz = 64 << ((config >> 13) & 1); 1453 c->scache.linesz = 64 << ((config >> 13) & 1);
1443 c->scache.ways = 2; 1454 c->scache.ways = 2;
diff --git a/arch/mips/mm/cache.c b/arch/mips/mm/cache.c
index 7e3ea7766822..77d96db8253c 100644
--- a/arch/mips/mm/cache.c
+++ b/arch/mips/mm/cache.c
@@ -119,36 +119,37 @@ void __flush_anon_page(struct page *page, unsigned long vmaddr)
119 119
120EXPORT_SYMBOL(__flush_anon_page); 120EXPORT_SYMBOL(__flush_anon_page);
121 121
122static void mips_flush_dcache_from_pte(pte_t pteval, unsigned long address) 122void __flush_icache_page(struct vm_area_struct *vma, struct page *page)
123{
124 unsigned long addr;
125
126 if (PageHighMem(page))
127 return;
128
129 addr = (unsigned long) page_address(page);
130 flush_data_cache_page(addr);
131}
132EXPORT_SYMBOL_GPL(__flush_icache_page);
133
134void __update_cache(struct vm_area_struct *vma, unsigned long address,
135 pte_t pte)
123{ 136{
124 struct page *page; 137 struct page *page;
125 unsigned long pfn = pte_pfn(pteval); 138 unsigned long pfn, addr;
139 int exec = (vma->vm_flags & VM_EXEC) && !cpu_has_ic_fills_f_dc;
126 140
141 pfn = pte_pfn(pte);
127 if (unlikely(!pfn_valid(pfn))) 142 if (unlikely(!pfn_valid(pfn)))
128 return; 143 return;
129
130 page = pfn_to_page(pfn); 144 page = pfn_to_page(pfn);
131 if (page_mapping(page) && Page_dcache_dirty(page)) { 145 if (page_mapping(page) && Page_dcache_dirty(page)) {
132 unsigned long page_addr = (unsigned long) page_address(page); 146 addr = (unsigned long) page_address(page);
133 147 if (exec || pages_do_alias(addr, address & PAGE_MASK))
134 if (!cpu_has_ic_fills_f_dc || 148 flush_data_cache_page(addr);
135 pages_do_alias(page_addr, address & PAGE_MASK))
136 flush_data_cache_page(page_addr);
137 ClearPageDcacheDirty(page); 149 ClearPageDcacheDirty(page);
138 } 150 }
139} 151}
140 152
141void set_pte_at(struct mm_struct *mm, unsigned long addr,
142 pte_t *ptep, pte_t pteval)
143{
144 if (cpu_has_dc_aliases || !cpu_has_ic_fills_f_dc) {
145 if (pte_present(pteval))
146 mips_flush_dcache_from_pte(pteval, addr);
147 }
148
149 set_pte(ptep, pteval);
150}
151
152unsigned long _page_cachable_default; 153unsigned long _page_cachable_default;
153EXPORT_SYMBOL(_page_cachable_default); 154EXPORT_SYMBOL(_page_cachable_default);
154 155
diff --git a/arch/mips/mm/dma-default.c b/arch/mips/mm/dma-default.c
index af5f046e627e..609d1241b0c4 100644
--- a/arch/mips/mm/dma-default.c
+++ b/arch/mips/mm/dma-default.c
@@ -258,7 +258,7 @@ static void mips_dma_unmap_page(struct device *dev, dma_addr_t dma_addr,
258 if (cpu_needs_post_dma_flush(dev)) 258 if (cpu_needs_post_dma_flush(dev))
259 __dma_sync(dma_addr_to_page(dev, dma_addr), 259 __dma_sync(dma_addr_to_page(dev, dma_addr),
260 dma_addr & ~PAGE_MASK, size, direction); 260 dma_addr & ~PAGE_MASK, size, direction);
261 261 plat_post_dma_flush(dev);
262 plat_unmap_dma_mem(dev, dma_addr, size, direction); 262 plat_unmap_dma_mem(dev, dma_addr, size, direction);
263} 263}
264 264
@@ -312,6 +312,7 @@ static void mips_dma_sync_single_for_cpu(struct device *dev,
312 if (cpu_needs_post_dma_flush(dev)) 312 if (cpu_needs_post_dma_flush(dev))
313 __dma_sync(dma_addr_to_page(dev, dma_handle), 313 __dma_sync(dma_addr_to_page(dev, dma_handle),
314 dma_handle & ~PAGE_MASK, size, direction); 314 dma_handle & ~PAGE_MASK, size, direction);
315 plat_post_dma_flush(dev);
315} 316}
316 317
317static void mips_dma_sync_single_for_device(struct device *dev, 318static void mips_dma_sync_single_for_device(struct device *dev,
@@ -331,6 +332,7 @@ static void mips_dma_sync_sg_for_cpu(struct device *dev,
331 for (i = 0; i < nelems; i++, sg++) 332 for (i = 0; i < nelems; i++, sg++)
332 __dma_sync(sg_page(sg), sg->offset, sg->length, 333 __dma_sync(sg_page(sg), sg->offset, sg->length,
333 direction); 334 direction);
335 plat_post_dma_flush(dev);
334} 336}
335 337
336static void mips_dma_sync_sg_for_device(struct device *dev, 338static void mips_dma_sync_sg_for_device(struct device *dev,
diff --git a/arch/mips/mm/init.c b/arch/mips/mm/init.c
index 448cde372af0..faa5c9822ecc 100644
--- a/arch/mips/mm/init.c
+++ b/arch/mips/mm/init.c
@@ -96,7 +96,7 @@ static void *__kmap_pgprot(struct page *page, unsigned long addr, pgprot_t prot)
96 vaddr = __fix_to_virt(FIX_CMAP_END - idx); 96 vaddr = __fix_to_virt(FIX_CMAP_END - idx);
97 pte = mk_pte(page, prot); 97 pte = mk_pte(page, prot);
98#if defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32) 98#if defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32)
99 entrylo = pte.pte_high; 99 entrylo = pte_to_entrylo(pte.pte_high);
100#else 100#else
101 entrylo = pte_to_entrylo(pte_val(pte)); 101 entrylo = pte_to_entrylo(pte_val(pte));
102#endif 102#endif
@@ -106,6 +106,11 @@ static void *__kmap_pgprot(struct page *page, unsigned long addr, pgprot_t prot)
106 write_c0_entryhi(vaddr & (PAGE_MASK << 1)); 106 write_c0_entryhi(vaddr & (PAGE_MASK << 1));
107 write_c0_entrylo0(entrylo); 107 write_c0_entrylo0(entrylo);
108 write_c0_entrylo1(entrylo); 108 write_c0_entrylo1(entrylo);
109#ifdef CONFIG_XPA
110 entrylo = (pte.pte_low & _PFNX_MASK);
111 writex_c0_entrylo0(entrylo);
112 writex_c0_entrylo1(entrylo);
113#endif
109 tlbidx = read_c0_wired(); 114 tlbidx = read_c0_wired();
110 write_c0_wired(tlbidx + 1); 115 write_c0_wired(tlbidx + 1);
111 write_c0_index(tlbidx); 116 write_c0_index(tlbidx);
diff --git a/arch/mips/mm/page.c b/arch/mips/mm/page.c
index 3f85f921801b..885d73ffd6fb 100644
--- a/arch/mips/mm/page.c
+++ b/arch/mips/mm/page.c
@@ -157,6 +157,7 @@ static void set_prefetch_parameters(void)
157 case CPU_R10000: 157 case CPU_R10000:
158 case CPU_R12000: 158 case CPU_R12000:
159 case CPU_R14000: 159 case CPU_R14000:
160 case CPU_R16000:
160 /* 161 /*
161 * Those values have been experimentally tuned for an 162 * Those values have been experimentally tuned for an
162 * Origin 200. 163 * Origin 200.
diff --git a/arch/mips/mm/tlb-r4k.c b/arch/mips/mm/tlb-r4k.c
index b2afa49beab0..a27a088e6f9f 100644
--- a/arch/mips/mm/tlb-r4k.c
+++ b/arch/mips/mm/tlb-r4k.c
@@ -333,9 +333,17 @@ void __update_tlb(struct vm_area_struct * vma, unsigned long address, pte_t pte)
333 ptep = pte_offset_map(pmdp, address); 333 ptep = pte_offset_map(pmdp, address);
334 334
335#if defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32) 335#if defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32)
336#ifdef CONFIG_XPA
337 write_c0_entrylo0(pte_to_entrylo(ptep->pte_high));
338 writex_c0_entrylo0(ptep->pte_low & _PFNX_MASK);
339 ptep++;
340 write_c0_entrylo1(pte_to_entrylo(ptep->pte_high));
341 writex_c0_entrylo1(ptep->pte_low & _PFNX_MASK);
342#else
336 write_c0_entrylo0(ptep->pte_high); 343 write_c0_entrylo0(ptep->pte_high);
337 ptep++; 344 ptep++;
338 write_c0_entrylo1(ptep->pte_high); 345 write_c0_entrylo1(ptep->pte_high);
346#endif
339#else 347#else
340 write_c0_entrylo0(pte_to_entrylo(pte_val(*ptep++))); 348 write_c0_entrylo0(pte_to_entrylo(pte_val(*ptep++)));
341 write_c0_entrylo1(pte_to_entrylo(pte_val(*ptep))); 349 write_c0_entrylo1(pte_to_entrylo(pte_val(*ptep)));
@@ -355,6 +363,9 @@ void __update_tlb(struct vm_area_struct * vma, unsigned long address, pte_t pte)
355void add_wired_entry(unsigned long entrylo0, unsigned long entrylo1, 363void add_wired_entry(unsigned long entrylo0, unsigned long entrylo1,
356 unsigned long entryhi, unsigned long pagemask) 364 unsigned long entryhi, unsigned long pagemask)
357{ 365{
366#ifdef CONFIG_XPA
367 panic("Broken for XPA kernels");
368#else
358 unsigned long flags; 369 unsigned long flags;
359 unsigned long wired; 370 unsigned long wired;
360 unsigned long old_pagemask; 371 unsigned long old_pagemask;
@@ -383,6 +394,7 @@ void add_wired_entry(unsigned long entrylo0, unsigned long entrylo1,
383 write_c0_pagemask(old_pagemask); 394 write_c0_pagemask(old_pagemask);
384 local_flush_tlb_all(); 395 local_flush_tlb_all();
385 local_irq_restore(flags); 396 local_irq_restore(flags);
397#endif
386} 398}
387 399
388#ifdef CONFIG_TRANSPARENT_HUGEPAGE 400#ifdef CONFIG_TRANSPARENT_HUGEPAGE
@@ -477,7 +489,8 @@ static void r4k_tlb_configure(void)
477 write_c0_wired(0); 489 write_c0_wired(0);
478 if (current_cpu_type() == CPU_R10000 || 490 if (current_cpu_type() == CPU_R10000 ||
479 current_cpu_type() == CPU_R12000 || 491 current_cpu_type() == CPU_R12000 ||
480 current_cpu_type() == CPU_R14000) 492 current_cpu_type() == CPU_R14000 ||
493 current_cpu_type() == CPU_R16000)
481 write_c0_framemask(0); 494 write_c0_framemask(0);
482 495
483 if (cpu_has_rixi) { 496 if (cpu_has_rixi) {
diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index d75ff73a2012..97c87027c17f 100644
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -35,6 +35,17 @@
35#include <asm/uasm.h> 35#include <asm/uasm.h>
36#include <asm/setup.h> 36#include <asm/setup.h>
37 37
38static int __cpuinitdata mips_xpa_disabled;
39
40static int __init xpa_disable(char *s)
41{
42 mips_xpa_disabled = 1;
43
44 return 1;
45}
46
47__setup("noxpa", xpa_disable);
48
38/* 49/*
39 * TLB load/store/modify handlers. 50 * TLB load/store/modify handlers.
40 * 51 *
@@ -231,14 +242,14 @@ static void output_pgtable_bits_defines(void)
231 pr_define("_PAGE_HUGE_SHIFT %d\n", _PAGE_HUGE_SHIFT); 242 pr_define("_PAGE_HUGE_SHIFT %d\n", _PAGE_HUGE_SHIFT);
232 pr_define("_PAGE_SPLITTING_SHIFT %d\n", _PAGE_SPLITTING_SHIFT); 243 pr_define("_PAGE_SPLITTING_SHIFT %d\n", _PAGE_SPLITTING_SHIFT);
233#endif 244#endif
245#ifdef CONFIG_CPU_MIPSR2
234 if (cpu_has_rixi) { 246 if (cpu_has_rixi) {
235#ifdef _PAGE_NO_EXEC_SHIFT 247#ifdef _PAGE_NO_EXEC_SHIFT
236 pr_define("_PAGE_NO_EXEC_SHIFT %d\n", _PAGE_NO_EXEC_SHIFT); 248 pr_define("_PAGE_NO_EXEC_SHIFT %d\n", _PAGE_NO_EXEC_SHIFT);
237#endif
238#ifdef _PAGE_NO_READ_SHIFT
239 pr_define("_PAGE_NO_READ_SHIFT %d\n", _PAGE_NO_READ_SHIFT); 249 pr_define("_PAGE_NO_READ_SHIFT %d\n", _PAGE_NO_READ_SHIFT);
240#endif 250#endif
241 } 251 }
252#endif
242 pr_define("_PAGE_GLOBAL_SHIFT %d\n", _PAGE_GLOBAL_SHIFT); 253 pr_define("_PAGE_GLOBAL_SHIFT %d\n", _PAGE_GLOBAL_SHIFT);
243 pr_define("_PAGE_VALID_SHIFT %d\n", _PAGE_VALID_SHIFT); 254 pr_define("_PAGE_VALID_SHIFT %d\n", _PAGE_VALID_SHIFT);
244 pr_define("_PAGE_DIRTY_SHIFT %d\n", _PAGE_DIRTY_SHIFT); 255 pr_define("_PAGE_DIRTY_SHIFT %d\n", _PAGE_DIRTY_SHIFT);
@@ -501,26 +512,9 @@ static void build_tlb_write_entry(u32 **p, struct uasm_label **l,
501 case tlb_indexed: tlbw = uasm_i_tlbwi; break; 512 case tlb_indexed: tlbw = uasm_i_tlbwi; break;
502 } 513 }
503 514
504 if (cpu_has_mips_r2_exec_hazard) { 515 if (cpu_has_mips_r2_r6) {
505 /* 516 if (cpu_has_mips_r2_exec_hazard)
506 * The architecture spec says an ehb is required here,
507 * but a number of cores do not have the hazard and
508 * using an ehb causes an expensive pipeline stall.
509 */
510 switch (current_cpu_type()) {
511 case CPU_M14KC:
512 case CPU_74K:
513 case CPU_1074K:
514 case CPU_PROAPTIV:
515 case CPU_P5600:
516 case CPU_M5150:
517 case CPU_QEMU_GENERIC:
518 break;
519
520 default:
521 uasm_i_ehb(p); 517 uasm_i_ehb(p);
522 break;
523 }
524 tlbw(p); 518 tlbw(p);
525 return; 519 return;
526 } 520 }
@@ -569,6 +563,7 @@ static void build_tlb_write_entry(u32 **p, struct uasm_label **l,
569 case CPU_R10000: 563 case CPU_R10000:
570 case CPU_R12000: 564 case CPU_R12000:
571 case CPU_R14000: 565 case CPU_R14000:
566 case CPU_R16000:
572 case CPU_4KC: 567 case CPU_4KC:
573 case CPU_4KEC: 568 case CPU_4KEC:
574 case CPU_M14KC: 569 case CPU_M14KC:
@@ -1027,12 +1022,27 @@ static void build_update_entries(u32 **p, unsigned int tmp, unsigned int ptep)
1027 } else { 1022 } else {
1028 int pte_off_even = sizeof(pte_t) / 2; 1023 int pte_off_even = sizeof(pte_t) / 2;
1029 int pte_off_odd = pte_off_even + sizeof(pte_t); 1024 int pte_off_odd = pte_off_even + sizeof(pte_t);
1025#ifdef CONFIG_XPA
1026 const int scratch = 1; /* Our extra working register */
1030 1027
1031 /* The pte entries are pre-shifted */ 1028 uasm_i_addu(p, scratch, 0, ptep);
1032 uasm_i_lw(p, tmp, pte_off_even, ptep); /* get even pte */ 1029#endif
1033 UASM_i_MTC0(p, tmp, C0_ENTRYLO0); /* load it */ 1030 uasm_i_lw(p, tmp, pte_off_even, ptep); /* even pte */
1034 uasm_i_lw(p, ptep, pte_off_odd, ptep); /* get odd pte */ 1031 uasm_i_lw(p, ptep, pte_off_odd, ptep); /* odd pte */
1035 UASM_i_MTC0(p, ptep, C0_ENTRYLO1); /* load it */ 1032 UASM_i_ROTR(p, tmp, tmp, ilog2(_PAGE_GLOBAL));
1033 UASM_i_ROTR(p, ptep, ptep, ilog2(_PAGE_GLOBAL));
1034 UASM_i_MTC0(p, tmp, C0_ENTRYLO0);
1035 UASM_i_MTC0(p, ptep, C0_ENTRYLO1);
1036#ifdef CONFIG_XPA
1037 uasm_i_lw(p, tmp, 0, scratch);
1038 uasm_i_lw(p, ptep, sizeof(pte_t), scratch);
1039 uasm_i_lui(p, scratch, 0xff);
1040 uasm_i_ori(p, scratch, scratch, 0xffff);
1041 uasm_i_and(p, tmp, scratch, tmp);
1042 uasm_i_and(p, ptep, scratch, ptep);
1043 uasm_i_mthc0(p, tmp, C0_ENTRYLO0);
1044 uasm_i_mthc0(p, ptep, C0_ENTRYLO1);
1045#endif
1036 } 1046 }
1037#else 1047#else
1038 UASM_i_LW(p, tmp, 0, ptep); /* get even pte */ 1048 UASM_i_LW(p, tmp, 0, ptep); /* get even pte */
@@ -1533,8 +1543,14 @@ iPTE_SW(u32 **p, struct uasm_reloc **r, unsigned int pte, unsigned int ptr,
1533{ 1543{
1534#ifdef CONFIG_PHYS_ADDR_T_64BIT 1544#ifdef CONFIG_PHYS_ADDR_T_64BIT
1535 unsigned int hwmode = mode & (_PAGE_VALID | _PAGE_DIRTY); 1545 unsigned int hwmode = mode & (_PAGE_VALID | _PAGE_DIRTY);
1536#endif
1537 1546
1547 if (!cpu_has_64bits) {
1548 const int scratch = 1; /* Our extra working register */
1549
1550 uasm_i_lui(p, scratch, (mode >> 16));
1551 uasm_i_or(p, pte, pte, scratch);
1552 } else
1553#endif
1538 uasm_i_ori(p, pte, pte, mode); 1554 uasm_i_ori(p, pte, pte, mode);
1539#ifdef CONFIG_SMP 1555#ifdef CONFIG_SMP
1540# ifdef CONFIG_PHYS_ADDR_T_64BIT 1556# ifdef CONFIG_PHYS_ADDR_T_64BIT
@@ -1598,15 +1614,17 @@ build_pte_present(u32 **p, struct uasm_reloc **r,
1598 uasm_il_bbit0(p, r, pte, ilog2(_PAGE_PRESENT), lid); 1614 uasm_il_bbit0(p, r, pte, ilog2(_PAGE_PRESENT), lid);
1599 uasm_i_nop(p); 1615 uasm_i_nop(p);
1600 } else { 1616 } else {
1601 uasm_i_andi(p, t, pte, _PAGE_PRESENT); 1617 uasm_i_srl(p, t, pte, _PAGE_PRESENT_SHIFT);
1618 uasm_i_andi(p, t, t, 1);
1602 uasm_il_beqz(p, r, t, lid); 1619 uasm_il_beqz(p, r, t, lid);
1603 if (pte == t) 1620 if (pte == t)
1604 /* You lose the SMP race :-(*/ 1621 /* You lose the SMP race :-(*/
1605 iPTE_LW(p, pte, ptr); 1622 iPTE_LW(p, pte, ptr);
1606 } 1623 }
1607 } else { 1624 } else {
1608 uasm_i_andi(p, t, pte, _PAGE_PRESENT | _PAGE_READ); 1625 uasm_i_srl(p, t, pte, _PAGE_PRESENT_SHIFT);
1609 uasm_i_xori(p, t, t, _PAGE_PRESENT | _PAGE_READ); 1626 uasm_i_andi(p, t, t, 3);
1627 uasm_i_xori(p, t, t, 3);
1610 uasm_il_bnez(p, r, t, lid); 1628 uasm_il_bnez(p, r, t, lid);
1611 if (pte == t) 1629 if (pte == t)
1612 /* You lose the SMP race :-(*/ 1630 /* You lose the SMP race :-(*/
@@ -1635,8 +1653,9 @@ build_pte_writable(u32 **p, struct uasm_reloc **r,
1635{ 1653{
1636 int t = scratch >= 0 ? scratch : pte; 1654 int t = scratch >= 0 ? scratch : pte;
1637 1655
1638 uasm_i_andi(p, t, pte, _PAGE_PRESENT | _PAGE_WRITE); 1656 uasm_i_srl(p, t, pte, _PAGE_PRESENT_SHIFT);
1639 uasm_i_xori(p, t, t, _PAGE_PRESENT | _PAGE_WRITE); 1657 uasm_i_andi(p, t, t, 5);
1658 uasm_i_xori(p, t, t, 5);
1640 uasm_il_bnez(p, r, t, lid); 1659 uasm_il_bnez(p, r, t, lid);
1641 if (pte == t) 1660 if (pte == t)
1642 /* You lose the SMP race :-(*/ 1661 /* You lose the SMP race :-(*/
@@ -1672,7 +1691,8 @@ build_pte_modifiable(u32 **p, struct uasm_reloc **r,
1672 uasm_i_nop(p); 1691 uasm_i_nop(p);
1673 } else { 1692 } else {
1674 int t = scratch >= 0 ? scratch : pte; 1693 int t = scratch >= 0 ? scratch : pte;
1675 uasm_i_andi(p, t, pte, _PAGE_WRITE); 1694 uasm_i_srl(p, t, pte, _PAGE_WRITE_SHIFT);
1695 uasm_i_andi(p, t, t, 1);
1676 uasm_il_beqz(p, r, t, lid); 1696 uasm_il_beqz(p, r, t, lid);
1677 if (pte == t) 1697 if (pte == t)
1678 /* You lose the SMP race :-(*/ 1698 /* You lose the SMP race :-(*/
@@ -2285,6 +2305,11 @@ static void config_htw_params(void)
2285 2305
2286 pwsize = ilog2(PTRS_PER_PGD) << MIPS_PWSIZE_GDW_SHIFT; 2306 pwsize = ilog2(PTRS_PER_PGD) << MIPS_PWSIZE_GDW_SHIFT;
2287 pwsize |= ilog2(PTRS_PER_PTE) << MIPS_PWSIZE_PTW_SHIFT; 2307 pwsize |= ilog2(PTRS_PER_PTE) << MIPS_PWSIZE_PTW_SHIFT;
2308
2309 /* If XPA has been enabled, PTEs are 64-bit in size. */
2310 if (read_c0_pagegrain() & PG_ELPA)
2311 pwsize |= 1;
2312
2288 write_c0_pwsize(pwsize); 2313 write_c0_pwsize(pwsize);
2289 2314
2290 /* Make sure everything is set before we enable the HTW */ 2315 /* Make sure everything is set before we enable the HTW */
@@ -2298,6 +2323,28 @@ static void config_htw_params(void)
2298 print_htw_config(); 2323 print_htw_config();
2299} 2324}
2300 2325
2326static void config_xpa_params(void)
2327{
2328#ifdef CONFIG_XPA
2329 unsigned int pagegrain;
2330
2331 if (mips_xpa_disabled) {
2332 pr_info("Extended Physical Addressing (XPA) disabled\n");
2333 return;
2334 }
2335
2336 pagegrain = read_c0_pagegrain();
2337 write_c0_pagegrain(pagegrain | PG_ELPA);
2338 back_to_back_c0_hazard();
2339 pagegrain = read_c0_pagegrain();
2340
2341 if (pagegrain & PG_ELPA)
2342 pr_info("Extended Physical Addressing (XPA) enabled\n");
2343 else
2344 panic("Extended Physical Addressing (XPA) disabled");
2345#endif
2346}
2347
2301void build_tlb_refill_handler(void) 2348void build_tlb_refill_handler(void)
2302{ 2349{
2303 /* 2350 /*
@@ -2362,8 +2409,9 @@ void build_tlb_refill_handler(void)
2362 } 2409 }
2363 if (cpu_has_local_ebase) 2410 if (cpu_has_local_ebase)
2364 build_r4000_tlb_refill_handler(); 2411 build_r4000_tlb_refill_handler();
2412 if (cpu_has_xpa)
2413 config_xpa_params();
2365 if (cpu_has_htw) 2414 if (cpu_has_htw)
2366 config_htw_params(); 2415 config_htw_params();
2367
2368 } 2416 }
2369} 2417}
diff --git a/arch/mips/mti-malta/malta-memory.c b/arch/mips/mti-malta/malta-memory.c
index 8fddd2cdbff7..b769657be4d4 100644
--- a/arch/mips/mti-malta/malta-memory.c
+++ b/arch/mips/mti-malta/malta-memory.c
@@ -16,6 +16,7 @@
16#include <linux/string.h> 16#include <linux/string.h>
17 17
18#include <asm/bootinfo.h> 18#include <asm/bootinfo.h>
19#include <asm/cdmm.h>
19#include <asm/maar.h> 20#include <asm/maar.h>
20#include <asm/sections.h> 21#include <asm/sections.h>
21#include <asm/fw/fw.h> 22#include <asm/fw/fw.h>
@@ -53,6 +54,12 @@ fw_memblock_t * __init fw_getmdesc(int eva)
53 pr_warn("memsize not set in YAMON, set to default (32Mb)\n"); 54 pr_warn("memsize not set in YAMON, set to default (32Mb)\n");
54 physical_memsize = 0x02000000; 55 physical_memsize = 0x02000000;
55 } else { 56 } else {
57 if (memsize > (256 << 20)) { /* memsize should be capped to 256M */
58 pr_warn("Unsupported memsize value (0x%lx) detected! "
59 "Using 0x10000000 (256M) instead\n",
60 memsize);
61 memsize = 256 << 20;
62 }
56 /* If ememsize is set, then set physical_memsize to that */ 63 /* If ememsize is set, then set physical_memsize to that */
57 physical_memsize = ememsize ? : memsize; 64 physical_memsize = ememsize ? : memsize;
58 } 65 }
@@ -196,3 +203,9 @@ unsigned platform_maar_init(unsigned num_pairs)
196 203
197 return maar_config(cfg, num_cfg, num_pairs); 204 return maar_config(cfg, num_cfg, num_pairs);
198} 205}
206
207phys_addr_t mips_cdmm_phys_base(void)
208{
209 /* This address is "typically unused" */
210 return 0x1fc10000;
211}
diff --git a/arch/mips/mti-malta/malta-time.c b/arch/mips/mti-malta/malta-time.c
index ce02dbdedc62..185e68261f45 100644
--- a/arch/mips/mti-malta/malta-time.c
+++ b/arch/mips/mti-malta/malta-time.c
@@ -87,8 +87,10 @@ static void __init estimate_frequencies(void)
87 87
88 /* Initialize counters. */ 88 /* Initialize counters. */
89 start = read_c0_count(); 89 start = read_c0_count();
90 if (gic_present) 90 if (gic_present) {
91 gic_start_count();
91 gicstart = gic_read_count(); 92 gicstart = gic_read_count();
93 }
92 94
93 /* Read counter exactly on falling edge of update flag. */ 95 /* Read counter exactly on falling edge of update flag. */
94 while (CMOS_READ(RTC_REG_A) & RTC_UIP); 96 while (CMOS_READ(RTC_REG_A) & RTC_UIP);
@@ -115,6 +117,22 @@ void read_persistent_clock(struct timespec *ts)
115 ts->tv_nsec = 0; 117 ts->tv_nsec = 0;
116} 118}
117 119
120int get_c0_fdc_int(void)
121{
122 int mips_cpu_fdc_irq;
123
124 if (cpu_has_veic)
125 mips_cpu_fdc_irq = -1;
126 else if (gic_present)
127 mips_cpu_fdc_irq = gic_get_c0_fdc_int();
128 else if (cp0_fdc_irq >= 0)
129 mips_cpu_fdc_irq = MIPS_CPU_IRQ_BASE + cp0_fdc_irq;
130 else
131 mips_cpu_fdc_irq = -1;
132
133 return mips_cpu_fdc_irq;
134}
135
118int get_c0_perfcount_int(void) 136int get_c0_perfcount_int(void)
119{ 137{
120 if (cpu_has_veic) { 138 if (cpu_has_veic) {
diff --git a/arch/mips/mti-sead3/Makefile b/arch/mips/mti-sead3/Makefile
index 2ae49e99eb67..ecd71db6258b 100644
--- a/arch/mips/mti-sead3/Makefile
+++ b/arch/mips/mti-sead3/Makefile
@@ -9,14 +9,11 @@
9# Steven J. Hill <sjhill@mips.com> 9# Steven J. Hill <sjhill@mips.com>
10# 10#
11obj-y := sead3-lcd.o sead3-display.o sead3-init.o \ 11obj-y := sead3-lcd.o sead3-display.o sead3-init.o \
12 sead3-int.o sead3-mtd.o sead3-net.o \ 12 sead3-int.o sead3-platform.o sead3-reset.o \
13 sead3-platform.o sead3-reset.o \
14 sead3-setup.o sead3-time.o 13 sead3-setup.o sead3-time.o
15 14
16obj-y += sead3-i2c-dev.o sead3-i2c.o \ 15obj-y += leds-sead3.o
17 leds-sead3.o sead3-leds.o
18 16
19obj-$(CONFIG_EARLY_PRINTK) += sead3-console.o 17obj-$(CONFIG_EARLY_PRINTK) += sead3-console.o
20obj-$(CONFIG_USB_EHCI_HCD) += sead3-ehci.o
21 18
22CFLAGS_sead3-setup.o = -I$(src)/../../../scripts/dtc/libfdt 19CFLAGS_sead3-setup.o = -I$(src)/../../../scripts/dtc/libfdt
diff --git a/arch/mips/mti-sead3/leds-sead3.c b/arch/mips/mti-sead3/leds-sead3.c
index 3abe47b316aa..c938ceeb8848 100644
--- a/arch/mips/mti-sead3/leds-sead3.c
+++ b/arch/mips/mti-sead3/leds-sead3.c
@@ -4,6 +4,7 @@
4 * for more details. 4 * for more details.
5 * 5 *
6 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. 6 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
7 * Copyright (C) 2015 Imagination Technologies, Inc.
7 */ 8 */
8#include <linux/kernel.h> 9#include <linux/kernel.h>
9#include <linux/module.h> 10#include <linux/module.h>
@@ -13,22 +14,18 @@
13#include <linux/err.h> 14#include <linux/err.h>
14#include <linux/io.h> 15#include <linux/io.h>
15 16
16#define DRVNAME "sead3-led" 17#include <asm/mips-boards/sead3-addr.h>
17
18static struct platform_device *pdev;
19 18
20static void sead3_pled_set(struct led_classdev *led_cdev, 19static void sead3_pled_set(struct led_classdev *led_cdev,
21 enum led_brightness value) 20 enum led_brightness value)
22{ 21{
23 pr_debug("sead3_pled_set\n"); 22 writel(value, (void __iomem *)SEAD3_CPLD_P_LED);
24 writel(value, (void __iomem *)0xBF000210); /* FIXME */
25} 23}
26 24
27static void sead3_fled_set(struct led_classdev *led_cdev, 25static void sead3_fled_set(struct led_classdev *led_cdev,
28 enum led_brightness value) 26 enum led_brightness value)
29{ 27{
30 pr_debug("sead3_fled_set\n"); 28 writel(value, (void __iomem *)SEAD3_CPLD_F_LED);
31 writel(value, (void __iomem *)0xBF000218); /* FIXME */
32} 29}
33 30
34static struct led_classdev sead3_pled = { 31static struct led_classdev sead3_pled = {
@@ -69,37 +66,11 @@ static struct platform_driver sead3_led_driver = {
69 .probe = sead3_led_probe, 66 .probe = sead3_led_probe,
70 .remove = sead3_led_remove, 67 .remove = sead3_led_remove,
71 .driver = { 68 .driver = {
72 .name = DRVNAME, 69 .name = "sead3-led",
73 }, 70 },
74}; 71};
75 72
76static int __init sead3_led_init(void) 73module_platform_driver(sead3_led_driver);
77{
78 int ret;
79
80 ret = platform_driver_register(&sead3_led_driver);
81 if (ret < 0)
82 goto out;
83
84 pdev = platform_device_register_simple(DRVNAME, -1, NULL, 0);
85 if (IS_ERR(pdev)) {
86 ret = PTR_ERR(pdev);
87 platform_driver_unregister(&sead3_led_driver);
88 goto out;
89 }
90
91out:
92 return ret;
93}
94
95static void __exit sead3_led_exit(void)
96{
97 platform_device_unregister(pdev);
98 platform_driver_unregister(&sead3_led_driver);
99}
100
101module_init(sead3_led_init);
102module_exit(sead3_led_exit);
103 74
104MODULE_AUTHOR("Kristian Kielhofner <kris@krisk.org>"); 75MODULE_AUTHOR("Kristian Kielhofner <kris@krisk.org>");
105MODULE_DESCRIPTION("SEAD3 LED driver"); 76MODULE_DESCRIPTION("SEAD3 LED driver");
diff --git a/arch/mips/mti-sead3/sead3-ehci.c b/arch/mips/mti-sead3/sead3-ehci.c
deleted file mode 100644
index 014dd7ba4d68..000000000000
--- a/arch/mips/mti-sead3/sead3-ehci.c
+++ /dev/null
@@ -1,53 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
7 */
8#include <linux/module.h>
9#include <linux/irq.h>
10#include <linux/dma-mapping.h>
11#include <linux/platform_device.h>
12#include <linux/irqchip/mips-gic.h>
13
14#include <asm/mips-boards/sead3int.h>
15
16struct resource ehci_resources[] = {
17 {
18 .start = 0x1b200000,
19 .end = 0x1b200fff,
20 .flags = IORESOURCE_MEM
21 },
22 {
23 .flags = IORESOURCE_IRQ
24 }
25};
26
27u64 sead3_usbdev_dma_mask = DMA_BIT_MASK(32);
28
29static struct platform_device ehci_device = {
30 .name = "sead3-ehci",
31 .id = 0,
32 .dev = {
33 .dma_mask = &sead3_usbdev_dma_mask,
34 .coherent_dma_mask = DMA_BIT_MASK(32)
35 },
36 .num_resources = ARRAY_SIZE(ehci_resources),
37 .resource = ehci_resources
38};
39
40static int __init ehci_init(void)
41{
42 if (gic_present)
43 ehci_resources[1].start = MIPS_GIC_IRQ_BASE + GIC_INT_EHCI;
44 else
45 ehci_resources[1].start = MIPS_CPU_IRQ_BASE + CPU_INT_EHCI;
46 return platform_device_register(&ehci_device);
47}
48
49module_init(ehci_init);
50
51MODULE_AUTHOR("Chris Dearman <chris@mips.com>");
52MODULE_LICENSE("GPL");
53MODULE_DESCRIPTION("EHCI probe driver for SEAD3");
diff --git a/arch/mips/mti-sead3/sead3-i2c-dev.c b/arch/mips/mti-sead3/sead3-i2c-dev.c
deleted file mode 100644
index eca0b53a71dd..000000000000
--- a/arch/mips/mti-sead3/sead3-i2c-dev.c
+++ /dev/null
@@ -1,33 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
7 */
8#include <linux/init.h>
9#include <linux/i2c.h>
10
11static struct i2c_board_info __initdata sead3_i2c_devices[] = {
12 {
13 I2C_BOARD_INFO("adt7476", 0x2c),
14 .irq = 0,
15 },
16 {
17 I2C_BOARD_INFO("m41t80", 0x68),
18 .irq = 0,
19 },
20};
21
22static int __init sead3_i2c_init(void)
23{
24 int err;
25
26 err = i2c_register_board_info(0, sead3_i2c_devices,
27 ARRAY_SIZE(sead3_i2c_devices));
28 if (err < 0)
29 pr_err("sead3-i2c-dev: cannot register board I2C devices\n");
30 return err;
31}
32
33arch_initcall(sead3_i2c_init);
diff --git a/arch/mips/mti-sead3/sead3-i2c-drv.c b/arch/mips/mti-sead3/sead3-i2c-drv.c
deleted file mode 100644
index 2bebf0974e39..000000000000
--- a/arch/mips/mti-sead3/sead3-i2c-drv.c
+++ /dev/null
@@ -1,404 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
7 */
8#include <linux/init.h>
9#include <linux/module.h>
10#include <linux/slab.h>
11#include <linux/delay.h>
12#include <linux/i2c.h>
13#include <linux/platform_device.h>
14
15#define PIC32_I2CxCON 0x0000
16#define PIC32_I2CCON_ON (1<<15)
17#define PIC32_I2CCON_ACKDT (1<<5)
18#define PIC32_I2CCON_ACKEN (1<<4)
19#define PIC32_I2CCON_RCEN (1<<3)
20#define PIC32_I2CCON_PEN (1<<2)
21#define PIC32_I2CCON_RSEN (1<<1)
22#define PIC32_I2CCON_SEN (1<<0)
23#define PIC32_I2CxCONCLR 0x0004
24#define PIC32_I2CxCONSET 0x0008
25#define PIC32_I2CxSTAT 0x0010
26#define PIC32_I2CxSTATCLR 0x0014
27#define PIC32_I2CSTAT_ACKSTAT (1<<15)
28#define PIC32_I2CSTAT_TRSTAT (1<<14)
29#define PIC32_I2CSTAT_BCL (1<<10)
30#define PIC32_I2CSTAT_IWCOL (1<<7)
31#define PIC32_I2CSTAT_I2COV (1<<6)
32#define PIC32_I2CxBRG 0x0040
33#define PIC32_I2CxTRN 0x0050
34#define PIC32_I2CxRCV 0x0060
35
36static DEFINE_SPINLOCK(pic32_bus_lock);
37
38static void __iomem *bus_xfer = (void __iomem *)0xbf000600;
39static void __iomem *bus_status = (void __iomem *)0xbf000060;
40
41#define DELAY() udelay(100)
42
43static inline unsigned int ioready(void)
44{
45 return readl(bus_status) & 1;
46}
47
48static inline void wait_ioready(void)
49{
50 do { } while (!ioready());
51}
52
53static inline void wait_ioclear(void)
54{
55 do { } while (ioready());
56}
57
58static inline void check_ioclear(void)
59{
60 if (ioready()) {
61 do {
62 (void) readl(bus_xfer);
63 DELAY();
64 } while (ioready());
65 }
66}
67
68static u32 pic32_bus_readl(u32 reg)
69{
70 unsigned long flags;
71 u32 status, val;
72
73 spin_lock_irqsave(&pic32_bus_lock, flags);
74
75 check_ioclear();
76 writel((0x01 << 24) | (reg & 0x00ffffff), bus_xfer);
77 DELAY();
78 wait_ioready();
79 status = readl(bus_xfer);
80 DELAY();
81 val = readl(bus_xfer);
82 wait_ioclear();
83
84 spin_unlock_irqrestore(&pic32_bus_lock, flags);
85
86 return val;
87}
88
89static void pic32_bus_writel(u32 val, u32 reg)
90{
91 unsigned long flags;
92 u32 status;
93
94 spin_lock_irqsave(&pic32_bus_lock, flags);
95
96 check_ioclear();
97 writel((0x10 << 24) | (reg & 0x00ffffff), bus_xfer);
98 DELAY();
99 writel(val, bus_xfer);
100 DELAY();
101 wait_ioready();
102 status = readl(bus_xfer);
103 wait_ioclear();
104
105 spin_unlock_irqrestore(&pic32_bus_lock, flags);
106}
107
108struct pic32_i2c_platform_data {
109 u32 base;
110 struct i2c_adapter adap;
111 u32 xfer_timeout;
112 u32 ack_timeout;
113 u32 ctl_timeout;
114};
115
116static inline void pic32_i2c_start(struct pic32_i2c_platform_data *adap)
117{
118 pic32_bus_writel(PIC32_I2CCON_SEN, adap->base + PIC32_I2CxCONSET);
119}
120
121static inline void pic32_i2c_stop(struct pic32_i2c_platform_data *adap)
122{
123 pic32_bus_writel(PIC32_I2CCON_PEN, adap->base + PIC32_I2CxCONSET);
124}
125
126static inline void pic32_i2c_ack(struct pic32_i2c_platform_data *adap)
127{
128 pic32_bus_writel(PIC32_I2CCON_ACKDT, adap->base + PIC32_I2CxCONCLR);
129 pic32_bus_writel(PIC32_I2CCON_ACKEN, adap->base + PIC32_I2CxCONSET);
130}
131
132static inline void pic32_i2c_nack(struct pic32_i2c_platform_data *adap)
133{
134 pic32_bus_writel(PIC32_I2CCON_ACKDT, adap->base + PIC32_I2CxCONSET);
135 pic32_bus_writel(PIC32_I2CCON_ACKEN, adap->base + PIC32_I2CxCONSET);
136}
137
138static inline int pic32_i2c_idle(struct pic32_i2c_platform_data *adap)
139{
140 int i;
141
142 for (i = 0; i < adap->ctl_timeout; i++) {
143 if (((pic32_bus_readl(adap->base + PIC32_I2CxCON) &
144 (PIC32_I2CCON_ACKEN | PIC32_I2CCON_RCEN |
145 PIC32_I2CCON_PEN | PIC32_I2CCON_RSEN |
146 PIC32_I2CCON_SEN)) == 0) &&
147 ((pic32_bus_readl(adap->base + PIC32_I2CxSTAT) &
148 (PIC32_I2CSTAT_TRSTAT)) == 0))
149 return 0;
150 udelay(1);
151 }
152 return -ETIMEDOUT;
153}
154
155static inline u32 pic32_i2c_master_write(struct pic32_i2c_platform_data *adap,
156 u32 byte)
157{
158 pic32_bus_writel(byte, adap->base + PIC32_I2CxTRN);
159 return pic32_bus_readl(adap->base + PIC32_I2CxSTAT) &
160 PIC32_I2CSTAT_IWCOL;
161}
162
163static inline u32 pic32_i2c_master_read(struct pic32_i2c_platform_data *adap)
164{
165 pic32_bus_writel(PIC32_I2CCON_RCEN, adap->base + PIC32_I2CxCONSET);
166 while (pic32_bus_readl(adap->base + PIC32_I2CxCON) & PIC32_I2CCON_RCEN)
167 ;
168 pic32_bus_writel(PIC32_I2CSTAT_I2COV, adap->base + PIC32_I2CxSTATCLR);
169 return pic32_bus_readl(adap->base + PIC32_I2CxRCV);
170}
171
172static int pic32_i2c_address(struct pic32_i2c_platform_data *adap,
173 unsigned int addr, int rd)
174{
175 pic32_i2c_idle(adap);
176 pic32_i2c_start(adap);
177 pic32_i2c_idle(adap);
178
179 addr <<= 1;
180 if (rd)
181 addr |= 1;
182
183 if (pic32_i2c_master_write(adap, addr))
184 return -EIO;
185 pic32_i2c_idle(adap);
186 if (pic32_bus_readl(adap->base + PIC32_I2CxSTAT) &
187 PIC32_I2CSTAT_ACKSTAT)
188 return -EIO;
189 return 0;
190}
191
192static int sead3_i2c_read(struct pic32_i2c_platform_data *adap,
193 unsigned char *buf, unsigned int len)
194{
195 u32 data;
196 int i;
197
198 i = 0;
199 while (i < len) {
200 data = pic32_i2c_master_read(adap);
201 buf[i++] = data;
202 if (i < len)
203 pic32_i2c_ack(adap);
204 else
205 pic32_i2c_nack(adap);
206 }
207
208 pic32_i2c_stop(adap);
209 pic32_i2c_idle(adap);
210 return 0;
211}
212
213static int sead3_i2c_write(struct pic32_i2c_platform_data *adap,
214 unsigned char *buf, unsigned int len)
215{
216 int i;
217 u32 data;
218
219 i = 0;
220 while (i < len) {
221 data = buf[i];
222 if (pic32_i2c_master_write(adap, data))
223 return -EIO;
224 pic32_i2c_idle(adap);
225 if (pic32_bus_readl(adap->base + PIC32_I2CxSTAT) &
226 PIC32_I2CSTAT_ACKSTAT)
227 return -EIO;
228 i++;
229 }
230
231 pic32_i2c_stop(adap);
232 pic32_i2c_idle(adap);
233 return 0;
234}
235
236static int sead3_pic32_platform_xfer(struct i2c_adapter *i2c_adap,
237 struct i2c_msg *msgs, int num)
238{
239 struct pic32_i2c_platform_data *adap = i2c_adap->algo_data;
240 struct i2c_msg *p;
241 int i, err = 0;
242
243 for (i = 0; i < num; i++) {
244#define __BUFSIZE 80
245 int ii;
246 static char buf[__BUFSIZE];
247 char *b = buf;
248
249 p = &msgs[i];
250 b += sprintf(buf, " [%d bytes]", p->len);
251 if ((p->flags & I2C_M_RD) == 0) {
252 for (ii = 0; ii < p->len; ii++) {
253 if (b < &buf[__BUFSIZE-4]) {
254 b += sprintf(b, " %02x", p->buf[ii]);
255 } else {
256 strcat(b, "...");
257 break;
258 }
259 }
260 }
261 }
262
263 for (i = 0; !err && i < num; i++) {
264 p = &msgs[i];
265 err = pic32_i2c_address(adap, p->addr, p->flags & I2C_M_RD);
266 if (err || !p->len)
267 continue;
268 if (p->flags & I2C_M_RD)
269 err = sead3_i2c_read(adap, p->buf, p->len);
270 else
271 err = sead3_i2c_write(adap, p->buf, p->len);
272 }
273
274 /* Return the number of messages processed, or the error code. */
275 if (err == 0)
276 err = num;
277
278 return err;
279}
280
281static u32 sead3_pic32_platform_func(struct i2c_adapter *adap)
282{
283 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
284}
285
286static const struct i2c_algorithm sead3_platform_algo = {
287 .master_xfer = sead3_pic32_platform_xfer,
288 .functionality = sead3_pic32_platform_func,
289};
290
291static void sead3_i2c_platform_setup(struct pic32_i2c_platform_data *priv)
292{
293 pic32_bus_writel(500, priv->base + PIC32_I2CxBRG);
294 pic32_bus_writel(PIC32_I2CCON_ON, priv->base + PIC32_I2CxCONCLR);
295 pic32_bus_writel(PIC32_I2CCON_ON, priv->base + PIC32_I2CxCONSET);
296 pic32_bus_writel(PIC32_I2CSTAT_BCL | PIC32_I2CSTAT_IWCOL,
297 priv->base + PIC32_I2CxSTATCLR);
298}
299
300static int sead3_i2c_platform_probe(struct platform_device *pdev)
301{
302 struct pic32_i2c_platform_data *priv;
303 struct resource *r;
304 int ret;
305
306 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
307 if (!r) {
308 ret = -ENODEV;
309 goto out;
310 }
311
312 priv = kzalloc(sizeof(struct pic32_i2c_platform_data), GFP_KERNEL);
313 if (!priv) {
314 ret = -ENOMEM;
315 goto out;
316 }
317
318 priv->base = r->start;
319 if (!priv->base) {
320 ret = -EBUSY;
321 goto out_mem;
322 }
323
324 priv->xfer_timeout = 200;
325 priv->ack_timeout = 200;
326 priv->ctl_timeout = 200;
327
328 priv->adap.nr = pdev->id;
329 priv->adap.algo = &sead3_platform_algo;
330 priv->adap.algo_data = priv;
331 priv->adap.dev.parent = &pdev->dev;
332 strlcpy(priv->adap.name, "SEAD3 PIC32", sizeof(priv->adap.name));
333
334 sead3_i2c_platform_setup(priv);
335
336 ret = i2c_add_numbered_adapter(&priv->adap);
337 if (ret == 0) {
338 platform_set_drvdata(pdev, priv);
339 return 0;
340 }
341
342out_mem:
343 kfree(priv);
344out:
345 return ret;
346}
347
348static int sead3_i2c_platform_remove(struct platform_device *pdev)
349{
350 struct pic32_i2c_platform_data *priv = platform_get_drvdata(pdev);
351
352 platform_set_drvdata(pdev, NULL);
353 i2c_del_adapter(&priv->adap);
354 kfree(priv);
355 return 0;
356}
357
358#ifdef CONFIG_PM
359static int sead3_i2c_platform_suspend(struct platform_device *pdev,
360 pm_message_t state)
361{
362 dev_dbg(&pdev->dev, "i2c_platform_disable\n");
363 return 0;
364}
365
366static int sead3_i2c_platform_resume(struct platform_device *pdev)
367{
368 struct pic32_i2c_platform_data *priv = platform_get_drvdata(pdev);
369
370 dev_dbg(&pdev->dev, "sead3_i2c_platform_setup\n");
371 sead3_i2c_platform_setup(priv);
372
373 return 0;
374}
375#else
376#define sead3_i2c_platform_suspend NULL
377#define sead3_i2c_platform_resume NULL
378#endif
379
380static struct platform_driver sead3_i2c_platform_driver = {
381 .driver = {
382 .name = "sead3-i2c",
383 },
384 .probe = sead3_i2c_platform_probe,
385 .remove = sead3_i2c_platform_remove,
386 .suspend = sead3_i2c_platform_suspend,
387 .resume = sead3_i2c_platform_resume,
388};
389
390static int __init sead3_i2c_platform_init(void)
391{
392 return platform_driver_register(&sead3_i2c_platform_driver);
393}
394module_init(sead3_i2c_platform_init);
395
396static void __exit sead3_i2c_platform_exit(void)
397{
398 platform_driver_unregister(&sead3_i2c_platform_driver);
399}
400module_exit(sead3_i2c_platform_exit);
401
402MODULE_AUTHOR("Chris Dearman, MIPS Technologies INC.");
403MODULE_DESCRIPTION("SEAD3 PIC32 I2C driver");
404MODULE_LICENSE("GPL");
diff --git a/arch/mips/mti-sead3/sead3-i2c.c b/arch/mips/mti-sead3/sead3-i2c.c
deleted file mode 100644
index 795ae83894e0..000000000000
--- a/arch/mips/mti-sead3/sead3-i2c.c
+++ /dev/null
@@ -1,31 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
7 */
8#include <linux/init.h>
9#include <linux/platform_device.h>
10
11struct resource sead3_i2c_resources[] = {
12 {
13 .start = 0x805200,
14 .end = 0x8053ff,
15 .flags = IORESOURCE_MEM,
16 },
17};
18
19static struct platform_device sead3_i2c_device = {
20 .name = "sead3-i2c",
21 .id = 0,
22 .num_resources = ARRAY_SIZE(sead3_i2c_resources),
23 .resource = sead3_i2c_resources,
24};
25
26static int __init sead3_i2c_init(void)
27{
28 return platform_device_register(&sead3_i2c_device);
29}
30
31device_initcall(sead3_i2c_init);
diff --git a/arch/mips/mti-sead3/sead3-init.c b/arch/mips/mti-sead3/sead3-init.c
index bfbd17b120a2..3572ea30173e 100644
--- a/arch/mips/mti-sead3/sead3-init.c
+++ b/arch/mips/mti-sead3/sead3-init.c
@@ -147,6 +147,6 @@ void __init prom_init(void)
147#endif 147#endif
148} 148}
149 149
150void prom_free_prom_memory(void) 150void __init prom_free_prom_memory(void)
151{ 151{
152} 152}
diff --git a/arch/mips/mti-sead3/sead3-leds.c b/arch/mips/mti-sead3/sead3-leds.c
deleted file mode 100644
index c427c5778186..000000000000
--- a/arch/mips/mti-sead3/sead3-leds.c
+++ /dev/null
@@ -1,79 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
7 */
8#include <linux/init.h>
9#include <linux/leds.h>
10#include <linux/platform_device.h>
11
12#define LEDFLAGS(bits, shift) \
13 ((bits << 8) | (shift << 8))
14
15#define LEDBITS(id, shift, bits) \
16 .name = id #shift, \
17 .flags = LEDFLAGS(bits, shift)
18
19struct led_info led_data_info[] = {
20 { LEDBITS("bit", 0, 1) },
21 { LEDBITS("bit", 1, 1) },
22 { LEDBITS("bit", 2, 1) },
23 { LEDBITS("bit", 3, 1) },
24 { LEDBITS("bit", 4, 1) },
25 { LEDBITS("bit", 5, 1) },
26 { LEDBITS("bit", 6, 1) },
27 { LEDBITS("bit", 7, 1) },
28 { LEDBITS("all", 0, 8) },
29};
30
31static struct led_platform_data led_data = {
32 .num_leds = ARRAY_SIZE(led_data_info),
33 .leds = led_data_info
34};
35
36static struct resource pled_resources[] = {
37 {
38 .start = 0x1f000210,
39 .end = 0x1f000217,
40 .flags = IORESOURCE_MEM
41 }
42};
43
44static struct platform_device pled_device = {
45 .name = "sead3::pled",
46 .id = 0,
47 .dev = {
48 .platform_data = &led_data,
49 },
50 .num_resources = ARRAY_SIZE(pled_resources),
51 .resource = pled_resources
52};
53
54
55static struct resource fled_resources[] = {
56 {
57 .start = 0x1f000218,
58 .end = 0x1f00021f,
59 .flags = IORESOURCE_MEM
60 }
61};
62
63static struct platform_device fled_device = {
64 .name = "sead3::fled",
65 .id = 0,
66 .dev = {
67 .platform_data = &led_data,
68 },
69 .num_resources = ARRAY_SIZE(fled_resources),
70 .resource = fled_resources
71};
72
73static int __init led_init(void)
74{
75 platform_device_register(&pled_device);
76 return platform_device_register(&fled_device);
77}
78
79device_initcall(led_init);
diff --git a/arch/mips/mti-sead3/sead3-mtd.c b/arch/mips/mti-sead3/sead3-mtd.c
deleted file mode 100644
index f9c890d72677..000000000000
--- a/arch/mips/mti-sead3/sead3-mtd.c
+++ /dev/null
@@ -1,53 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
7 */
8#include <linux/init.h>
9#include <linux/platform_device.h>
10#include <linux/mtd/physmap.h>
11
12static struct mtd_partition sead3_mtd_partitions[] = {
13 {
14 .name = "User FS",
15 .offset = 0x00000000,
16 .size = 0x01fc0000,
17 }, {
18 .name = "Board Config",
19 .offset = 0x01fc0000,
20 .size = 0x00040000,
21 .mask_flags = MTD_WRITEABLE
22 },
23};
24
25static struct physmap_flash_data sead3_flash_data = {
26 .width = 4,
27 .nr_parts = ARRAY_SIZE(sead3_mtd_partitions),
28 .parts = sead3_mtd_partitions
29};
30
31static struct resource sead3_flash_resource = {
32 .start = 0x1c000000,
33 .end = 0x1dffffff,
34 .flags = IORESOURCE_MEM
35};
36
37static struct platform_device sead3_flash = {
38 .name = "physmap-flash",
39 .id = 0,
40 .dev = {
41 .platform_data = &sead3_flash_data,
42 },
43 .num_resources = 1,
44 .resource = &sead3_flash_resource,
45};
46
47static int __init sead3_mtd_init(void)
48{
49 platform_device_register(&sead3_flash);
50
51 return 0;
52}
53device_initcall(sead3_mtd_init);
diff --git a/arch/mips/mti-sead3/sead3-net.c b/arch/mips/mti-sead3/sead3-net.c
deleted file mode 100644
index 46176b804576..000000000000
--- a/arch/mips/mti-sead3/sead3-net.c
+++ /dev/null
@@ -1,57 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
7 */
8#include <linux/module.h>
9#include <linux/irq.h>
10#include <linux/irqchip/mips-gic.h>
11#include <linux/platform_device.h>
12#include <linux/smsc911x.h>
13
14#include <asm/mips-boards/sead3int.h>
15
16static struct smsc911x_platform_config sead3_smsc911x_data = {
17 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
18 .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
19 .flags = SMSC911X_USE_32BIT | SMSC911X_SAVE_MAC_ADDRESS,
20 .phy_interface = PHY_INTERFACE_MODE_MII,
21};
22
23struct resource sead3_net_resources[] = {
24 {
25 .start = 0x1f010000,
26 .end = 0x1f01ffff,
27 .flags = IORESOURCE_MEM
28 },
29 {
30 .flags = IORESOURCE_IRQ
31 }
32};
33
34static struct platform_device sead3_net_device = {
35 .name = "smsc911x",
36 .id = 0,
37 .dev = {
38 .platform_data = &sead3_smsc911x_data,
39 },
40 .num_resources = ARRAY_SIZE(sead3_net_resources),
41 .resource = sead3_net_resources
42};
43
44static int __init sead3_net_init(void)
45{
46 if (gic_present)
47 sead3_net_resources[1].start = MIPS_GIC_IRQ_BASE + GIC_INT_NET;
48 else
49 sead3_net_resources[1].start = MIPS_CPU_IRQ_BASE + CPU_INT_NET;
50 return platform_device_register(&sead3_net_device);
51}
52
53module_init(sead3_net_init);
54
55MODULE_AUTHOR("Chris Dearman <chris@mips.com>");
56MODULE_LICENSE("GPL");
57MODULE_DESCRIPTION("Network probe driver for SEAD-3");
diff --git a/arch/mips/mti-sead3/sead3-platform.c b/arch/mips/mti-sead3/sead3-platform.c
index 53ee6f1f018d..73b73efbfb05 100644
--- a/arch/mips/mti-sead3/sead3-platform.c
+++ b/arch/mips/mti-sead3/sead3-platform.c
@@ -5,10 +5,15 @@
5 * 5 *
6 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. 6 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
7 */ 7 */
8#include <linux/module.h> 8#include <linux/dma-mapping.h>
9#include <linux/init.h> 9#include <linux/init.h>
10#include <linux/irq.h>
10#include <linux/irqchip/mips-gic.h> 11#include <linux/irqchip/mips-gic.h>
12#include <linux/leds.h>
13#include <linux/mtd/physmap.h>
14#include <linux/platform_device.h>
11#include <linux/serial_8250.h> 15#include <linux/serial_8250.h>
16#include <linux/smsc911x.h>
12 17
13#include <asm/mips-boards/sead3int.h> 18#include <asm/mips-boards/sead3int.h>
14 19
@@ -36,20 +41,183 @@ static struct platform_device uart8250_device = {
36 }, 41 },
37}; 42};
38 43
39static int __init uart8250_init(void) 44static struct smsc911x_platform_config sead3_smsc911x_data = {
45 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
46 .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
47 .flags = SMSC911X_USE_32BIT | SMSC911X_SAVE_MAC_ADDRESS,
48 .phy_interface = PHY_INTERFACE_MODE_MII,
49};
50
51static struct resource sead3_net_resources[] = {
52 {
53 .start = 0x1f010000,
54 .end = 0x1f01ffff,
55 .flags = IORESOURCE_MEM
56 }, {
57 .flags = IORESOURCE_IRQ
58 }
59};
60
61static struct platform_device sead3_net_device = {
62 .name = "smsc911x",
63 .id = 0,
64 .dev = {
65 .platform_data = &sead3_smsc911x_data,
66 },
67 .num_resources = ARRAY_SIZE(sead3_net_resources),
68 .resource = sead3_net_resources
69};
70
71static struct mtd_partition sead3_mtd_partitions[] = {
72 {
73 .name = "User FS",
74 .offset = 0x00000000,
75 .size = 0x01fc0000,
76 }, {
77 .name = "Board Config",
78 .offset = 0x01fc0000,
79 .size = 0x00040000,
80 .mask_flags = MTD_WRITEABLE
81 },
82};
83
84static struct physmap_flash_data sead3_flash_data = {
85 .width = 4,
86 .nr_parts = ARRAY_SIZE(sead3_mtd_partitions),
87 .parts = sead3_mtd_partitions
88};
89
90static struct resource sead3_flash_resource = {
91 .start = 0x1c000000,
92 .end = 0x1dffffff,
93 .flags = IORESOURCE_MEM
94};
95
96static struct platform_device sead3_flash = {
97 .name = "physmap-flash",
98 .id = 0,
99 .dev = {
100 .platform_data = &sead3_flash_data,
101 },
102 .num_resources = 1,
103 .resource = &sead3_flash_resource,
104};
105
106#define LEDFLAGS(bits, shift) \
107 ((bits << 8) | (shift << 8))
108
109#define LEDBITS(id, shift, bits) \
110 .name = id #shift, \
111 .flags = LEDFLAGS(bits, shift)
112
113static struct led_info led_data_info[] = {
114 { LEDBITS("bit", 0, 1) },
115 { LEDBITS("bit", 1, 1) },
116 { LEDBITS("bit", 2, 1) },
117 { LEDBITS("bit", 3, 1) },
118 { LEDBITS("bit", 4, 1) },
119 { LEDBITS("bit", 5, 1) },
120 { LEDBITS("bit", 6, 1) },
121 { LEDBITS("bit", 7, 1) },
122 { LEDBITS("all", 0, 8) },
123};
124
125static struct led_platform_data led_data = {
126 .num_leds = ARRAY_SIZE(led_data_info),
127 .leds = led_data_info
128};
129
130static struct resource pled_resources[] = {
131 {
132 .start = 0x1f000210,
133 .end = 0x1f000217,
134 .flags = IORESOURCE_MEM
135 }
136};
137
138static struct platform_device pled_device = {
139 .name = "sead3::pled",
140 .id = 0,
141 .dev = {
142 .platform_data = &led_data,
143 },
144 .num_resources = ARRAY_SIZE(pled_resources),
145 .resource = pled_resources
146};
147
148
149static struct resource fled_resources[] = {
150 {
151 .start = 0x1f000218,
152 .end = 0x1f00021f,
153 .flags = IORESOURCE_MEM
154 }
155};
156
157static struct platform_device fled_device = {
158 .name = "sead3::fled",
159 .id = 0,
160 .dev = {
161 .platform_data = &led_data,
162 },
163 .num_resources = ARRAY_SIZE(fled_resources),
164 .resource = fled_resources
165};
166
167static struct platform_device sead3_led_device = {
168 .name = "sead3-led",
169 .id = -1,
170};
171
172static struct resource ehci_resources[] = {
173 {
174 .start = 0x1b200000,
175 .end = 0x1b200fff,
176 .flags = IORESOURCE_MEM
177 }, {
178 .flags = IORESOURCE_IRQ
179 }
180};
181
182static u64 sead3_usbdev_dma_mask = DMA_BIT_MASK(32);
183
184static struct platform_device ehci_device = {
185 .name = "sead3-ehci",
186 .id = 0,
187 .dev = {
188 .dma_mask = &sead3_usbdev_dma_mask,
189 .coherent_dma_mask = DMA_BIT_MASK(32)
190 },
191 .num_resources = ARRAY_SIZE(ehci_resources),
192 .resource = ehci_resources
193};
194
195static struct platform_device *sead3_platform_devices[] __initdata = {
196 &uart8250_device,
197 &sead3_flash,
198 &pled_device,
199 &fled_device,
200 &sead3_led_device,
201 &ehci_device,
202 &sead3_net_device,
203};
204
205static int __init sead3_platforms_device_init(void)
40{ 206{
41 if (gic_present) { 207 if (gic_present) {
42 uart8250_data[0].irq = MIPS_GIC_IRQ_BASE + GIC_INT_UART0; 208 uart8250_data[0].irq = MIPS_GIC_IRQ_BASE + GIC_INT_UART0;
43 uart8250_data[1].irq = MIPS_GIC_IRQ_BASE + GIC_INT_UART1; 209 uart8250_data[1].irq = MIPS_GIC_IRQ_BASE + GIC_INT_UART1;
210 ehci_resources[1].start = MIPS_GIC_IRQ_BASE + GIC_INT_EHCI;
211 sead3_net_resources[1].start = MIPS_GIC_IRQ_BASE + GIC_INT_NET;
44 } else { 212 } else {
45 uart8250_data[0].irq = MIPS_CPU_IRQ_BASE + CPU_INT_UART0; 213 uart8250_data[0].irq = MIPS_CPU_IRQ_BASE + CPU_INT_UART0;
46 uart8250_data[1].irq = MIPS_CPU_IRQ_BASE + CPU_INT_UART1; 214 uart8250_data[1].irq = MIPS_CPU_IRQ_BASE + CPU_INT_UART1;
215 ehci_resources[1].start = MIPS_CPU_IRQ_BASE + CPU_INT_EHCI;
216 sead3_net_resources[1].start = MIPS_CPU_IRQ_BASE + CPU_INT_NET;
47 } 217 }
48 return platform_device_register(&uart8250_device);
49}
50 218
51module_init(uart8250_init); 219 return platform_add_devices(sead3_platform_devices,
220 ARRAY_SIZE(sead3_platform_devices));
221}
52 222
53MODULE_AUTHOR("Chris Dearman <chris@mips.com>"); 223device_initcall(sead3_platforms_device_init);
54MODULE_LICENSE("GPL");
55MODULE_DESCRIPTION("8250 UART probe driver for SEAD3");
diff --git a/arch/mips/netlogic/Kconfig b/arch/mips/netlogic/Kconfig
index 0823321c10e0..fb00606e352d 100644
--- a/arch/mips/netlogic/Kconfig
+++ b/arch/mips/netlogic/Kconfig
@@ -41,6 +41,15 @@ config DT_XLP_GVP
41 pointer to the kernel. The corresponding DTS file is at 41 pointer to the kernel. The corresponding DTS file is at
42 arch/mips/netlogic/dts/xlp_gvp.dts 42 arch/mips/netlogic/dts/xlp_gvp.dts
43 43
44config DT_XLP_RVP
45 bool "Built-in device tree for XLP RVP boards"
46 default y
47 help
48 Add an FDT blob for XLP RVP board into the kernel.
49 This DTB will be used if the firmware does not pass in a DTB
50 pointer to the kernel. The corresponding DTS file is at
51 arch/mips/netlogic/dts/xlp_rvp.dts
52
44config NLM_MULTINODE 53config NLM_MULTINODE
45 bool "Support for multi-chip boards" 54 bool "Support for multi-chip boards"
46 depends on NLM_XLP_BOARD 55 depends on NLM_XLP_BOARD
diff --git a/arch/mips/netlogic/common/irq.c b/arch/mips/netlogic/common/irq.c
index c100b9afa0ab..5f5d18b0e94d 100644
--- a/arch/mips/netlogic/common/irq.c
+++ b/arch/mips/netlogic/common/irq.c
@@ -230,16 +230,16 @@ static void nlm_init_node_irqs(int node)
230 } 230 }
231} 231}
232 232
233void nlm_smp_irq_init(int hwcpuid) 233void nlm_smp_irq_init(int hwtid)
234{ 234{
235 int node, cpu; 235 int cpu, node;
236 236
237 node = nlm_cpuid_to_node(hwcpuid); 237 cpu = hwtid % nlm_threads_per_node();
238 cpu = hwcpuid % nlm_threads_per_node(); 238 node = hwtid / nlm_threads_per_node();
239 239
240 if (cpu == 0 && node != 0) 240 if (cpu == 0 && node != 0)
241 nlm_init_node_irqs(node); 241 nlm_init_node_irqs(node);
242 write_c0_eimr(nlm_current_node()->irqmask); 242 write_c0_eimr(nlm_get_node(node)->irqmask);
243} 243}
244 244
245asmlinkage void plat_irq_dispatch(void) 245asmlinkage void plat_irq_dispatch(void)
diff --git a/arch/mips/netlogic/common/reset.S b/arch/mips/netlogic/common/reset.S
index 701c4bcb9e47..edbab9b8691f 100644
--- a/arch/mips/netlogic/common/reset.S
+++ b/arch/mips/netlogic/common/reset.S
@@ -60,7 +60,7 @@
60 li t0, LSU_DEFEATURE 60 li t0, LSU_DEFEATURE
61 mfcr t1, t0 61 mfcr t1, t0
62 62
63 lui t2, 0xc080 /* SUE, Enable Unaligned Access, L2HPE */ 63 lui t2, 0x4080 /* Enable Unaligned Access, L2HPE */
64 or t1, t1, t2 64 or t1, t1, t2
65 mtcr t1, t0 65 mtcr t1, t0
66 66
@@ -235,6 +235,26 @@ EXPORT(nlm_boot_siblings)
235 mfc0 v0, CP0_EBASE, 1 235 mfc0 v0, CP0_EBASE, 1
236 andi v0, 0x3ff /* v0 <- node/core */ 236 andi v0, 0x3ff /* v0 <- node/core */
237 237
238 /*
239 * Errata: to avoid potential live lock, setup IFU_BRUB_RESERVE
240 * when running 4 threads per core
241 */
242 andi v1, v0, 0x3 /* v1 <- thread id */
243 bnez v1, 2f
244 nop
245
246 /* thread 0 of each core. */
247 li t0, CKSEG1ADDR(RESET_DATA_PHYS)
248 lw t1, BOOT_THREAD_MODE(t0) /* t1 <- thread mode */
249 subu t1, 0x3 /* 4-thread per core mode? */
250 bnez t1, 2f
251 nop
252
253 li t0, IFU_BRUB_RESERVE
254 li t1, 0x55
255 mtcr t1, t0
256 _ehb
2572:
238 beqz v0, 4f /* boot cpu (cpuid == 0)? */ 258 beqz v0, 4f /* boot cpu (cpuid == 0)? */
239 nop 259 nop
240 260
diff --git a/arch/mips/netlogic/common/smp.c b/arch/mips/netlogic/common/smp.c
index e743bdd6e20c..dc3e327fbbac 100644
--- a/arch/mips/netlogic/common/smp.c
+++ b/arch/mips/netlogic/common/smp.c
@@ -59,17 +59,17 @@
59 59
60void nlm_send_ipi_single(int logical_cpu, unsigned int action) 60void nlm_send_ipi_single(int logical_cpu, unsigned int action)
61{ 61{
62 int cpu, node; 62 unsigned int hwtid;
63 uint64_t picbase; 63 uint64_t picbase;
64 64
65 cpu = cpu_logical_map(logical_cpu); 65 /* node id is part of hwtid, and needed for send_ipi */
66 node = nlm_cpuid_to_node(cpu); 66 hwtid = cpu_logical_map(logical_cpu);
67 picbase = nlm_get_node(node)->picbase; 67 picbase = nlm_get_node(nlm_hwtid_to_node(hwtid))->picbase;
68 68
69 if (action & SMP_CALL_FUNCTION) 69 if (action & SMP_CALL_FUNCTION)
70 nlm_pic_send_ipi(picbase, cpu, IRQ_IPI_SMP_FUNCTION, 0); 70 nlm_pic_send_ipi(picbase, hwtid, IRQ_IPI_SMP_FUNCTION, 0);
71 if (action & SMP_RESCHEDULE_YOURSELF) 71 if (action & SMP_RESCHEDULE_YOURSELF)
72 nlm_pic_send_ipi(picbase, cpu, IRQ_IPI_SMP_RESCHEDULE, 0); 72 nlm_pic_send_ipi(picbase, hwtid, IRQ_IPI_SMP_RESCHEDULE, 0);
73} 73}
74 74
75void nlm_send_ipi_mask(const struct cpumask *mask, unsigned int action) 75void nlm_send_ipi_mask(const struct cpumask *mask, unsigned int action)
@@ -120,6 +120,7 @@ static void nlm_init_secondary(void)
120 120
121 hwtid = hard_smp_processor_id(); 121 hwtid = hard_smp_processor_id();
122 current_cpu_data.core = hwtid / NLM_THREADS_PER_CORE; 122 current_cpu_data.core = hwtid / NLM_THREADS_PER_CORE;
123 current_cpu_data.package = nlm_nodeid();
123 nlm_percpu_init(hwtid); 124 nlm_percpu_init(hwtid);
124 nlm_smp_irq_init(hwtid); 125 nlm_smp_irq_init(hwtid);
125} 126}
@@ -145,16 +146,18 @@ static cpumask_t phys_cpu_present_mask;
145 146
146void nlm_boot_secondary(int logical_cpu, struct task_struct *idle) 147void nlm_boot_secondary(int logical_cpu, struct task_struct *idle)
147{ 148{
148 int cpu, node; 149 uint64_t picbase;
150 int hwtid;
151
152 hwtid = cpu_logical_map(logical_cpu);
153 picbase = nlm_get_node(nlm_hwtid_to_node(hwtid))->picbase;
149 154
150 cpu = cpu_logical_map(logical_cpu);
151 node = nlm_cpuid_to_node(logical_cpu);
152 nlm_next_sp = (unsigned long)__KSTK_TOS(idle); 155 nlm_next_sp = (unsigned long)__KSTK_TOS(idle);
153 nlm_next_gp = (unsigned long)task_thread_info(idle); 156 nlm_next_gp = (unsigned long)task_thread_info(idle);
154 157
155 /* barrier for sp/gp store above */ 158 /* barrier for sp/gp store above */
156 __sync(); 159 __sync();
157 nlm_pic_send_ipi(nlm_get_node(node)->picbase, cpu, 1, 1); /* NMI */ 160 nlm_pic_send_ipi(picbase, hwtid, 1, 1); /* NMI */
158} 161}
159 162
160void __init nlm_smp_setup(void) 163void __init nlm_smp_setup(void)
@@ -182,7 +185,7 @@ void __init nlm_smp_setup(void)
182 __cpu_number_map[i] = num_cpus; 185 __cpu_number_map[i] = num_cpus;
183 __cpu_logical_map[num_cpus] = i; 186 __cpu_logical_map[num_cpus] = i;
184 set_cpu_possible(num_cpus, true); 187 set_cpu_possible(num_cpus, true);
185 node = nlm_cpuid_to_node(i); 188 node = nlm_hwtid_to_node(i);
186 cpumask_set_cpu(num_cpus, &nlm_get_node(node)->cpumask); 189 cpumask_set_cpu(num_cpus, &nlm_get_node(node)->cpumask);
187 ++num_cpus; 190 ++num_cpus;
188 } 191 }
diff --git a/arch/mips/netlogic/common/time.c b/arch/mips/netlogic/common/time.c
index 0c0a1a606f73..5873c83e65be 100644
--- a/arch/mips/netlogic/common/time.c
+++ b/arch/mips/netlogic/common/time.c
@@ -40,7 +40,6 @@
40#include <asm/netlogic/interrupt.h> 40#include <asm/netlogic/interrupt.h>
41#include <asm/netlogic/common.h> 41#include <asm/netlogic/common.h>
42#include <asm/netlogic/haldefs.h> 42#include <asm/netlogic/haldefs.h>
43#include <asm/netlogic/common.h>
44 43
45#if defined(CONFIG_CPU_XLP) 44#if defined(CONFIG_CPU_XLP)
46#include <asm/netlogic/xlp-hal/iomap.h> 45#include <asm/netlogic/xlp-hal/iomap.h>
diff --git a/arch/mips/netlogic/xlp/ahci-init-xlp2.c b/arch/mips/netlogic/xlp/ahci-init-xlp2.c
index c83dbf3689e2..7b066a44e679 100644
--- a/arch/mips/netlogic/xlp/ahci-init-xlp2.c
+++ b/arch/mips/netlogic/xlp/ahci-init-xlp2.c
@@ -203,6 +203,7 @@ static u8 read_phy_reg(u64 regbase, u32 addr, u32 physel)
203static void config_sata_phy(u64 regbase) 203static void config_sata_phy(u64 regbase)
204{ 204{
205 u32 port, i, reg; 205 u32 port, i, reg;
206 u8 val;
206 207
207 for (port = 0; port < 2; port++) { 208 for (port = 0; port < 2; port++) {
208 for (i = 0, reg = RXCDRCALFOSC0; reg <= CALDUTY; reg++, i++) 209 for (i = 0, reg = RXCDRCALFOSC0; reg <= CALDUTY; reg++, i++)
@@ -210,6 +211,18 @@ static void config_sata_phy(u64 regbase)
210 211
211 for (i = 0, reg = RXDPIF; reg <= PPMDRIFTMAX_HI; reg++, i++) 212 for (i = 0, reg = RXDPIF; reg <= PPMDRIFTMAX_HI; reg++, i++)
212 write_phy_reg(regbase, reg, port, sata_phy_config2[i]); 213 write_phy_reg(regbase, reg, port, sata_phy_config2[i]);
214
215 /* Fix for PHY link up failures at lower temperatures */
216 write_phy_reg(regbase, 0x800F, port, 0x1f);
217
218 val = read_phy_reg(regbase, 0x0029, port);
219 write_phy_reg(regbase, 0x0029, port, val | (0x7 << 1));
220
221 val = read_phy_reg(regbase, 0x0056, port);
222 write_phy_reg(regbase, 0x0056, port, val & ~(1 << 3));
223
224 val = read_phy_reg(regbase, 0x0018, port);
225 write_phy_reg(regbase, 0x0018, port, val & ~(0x7 << 0));
213 } 226 }
214} 227}
215 228
diff --git a/arch/mips/netlogic/xlp/ahci-init.c b/arch/mips/netlogic/xlp/ahci-init.c
index a9d0fae02103..92be1a3258b1 100644
--- a/arch/mips/netlogic/xlp/ahci-init.c
+++ b/arch/mips/netlogic/xlp/ahci-init.c
@@ -151,7 +151,7 @@ static void nlm_sata_firmware_init(int node)
151static int __init nlm_ahci_init(void) 151static int __init nlm_ahci_init(void)
152{ 152{
153 int node = 0; 153 int node = 0;
154 int chip = read_c0_prid() & PRID_REV_MASK; 154 int chip = read_c0_prid() & PRID_IMP_MASK;
155 155
156 if (chip == PRID_IMP_NETLOGIC_XLP3XX) 156 if (chip == PRID_IMP_NETLOGIC_XLP3XX)
157 nlm_sata_firmware_init(node); 157 nlm_sata_firmware_init(node);
diff --git a/arch/mips/netlogic/xlp/dt.c b/arch/mips/netlogic/xlp/dt.c
index 7cc46032b28e..a625bdb6d6aa 100644
--- a/arch/mips/netlogic/xlp/dt.c
+++ b/arch/mips/netlogic/xlp/dt.c
@@ -41,17 +41,21 @@
41 41
42#include <asm/prom.h> 42#include <asm/prom.h>
43 43
44extern u32 __dtb_xlp_evp_begin[], __dtb_xlp_svp_begin[], 44extern u32 __dtb_xlp_evp_begin[], __dtb_xlp_svp_begin[], __dtb_xlp_fvp_begin[],
45 __dtb_xlp_fvp_begin[], __dtb_xlp_gvp_begin[]; 45 __dtb_xlp_gvp_begin[], __dtb_xlp_rvp_begin[];
46static void *xlp_fdt_blob; 46static void *xlp_fdt_blob;
47 47
48void __init *xlp_dt_init(void *fdtp) 48void __init *xlp_dt_init(void *fdtp)
49{ 49{
50 if (!fdtp) { 50 if (!fdtp) {
51 switch (current_cpu_data.processor_id & PRID_IMP_MASK) { 51 switch (current_cpu_data.processor_id & PRID_IMP_MASK) {
52#ifdef CONFIG_DT_XLP_RVP
53 case PRID_IMP_NETLOGIC_XLP5XX:
54 fdtp = __dtb_xlp_rvp_begin;
55 break;
56#endif
52#ifdef CONFIG_DT_XLP_GVP 57#ifdef CONFIG_DT_XLP_GVP
53 case PRID_IMP_NETLOGIC_XLP9XX: 58 case PRID_IMP_NETLOGIC_XLP9XX:
54 case PRID_IMP_NETLOGIC_XLP5XX:
55 fdtp = __dtb_xlp_gvp_begin; 59 fdtp = __dtb_xlp_gvp_begin;
56 break; 60 break;
57#endif 61#endif
diff --git a/arch/mips/netlogic/xlp/nlm_hal.c b/arch/mips/netlogic/xlp/nlm_hal.c
index bc24beb3a426..a8f4144a0297 100644
--- a/arch/mips/netlogic/xlp/nlm_hal.c
+++ b/arch/mips/netlogic/xlp/nlm_hal.c
@@ -71,10 +71,20 @@ static int xlp9xx_irq_to_irt(int irq)
71 switch (irq) { 71 switch (irq) {
72 case PIC_GPIO_IRQ: 72 case PIC_GPIO_IRQ:
73 return 12; 73 return 12;
74 case PIC_I2C_0_IRQ:
75 return 125;
76 case PIC_I2C_1_IRQ:
77 return 126;
78 case PIC_I2C_2_IRQ:
79 return 127;
80 case PIC_I2C_3_IRQ:
81 return 128;
74 case PIC_9XX_XHCI_0_IRQ: 82 case PIC_9XX_XHCI_0_IRQ:
75 return 114; 83 return 114;
76 case PIC_9XX_XHCI_1_IRQ: 84 case PIC_9XX_XHCI_1_IRQ:
77 return 115; 85 return 115;
86 case PIC_9XX_XHCI_2_IRQ:
87 return 116;
78 case PIC_UART_0_IRQ: 88 case PIC_UART_0_IRQ:
79 return 133; 89 return 133;
80 case PIC_UART_1_IRQ: 90 case PIC_UART_1_IRQ:
@@ -170,16 +180,23 @@ static int xlp_irq_to_irt(int irq)
170 } 180 }
171 181
172 if (devoff != 0) { 182 if (devoff != 0) {
183 uint32_t val;
184
173 pcibase = nlm_pcicfg_base(devoff); 185 pcibase = nlm_pcicfg_base(devoff);
174 irt = nlm_read_reg(pcibase, XLP_PCI_IRTINFO_REG) & 0xffff; 186 val = nlm_read_reg(pcibase, XLP_PCI_IRTINFO_REG);
175 /* HW weirdness, I2C IRT entry has to be fixed up */ 187 if (val == 0xffffffff) {
176 switch (irq) { 188 irt = -1;
177 case PIC_I2C_1_IRQ: 189 } else {
178 irt = irt + 1; break; 190 irt = val & 0xffff;
179 case PIC_I2C_2_IRQ: 191 /* HW weirdness, I2C IRT entry has to be fixed up */
180 irt = irt + 2; break; 192 switch (irq) {
181 case PIC_I2C_3_IRQ: 193 case PIC_I2C_1_IRQ:
182 irt = irt + 3; break; 194 irt = irt + 1; break;
195 case PIC_I2C_2_IRQ:
196 irt = irt + 2; break;
197 case PIC_I2C_3_IRQ:
198 irt = irt + 3; break;
199 }
183 } 200 }
184 } else if (irq >= PIC_PCIE_LINK_LEGACY_IRQ(0) && 201 } else if (irq >= PIC_PCIE_LINK_LEGACY_IRQ(0) &&
185 irq <= PIC_PCIE_LINK_LEGACY_IRQ(3)) { 202 irq <= PIC_PCIE_LINK_LEGACY_IRQ(3)) {
@@ -325,7 +342,7 @@ static unsigned int nlm_xlp2_get_pic_frequency(int node)
325 /* Find the clock source PLL device for PIC */ 342 /* Find the clock source PLL device for PIC */
326 if (cpu_xlp9xx) { 343 if (cpu_xlp9xx) {
327 reg_select = nlm_read_sys_reg(clockbase, 344 reg_select = nlm_read_sys_reg(clockbase,
328 SYS_9XX_CLK_DEV_SEL) & 0x3; 345 SYS_9XX_CLK_DEV_SEL_REG) & 0x3;
329 switch (reg_select) { 346 switch (reg_select) {
330 case 0: 347 case 0:
331 ctrl_val0 = nlm_read_sys_reg(clockbase, 348 ctrl_val0 = nlm_read_sys_reg(clockbase,
@@ -354,7 +371,7 @@ static unsigned int nlm_xlp2_get_pic_frequency(int node)
354 } 371 }
355 } else { 372 } else {
356 reg_select = (nlm_read_sys_reg(sysbase, 373 reg_select = (nlm_read_sys_reg(sysbase,
357 SYS_CLK_DEV_SEL) >> 22) & 0x3; 374 SYS_CLK_DEV_SEL_REG) >> 22) & 0x3;
358 switch (reg_select) { 375 switch (reg_select) {
359 case 0: 376 case 0:
360 ctrl_val0 = nlm_read_sys_reg(sysbase, 377 ctrl_val0 = nlm_read_sys_reg(sysbase,
@@ -410,7 +427,7 @@ static unsigned int nlm_xlp2_get_pic_frequency(int node)
410 427
411 fdiv = fdiv/(1 << 13); 428 fdiv = fdiv/(1 << 13);
412 pll_out_freq_num = ((ref_clk >> 1) * (6 + mdiv)) + fdiv; 429 pll_out_freq_num = ((ref_clk >> 1) * (6 + mdiv)) + fdiv;
413 pll_out_freq_den = (1 << vco_post_div) * pll_post_div * 3; 430 pll_out_freq_den = (1 << vco_post_div) * pll_post_div * ref_div;
414 431
415 if (pll_out_freq_den > 0) 432 if (pll_out_freq_den > 0)
416 do_div(pll_out_freq_num, pll_out_freq_den); 433 do_div(pll_out_freq_num, pll_out_freq_den);
@@ -418,10 +435,10 @@ static unsigned int nlm_xlp2_get_pic_frequency(int node)
418 /* PIC post divider, which happens after PLL */ 435 /* PIC post divider, which happens after PLL */
419 if (cpu_xlp9xx) 436 if (cpu_xlp9xx)
420 pic_div = nlm_read_sys_reg(clockbase, 437 pic_div = nlm_read_sys_reg(clockbase,
421 SYS_9XX_CLK_DEV_DIV) & 0x3; 438 SYS_9XX_CLK_DEV_DIV_REG) & 0x3;
422 else 439 else
423 pic_div = (nlm_read_sys_reg(sysbase, 440 pic_div = (nlm_read_sys_reg(sysbase,
424 SYS_CLK_DEV_DIV) >> 22) & 0x3; 441 SYS_CLK_DEV_DIV_REG) >> 22) & 0x3;
425 do_div(pll_out_freq_num, 1 << pic_div); 442 do_div(pll_out_freq_num, 1 << pic_div);
426 443
427 return pll_out_freq_num; 444 return pll_out_freq_num;
@@ -442,19 +459,21 @@ unsigned int nlm_get_cpu_frequency(void)
442 459
443/* 460/*
444 * Fills upto 8 pairs of entries containing the DRAM map of a node 461 * Fills upto 8 pairs of entries containing the DRAM map of a node
445 * if n < 0, get dram map for all nodes 462 * if node < 0, get dram map for all nodes
446 */ 463 */
447int xlp_get_dram_map(int n, uint64_t *dram_map) 464int nlm_get_dram_map(int node, uint64_t *dram_map, int nentries)
448{ 465{
449 uint64_t bridgebase, base, lim; 466 uint64_t bridgebase, base, lim;
450 uint32_t val; 467 uint32_t val;
451 unsigned int barreg, limreg, xlatreg; 468 unsigned int barreg, limreg, xlatreg;
452 int i, node, rv; 469 int i, n, rv;
453 470
454 /* Look only at mapping on Node 0, we don't handle crazy configs */ 471 /* Look only at mapping on Node 0, we don't handle crazy configs */
455 bridgebase = nlm_get_bridge_regbase(0); 472 bridgebase = nlm_get_bridge_regbase(0);
456 rv = 0; 473 rv = 0;
457 for (i = 0; i < 8; i++) { 474 for (i = 0; i < 8; i++) {
475 if (rv + 1 >= nentries)
476 break;
458 if (cpu_is_xlp9xx()) { 477 if (cpu_is_xlp9xx()) {
459 barreg = BRIDGE_9XX_DRAM_BAR(i); 478 barreg = BRIDGE_9XX_DRAM_BAR(i);
460 limreg = BRIDGE_9XX_DRAM_LIMIT(i); 479 limreg = BRIDGE_9XX_DRAM_LIMIT(i);
@@ -464,10 +483,10 @@ int xlp_get_dram_map(int n, uint64_t *dram_map)
464 limreg = BRIDGE_DRAM_LIMIT(i); 483 limreg = BRIDGE_DRAM_LIMIT(i);
465 xlatreg = BRIDGE_DRAM_NODE_TRANSLN(i); 484 xlatreg = BRIDGE_DRAM_NODE_TRANSLN(i);
466 } 485 }
467 if (n >= 0) { 486 if (node >= 0) {
468 /* node specified, get node mapping of BAR */ 487 /* node specified, get node mapping of BAR */
469 val = nlm_read_bridge_reg(bridgebase, xlatreg); 488 val = nlm_read_bridge_reg(bridgebase, xlatreg);
470 node = (val >> 1) & 0x3; 489 n = (val >> 1) & 0x3;
471 if (n != node) 490 if (n != node)
472 continue; 491 continue;
473 } 492 }
diff --git a/arch/mips/netlogic/xlp/setup.c b/arch/mips/netlogic/xlp/setup.c
index 4fdd9fd29d1d..f743fd9da323 100644
--- a/arch/mips/netlogic/xlp/setup.c
+++ b/arch/mips/netlogic/xlp/setup.c
@@ -51,7 +51,6 @@ uint64_t nlm_io_base;
51struct nlm_soc_info nlm_nodes[NLM_NR_NODES]; 51struct nlm_soc_info nlm_nodes[NLM_NR_NODES];
52cpumask_t nlm_cpumask = CPU_MASK_CPU0; 52cpumask_t nlm_cpumask = CPU_MASK_CPU0;
53unsigned int nlm_threads_per_core; 53unsigned int nlm_threads_per_core;
54unsigned int xlp_cores_per_node;
55 54
56static void nlm_linux_exit(void) 55static void nlm_linux_exit(void)
57{ 56{
@@ -82,7 +81,7 @@ static void __init xlp_init_mem_from_bars(void)
82 uint64_t map[16]; 81 uint64_t map[16];
83 int i, n; 82 int i, n;
84 83
85 n = xlp_get_dram_map(-1, map); /* -1: info for all nodes */ 84 n = nlm_get_dram_map(-1, map, ARRAY_SIZE(map)); /* -1 : all nodes */
86 for (i = 0; i < n; i += 2) { 85 for (i = 0; i < n; i += 2) {
87 /* exclude 0x1000_0000-0x2000_0000, u-boot device */ 86 /* exclude 0x1000_0000-0x2000_0000, u-boot device */
88 if (map[i] <= 0x10000000 && map[i+1] > 0x10000000) 87 if (map[i] <= 0x10000000 && map[i+1] > 0x10000000)
@@ -163,10 +162,6 @@ void __init prom_init(void)
163 void *reset_vec; 162 void *reset_vec;
164 163
165 nlm_io_base = CKSEG1ADDR(XLP_DEFAULT_IO_BASE); 164 nlm_io_base = CKSEG1ADDR(XLP_DEFAULT_IO_BASE);
166 if (cpu_is_xlp9xx())
167 xlp_cores_per_node = 32;
168 else
169 xlp_cores_per_node = 8;
170 nlm_init_boot_cpu(); 165 nlm_init_boot_cpu();
171 xlp_mmu_init(); 166 xlp_mmu_init();
172 nlm_node_init(0); 167 nlm_node_init(0);
diff --git a/arch/mips/netlogic/xlp/usb-init-xlp2.c b/arch/mips/netlogic/xlp/usb-init-xlp2.c
index 17ade1ce5dfd..2524939a5e3a 100644
--- a/arch/mips/netlogic/xlp/usb-init-xlp2.c
+++ b/arch/mips/netlogic/xlp/usb-init-xlp2.c
@@ -128,6 +128,9 @@ static void xlp9xx_usb_ack(struct irq_data *data)
128 case PIC_9XX_XHCI_1_IRQ: 128 case PIC_9XX_XHCI_1_IRQ:
129 port_addr = nlm_xlpii_get_usb_regbase(node, 2); 129 port_addr = nlm_xlpii_get_usb_regbase(node, 2);
130 break; 130 break;
131 case PIC_9XX_XHCI_2_IRQ:
132 port_addr = nlm_xlpii_get_usb_regbase(node, 3);
133 break;
131 default: 134 default:
132 pr_err("No matching USB irq %d node %d!\n", irq, node); 135 pr_err("No matching USB irq %d node %d!\n", irq, node);
133 return; 136 return;
@@ -222,14 +225,16 @@ static int __init nlm_platform_xlpii_usb_init(void)
222 } 225 }
223 226
224 /* XLP 9XX, multi-node */ 227 /* XLP 9XX, multi-node */
225 pr_info("Initializing 9XX USB Interface\n"); 228 pr_info("Initializing 9XX/5XX USB Interface\n");
226 for (node = 0; node < NLM_NR_NODES; node++) { 229 for (node = 0; node < NLM_NR_NODES; node++) {
227 if (!nlm_node_present(node)) 230 if (!nlm_node_present(node))
228 continue; 231 continue;
229 nlm_xlpii_usb_hw_reset(node, 1); 232 nlm_xlpii_usb_hw_reset(node, 1);
230 nlm_xlpii_usb_hw_reset(node, 2); 233 nlm_xlpii_usb_hw_reset(node, 2);
234 nlm_xlpii_usb_hw_reset(node, 3);
231 nlm_set_pic_extra_ack(node, PIC_9XX_XHCI_0_IRQ, xlp9xx_usb_ack); 235 nlm_set_pic_extra_ack(node, PIC_9XX_XHCI_0_IRQ, xlp9xx_usb_ack);
232 nlm_set_pic_extra_ack(node, PIC_9XX_XHCI_1_IRQ, xlp9xx_usb_ack); 236 nlm_set_pic_extra_ack(node, PIC_9XX_XHCI_1_IRQ, xlp9xx_usb_ack);
237 nlm_set_pic_extra_ack(node, PIC_9XX_XHCI_2_IRQ, xlp9xx_usb_ack);
233 } 238 }
234 return 0; 239 return 0;
235} 240}
@@ -253,6 +258,9 @@ static void nlm_xlp9xx_usb_fixup_final(struct pci_dev *dev)
253 case 0x22: 258 case 0x22:
254 dev->irq = nlm_irq_to_xirq(node, PIC_9XX_XHCI_1_IRQ); 259 dev->irq = nlm_irq_to_xirq(node, PIC_9XX_XHCI_1_IRQ);
255 break; 260 break;
261 case 0x23:
262 dev->irq = nlm_irq_to_xirq(node, PIC_9XX_XHCI_2_IRQ);
263 break;
256 } 264 }
257} 265}
258 266
diff --git a/arch/mips/netlogic/xlp/wakeup.c b/arch/mips/netlogic/xlp/wakeup.c
index e5f44d2605a8..87d7846af2d0 100644
--- a/arch/mips/netlogic/xlp/wakeup.c
+++ b/arch/mips/netlogic/xlp/wakeup.c
@@ -99,7 +99,7 @@ static int wait_for_cpus(int cpu, int bootcpu)
99 do { 99 do {
100 notready = nlm_threads_per_core; 100 notready = nlm_threads_per_core;
101 for (i = 0; i < nlm_threads_per_core; i++) 101 for (i = 0; i < nlm_threads_per_core; i++)
102 if (cpu_ready[cpu + i] || cpu == bootcpu) 102 if (cpu_ready[cpu + i] || (cpu + i) == bootcpu)
103 --notready; 103 --notready;
104 } while (notready != 0 && --count > 0); 104 } while (notready != 0 && --count > 0);
105 105
@@ -111,7 +111,7 @@ static void xlp_enable_secondary_cores(const cpumask_t *wakeup_mask)
111 struct nlm_soc_info *nodep; 111 struct nlm_soc_info *nodep;
112 uint64_t syspcibase, fusebase; 112 uint64_t syspcibase, fusebase;
113 uint32_t syscoremask, mask, fusemask; 113 uint32_t syscoremask, mask, fusemask;
114 int core, n, cpu; 114 int core, n, cpu, ncores;
115 115
116 for (n = 0; n < NLM_NR_NODES; n++) { 116 for (n = 0; n < NLM_NR_NODES; n++) {
117 if (n != 0) { 117 if (n != 0) {
@@ -168,7 +168,8 @@ static void xlp_enable_secondary_cores(const cpumask_t *wakeup_mask)
168 syscoremask = (1 << hweight32(~fusemask & mask)) - 1; 168 syscoremask = (1 << hweight32(~fusemask & mask)) - 1;
169 169
170 pr_info("Node %d - SYS/FUSE coremask %x\n", n, syscoremask); 170 pr_info("Node %d - SYS/FUSE coremask %x\n", n, syscoremask);
171 for (core = 0; core < nlm_cores_per_node(); core++) { 171 ncores = nlm_cores_per_node();
172 for (core = 0; core < ncores; core++) {
172 /* we will be on node 0 core 0 */ 173 /* we will be on node 0 core 0 */
173 if (n == 0 && core == 0) 174 if (n == 0 && core == 0)
174 continue; 175 continue;
@@ -178,8 +179,7 @@ static void xlp_enable_secondary_cores(const cpumask_t *wakeup_mask)
178 continue; 179 continue;
179 180
180 /* see if at least the first hw thread is enabled */ 181 /* see if at least the first hw thread is enabled */
181 cpu = (n * nlm_cores_per_node() + core) 182 cpu = (n * ncores + core) * NLM_THREADS_PER_CORE;
182 * NLM_THREADS_PER_CORE;
183 if (!cpumask_test_cpu(cpu, wakeup_mask)) 183 if (!cpumask_test_cpu(cpu, wakeup_mask))
184 continue; 184 continue;
185 185
diff --git a/arch/mips/oprofile/common.c b/arch/mips/oprofile/common.c
index a26cbe372e06..81f58958cf08 100644
--- a/arch/mips/oprofile/common.c
+++ b/arch/mips/oprofile/common.c
@@ -98,6 +98,7 @@ int __init oprofile_arch_init(struct oprofile_operations *ops)
98 case CPU_R10000: 98 case CPU_R10000:
99 case CPU_R12000: 99 case CPU_R12000:
100 case CPU_R14000: 100 case CPU_R14000:
101 case CPU_R16000:
101 case CPU_XLR: 102 case CPU_XLR:
102 lmodel = &op_model_mipsxx_ops; 103 lmodel = &op_model_mipsxx_ops;
103 break; 104 break;
diff --git a/arch/mips/oprofile/op_model_mipsxx.c b/arch/mips/oprofile/op_model_mipsxx.c
index 01f721a85c5b..6a6e2cc55b89 100644
--- a/arch/mips/oprofile/op_model_mipsxx.c
+++ b/arch/mips/oprofile/op_model_mipsxx.c
@@ -246,7 +246,7 @@ static int mipsxx_perfcount_handler(void)
246 unsigned int counter; 246 unsigned int counter;
247 int handled = IRQ_NONE; 247 int handled = IRQ_NONE;
248 248
249 if (cpu_has_mips_r2 && !(read_c0_cause() & (1 << 26))) 249 if (cpu_has_mips_r2 && !(read_c0_cause() & CAUSEF_PCI))
250 return handled; 250 return handled;
251 251
252 switch (counters) { 252 switch (counters) {
@@ -296,6 +296,7 @@ static inline int n_counters(void)
296 296
297 case CPU_R12000: 297 case CPU_R12000:
298 case CPU_R14000: 298 case CPU_R14000:
299 case CPU_R16000:
299 counters = 4; 300 counters = 4;
300 break; 301 break;
301 302
@@ -411,6 +412,10 @@ static int __init mipsxx_init(void)
411 op_model_mipsxx_ops.cpu_type = "mips/r12000"; 412 op_model_mipsxx_ops.cpu_type = "mips/r12000";
412 break; 413 break;
413 414
415 case CPU_R16000:
416 op_model_mipsxx_ops.cpu_type = "mips/r16000";
417 break;
418
414 case CPU_SB1: 419 case CPU_SB1:
415 case CPU_SB1A: 420 case CPU_SB1A:
416 op_model_mipsxx_ops.cpu_type = "mips/sb1"; 421 op_model_mipsxx_ops.cpu_type = "mips/sb1";
@@ -435,15 +440,17 @@ static int __init mipsxx_init(void)
435 440
436 if (get_c0_perfcount_int) 441 if (get_c0_perfcount_int)
437 perfcount_irq = get_c0_perfcount_int(); 442 perfcount_irq = get_c0_perfcount_int();
438 else if ((cp0_perfcount_irq >= 0) && 443 else if (cp0_perfcount_irq >= 0)
439 (cp0_compare_irq != cp0_perfcount_irq))
440 perfcount_irq = MIPS_CPU_IRQ_BASE + cp0_perfcount_irq; 444 perfcount_irq = MIPS_CPU_IRQ_BASE + cp0_perfcount_irq;
441 else 445 else
442 perfcount_irq = -1; 446 perfcount_irq = -1;
443 447
444 if (perfcount_irq >= 0) 448 if (perfcount_irq >= 0)
445 return request_irq(perfcount_irq, mipsxx_perfcount_int, 449 return request_irq(perfcount_irq, mipsxx_perfcount_int,
446 0, "Perfcounter", save_perf_irq); 450 IRQF_PERCPU | IRQF_NOBALANCING |
451 IRQF_NO_THREAD | IRQF_NO_SUSPEND |
452 IRQF_SHARED,
453 "Perfcounter", save_perf_irq);
447 454
448 return 0; 455 return 0;
449} 456}
diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile
index 300591c6278d..2eda01e6e08f 100644
--- a/arch/mips/pci/Makefile
+++ b/arch/mips/pci/Makefile
@@ -43,7 +43,7 @@ obj-$(CONFIG_SIBYTE_BCM1x80) += pci-bcm1480.o pci-bcm1480ht.o
43obj-$(CONFIG_SNI_RM) += fixup-sni.o ops-sni.o 43obj-$(CONFIG_SNI_RM) += fixup-sni.o ops-sni.o
44obj-$(CONFIG_LANTIQ) += fixup-lantiq.o 44obj-$(CONFIG_LANTIQ) += fixup-lantiq.o
45obj-$(CONFIG_PCI_LANTIQ) += pci-lantiq.o ops-lantiq.o 45obj-$(CONFIG_PCI_LANTIQ) += pci-lantiq.o ops-lantiq.o
46obj-$(CONFIG_SOC_RT2880) += pci-rt2880.o 46obj-$(CONFIG_SOC_RT288X) += pci-rt2880.o
47obj-$(CONFIG_SOC_RT3883) += pci-rt3883.o 47obj-$(CONFIG_SOC_RT3883) += pci-rt3883.o
48obj-$(CONFIG_TANBAC_TB0219) += fixup-tb0219.o 48obj-$(CONFIG_TANBAC_TB0219) += fixup-tb0219.o
49obj-$(CONFIG_TANBAC_TB0226) += fixup-tb0226.o 49obj-$(CONFIG_TANBAC_TB0226) += fixup-tb0226.o
diff --git a/arch/mips/pci/msi-xlp.c b/arch/mips/pci/msi-xlp.c
index 6a40f24c91b4..3407495fcbe2 100644
--- a/arch/mips/pci/msi-xlp.c
+++ b/arch/mips/pci/msi-xlp.c
@@ -178,13 +178,6 @@ static void xlp_msi_mask_ack(struct irq_data *d)
178 else 178 else
179 nlm_write_reg(md->lnkbase, PCIE_MSI_STATUS, 1u << vec); 179 nlm_write_reg(md->lnkbase, PCIE_MSI_STATUS, 1u << vec);
180 180
181 /* Ack at eirr and PIC */
182 ack_c0_eirr(PIC_PCIE_LINK_MSI_IRQ(link));
183 if (cpu_is_xlp9xx())
184 nlm_pic_ack(md->node->picbase,
185 PIC_9XX_IRT_PCIE_LINK_INDEX(link));
186 else
187 nlm_pic_ack(md->node->picbase, PIC_IRT_PCIE_LINK_INDEX(link));
188} 181}
189 182
190static struct irq_chip xlp_msi_chip = { 183static struct irq_chip xlp_msi_chip = {
@@ -230,8 +223,6 @@ static void xlp_msix_mask_ack(struct irq_data *d)
230 } 223 }
231 nlm_write_reg(md->lnkbase, status_reg, 1u << bit); 224 nlm_write_reg(md->lnkbase, status_reg, 1u << bit);
232 225
233 /* Ack at eirr and PIC */
234 ack_c0_eirr(PIC_PCIE_MSIX_IRQ(link));
235 if (!cpu_is_xlp9xx()) 226 if (!cpu_is_xlp9xx())
236 nlm_pic_ack(md->node->picbase, 227 nlm_pic_ack(md->node->picbase,
237 PIC_IRT_PCIE_MSIX_INDEX(msixvec)); 228 PIC_IRT_PCIE_MSIX_INDEX(msixvec));
@@ -541,6 +532,14 @@ void nlm_dispatch_msi(int node, int lirq)
541 do_IRQ(irqbase + i); 532 do_IRQ(irqbase + i);
542 status &= status - 1; 533 status &= status - 1;
543 } 534 }
535
536 /* Ack at eirr and PIC */
537 ack_c0_eirr(PIC_PCIE_LINK_MSI_IRQ(link));
538 if (cpu_is_xlp9xx())
539 nlm_pic_ack(md->node->picbase,
540 PIC_9XX_IRT_PCIE_LINK_INDEX(link));
541 else
542 nlm_pic_ack(md->node->picbase, PIC_IRT_PCIE_LINK_INDEX(link));
544} 543}
545 544
546void nlm_dispatch_msix(int node, int lirq) 545void nlm_dispatch_msix(int node, int lirq)
@@ -567,4 +566,6 @@ void nlm_dispatch_msix(int node, int lirq)
567 do_IRQ(irqbase + i); 566 do_IRQ(irqbase + i);
568 status &= status - 1; 567 status &= status - 1;
569 } 568 }
569 /* Ack at eirr and PIC */
570 ack_c0_eirr(PIC_PCIE_MSIX_IRQ(link));
570} 571}
diff --git a/arch/mips/pci/pci-ar2315.c b/arch/mips/pci/pci-ar2315.c
index bd2b3b60da83..07a18228e63a 100644
--- a/arch/mips/pci/pci-ar2315.c
+++ b/arch/mips/pci/pci-ar2315.c
@@ -488,7 +488,6 @@ static struct platform_driver ar2315_pci_driver = {
488 .probe = ar2315_pci_probe, 488 .probe = ar2315_pci_probe,
489 .driver = { 489 .driver = {
490 .name = "ar2315-pci", 490 .name = "ar2315-pci",
491 .owner = THIS_MODULE,
492 }, 491 },
493}; 492};
494 493
diff --git a/arch/mips/pci/pci-octeon.c b/arch/mips/pci/pci-octeon.c
index a04af55d89f1..c258cd406fbb 100644
--- a/arch/mips/pci/pci-octeon.c
+++ b/arch/mips/pci/pci-octeon.c
@@ -214,6 +214,8 @@ const char *octeon_get_pci_interrupts(void)
214 return "AAABAAAAAAAAAAAAAAAAAAAAAAAAAAAA"; 214 return "AAABAAAAAAAAAAAAAAAAAAAAAAAAAAAA";
215 case CVMX_BOARD_TYPE_BBGW_REF: 215 case CVMX_BOARD_TYPE_BBGW_REF:
216 return "AABCD"; 216 return "AABCD";
217 case CVMX_BOARD_TYPE_CUST_DSR1000N:
218 return "CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC";
217 case CVMX_BOARD_TYPE_THUNDER: 219 case CVMX_BOARD_TYPE_THUNDER:
218 case CVMX_BOARD_TYPE_EBH3000: 220 case CVMX_BOARD_TYPE_EBH3000:
219 default: 221 default:
@@ -271,9 +273,6 @@ static int octeon_read_config(struct pci_bus *bus, unsigned int devfn,
271 pci_addr.s.func = devfn & 0x7; 273 pci_addr.s.func = devfn & 0x7;
272 pci_addr.s.reg = reg; 274 pci_addr.s.reg = reg;
273 275
274#if PCI_CONFIG_SPACE_DELAY
275 udelay(PCI_CONFIG_SPACE_DELAY);
276#endif
277 switch (size) { 276 switch (size) {
278 case 4: 277 case 4:
279 *val = le32_to_cpu(cvmx_read64_uint32(pci_addr.u64)); 278 *val = le32_to_cpu(cvmx_read64_uint32(pci_addr.u64));
@@ -308,9 +307,6 @@ static int octeon_write_config(struct pci_bus *bus, unsigned int devfn,
308 pci_addr.s.func = devfn & 0x7; 307 pci_addr.s.func = devfn & 0x7;
309 pci_addr.s.reg = reg; 308 pci_addr.s.reg = reg;
310 309
311#if PCI_CONFIG_SPACE_DELAY
312 udelay(PCI_CONFIG_SPACE_DELAY);
313#endif
314 switch (size) { 310 switch (size) {
315 case 4: 311 case 4:
316 cvmx_write64_uint32(pci_addr.u64, cpu_to_le32(val)); 312 cvmx_write64_uint32(pci_addr.u64, cpu_to_le32(val));
diff --git a/arch/mips/pci/pci-rt2880.c b/arch/mips/pci/pci-rt2880.c
index a4574947e698..8a978022630b 100644
--- a/arch/mips/pci/pci-rt2880.c
+++ b/arch/mips/pci/pci-rt2880.c
@@ -267,7 +267,6 @@ static struct platform_driver rt288x_pci_driver = {
267 .probe = rt288x_pci_probe, 267 .probe = rt288x_pci_probe,
268 .driver = { 268 .driver = {
269 .name = "rt288x-pci", 269 .name = "rt288x-pci",
270 .owner = THIS_MODULE,
271 .of_match_table = rt288x_pci_match, 270 .of_match_table = rt288x_pci_match,
272 }, 271 },
273}; 272};
diff --git a/arch/mips/pci/pci.c b/arch/mips/pci/pci.c
index 8bb13a4af68a..b8a0bf5766f2 100644
--- a/arch/mips/pci/pci.c
+++ b/arch/mips/pci/pci.c
@@ -91,7 +91,10 @@ static void pcibios_scanbus(struct pci_controller *hose)
91 91
92 pci_add_resource_offset(&resources, 92 pci_add_resource_offset(&resources,
93 hose->mem_resource, hose->mem_offset); 93 hose->mem_resource, hose->mem_offset);
94 pci_add_resource_offset(&resources, hose->io_resource, hose->io_offset); 94 pci_add_resource_offset(&resources,
95 hose->io_resource, hose->io_offset);
96 pci_add_resource_offset(&resources,
97 hose->busn_resource, hose->busn_offset);
95 bus = pci_scan_root_bus(NULL, next_busno, hose->pci_ops, hose, 98 bus = pci_scan_root_bus(NULL, next_busno, hose->pci_ops, hose,
96 &resources); 99 &resources);
97 hose->bus = bus; 100 hose->bus = bus;
diff --git a/arch/mips/pci/pcie-octeon.c b/arch/mips/pci/pcie-octeon.c
index 1bb0b2bf8d6e..99f3db4f0a9b 100644
--- a/arch/mips/pci/pcie-octeon.c
+++ b/arch/mips/pci/pcie-octeon.c
@@ -1762,14 +1762,6 @@ static int octeon_pcie_write_config(unsigned int pcie_port, struct pci_bus *bus,
1762 default: 1762 default:
1763 return PCIBIOS_FUNC_NOT_SUPPORTED; 1763 return PCIBIOS_FUNC_NOT_SUPPORTED;
1764 } 1764 }
1765#if PCI_CONFIG_SPACE_DELAY
1766 /*
1767 * Delay on writes so that devices have time to come up. Some
1768 * bridges need this to allow time for the secondary busses to
1769 * work
1770 */
1771 udelay(PCI_CONFIG_SPACE_DELAY);
1772#endif
1773 return PCIBIOS_SUCCESSFUL; 1765 return PCIBIOS_SUCCESSFUL;
1774} 1766}
1775 1767
diff --git a/arch/mips/pistachio/Makefile b/arch/mips/pistachio/Makefile
new file mode 100644
index 000000000000..32189c6ebea5
--- /dev/null
+++ b/arch/mips/pistachio/Makefile
@@ -0,0 +1 @@
obj-y += init.o irq.o time.o
diff --git a/arch/mips/pistachio/Platform b/arch/mips/pistachio/Platform
new file mode 100644
index 000000000000..d80cd612df1f
--- /dev/null
+++ b/arch/mips/pistachio/Platform
@@ -0,0 +1,8 @@
1#
2# IMG Pistachio SoC
3#
4platform-$(CONFIG_MACH_PISTACHIO) += pistachio/
5cflags-$(CONFIG_MACH_PISTACHIO) += \
6 -I$(srctree)/arch/mips/include/asm/mach-pistachio
7load-$(CONFIG_MACH_PISTACHIO) += 0xffffffff80400000
8zload-$(CONFIG_MACH_PISTACHIO) += 0xffffffff81000000
diff --git a/arch/mips/pistachio/init.c b/arch/mips/pistachio/init.c
new file mode 100644
index 000000000000..d2dc836523a3
--- /dev/null
+++ b/arch/mips/pistachio/init.c
@@ -0,0 +1,131 @@
1/*
2 * Pistachio platform setup
3 *
4 * Copyright (C) 2014 Google, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 */
10
11#include <linux/init.h>
12#include <linux/kernel.h>
13#include <linux/of_address.h>
14#include <linux/of_fdt.h>
15#include <linux/of_platform.h>
16
17#include <asm/cacheflush.h>
18#include <asm/dma-coherence.h>
19#include <asm/fw/fw.h>
20#include <asm/mips-boards/generic.h>
21#include <asm/mips-cm.h>
22#include <asm/mips-cpc.h>
23#include <asm/prom.h>
24#include <asm/smp-ops.h>
25#include <asm/traps.h>
26
27const char *get_system_type(void)
28{
29 return "IMG Pistachio SoC";
30}
31
32static void __init plat_setup_iocoherency(void)
33{
34 /*
35 * Kernel has been configured with software coherency
36 * but we might choose to turn it off and use hardware
37 * coherency instead.
38 */
39 if (mips_cm_numiocu() != 0) {
40 /* Nothing special needs to be done to enable coherency */
41 pr_info("CMP IOCU detected\n");
42 hw_coherentio = 1;
43 if (coherentio == 0)
44 pr_info("Hardware DMA cache coherency disabled\n");
45 else
46 pr_info("Hardware DMA cache coherency enabled\n");
47 } else {
48 if (coherentio == 1)
49 pr_info("Hardware DMA cache coherency unsupported, but enabled from command line!\n");
50 else
51 pr_info("Software DMA cache coherency enabled\n");
52 }
53}
54
55void __init plat_mem_setup(void)
56{
57 if (fw_arg0 != -2)
58 panic("Device-tree not present");
59
60 __dt_setup_arch((void *)fw_arg1);
61 strlcpy(arcs_cmdline, boot_command_line, COMMAND_LINE_SIZE);
62
63 plat_setup_iocoherency();
64}
65
66#define DEFAULT_CPC_BASE_ADDR 0x1bde0000
67
68phys_addr_t mips_cpc_default_phys_base(void)
69{
70 return DEFAULT_CPC_BASE_ADDR;
71}
72
73static void __init mips_nmi_setup(void)
74{
75 void *base;
76 extern char except_vec_nmi;
77
78 base = cpu_has_veic ?
79 (void *)(CAC_BASE + 0xa80) :
80 (void *)(CAC_BASE + 0x380);
81 memcpy(base, &except_vec_nmi, 0x80);
82 flush_icache_range((unsigned long)base,
83 (unsigned long)base + 0x80);
84}
85
86static void __init mips_ejtag_setup(void)
87{
88 void *base;
89 extern char except_vec_ejtag_debug;
90
91 base = cpu_has_veic ?
92 (void *)(CAC_BASE + 0xa00) :
93 (void *)(CAC_BASE + 0x300);
94 memcpy(base, &except_vec_ejtag_debug, 0x80);
95 flush_icache_range((unsigned long)base,
96 (unsigned long)base + 0x80);
97}
98
99void __init prom_init(void)
100{
101 board_nmi_handler_setup = mips_nmi_setup;
102 board_ejtag_handler_setup = mips_ejtag_setup;
103
104 mips_cm_probe();
105 mips_cpc_probe();
106 register_cps_smp_ops();
107}
108
109void __init prom_free_prom_memory(void)
110{
111}
112
113void __init device_tree_init(void)
114{
115 if (!initial_boot_params)
116 return;
117
118 unflatten_and_copy_device_tree();
119}
120
121static int __init plat_of_setup(void)
122{
123 if (!of_have_populated_dt())
124 panic("Device tree not present");
125
126 if (of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL))
127 panic("Failed to populate DT");
128
129 return 0;
130}
131arch_initcall(plat_of_setup);
diff --git a/arch/mips/pistachio/irq.c b/arch/mips/pistachio/irq.c
new file mode 100644
index 000000000000..0a6b24c24652
--- /dev/null
+++ b/arch/mips/pistachio/irq.c
@@ -0,0 +1,28 @@
1/*
2 * Pistachio IRQ setup
3 *
4 * Copyright (C) 2014 Google, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 */
10
11#include <linux/init.h>
12#include <linux/irqchip.h>
13#include <linux/irqchip/mips-gic.h>
14#include <linux/kernel.h>
15
16#include <asm/cpu-features.h>
17#include <asm/irq_cpu.h>
18
19void __init arch_init_irq(void)
20{
21 pr_info("EIC is %s\n", cpu_has_veic ? "on" : "off");
22 pr_info("VINT is %s\n", cpu_has_vint ? "on" : "off");
23
24 if (!cpu_has_veic)
25 mips_cpu_irq_init();
26
27 irqchip_init();
28}
diff --git a/arch/mips/pistachio/time.c b/arch/mips/pistachio/time.c
new file mode 100644
index 000000000000..67889fcea8aa
--- /dev/null
+++ b/arch/mips/pistachio/time.c
@@ -0,0 +1,52 @@
1/*
2 * Pistachio clocksource/timer setup
3 *
4 * Copyright (C) 2014 Google, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 */
10
11#include <linux/clk.h>
12#include <linux/clk-provider.h>
13#include <linux/clocksource.h>
14#include <linux/init.h>
15#include <linux/irqchip/mips-gic.h>
16#include <linux/of.h>
17
18#include <asm/time.h>
19
20unsigned int get_c0_compare_int(void)
21{
22 return gic_get_c0_compare_int();
23}
24
25int get_c0_perfcount_int(void)
26{
27 return gic_get_c0_perfcount_int();
28}
29
30void __init plat_time_init(void)
31{
32 struct device_node *np;
33 struct clk *clk;
34
35 of_clk_init(NULL);
36 clocksource_of_init();
37
38 np = of_get_cpu_node(0, NULL);
39 if (!np) {
40 pr_err("Failed to get CPU node\n");
41 return;
42 }
43
44 clk = of_clk_get(np, 0);
45 if (IS_ERR(clk)) {
46 pr_err("Failed to get CPU clock: %ld\n", PTR_ERR(clk));
47 return;
48 }
49
50 mips_hpt_frequency = clk_get_rate(clk) / 2;
51 clk_put(clk);
52}
diff --git a/arch/mips/power/Makefile b/arch/mips/power/Makefile
index 73d56b87cb9b..70bd7883bc1b 100644
--- a/arch/mips/power/Makefile
+++ b/arch/mips/power/Makefile
@@ -1 +1 @@
obj-$(CONFIG_HIBERNATION) += cpu.o hibernate.o obj-$(CONFIG_HIBERNATION) += cpu.o hibernate.o hibernate_asm.o
diff --git a/arch/mips/power/hibernate.c b/arch/mips/power/hibernate.c
new file mode 100644
index 000000000000..19a9af68bcdb
--- /dev/null
+++ b/arch/mips/power/hibernate.c
@@ -0,0 +1,10 @@
1#include <asm/tlbflush.h>
2
3extern int restore_image(void);
4
5int swsusp_arch_resume(void)
6{
7 /* Avoid TLB mismatch during and after kernel resume */
8 local_flush_tlb_all();
9 return restore_image();
10}
diff --git a/arch/mips/power/hibernate.S b/arch/mips/power/hibernate_asm.S
index 32a7c828f073..b1fab951100f 100644
--- a/arch/mips/power/hibernate.S
+++ b/arch/mips/power/hibernate_asm.S
@@ -29,7 +29,7 @@ LEAF(swsusp_arch_suspend)
29 j swsusp_save 29 j swsusp_save
30END(swsusp_arch_suspend) 30END(swsusp_arch_suspend)
31 31
32LEAF(swsusp_arch_resume) 32LEAF(restore_image)
33 PTR_L t0, restore_pblist 33 PTR_L t0, restore_pblist
340: 340:
35 PTR_L t1, PBE_ADDRESS(t0) /* source */ 35 PTR_L t1, PBE_ADDRESS(t0) /* source */
@@ -43,7 +43,6 @@ LEAF(swsusp_arch_resume)
43 bne t1, t3, 1b 43 bne t1, t3, 1b
44 PTR_L t0, PBE_NEXT(t0) 44 PTR_L t0, PBE_NEXT(t0)
45 bnez t0, 0b 45 bnez t0, 0b
46 jal local_flush_tlb_all /* Avoid TLB mismatch after kernel resume */
47 PTR_LA t0, saved_regs 46 PTR_LA t0, saved_regs
48 PTR_L ra, PT_R31(t0) 47 PTR_L ra, PT_R31(t0)
49 PTR_L sp, PT_R29(t0) 48 PTR_L sp, PT_R29(t0)
@@ -59,4 +58,4 @@ LEAF(swsusp_arch_resume)
59 PTR_L s7, PT_R23(t0) 58 PTR_L s7, PT_R23(t0)
60 PTR_LI v0, 0x0 59 PTR_LI v0, 0x0
61 jr ra 60 jr ra
62END(swsusp_arch_resume) 61END(restore_image)
diff --git a/arch/mips/ralink/Kconfig b/arch/mips/ralink/Kconfig
index b1c52ca580f9..e9bc8c96174e 100644
--- a/arch/mips/ralink/Kconfig
+++ b/arch/mips/ralink/Kconfig
@@ -7,6 +7,11 @@ config CLKEVT_RT3352
7 select CLKSRC_OF 7 select CLKSRC_OF
8 select CLKSRC_MMIO 8 select CLKSRC_MMIO
9 9
10config RALINK_ILL_ACC
11 bool
12 depends on SOC_RT305X
13 default y
14
10choice 15choice
11 prompt "Ralink SoC selection" 16 prompt "Ralink SoC selection"
12 default SOC_RT305X 17 default SOC_RT305X
diff --git a/arch/mips/sgi-ip27/ip27-timer.c b/arch/mips/sgi-ip27/ip27-timer.c
index 1d97eaba0c5f..a6d10f607f34 100644
--- a/arch/mips/sgi-ip27/ip27-timer.c
+++ b/arch/mips/sgi-ip27/ip27-timer.c
@@ -7,6 +7,7 @@
7#include <linux/init.h> 7#include <linux/init.h>
8#include <linux/kernel.h> 8#include <linux/kernel.h>
9#include <linux/sched.h> 9#include <linux/sched.h>
10#include <linux/sched_clock.h>
10#include <linux/interrupt.h> 11#include <linux/interrupt.h>
11#include <linux/kernel_stat.h> 12#include <linux/kernel_stat.h>
12#include <linux/param.h> 13#include <linux/param.h>
@@ -159,11 +160,18 @@ struct clocksource hub_rt_clocksource = {
159 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 160 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
160}; 161};
161 162
163static u64 notrace hub_rt_read_sched_clock(void)
164{
165 return REMOTE_HUB_L(cputonasid(0), PI_RT_COUNT);
166}
167
162static void __init hub_rt_clocksource_init(void) 168static void __init hub_rt_clocksource_init(void)
163{ 169{
164 struct clocksource *cs = &hub_rt_clocksource; 170 struct clocksource *cs = &hub_rt_clocksource;
165 171
166 clocksource_register_hz(cs, CYCLES_PER_SEC); 172 clocksource_register_hz(cs, CYCLES_PER_SEC);
173
174 sched_clock_register(hub_rt_read_sched_clock, 52, CYCLES_PER_SEC);
167} 175}
168 176
169void __init plat_time_init(void) 177void __init plat_time_init(void)
diff --git a/arch/mips/sgi-ip32/ip32-platform.c b/arch/mips/sgi-ip32/ip32-platform.c
index b522477129a5..0134db2ad0a8 100644
--- a/arch/mips/sgi-ip32/ip32-platform.c
+++ b/arch/mips/sgi-ip32/ip32-platform.c
@@ -5,7 +5,6 @@
5 * 5 *
6 * Copyright (C) 2007 Ralf Baechle (ralf@linux-mips.org) 6 * Copyright (C) 2007 Ralf Baechle (ralf@linux-mips.org)
7 */ 7 */
8#include <linux/module.h>
9#include <linux/init.h> 8#include <linux/init.h>
10#include <linux/platform_device.h> 9#include <linux/platform_device.h>
11#include <linux/serial_8250.h> 10#include <linux/serial_8250.h>
@@ -137,7 +136,3 @@ struct platform_device ip32_rtc_device = {
137} 136}
138 137
139device_initcall(sgio2_cmos_devinit); 138device_initcall(sgio2_cmos_devinit);
140
141MODULE_AUTHOR("Ralf Baechle <ralf@linux-mips.org>");
142MODULE_LICENSE("GPL");
143MODULE_DESCRIPTION("8250 UART probe driver for SGI IP32 aka O2");
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-18 02:36:51 -0500