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authorHuacai Chen <chenhc@lemote.com>2014-11-04 01:13:23 -0500
committerRalf Baechle <ralf@linux-mips.org>2014-11-19 12:22:07 -0500
commit7352c8b13dd9a848b0c5d6209d62761afb164dcb (patch)
tree307be3b53c379ccbcf63815f4f0701735dbac33b /arch/mips
parentcc94ea31150f83d1f70ad854c920dd6b739c1628 (diff)
MIPS: Loongson: Set Loongson-3's ISA level to MIPS64R1
In CPU manual Loongson-3 is MIPS64R2 compatible, but during tests we found that its EI/DI instructions have problems. So we just set the ISA level to MIPS64R1. Signed-off-by: Huacai Chen <chenhc@lemote.com> Cc: John Crispin <john@phrozen.org> Cc: Steven J. Hill <Steven.Hill@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/8320/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips')
-rw-r--r--arch/mips/include/asm/mach-loongson/cpu-feature-overrides.h2
-rw-r--r--arch/mips/kernel/cpu-probe.c5
2 files changed, 4 insertions, 3 deletions
diff --git a/arch/mips/include/asm/mach-loongson/cpu-feature-overrides.h b/arch/mips/include/asm/mach-loongson/cpu-feature-overrides.h
index 7d28f95b0512..6d69332f21ec 100644
--- a/arch/mips/include/asm/mach-loongson/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-loongson/cpu-feature-overrides.h
@@ -41,10 +41,8 @@
41#define cpu_has_mcheck 0 41#define cpu_has_mcheck 0
42#define cpu_has_mdmx 0 42#define cpu_has_mdmx 0
43#define cpu_has_mips16 0 43#define cpu_has_mips16 0
44#define cpu_has_mips32r1 0
45#define cpu_has_mips32r2 0 44#define cpu_has_mips32r2 0
46#define cpu_has_mips3d 0 45#define cpu_has_mips3d 0
47#define cpu_has_mips64r1 0
48#define cpu_has_mips64r2 0 46#define cpu_has_mips64r2 0
49#define cpu_has_mipsmt 0 47#define cpu_has_mipsmt 0
50#define cpu_has_prefetch 0 48#define cpu_has_prefetch 0
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index 08dc945f7608..d5a4f380b019 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -757,26 +757,29 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
757 c->cputype = CPU_LOONGSON2; 757 c->cputype = CPU_LOONGSON2;
758 __cpu_name[cpu] = "ICT Loongson-2"; 758 __cpu_name[cpu] = "ICT Loongson-2";
759 set_elf_platform(cpu, "loongson2e"); 759 set_elf_platform(cpu, "loongson2e");
760 set_isa(c, MIPS_CPU_ISA_III);
760 break; 761 break;
761 case PRID_REV_LOONGSON2F: 762 case PRID_REV_LOONGSON2F:
762 c->cputype = CPU_LOONGSON2; 763 c->cputype = CPU_LOONGSON2;
763 __cpu_name[cpu] = "ICT Loongson-2"; 764 __cpu_name[cpu] = "ICT Loongson-2";
764 set_elf_platform(cpu, "loongson2f"); 765 set_elf_platform(cpu, "loongson2f");
766 set_isa(c, MIPS_CPU_ISA_III);
765 break; 767 break;
766 case PRID_REV_LOONGSON3A: 768 case PRID_REV_LOONGSON3A:
767 c->cputype = CPU_LOONGSON3; 769 c->cputype = CPU_LOONGSON3;
768 __cpu_name[cpu] = "ICT Loongson-3"; 770 __cpu_name[cpu] = "ICT Loongson-3";
769 set_elf_platform(cpu, "loongson3a"); 771 set_elf_platform(cpu, "loongson3a");
772 set_isa(c, MIPS_CPU_ISA_M64R1);
770 break; 773 break;
771 case PRID_REV_LOONGSON3B_R1: 774 case PRID_REV_LOONGSON3B_R1:
772 case PRID_REV_LOONGSON3B_R2: 775 case PRID_REV_LOONGSON3B_R2:
773 c->cputype = CPU_LOONGSON3; 776 c->cputype = CPU_LOONGSON3;
774 __cpu_name[cpu] = "ICT Loongson-3"; 777 __cpu_name[cpu] = "ICT Loongson-3";
775 set_elf_platform(cpu, "loongson3b"); 778 set_elf_platform(cpu, "loongson3b");
779 set_isa(c, MIPS_CPU_ISA_M64R1);
776 break; 780 break;
777 } 781 }
778 782
779 set_isa(c, MIPS_CPU_ISA_III);
780 c->options = R4K_OPTS | 783 c->options = R4K_OPTS |
781 MIPS_CPU_FPU | MIPS_CPU_LLSC | 784 MIPS_CPU_FPU | MIPS_CPU_LLSC |
782 MIPS_CPU_32FPR; 785 MIPS_CPU_32FPR;