diff options
author | Thomas Gleixner <tglx@linutronix.de> | 2011-03-23 17:08:58 -0400 |
---|---|---|
committer | Ralf Baechle <ralf@linux-mips.org> | 2011-03-25 13:45:16 -0400 |
commit | 161d049e8c6435284a792cbd00d420a506edd2cb (patch) | |
tree | 7f84c4b67f5116fb8379d6d70e1f7cd3f49e8e63 /arch/mips | |
parent | 7c8d948f1633da5ff81e4f5b31ef237d74c40127 (diff) |
MIPS: GIC: Convert to new irq_chip functions
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
To: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/2186/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips')
-rw-r--r-- | arch/mips/kernel/irq-gic.c | 43 |
1 files changed, 18 insertions, 25 deletions
diff --git a/arch/mips/kernel/irq-gic.c b/arch/mips/kernel/irq-gic.c index 1774271af848..43cd9628251a 100644 --- a/arch/mips/kernel/irq-gic.c +++ b/arch/mips/kernel/irq-gic.c | |||
@@ -87,17 +87,10 @@ unsigned int gic_get_int(void) | |||
87 | return i; | 87 | return i; |
88 | } | 88 | } |
89 | 89 | ||
90 | static unsigned int gic_irq_startup(unsigned int irq) | 90 | static void gic_irq_ack(struct irq_data *d) |
91 | { | 91 | { |
92 | irq -= _irqbase; | 92 | unsigned int irq = d->irq - _irqbase; |
93 | pr_debug("CPU%d: %s: irq%d\n", smp_processor_id(), __func__, irq); | ||
94 | GIC_SET_INTR_MASK(irq); | ||
95 | return 0; | ||
96 | } | ||
97 | 93 | ||
98 | static void gic_irq_ack(unsigned int irq) | ||
99 | { | ||
100 | irq -= _irqbase; | ||
101 | pr_debug("CPU%d: %s: irq%d\n", smp_processor_id(), __func__, irq); | 94 | pr_debug("CPU%d: %s: irq%d\n", smp_processor_id(), __func__, irq); |
102 | GIC_CLR_INTR_MASK(irq); | 95 | GIC_CLR_INTR_MASK(irq); |
103 | 96 | ||
@@ -105,16 +98,16 @@ static void gic_irq_ack(unsigned int irq) | |||
105 | GICWRITE(GIC_REG(SHARED, GIC_SH_WEDGE), irq); | 98 | GICWRITE(GIC_REG(SHARED, GIC_SH_WEDGE), irq); |
106 | } | 99 | } |
107 | 100 | ||
108 | static void gic_mask_irq(unsigned int irq) | 101 | static void gic_mask_irq(struct irq_data *d) |
109 | { | 102 | { |
110 | irq -= _irqbase; | 103 | unsigned int irq = d->irq - _irqbase; |
111 | pr_debug("CPU%d: %s: irq%d\n", smp_processor_id(), __func__, irq); | 104 | pr_debug("CPU%d: %s: irq%d\n", smp_processor_id(), __func__, irq); |
112 | GIC_CLR_INTR_MASK(irq); | 105 | GIC_CLR_INTR_MASK(irq); |
113 | } | 106 | } |
114 | 107 | ||
115 | static void gic_unmask_irq(unsigned int irq) | 108 | static void gic_unmask_irq(struct irq_data *d) |
116 | { | 109 | { |
117 | irq -= _irqbase; | 110 | unsigned int irq = d->irq - _irqbase; |
118 | pr_debug("CPU%d: %s: irq%d\n", smp_processor_id(), __func__, irq); | 111 | pr_debug("CPU%d: %s: irq%d\n", smp_processor_id(), __func__, irq); |
119 | GIC_SET_INTR_MASK(irq); | 112 | GIC_SET_INTR_MASK(irq); |
120 | } | 113 | } |
@@ -123,13 +116,14 @@ static void gic_unmask_irq(unsigned int irq) | |||
123 | 116 | ||
124 | static DEFINE_SPINLOCK(gic_lock); | 117 | static DEFINE_SPINLOCK(gic_lock); |
125 | 118 | ||
126 | static int gic_set_affinity(unsigned int irq, const struct cpumask *cpumask) | 119 | static int gic_set_affinity(struct irq_data *d, const struct cpumask *cpumask, |
120 | bool force) | ||
127 | { | 121 | { |
122 | unsigned int irq = d->irq - _irqbase; | ||
128 | cpumask_t tmp = CPU_MASK_NONE; | 123 | cpumask_t tmp = CPU_MASK_NONE; |
129 | unsigned long flags; | 124 | unsigned long flags; |
130 | int i; | 125 | int i; |
131 | 126 | ||
132 | irq -= _irqbase; | ||
133 | pr_debug("%s(%d) called\n", __func__, irq); | 127 | pr_debug("%s(%d) called\n", __func__, irq); |
134 | cpumask_and(&tmp, cpumask, cpu_online_mask); | 128 | cpumask_and(&tmp, cpumask, cpu_online_mask); |
135 | if (cpus_empty(tmp)) | 129 | if (cpus_empty(tmp)) |
@@ -147,23 +141,22 @@ static int gic_set_affinity(unsigned int irq, const struct cpumask *cpumask) | |||
147 | set_bit(irq, pcpu_masks[first_cpu(tmp)].pcpu_mask); | 141 | set_bit(irq, pcpu_masks[first_cpu(tmp)].pcpu_mask); |
148 | 142 | ||
149 | } | 143 | } |
150 | cpumask_copy(irq_desc[irq].affinity, cpumask); | 144 | cpumask_copy(d->affinity, cpumask); |
151 | spin_unlock_irqrestore(&gic_lock, flags); | 145 | spin_unlock_irqrestore(&gic_lock, flags); |
152 | 146 | ||
153 | return 0; | 147 | return IRQ_SET_MASK_OK_NOCOPY; |
154 | } | 148 | } |
155 | #endif | 149 | #endif |
156 | 150 | ||
157 | static struct irq_chip gic_irq_controller = { | 151 | static struct irq_chip gic_irq_controller = { |
158 | .name = "MIPS GIC", | 152 | .name = "MIPS GIC", |
159 | .startup = gic_irq_startup, | 153 | .irq_ack = gic_irq_ack, |
160 | .ack = gic_irq_ack, | 154 | .irq_mask = gic_mask_irq, |
161 | .mask = gic_mask_irq, | 155 | .irq_mask_ack = gic_mask_irq, |
162 | .mask_ack = gic_mask_irq, | 156 | .irq_unmask = gic_unmask_irq, |
163 | .unmask = gic_unmask_irq, | 157 | .irq_eoi = gic_unmask_irq, |
164 | .eoi = gic_unmask_irq, | ||
165 | #ifdef CONFIG_SMP | 158 | #ifdef CONFIG_SMP |
166 | .set_affinity = gic_set_affinity, | 159 | .irq_set_affinity = gic_set_affinity, |
167 | #endif | 160 | #endif |
168 | }; | 161 | }; |
169 | 162 | ||