diff options
| author | Peter Horton <pdh@colonel-panic.org> | 2006-01-29 16:33:48 -0500 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2006-02-07 08:30:24 -0500 |
| commit | 52378445da0253d5031590e5e9186ee448dc0b4a (patch) | |
| tree | bb4028a9ff2543e29c5f31863a441f1f9d7608f5 /arch/mips | |
| parent | c315a2b5fed42aea4dda98b5ced35d1d1a3a8349 (diff) | |
[MIPS] Fix Cobalt PCI cache line sizes
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips')
| -rw-r--r-- | arch/mips/pci/fixup-cobalt.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/mips/pci/fixup-cobalt.c b/arch/mips/pci/fixup-cobalt.c index b664df150a3e..75a01e764898 100644 --- a/arch/mips/pci/fixup-cobalt.c +++ b/arch/mips/pci/fixup-cobalt.c | |||
| @@ -52,7 +52,7 @@ static void qube_raq_via_bmIDE_fixup(struct pci_dev *dev) | |||
| 52 | pci_read_config_byte(dev, PCI_LATENCY_TIMER, <); | 52 | pci_read_config_byte(dev, PCI_LATENCY_TIMER, <); |
| 53 | if (lt < 64) | 53 | if (lt < 64) |
| 54 | pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64); | 54 | pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64); |
| 55 | pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 7); | 55 | pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 8); |
| 56 | } | 56 | } |
| 57 | 57 | ||
| 58 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1, | 58 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1, |
| @@ -69,7 +69,7 @@ static void qube_raq_galileo_fixup(struct pci_dev *dev) | |||
| 69 | * host bridge. | 69 | * host bridge. |
| 70 | */ | 70 | */ |
| 71 | pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64); | 71 | pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64); |
| 72 | pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 7); | 72 | pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 8); |
| 73 | 73 | ||
| 74 | /* | 74 | /* |
| 75 | * The code described by the comment below has been removed | 75 | * The code described by the comment below has been removed |