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authorRalf Baechle <ralf@linux-mips.org>2007-03-26 03:59:52 -0400
committerRalf Baechle <ralf@linux-mips.org>2007-03-29 18:46:34 -0400
commit448f283c11ac66793c7231bcbd729a417a9f9a04 (patch)
tree76aee5217c9b89c3aa683b4a856c390ffdacf89b /arch/mips
parentefab03d998da03f67836ffc664b04e0400f85448 (diff)
[MIPS] Ocelot: Give PMON_v1_setup a proper prototype.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips')
-rw-r--r--arch/mips/gt64120/momenco_ocelot/setup.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/mips/gt64120/momenco_ocelot/setup.c b/arch/mips/gt64120/momenco_ocelot/setup.c
index 94f94ebbda6c..98b6fb38096d 100644
--- a/arch/mips/gt64120/momenco_ocelot/setup.c
+++ b/arch/mips/gt64120/momenco_ocelot/setup.c
@@ -79,7 +79,7 @@ static char reset_reason;
79static void __init setup_l3cache(unsigned long size); 79static void __init setup_l3cache(unsigned long size);
80 80
81/* setup code for a handoff from a version 1 PMON 2000 PROM */ 81/* setup code for a handoff from a version 1 PMON 2000 PROM */
82void PMON_v1_setup() 82static void PMON_v1_setup(void)
83{ 83{
84 /* A wired TLB entry for the GT64120A and the serial port. The 84 /* A wired TLB entry for the GT64120A and the serial port. The
85 GT64120A is going to be hit on every IRQ anyway - there's 85 GT64120A is going to be hit on every IRQ anyway - there's