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authorGabor Juhos <juhosg@openwrt.org>2011-01-04 15:28:14 -0500
committerRalf Baechle <ralf@linux-mips.org>2011-01-18 13:30:24 -0500
commitd4a67d9dc8a5a80c4ec1814791af8c0252c158b8 (patch)
tree28c9797f2ec5bf46325e1d5dd7db675ac0ac6713 /arch/mips
parent94bb0c1ab293c298a8852e4f10c4215bad6daa9b (diff)
MIPS: Add initial support for the Atheros AR71XX/AR724X/AR931X SoCs
This patch adds initial support for various Atheros SoCs based on the MIPS 24Kc core. The following models are supported at the moment: - AR7130 - AR7141 - AR7161 - AR9130 - AR9132 - AR7240 - AR7241 - AR7242 The current patch contains minimal support only, but the resulting kernel can boot into user-space with using of an initramfs image on various boards which are using these SoCs. Support for more built-in devices and individual boards will be implemented in further patches. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Signed-off-by: Imre Kaloz <kaloz@openwrt.org> Cc: linux-mips@linux-mips.org Cc: Luis R. Rodriguez <lrodriguez@atheros.com> Cc: Cliff Holden <Cliff.Holden@Atheros.com> Cc: Kathy Giori <Kathy.Giori@Atheros.com> Patchwork: https://patchwork.linux-mips.org/patch/1947/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips')
-rw-r--r--arch/mips/Kbuild.platforms1
-rw-r--r--arch/mips/Kconfig15
-rw-r--r--arch/mips/ath79/Kconfig12
-rw-r--r--arch/mips/ath79/Makefile18
-rw-r--r--arch/mips/ath79/Platform7
-rw-r--r--arch/mips/ath79/clock.c183
-rw-r--r--arch/mips/ath79/common.c97
-rw-r--r--arch/mips/ath79/common.h26
-rw-r--r--arch/mips/ath79/dev-common.c67
-rw-r--r--arch/mips/ath79/dev-common.h17
-rw-r--r--arch/mips/ath79/early_printk.c36
-rw-r--r--arch/mips/ath79/irq.c187
-rw-r--r--arch/mips/ath79/prom.c57
-rw-r--r--arch/mips/ath79/setup.c190
-rw-r--r--arch/mips/include/asm/mach-ath79/ar71xx_regs.h207
-rw-r--r--arch/mips/include/asm/mach-ath79/ath79.h96
-rw-r--r--arch/mips/include/asm/mach-ath79/cpu-feature-overrides.h56
-rw-r--r--arch/mips/include/asm/mach-ath79/irq.h36
-rw-r--r--arch/mips/include/asm/mach-ath79/kernel-entry-init.h32
-rw-r--r--arch/mips/include/asm/mach-ath79/war.h25
20 files changed, 1365 insertions, 0 deletions
diff --git a/arch/mips/Kbuild.platforms b/arch/mips/Kbuild.platforms
index 78439b8a83c4..7ff9b5492041 100644
--- a/arch/mips/Kbuild.platforms
+++ b/arch/mips/Kbuild.platforms
@@ -2,6 +2,7 @@
2 2
3platforms += alchemy 3platforms += alchemy
4platforms += ar7 4platforms += ar7
5platforms += ath79
5platforms += bcm47xx 6platforms += bcm47xx
6platforms += bcm63xx 7platforms += bcm63xx
7platforms += cavium-octeon 8platforms += cavium-octeon
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 954304068228..e0215d93df82 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -66,6 +66,20 @@ config AR7
66 Support for the Texas Instruments AR7 System-on-a-Chip 66 Support for the Texas Instruments AR7 System-on-a-Chip
67 family: TNETD7100, 7200 and 7300. 67 family: TNETD7100, 7200 and 7300.
68 68
69config ATH79
70 bool "Atheros AR71XX/AR724X/AR913X based boards"
71 select BOOT_RAW
72 select CEVT_R4K
73 select CSRC_R4K
74 select DMA_NONCOHERENT
75 select IRQ_CPU
76 select SYS_HAS_CPU_MIPS32_R2
77 select SYS_HAS_EARLY_PRINTK
78 select SYS_SUPPORTS_32BIT_KERNEL
79 select SYS_SUPPORTS_BIG_ENDIAN
80 help
81 Support for the Atheros AR71XX/AR724X/AR913X SoCs.
82
69config BCM47XX 83config BCM47XX
70 bool "Broadcom BCM47XX based boards" 84 bool "Broadcom BCM47XX based boards"
71 select CEVT_R4K 85 select CEVT_R4K
@@ -718,6 +732,7 @@ config CAVIUM_OCTEON_REFERENCE_BOARD
718endchoice 732endchoice
719 733
720source "arch/mips/alchemy/Kconfig" 734source "arch/mips/alchemy/Kconfig"
735source "arch/mips/ath79/Kconfig"
721source "arch/mips/bcm63xx/Kconfig" 736source "arch/mips/bcm63xx/Kconfig"
722source "arch/mips/jazz/Kconfig" 737source "arch/mips/jazz/Kconfig"
723source "arch/mips/jz4740/Kconfig" 738source "arch/mips/jz4740/Kconfig"
diff --git a/arch/mips/ath79/Kconfig b/arch/mips/ath79/Kconfig
new file mode 100644
index 000000000000..50b933446cc0
--- /dev/null
+++ b/arch/mips/ath79/Kconfig
@@ -0,0 +1,12 @@
1if ATH79
2
3config SOC_AR71XX
4 def_bool n
5
6config SOC_AR724X
7 def_bool n
8
9config SOC_AR913X
10 def_bool n
11
12endif
diff --git a/arch/mips/ath79/Makefile b/arch/mips/ath79/Makefile
new file mode 100644
index 000000000000..31e0f83ddf68
--- /dev/null
+++ b/arch/mips/ath79/Makefile
@@ -0,0 +1,18 @@
1#
2# Makefile for the Atheros AR71XX/AR724X/AR913X specific parts of the kernel
3#
4# Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
5# Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
6#
7# This program is free software; you can redistribute it and/or modify it
8# under the terms of the GNU General Public License version 2 as published
9# by the Free Software Foundation.
10
11obj-y := prom.o setup.o irq.o common.o clock.o
12
13obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
14
15#
16# Devices
17#
18obj-y += dev-common.o
diff --git a/arch/mips/ath79/Platform b/arch/mips/ath79/Platform
new file mode 100644
index 000000000000..2bd663647d27
--- /dev/null
+++ b/arch/mips/ath79/Platform
@@ -0,0 +1,7 @@
1#
2# Atheros AR71xx/AR724x/AR913x
3#
4
5platform-$(CONFIG_ATH79) += ath79/
6cflags-$(CONFIG_ATH79) += -I$(srctree)/arch/mips/include/asm/mach-ath79
7load-$(CONFIG_ATH79) = 0xffffffff80060000
diff --git a/arch/mips/ath79/clock.c b/arch/mips/ath79/clock.c
new file mode 100644
index 000000000000..680bde99a26c
--- /dev/null
+++ b/arch/mips/ath79/clock.c
@@ -0,0 +1,183 @@
1/*
2 * Atheros AR71XX/AR724X/AR913X common routines
3 *
4 * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 */
10
11#include <linux/kernel.h>
12#include <linux/module.h>
13#include <linux/init.h>
14#include <linux/err.h>
15#include <linux/clk.h>
16
17#include <asm/mach-ath79/ath79.h>
18#include <asm/mach-ath79/ar71xx_regs.h>
19#include "common.h"
20
21#define AR71XX_BASE_FREQ 40000000
22#define AR724X_BASE_FREQ 5000000
23#define AR913X_BASE_FREQ 5000000
24
25struct clk {
26 unsigned long rate;
27};
28
29static struct clk ath79_ref_clk;
30static struct clk ath79_cpu_clk;
31static struct clk ath79_ddr_clk;
32static struct clk ath79_ahb_clk;
33static struct clk ath79_wdt_clk;
34static struct clk ath79_uart_clk;
35
36static void __init ar71xx_clocks_init(void)
37{
38 u32 pll;
39 u32 freq;
40 u32 div;
41
42 ath79_ref_clk.rate = AR71XX_BASE_FREQ;
43
44 pll = ath79_pll_rr(AR71XX_PLL_REG_CPU_CONFIG);
45
46 div = ((pll >> AR71XX_PLL_DIV_SHIFT) & AR71XX_PLL_DIV_MASK) + 1;
47 freq = div * ath79_ref_clk.rate;
48
49 div = ((pll >> AR71XX_CPU_DIV_SHIFT) & AR71XX_CPU_DIV_MASK) + 1;
50 ath79_cpu_clk.rate = freq / div;
51
52 div = ((pll >> AR71XX_DDR_DIV_SHIFT) & AR71XX_DDR_DIV_MASK) + 1;
53 ath79_ddr_clk.rate = freq / div;
54
55 div = (((pll >> AR71XX_AHB_DIV_SHIFT) & AR71XX_AHB_DIV_MASK) + 1) * 2;
56 ath79_ahb_clk.rate = ath79_cpu_clk.rate / div;
57
58 ath79_wdt_clk.rate = ath79_ahb_clk.rate;
59 ath79_uart_clk.rate = ath79_ahb_clk.rate;
60}
61
62static void __init ar724x_clocks_init(void)
63{
64 u32 pll;
65 u32 freq;
66 u32 div;
67
68 ath79_ref_clk.rate = AR724X_BASE_FREQ;
69 pll = ath79_pll_rr(AR724X_PLL_REG_CPU_CONFIG);
70
71 div = ((pll >> AR724X_PLL_DIV_SHIFT) & AR724X_PLL_DIV_MASK);
72 freq = div * ath79_ref_clk.rate;
73
74 div = ((pll >> AR724X_PLL_REF_DIV_SHIFT) & AR724X_PLL_REF_DIV_MASK);
75 freq *= div;
76
77 ath79_cpu_clk.rate = freq;
78
79 div = ((pll >> AR724X_DDR_DIV_SHIFT) & AR724X_DDR_DIV_MASK) + 1;
80 ath79_ddr_clk.rate = freq / div;
81
82 div = (((pll >> AR724X_AHB_DIV_SHIFT) & AR724X_AHB_DIV_MASK) + 1) * 2;
83 ath79_ahb_clk.rate = ath79_cpu_clk.rate / div;
84
85 ath79_wdt_clk.rate = ath79_ahb_clk.rate;
86 ath79_uart_clk.rate = ath79_ahb_clk.rate;
87}
88
89static void __init ar913x_clocks_init(void)
90{
91 u32 pll;
92 u32 freq;
93 u32 div;
94
95 ath79_ref_clk.rate = AR913X_BASE_FREQ;
96 pll = ath79_pll_rr(AR913X_PLL_REG_CPU_CONFIG);
97
98 div = ((pll >> AR913X_PLL_DIV_SHIFT) & AR913X_PLL_DIV_MASK);
99 freq = div * ath79_ref_clk.rate;
100
101 ath79_cpu_clk.rate = freq;
102
103 div = ((pll >> AR913X_DDR_DIV_SHIFT) & AR913X_DDR_DIV_MASK) + 1;
104 ath79_ddr_clk.rate = freq / div;
105
106 div = (((pll >> AR913X_AHB_DIV_SHIFT) & AR913X_AHB_DIV_MASK) + 1) * 2;
107 ath79_ahb_clk.rate = ath79_cpu_clk.rate / div;
108
109 ath79_wdt_clk.rate = ath79_ahb_clk.rate;
110 ath79_uart_clk.rate = ath79_ahb_clk.rate;
111}
112
113void __init ath79_clocks_init(void)
114{
115 if (soc_is_ar71xx())
116 ar71xx_clocks_init();
117 else if (soc_is_ar724x())
118 ar724x_clocks_init();
119 else if (soc_is_ar913x())
120 ar913x_clocks_init();
121 else
122 BUG();
123
124 pr_info("Clocks: CPU:%lu.%03luMHz, DDR:%lu.%03luMHz, AHB:%lu.%03luMHz, "
125 "Ref:%lu.%03luMHz",
126 ath79_cpu_clk.rate / 1000000,
127 (ath79_cpu_clk.rate / 1000) % 1000,
128 ath79_ddr_clk.rate / 1000000,
129 (ath79_ddr_clk.rate / 1000) % 1000,
130 ath79_ahb_clk.rate / 1000000,
131 (ath79_ahb_clk.rate / 1000) % 1000,
132 ath79_ref_clk.rate / 1000000,
133 (ath79_ref_clk.rate / 1000) % 1000);
134}
135
136/*
137 * Linux clock API
138 */
139struct clk *clk_get(struct device *dev, const char *id)
140{
141 if (!strcmp(id, "ref"))
142 return &ath79_ref_clk;
143
144 if (!strcmp(id, "cpu"))
145 return &ath79_cpu_clk;
146
147 if (!strcmp(id, "ddr"))
148 return &ath79_ddr_clk;
149
150 if (!strcmp(id, "ahb"))
151 return &ath79_ahb_clk;
152
153 if (!strcmp(id, "wdt"))
154 return &ath79_wdt_clk;
155
156 if (!strcmp(id, "uart"))
157 return &ath79_uart_clk;
158
159 return ERR_PTR(-ENOENT);
160}
161EXPORT_SYMBOL(clk_get);
162
163int clk_enable(struct clk *clk)
164{
165 return 0;
166}
167EXPORT_SYMBOL(clk_enable);
168
169void clk_disable(struct clk *clk)
170{
171}
172EXPORT_SYMBOL(clk_disable);
173
174unsigned long clk_get_rate(struct clk *clk)
175{
176 return clk->rate;
177}
178EXPORT_SYMBOL(clk_get_rate);
179
180void clk_put(struct clk *clk)
181{
182}
183EXPORT_SYMBOL(clk_put);
diff --git a/arch/mips/ath79/common.c b/arch/mips/ath79/common.c
new file mode 100644
index 000000000000..58f60e722a03
--- /dev/null
+++ b/arch/mips/ath79/common.c
@@ -0,0 +1,97 @@
1/*
2 * Atheros AR71XX/AR724X/AR913X common routines
3 *
4 * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published
9 * by the Free Software Foundation.
10 */
11
12#include <linux/kernel.h>
13#include <linux/module.h>
14#include <linux/types.h>
15#include <linux/spinlock.h>
16
17#include <asm/mach-ath79/ath79.h>
18#include <asm/mach-ath79/ar71xx_regs.h>
19#include "common.h"
20
21static DEFINE_SPINLOCK(ath79_device_reset_lock);
22
23u32 ath79_cpu_freq;
24EXPORT_SYMBOL_GPL(ath79_cpu_freq);
25
26u32 ath79_ahb_freq;
27EXPORT_SYMBOL_GPL(ath79_ahb_freq);
28
29u32 ath79_ddr_freq;
30EXPORT_SYMBOL_GPL(ath79_ddr_freq);
31
32enum ath79_soc_type ath79_soc;
33
34void __iomem *ath79_pll_base;
35void __iomem *ath79_reset_base;
36EXPORT_SYMBOL_GPL(ath79_reset_base);
37void __iomem *ath79_ddr_base;
38
39void ath79_ddr_wb_flush(u32 reg)
40{
41 void __iomem *flush_reg = ath79_ddr_base + reg;
42
43 /* Flush the DDR write buffer. */
44 __raw_writel(0x1, flush_reg);
45 while (__raw_readl(flush_reg) & 0x1)
46 ;
47
48 /* It must be run twice. */
49 __raw_writel(0x1, flush_reg);
50 while (__raw_readl(flush_reg) & 0x1)
51 ;
52}
53EXPORT_SYMBOL_GPL(ath79_ddr_wb_flush);
54
55void ath79_device_reset_set(u32 mask)
56{
57 unsigned long flags;
58 u32 reg;
59 u32 t;
60
61 if (soc_is_ar71xx())
62 reg = AR71XX_RESET_REG_RESET_MODULE;
63 else if (soc_is_ar724x())
64 reg = AR724X_RESET_REG_RESET_MODULE;
65 else if (soc_is_ar913x())
66 reg = AR913X_RESET_REG_RESET_MODULE;
67 else
68 BUG();
69
70 spin_lock_irqsave(&ath79_device_reset_lock, flags);
71 t = ath79_reset_rr(reg);
72 ath79_reset_wr(reg, t | mask);
73 spin_unlock_irqrestore(&ath79_device_reset_lock, flags);
74}
75EXPORT_SYMBOL_GPL(ath79_device_reset_set);
76
77void ath79_device_reset_clear(u32 mask)
78{
79 unsigned long flags;
80 u32 reg;
81 u32 t;
82
83 if (soc_is_ar71xx())
84 reg = AR71XX_RESET_REG_RESET_MODULE;
85 else if (soc_is_ar724x())
86 reg = AR724X_RESET_REG_RESET_MODULE;
87 else if (soc_is_ar913x())
88 reg = AR913X_RESET_REG_RESET_MODULE;
89 else
90 BUG();
91
92 spin_lock_irqsave(&ath79_device_reset_lock, flags);
93 t = ath79_reset_rr(reg);
94 ath79_reset_wr(reg, t & ~mask);
95 spin_unlock_irqrestore(&ath79_device_reset_lock, flags);
96}
97EXPORT_SYMBOL_GPL(ath79_device_reset_clear);
diff --git a/arch/mips/ath79/common.h b/arch/mips/ath79/common.h
new file mode 100644
index 000000000000..612a6b5d8702
--- /dev/null
+++ b/arch/mips/ath79/common.h
@@ -0,0 +1,26 @@
1/*
2 * Atheros AR71XX/AR724X/AR913X common definitions
3 *
4 * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
6 *
7 * Parts of this file are based on Atheros' 2.6.15 BSP
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
12 */
13
14#ifndef __ATH79_COMMON_H
15#define __ATH79_COMMON_H
16
17#include <linux/types.h>
18#include <linux/init.h>
19
20#define ATH79_MEM_SIZE_MIN (2 * 1024 * 1024)
21#define ATH79_MEM_SIZE_MAX (128 * 1024 * 1024)
22
23void ath79_clocks_init(void);
24void ath79_ddr_wb_flush(unsigned int reg);
25
26#endif /* __ATH79_COMMON_H */
diff --git a/arch/mips/ath79/dev-common.c b/arch/mips/ath79/dev-common.c
new file mode 100644
index 000000000000..3cfa10065d68
--- /dev/null
+++ b/arch/mips/ath79/dev-common.c
@@ -0,0 +1,67 @@
1/*
2 * Atheros AR71XX/AR724X/AR913X common devices
3 *
4 * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
6 *
7 * Parts of this file are based on Atheros' 2.6.15 BSP
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
12 */
13
14#include <linux/kernel.h>
15#include <linux/init.h>
16#include <linux/platform_device.h>
17#include <linux/serial_8250.h>
18#include <linux/clk.h>
19#include <linux/err.h>
20
21#include <asm/mach-ath79/ath79.h>
22#include <asm/mach-ath79/ar71xx_regs.h>
23#include "common.h"
24#include "dev-common.h"
25
26static struct resource ath79_uart_resources[] = {
27 {
28 .start = AR71XX_UART_BASE,
29 .end = AR71XX_UART_BASE + AR71XX_UART_SIZE - 1,
30 .flags = IORESOURCE_MEM,
31 },
32};
33
34#define AR71XX_UART_FLAGS (UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP)
35static struct plat_serial8250_port ath79_uart_data[] = {
36 {
37 .mapbase = AR71XX_UART_BASE,
38 .irq = ATH79_MISC_IRQ_UART,
39 .flags = AR71XX_UART_FLAGS,
40 .iotype = UPIO_MEM32,
41 .regshift = 2,
42 }, {
43 /* terminating entry */
44 }
45};
46
47static struct platform_device ath79_uart_device = {
48 .name = "serial8250",
49 .id = PLAT8250_DEV_PLATFORM,
50 .resource = ath79_uart_resources,
51 .num_resources = ARRAY_SIZE(ath79_uart_resources),
52 .dev = {
53 .platform_data = ath79_uart_data
54 },
55};
56
57void __init ath79_register_uart(void)
58{
59 struct clk *clk;
60
61 clk = clk_get(NULL, "uart");
62 if (IS_ERR(clk))
63 panic("unable to get UART clock, err=%ld", PTR_ERR(clk));
64
65 ath79_uart_data[0].uartclk = clk_get_rate(clk);
66 platform_device_register(&ath79_uart_device);
67}
diff --git a/arch/mips/ath79/dev-common.h b/arch/mips/ath79/dev-common.h
new file mode 100644
index 000000000000..248622cc7cd6
--- /dev/null
+++ b/arch/mips/ath79/dev-common.h
@@ -0,0 +1,17 @@
1/*
2 * Atheros AR71XX/AR724X/AR913X common devices
3 *
4 * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published
9 * by the Free Software Foundation.
10 */
11
12#ifndef _ATH79_DEV_COMMON_H
13#define _ATH79_DEV_COMMON_H
14
15void ath79_register_uart(void);
16
17#endif /* _ATH79_DEV_COMMON_H */
diff --git a/arch/mips/ath79/early_printk.c b/arch/mips/ath79/early_printk.c
new file mode 100644
index 000000000000..7499b0e9df26
--- /dev/null
+++ b/arch/mips/ath79/early_printk.c
@@ -0,0 +1,36 @@
1/*
2 * Atheros AR71XX/AR724X/AR913X SoC early printk support
3 *
4 * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published
9 * by the Free Software Foundation.
10 */
11
12#include <linux/io.h>
13#include <linux/serial_reg.h>
14#include <asm/addrspace.h>
15
16#include <asm/mach-ath79/ar71xx_regs.h>
17
18static inline void prom_wait_thre(void __iomem *base)
19{
20 u32 lsr;
21
22 do {
23 lsr = __raw_readl(base + UART_LSR * 4);
24 if (lsr & UART_LSR_THRE)
25 break;
26 } while (1);
27}
28
29void prom_putchar(unsigned char ch)
30{
31 void __iomem *base = (void __iomem *)(KSEG1ADDR(AR71XX_UART_BASE));
32
33 prom_wait_thre(base);
34 __raw_writel(ch, base + UART_TX * 4);
35 prom_wait_thre(base);
36}
diff --git a/arch/mips/ath79/irq.c b/arch/mips/ath79/irq.c
new file mode 100644
index 000000000000..1bf7f719ba53
--- /dev/null
+++ b/arch/mips/ath79/irq.c
@@ -0,0 +1,187 @@
1/*
2 * Atheros AR71xx/AR724x/AR913x specific interrupt handling
3 *
4 * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
6 *
7 * Parts of this file are based on Atheros' 2.6.15 BSP
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
12 */
13
14#include <linux/kernel.h>
15#include <linux/init.h>
16#include <linux/interrupt.h>
17#include <linux/irq.h>
18
19#include <asm/irq_cpu.h>
20#include <asm/mipsregs.h>
21
22#include <asm/mach-ath79/ath79.h>
23#include <asm/mach-ath79/ar71xx_regs.h>
24#include "common.h"
25
26static unsigned int ath79_ip2_flush_reg;
27static unsigned int ath79_ip3_flush_reg;
28
29static void ath79_misc_irq_handler(unsigned int irq, struct irq_desc *desc)
30{
31 void __iomem *base = ath79_reset_base;
32 u32 pending;
33
34 pending = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS) &
35 __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
36
37 if (pending & MISC_INT_UART)
38 generic_handle_irq(ATH79_MISC_IRQ_UART);
39
40 else if (pending & MISC_INT_DMA)
41 generic_handle_irq(ATH79_MISC_IRQ_DMA);
42
43 else if (pending & MISC_INT_PERFC)
44 generic_handle_irq(ATH79_MISC_IRQ_PERFC);
45
46 else if (pending & MISC_INT_TIMER)
47 generic_handle_irq(ATH79_MISC_IRQ_TIMER);
48
49 else if (pending & MISC_INT_OHCI)
50 generic_handle_irq(ATH79_MISC_IRQ_OHCI);
51
52 else if (pending & MISC_INT_ERROR)
53 generic_handle_irq(ATH79_MISC_IRQ_ERROR);
54
55 else if (pending & MISC_INT_GPIO)
56 generic_handle_irq(ATH79_MISC_IRQ_GPIO);
57
58 else if (pending & MISC_INT_WDOG)
59 generic_handle_irq(ATH79_MISC_IRQ_WDOG);
60
61 else
62 spurious_interrupt();
63}
64
65static void ar71xx_misc_irq_unmask(unsigned int irq)
66{
67 void __iomem *base = ath79_reset_base;
68 u32 t;
69
70 irq -= ATH79_MISC_IRQ_BASE;
71
72 t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
73 __raw_writel(t | (1 << irq), base + AR71XX_RESET_REG_MISC_INT_ENABLE);
74
75 /* flush write */
76 __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
77}
78
79static void ar71xx_misc_irq_mask(unsigned int irq)
80{
81 void __iomem *base = ath79_reset_base;
82 u32 t;
83
84 irq -= ATH79_MISC_IRQ_BASE;
85
86 t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
87 __raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_MISC_INT_ENABLE);
88
89 /* flush write */
90 __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
91}
92
93static void ar724x_misc_irq_ack(unsigned int irq)
94{
95 void __iomem *base = ath79_reset_base;
96 u32 t;
97
98 irq -= ATH79_MISC_IRQ_BASE;
99
100 t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS);
101 __raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_MISC_INT_STATUS);
102
103 /* flush write */
104 __raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS);
105}
106
107static struct irq_chip ath79_misc_irq_chip = {
108 .name = "MISC",
109 .unmask = ar71xx_misc_irq_unmask,
110 .mask = ar71xx_misc_irq_mask,
111};
112
113static void __init ath79_misc_irq_init(void)
114{
115 void __iomem *base = ath79_reset_base;
116 int i;
117
118 __raw_writel(0, base + AR71XX_RESET_REG_MISC_INT_ENABLE);
119 __raw_writel(0, base + AR71XX_RESET_REG_MISC_INT_STATUS);
120
121 if (soc_is_ar71xx() || soc_is_ar913x())
122 ath79_misc_irq_chip.mask_ack = ar71xx_misc_irq_mask;
123 else if (soc_is_ar724x())
124 ath79_misc_irq_chip.ack = ar724x_misc_irq_ack;
125 else
126 BUG();
127
128 for (i = ATH79_MISC_IRQ_BASE;
129 i < ATH79_MISC_IRQ_BASE + ATH79_MISC_IRQ_COUNT; i++) {
130 irq_desc[i].status = IRQ_DISABLED;
131 set_irq_chip_and_handler(i, &ath79_misc_irq_chip,
132 handle_level_irq);
133 }
134
135 set_irq_chained_handler(ATH79_CPU_IRQ_MISC, ath79_misc_irq_handler);
136}
137
138asmlinkage void plat_irq_dispatch(void)
139{
140 unsigned long pending;
141
142 pending = read_c0_status() & read_c0_cause() & ST0_IM;
143
144 if (pending & STATUSF_IP7)
145 do_IRQ(ATH79_CPU_IRQ_TIMER);
146
147 else if (pending & STATUSF_IP2) {
148 ath79_ddr_wb_flush(ath79_ip2_flush_reg);
149 do_IRQ(ATH79_CPU_IRQ_IP2);
150 }
151
152 else if (pending & STATUSF_IP4)
153 do_IRQ(ATH79_CPU_IRQ_GE0);
154
155 else if (pending & STATUSF_IP5)
156 do_IRQ(ATH79_CPU_IRQ_GE1);
157
158 else if (pending & STATUSF_IP3) {
159 ath79_ddr_wb_flush(ath79_ip3_flush_reg);
160 do_IRQ(ATH79_CPU_IRQ_USB);
161 }
162
163 else if (pending & STATUSF_IP6)
164 do_IRQ(ATH79_CPU_IRQ_MISC);
165
166 else
167 spurious_interrupt();
168}
169
170void __init arch_init_irq(void)
171{
172 if (soc_is_ar71xx()) {
173 ath79_ip2_flush_reg = AR71XX_DDR_REG_FLUSH_PCI;
174 ath79_ip3_flush_reg = AR71XX_DDR_REG_FLUSH_USB;
175 } else if (soc_is_ar724x()) {
176 ath79_ip2_flush_reg = AR724X_DDR_REG_FLUSH_PCIE;
177 ath79_ip3_flush_reg = AR724X_DDR_REG_FLUSH_USB;
178 } else if (soc_is_ar913x()) {
179 ath79_ip2_flush_reg = AR913X_DDR_REG_FLUSH_WMAC;
180 ath79_ip3_flush_reg = AR913X_DDR_REG_FLUSH_USB;
181 } else
182 BUG();
183
184 cp0_perfcount_irq = ATH79_MISC_IRQ_PERFC;
185 mips_cpu_irq_init();
186 ath79_misc_irq_init();
187}
diff --git a/arch/mips/ath79/prom.c b/arch/mips/ath79/prom.c
new file mode 100644
index 000000000000..e9cbd7c2918f
--- /dev/null
+++ b/arch/mips/ath79/prom.c
@@ -0,0 +1,57 @@
1/*
2 * Atheros AR71XX/AR724X/AR913X specific prom routines
3 *
4 * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published
9 * by the Free Software Foundation.
10 */
11
12#include <linux/kernel.h>
13#include <linux/init.h>
14#include <linux/io.h>
15#include <linux/string.h>
16
17#include <asm/bootinfo.h>
18#include <asm/addrspace.h>
19
20#include "common.h"
21
22static inline int is_valid_ram_addr(void *addr)
23{
24 if (((u32) addr > KSEG0) &&
25 ((u32) addr < (KSEG0 + ATH79_MEM_SIZE_MAX)))
26 return 1;
27
28 if (((u32) addr > KSEG1) &&
29 ((u32) addr < (KSEG1 + ATH79_MEM_SIZE_MAX)))
30 return 1;
31
32 return 0;
33}
34
35static __init void ath79_prom_init_cmdline(int argc, char **argv)
36{
37 int i;
38
39 if (!is_valid_ram_addr(argv))
40 return;
41
42 for (i = 0; i < argc; i++)
43 if (is_valid_ram_addr(argv[i])) {
44 strlcat(arcs_cmdline, " ", sizeof(arcs_cmdline));
45 strlcat(arcs_cmdline, argv[i], sizeof(arcs_cmdline));
46 }
47}
48
49void __init prom_init(void)
50{
51 ath79_prom_init_cmdline(fw_arg0, (char **)fw_arg1);
52}
53
54void __init prom_free_prom_memory(void)
55{
56 /* We do not have to prom memory to free */
57}
diff --git a/arch/mips/ath79/setup.c b/arch/mips/ath79/setup.c
new file mode 100644
index 000000000000..175def860165
--- /dev/null
+++ b/arch/mips/ath79/setup.c
@@ -0,0 +1,190 @@
1/*
2 * Atheros AR71XX/AR724X/AR913X specific setup
3 *
4 * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
6 *
7 * Parts of this file are based on Atheros' 2.6.15 BSP
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
12 */
13
14#include <linux/kernel.h>
15#include <linux/init.h>
16#include <linux/bootmem.h>
17#include <linux/err.h>
18#include <linux/clk.h>
19
20#include <asm/bootinfo.h>
21#include <asm/time.h> /* for mips_hpt_frequency */
22#include <asm/reboot.h> /* for _machine_{restart,halt} */
23
24#include <asm/mach-ath79/ath79.h>
25#include <asm/mach-ath79/ar71xx_regs.h>
26#include "common.h"
27#include "dev-common.h"
28
29#define ATH79_SYS_TYPE_LEN 64
30
31#define AR71XX_BASE_FREQ 40000000
32#define AR724X_BASE_FREQ 5000000
33#define AR913X_BASE_FREQ 5000000
34
35static char ath79_sys_type[ATH79_SYS_TYPE_LEN];
36
37static void ath79_restart(char *command)
38{
39 ath79_device_reset_set(AR71XX_RESET_FULL_CHIP);
40 for (;;)
41 if (cpu_wait)
42 cpu_wait();
43}
44
45static void ath79_halt(void)
46{
47 while (1)
48 cpu_wait();
49}
50
51static void __init ath79_detect_mem_size(void)
52{
53 unsigned long size;
54
55 for (size = ATH79_MEM_SIZE_MIN; size < ATH79_MEM_SIZE_MAX;
56 size <<= 1) {
57 if (!memcmp(ath79_detect_mem_size,
58 ath79_detect_mem_size + size, 1024))
59 break;
60 }
61
62 add_memory_region(0, size, BOOT_MEM_RAM);
63}
64
65static void __init ath79_detect_sys_type(void)
66{
67 char *chip = "????";
68 u32 id;
69 u32 major;
70 u32 minor;
71 u32 rev = 0;
72
73 id = ath79_reset_rr(AR71XX_RESET_REG_REV_ID);
74 major = id & REV_ID_MAJOR_MASK;
75
76 switch (major) {
77 case REV_ID_MAJOR_AR71XX:
78 minor = id & AR71XX_REV_ID_MINOR_MASK;
79 rev = id >> AR71XX_REV_ID_REVISION_SHIFT;
80 rev &= AR71XX_REV_ID_REVISION_MASK;
81 switch (minor) {
82 case AR71XX_REV_ID_MINOR_AR7130:
83 ath79_soc = ATH79_SOC_AR7130;
84 chip = "7130";
85 break;
86
87 case AR71XX_REV_ID_MINOR_AR7141:
88 ath79_soc = ATH79_SOC_AR7141;
89 chip = "7141";
90 break;
91
92 case AR71XX_REV_ID_MINOR_AR7161:
93 ath79_soc = ATH79_SOC_AR7161;
94 chip = "7161";
95 break;
96 }
97 break;
98
99 case REV_ID_MAJOR_AR7240:
100 ath79_soc = ATH79_SOC_AR7240;
101 chip = "7240";
102 rev = (id & AR724X_REV_ID_REVISION_MASK);
103 break;
104
105 case REV_ID_MAJOR_AR7241:
106 ath79_soc = ATH79_SOC_AR7241;
107 chip = "7241";
108 rev = (id & AR724X_REV_ID_REVISION_MASK);
109 break;
110
111 case REV_ID_MAJOR_AR7242:
112 ath79_soc = ATH79_SOC_AR7242;
113 chip = "7242";
114 rev = (id & AR724X_REV_ID_REVISION_MASK);
115 break;
116
117 case REV_ID_MAJOR_AR913X:
118 minor = id & AR913X_REV_ID_MINOR_MASK;
119 rev = id >> AR913X_REV_ID_REVISION_SHIFT;
120 rev &= AR913X_REV_ID_REVISION_MASK;
121 switch (minor) {
122 case AR913X_REV_ID_MINOR_AR9130:
123 ath79_soc = ATH79_SOC_AR9130;
124 chip = "9130";
125 break;
126
127 case AR913X_REV_ID_MINOR_AR9132:
128 ath79_soc = ATH79_SOC_AR9132;
129 chip = "9132";
130 break;
131 }
132 break;
133
134 default:
135 panic("ath79: unknown SoC, id:0x%08x\n", id);
136 }
137
138 sprintf(ath79_sys_type, "Atheros AR%s rev %u", chip, rev);
139 pr_info("SoC: %s\n", ath79_sys_type);
140}
141
142const char *get_system_type(void)
143{
144 return ath79_sys_type;
145}
146
147unsigned int __cpuinit get_c0_compare_int(void)
148{
149 return CP0_LEGACY_COMPARE_IRQ;
150}
151
152void __init plat_mem_setup(void)
153{
154 set_io_port_base(KSEG1);
155
156 ath79_reset_base = ioremap_nocache(AR71XX_RESET_BASE,
157 AR71XX_RESET_SIZE);
158 ath79_pll_base = ioremap_nocache(AR71XX_PLL_BASE,
159 AR71XX_PLL_SIZE);
160
161 ath79_ddr_base = ioremap_nocache(AR71XX_DDR_CTRL_BASE,
162 AR71XX_DDR_CTRL_SIZE);
163
164 ath79_detect_sys_type();
165 ath79_detect_mem_size();
166 ath79_clocks_init();
167
168 _machine_restart = ath79_restart;
169 _machine_halt = ath79_halt;
170 pm_power_off = ath79_halt;
171}
172
173void __init plat_time_init(void)
174{
175 struct clk *clk;
176
177 clk = clk_get(NULL, "cpu");
178 if (IS_ERR(clk))
179 panic("unable to get CPU clock, err=%ld", PTR_ERR(clk));
180
181 mips_hpt_frequency = clk_get_rate(clk) / 2;
182}
183
184static int __init ath79_setup(void)
185{
186 ath79_register_uart();
187 return 0;
188}
189
190arch_initcall(ath79_setup);
diff --git a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
new file mode 100644
index 000000000000..5a9e5e179463
--- /dev/null
+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
@@ -0,0 +1,207 @@
1/*
2 * Atheros AR71XX/AR724X/AR913X SoC register definitions
3 *
4 * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
6 *
7 * Parts of this file are based on Atheros' 2.6.15 BSP
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
12 */
13
14#ifndef __ASM_MACH_AR71XX_REGS_H
15#define __ASM_MACH_AR71XX_REGS_H
16
17#include <linux/types.h>
18#include <linux/init.h>
19#include <linux/io.h>
20#include <linux/bitops.h>
21
22#define AR71XX_APB_BASE 0x18000000
23
24#define AR71XX_DDR_CTRL_BASE (AR71XX_APB_BASE + 0x00000000)
25#define AR71XX_DDR_CTRL_SIZE 0x100
26#define AR71XX_UART_BASE (AR71XX_APB_BASE + 0x00020000)
27#define AR71XX_UART_SIZE 0x100
28#define AR71XX_PLL_BASE (AR71XX_APB_BASE + 0x00050000)
29#define AR71XX_PLL_SIZE 0x100
30#define AR71XX_RESET_BASE (AR71XX_APB_BASE + 0x00060000)
31#define AR71XX_RESET_SIZE 0x100
32
33/*
34 * DDR_CTRL block
35 */
36#define AR71XX_DDR_REG_PCI_WIN0 0x7c
37#define AR71XX_DDR_REG_PCI_WIN1 0x80
38#define AR71XX_DDR_REG_PCI_WIN2 0x84
39#define AR71XX_DDR_REG_PCI_WIN3 0x88
40#define AR71XX_DDR_REG_PCI_WIN4 0x8c
41#define AR71XX_DDR_REG_PCI_WIN5 0x90
42#define AR71XX_DDR_REG_PCI_WIN6 0x94
43#define AR71XX_DDR_REG_PCI_WIN7 0x98
44#define AR71XX_DDR_REG_FLUSH_GE0 0x9c
45#define AR71XX_DDR_REG_FLUSH_GE1 0xa0
46#define AR71XX_DDR_REG_FLUSH_USB 0xa4
47#define AR71XX_DDR_REG_FLUSH_PCI 0xa8
48
49#define AR724X_DDR_REG_FLUSH_GE0 0x7c
50#define AR724X_DDR_REG_FLUSH_GE1 0x80
51#define AR724X_DDR_REG_FLUSH_USB 0x84
52#define AR724X_DDR_REG_FLUSH_PCIE 0x88
53
54#define AR913X_DDR_REG_FLUSH_GE0 0x7c
55#define AR913X_DDR_REG_FLUSH_GE1 0x80
56#define AR913X_DDR_REG_FLUSH_USB 0x84
57#define AR913X_DDR_REG_FLUSH_WMAC 0x88
58
59/*
60 * PLL block
61 */
62#define AR71XX_PLL_REG_CPU_CONFIG 0x00
63#define AR71XX_PLL_REG_SEC_CONFIG 0x04
64#define AR71XX_PLL_REG_ETH0_INT_CLOCK 0x10
65#define AR71XX_PLL_REG_ETH1_INT_CLOCK 0x14
66
67#define AR71XX_PLL_DIV_SHIFT 3
68#define AR71XX_PLL_DIV_MASK 0x1f
69#define AR71XX_CPU_DIV_SHIFT 16
70#define AR71XX_CPU_DIV_MASK 0x3
71#define AR71XX_DDR_DIV_SHIFT 18
72#define AR71XX_DDR_DIV_MASK 0x3
73#define AR71XX_AHB_DIV_SHIFT 20
74#define AR71XX_AHB_DIV_MASK 0x7
75
76#define AR724X_PLL_REG_CPU_CONFIG 0x00
77#define AR724X_PLL_REG_PCIE_CONFIG 0x18
78
79#define AR724X_PLL_DIV_SHIFT 0
80#define AR724X_PLL_DIV_MASK 0x3ff
81#define AR724X_PLL_REF_DIV_SHIFT 10
82#define AR724X_PLL_REF_DIV_MASK 0xf
83#define AR724X_AHB_DIV_SHIFT 19
84#define AR724X_AHB_DIV_MASK 0x1
85#define AR724X_DDR_DIV_SHIFT 22
86#define AR724X_DDR_DIV_MASK 0x3
87
88#define AR913X_PLL_REG_CPU_CONFIG 0x00
89#define AR913X_PLL_REG_ETH_CONFIG 0x04
90#define AR913X_PLL_REG_ETH0_INT_CLOCK 0x14
91#define AR913X_PLL_REG_ETH1_INT_CLOCK 0x18
92
93#define AR913X_PLL_DIV_SHIFT 0
94#define AR913X_PLL_DIV_MASK 0x3ff
95#define AR913X_DDR_DIV_SHIFT 22
96#define AR913X_DDR_DIV_MASK 0x3
97#define AR913X_AHB_DIV_SHIFT 19
98#define AR913X_AHB_DIV_MASK 0x1
99
100/*
101 * RESET block
102 */
103#define AR71XX_RESET_REG_TIMER 0x00
104#define AR71XX_RESET_REG_TIMER_RELOAD 0x04
105#define AR71XX_RESET_REG_WDOG_CTRL 0x08
106#define AR71XX_RESET_REG_WDOG 0x0c
107#define AR71XX_RESET_REG_MISC_INT_STATUS 0x10
108#define AR71XX_RESET_REG_MISC_INT_ENABLE 0x14
109#define AR71XX_RESET_REG_PCI_INT_STATUS 0x18
110#define AR71XX_RESET_REG_PCI_INT_ENABLE 0x1c
111#define AR71XX_RESET_REG_GLOBAL_INT_STATUS 0x20
112#define AR71XX_RESET_REG_RESET_MODULE 0x24
113#define AR71XX_RESET_REG_PERFC_CTRL 0x2c
114#define AR71XX_RESET_REG_PERFC0 0x30
115#define AR71XX_RESET_REG_PERFC1 0x34
116#define AR71XX_RESET_REG_REV_ID 0x90
117
118#define AR913X_RESET_REG_GLOBAL_INT_STATUS 0x18
119#define AR913X_RESET_REG_RESET_MODULE 0x1c
120#define AR913X_RESET_REG_PERF_CTRL 0x20
121#define AR913X_RESET_REG_PERFC0 0x24
122#define AR913X_RESET_REG_PERFC1 0x28
123
124#define AR724X_RESET_REG_RESET_MODULE 0x1c
125
126#define MISC_INT_DMA BIT(7)
127#define MISC_INT_OHCI BIT(6)
128#define MISC_INT_PERFC BIT(5)
129#define MISC_INT_WDOG BIT(4)
130#define MISC_INT_UART BIT(3)
131#define MISC_INT_GPIO BIT(2)
132#define MISC_INT_ERROR BIT(1)
133#define MISC_INT_TIMER BIT(0)
134
135#define AR71XX_RESET_EXTERNAL BIT(28)
136#define AR71XX_RESET_FULL_CHIP BIT(24)
137#define AR71XX_RESET_CPU_NMI BIT(21)
138#define AR71XX_RESET_CPU_COLD BIT(20)
139#define AR71XX_RESET_DMA BIT(19)
140#define AR71XX_RESET_SLIC BIT(18)
141#define AR71XX_RESET_STEREO BIT(17)
142#define AR71XX_RESET_DDR BIT(16)
143#define AR71XX_RESET_GE1_MAC BIT(13)
144#define AR71XX_RESET_GE1_PHY BIT(12)
145#define AR71XX_RESET_USBSUS_OVERRIDE BIT(10)
146#define AR71XX_RESET_GE0_MAC BIT(9)
147#define AR71XX_RESET_GE0_PHY BIT(8)
148#define AR71XX_RESET_USB_OHCI_DLL BIT(6)
149#define AR71XX_RESET_USB_HOST BIT(5)
150#define AR71XX_RESET_USB_PHY BIT(4)
151#define AR71XX_RESET_PCI_BUS BIT(1)
152#define AR71XX_RESET_PCI_CORE BIT(0)
153
154#define AR724X_RESET_GE1_MDIO BIT(23)
155#define AR724X_RESET_GE0_MDIO BIT(22)
156#define AR724X_RESET_PCIE_PHY_SERIAL BIT(10)
157#define AR724X_RESET_PCIE_PHY BIT(7)
158#define AR724X_RESET_PCIE BIT(6)
159#define AR724X_RESET_OHCI_DLL BIT(3)
160
161#define AR913X_RESET_AMBA2WMAC BIT(22)
162
163#define REV_ID_MAJOR_MASK 0xfff0
164#define REV_ID_MAJOR_AR71XX 0x00a0
165#define REV_ID_MAJOR_AR913X 0x00b0
166#define REV_ID_MAJOR_AR7240 0x00c0
167#define REV_ID_MAJOR_AR7241 0x0100
168#define REV_ID_MAJOR_AR7242 0x1100
169
170#define AR71XX_REV_ID_MINOR_MASK 0x3
171#define AR71XX_REV_ID_MINOR_AR7130 0x0
172#define AR71XX_REV_ID_MINOR_AR7141 0x1
173#define AR71XX_REV_ID_MINOR_AR7161 0x2
174#define AR71XX_REV_ID_REVISION_MASK 0x3
175#define AR71XX_REV_ID_REVISION_SHIFT 2
176
177#define AR913X_REV_ID_MINOR_MASK 0x3
178#define AR913X_REV_ID_MINOR_AR9130 0x0
179#define AR913X_REV_ID_MINOR_AR9132 0x1
180#define AR913X_REV_ID_REVISION_MASK 0x3
181#define AR913X_REV_ID_REVISION_SHIFT 2
182
183#define AR724X_REV_ID_REVISION_MASK 0x3
184
185/*
186 * SPI block
187 */
188#define AR71XX_SPI_REG_FS 0x00 /* Function Select */
189#define AR71XX_SPI_REG_CTRL 0x04 /* SPI Control */
190#define AR71XX_SPI_REG_IOC 0x08 /* SPI I/O Control */
191#define AR71XX_SPI_REG_RDS 0x0c /* Read Data Shift */
192
193#define AR71XX_SPI_FS_GPIO BIT(0) /* Enable GPIO mode */
194
195#define AR71XX_SPI_CTRL_RD BIT(6) /* Remap Disable */
196#define AR71XX_SPI_CTRL_DIV_MASK 0x3f
197
198#define AR71XX_SPI_IOC_DO BIT(0) /* Data Out pin */
199#define AR71XX_SPI_IOC_CLK BIT(8) /* CLK pin */
200#define AR71XX_SPI_IOC_CS(n) BIT(16 + (n))
201#define AR71XX_SPI_IOC_CS0 AR71XX_SPI_IOC_CS(0)
202#define AR71XX_SPI_IOC_CS1 AR71XX_SPI_IOC_CS(1)
203#define AR71XX_SPI_IOC_CS2 AR71XX_SPI_IOC_CS(2)
204#define AR71XX_SPI_IOC_CS_ALL (AR71XX_SPI_IOC_CS0 | AR71XX_SPI_IOC_CS1 | \
205 AR71XX_SPI_IOC_CS2)
206
207#endif /* __ASM_MACH_AR71XX_REGS_H */
diff --git a/arch/mips/include/asm/mach-ath79/ath79.h b/arch/mips/include/asm/mach-ath79/ath79.h
new file mode 100644
index 000000000000..6a9f168506fe
--- /dev/null
+++ b/arch/mips/include/asm/mach-ath79/ath79.h
@@ -0,0 +1,96 @@
1/*
2 * Atheros AR71XX/AR724X/AR913X common definitions
3 *
4 * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
6 *
7 * Parts of this file are based on Atheros' 2.6.15 BSP
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
12 */
13
14#ifndef __ASM_MACH_ATH79_H
15#define __ASM_MACH_ATH79_H
16
17#include <linux/types.h>
18#include <linux/io.h>
19
20enum ath79_soc_type {
21 ATH79_SOC_UNKNOWN,
22 ATH79_SOC_AR7130,
23 ATH79_SOC_AR7141,
24 ATH79_SOC_AR7161,
25 ATH79_SOC_AR7240,
26 ATH79_SOC_AR7241,
27 ATH79_SOC_AR7242,
28 ATH79_SOC_AR9130,
29 ATH79_SOC_AR9132
30};
31
32extern enum ath79_soc_type ath79_soc;
33
34static inline int soc_is_ar71xx(void)
35{
36 return (ath79_soc == ATH79_SOC_AR7130 ||
37 ath79_soc == ATH79_SOC_AR7141 ||
38 ath79_soc == ATH79_SOC_AR7161);
39}
40
41static inline int soc_is_ar724x(void)
42{
43 return (ath79_soc == ATH79_SOC_AR7240 ||
44 ath79_soc == ATH79_SOC_AR7241 ||
45 ath79_soc == ATH79_SOC_AR7242);
46}
47
48static inline int soc_is_ar7240(void)
49{
50 return (ath79_soc == ATH79_SOC_AR7240);
51}
52
53static inline int soc_is_ar7241(void)
54{
55 return (ath79_soc == ATH79_SOC_AR7241);
56}
57
58static inline int soc_is_ar7242(void)
59{
60 return (ath79_soc == ATH79_SOC_AR7242);
61}
62
63static inline int soc_is_ar913x(void)
64{
65 return (ath79_soc == ATH79_SOC_AR9130 ||
66 ath79_soc == ATH79_SOC_AR9132);
67}
68
69extern void __iomem *ath79_ddr_base;
70extern void __iomem *ath79_pll_base;
71extern void __iomem *ath79_reset_base;
72
73static inline void ath79_pll_wr(unsigned reg, u32 val)
74{
75 __raw_writel(val, ath79_pll_base + reg);
76}
77
78static inline u32 ath79_pll_rr(unsigned reg)
79{
80 return __raw_readl(ath79_pll_base + reg);
81}
82
83static inline void ath79_reset_wr(unsigned reg, u32 val)
84{
85 __raw_writel(val, ath79_reset_base + reg);
86}
87
88static inline u32 ath79_reset_rr(unsigned reg)
89{
90 return __raw_readl(ath79_reset_base + reg);
91}
92
93void ath79_device_reset_set(u32 mask);
94void ath79_device_reset_clear(u32 mask);
95
96#endif /* __ASM_MACH_ATH79_H */
diff --git a/arch/mips/include/asm/mach-ath79/cpu-feature-overrides.h b/arch/mips/include/asm/mach-ath79/cpu-feature-overrides.h
new file mode 100644
index 000000000000..4476fa03bf36
--- /dev/null
+++ b/arch/mips/include/asm/mach-ath79/cpu-feature-overrides.h
@@ -0,0 +1,56 @@
1/*
2 * Atheros AR71XX/AR724X/AR913X specific CPU feature overrides
3 *
4 * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
6 *
7 * This file was derived from: include/asm-mips/cpu-features.h
8 * Copyright (C) 2003, 2004 Ralf Baechle
9 * Copyright (C) 2004 Maciej W. Rozycki
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License version 2 as published
13 * by the Free Software Foundation.
14 *
15 */
16#ifndef __ASM_MACH_ATH79_CPU_FEATURE_OVERRIDES_H
17#define __ASM_MACH_ATH79_CPU_FEATURE_OVERRIDES_H
18
19#define cpu_has_tlb 1
20#define cpu_has_4kex 1
21#define cpu_has_3k_cache 0
22#define cpu_has_4k_cache 1
23#define cpu_has_tx39_cache 0
24#define cpu_has_sb1_cache 0
25#define cpu_has_fpu 0
26#define cpu_has_32fpr 0
27#define cpu_has_counter 1
28#define cpu_has_watch 1
29#define cpu_has_divec 1
30
31#define cpu_has_prefetch 1
32#define cpu_has_ejtag 1
33#define cpu_has_llsc 1
34
35#define cpu_has_mips16 1
36#define cpu_has_mdmx 0
37#define cpu_has_mips3d 0
38#define cpu_has_smartmips 0
39
40#define cpu_has_mips32r1 1
41#define cpu_has_mips32r2 1
42#define cpu_has_mips64r1 0
43#define cpu_has_mips64r2 0
44
45#define cpu_has_dsp 0
46#define cpu_has_mipsmt 0
47
48#define cpu_has_64bits 0
49#define cpu_has_64bit_zero_reg 0
50#define cpu_has_64bit_gp_regs 0
51#define cpu_has_64bit_addresses 0
52
53#define cpu_dcache_line_size() 32
54#define cpu_icache_line_size() 32
55
56#endif /* __ASM_MACH_ATH79_CPU_FEATURE_OVERRIDES_H */
diff --git a/arch/mips/include/asm/mach-ath79/irq.h b/arch/mips/include/asm/mach-ath79/irq.h
new file mode 100644
index 000000000000..189bc6eb9c10
--- /dev/null
+++ b/arch/mips/include/asm/mach-ath79/irq.h
@@ -0,0 +1,36 @@
1/*
2 * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
3 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published
7 * by the Free Software Foundation.
8 */
9#ifndef __ASM_MACH_ATH79_IRQ_H
10#define __ASM_MACH_ATH79_IRQ_H
11
12#define MIPS_CPU_IRQ_BASE 0
13#define NR_IRQS 16
14
15#define ATH79_MISC_IRQ_BASE 8
16#define ATH79_MISC_IRQ_COUNT 8
17
18#define ATH79_CPU_IRQ_IP2 (MIPS_CPU_IRQ_BASE + 2)
19#define ATH79_CPU_IRQ_USB (MIPS_CPU_IRQ_BASE + 3)
20#define ATH79_CPU_IRQ_GE0 (MIPS_CPU_IRQ_BASE + 4)
21#define ATH79_CPU_IRQ_GE1 (MIPS_CPU_IRQ_BASE + 5)
22#define ATH79_CPU_IRQ_MISC (MIPS_CPU_IRQ_BASE + 6)
23#define ATH79_CPU_IRQ_TIMER (MIPS_CPU_IRQ_BASE + 7)
24
25#define ATH79_MISC_IRQ_TIMER (ATH79_MISC_IRQ_BASE + 0)
26#define ATH79_MISC_IRQ_ERROR (ATH79_MISC_IRQ_BASE + 1)
27#define ATH79_MISC_IRQ_GPIO (ATH79_MISC_IRQ_BASE + 2)
28#define ATH79_MISC_IRQ_UART (ATH79_MISC_IRQ_BASE + 3)
29#define ATH79_MISC_IRQ_WDOG (ATH79_MISC_IRQ_BASE + 4)
30#define ATH79_MISC_IRQ_PERFC (ATH79_MISC_IRQ_BASE + 5)
31#define ATH79_MISC_IRQ_OHCI (ATH79_MISC_IRQ_BASE + 6)
32#define ATH79_MISC_IRQ_DMA (ATH79_MISC_IRQ_BASE + 7)
33
34#include_next <irq.h>
35
36#endif /* __ASM_MACH_ATH79_IRQ_H */
diff --git a/arch/mips/include/asm/mach-ath79/kernel-entry-init.h b/arch/mips/include/asm/mach-ath79/kernel-entry-init.h
new file mode 100644
index 000000000000..d8d046bccc8e
--- /dev/null
+++ b/arch/mips/include/asm/mach-ath79/kernel-entry-init.h
@@ -0,0 +1,32 @@
1/*
2 * Atheros AR71XX/AR724X/AR913X specific kernel entry setup
3 *
4 * Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 *
10 */
11#ifndef __ASM_MACH_ATH79_KERNEL_ENTRY_H
12#define __ASM_MACH_ATH79_KERNEL_ENTRY_H
13
14 /*
15 * Some bootloaders set the 'Kseg0 coherency algorithm' to
16 * 'Cacheable, noncoherent, write-through, no write allocate'
17 * and this cause performance issues. Let's go and change it to
18 * 'Cacheable, noncoherent, write-back, write allocate'
19 */
20 .macro kernel_entry_setup
21 mfc0 t0, CP0_CONFIG
22 li t1, ~CONF_CM_CMASK
23 and t0, t1
24 ori t0, CONF_CM_CACHABLE_NONCOHERENT
25 mtc0 t0, CP0_CONFIG
26 nop
27 .endm
28
29 .macro smp_slave_setup
30 .endm
31
32#endif /* __ASM_MACH_ATH79_KERNEL_ENTRY_H */
diff --git a/arch/mips/include/asm/mach-ath79/war.h b/arch/mips/include/asm/mach-ath79/war.h
new file mode 100644
index 000000000000..323d9f1d8c45
--- /dev/null
+++ b/arch/mips/include/asm/mach-ath79/war.h
@@ -0,0 +1,25 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
7 */
8#ifndef __ASM_MACH_ATH79_WAR_H
9#define __ASM_MACH_ATH79_WAR_H
10
11#define R4600_V1_INDEX_ICACHEOP_WAR 0
12#define R4600_V1_HIT_CACHEOP_WAR 0
13#define R4600_V2_HIT_CACHEOP_WAR 0
14#define R5432_CP0_INTERRUPT_WAR 0
15#define BCM1250_M3_WAR 0
16#define SIBYTE_1956_WAR 0
17#define MIPS4K_ICACHE_REFILL_WAR 0
18#define MIPS_CACHE_SYNC_WAR 0
19#define TX49XX_ICACHE_INDEX_INV_WAR 0
20#define RM9000_CDEX_SMP_WAR 0
21#define ICACHE_REFILLS_WORKAROUND_WAR 0
22#define R10000_LLSC_WAR 0
23#define MIPS34K_MISSED_ITLB_WAR 0
24
25#endif /* __ASM_MACH_ATH79_WAR_H */
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-01 11:57:36 -0500