aboutsummaryrefslogtreecommitdiffstats
path: root/arch/mips
diff options
context:
space:
mode:
authorTejun Heo <tj@kernel.org>2011-05-24 03:59:36 -0400
committerTejun Heo <tj@kernel.org>2011-05-24 03:59:36 -0400
commit6988f20fe04e9ef3aea488cb8ab57fbeb78e12f0 (patch)
treec9d7fc50a2e2147a5ca07e3096e7eeb916ad2da9 /arch/mips
parent0415b00d175e0d8945e6785aad21b5f157976ce0 (diff)
parent6ea0c34dac89611126455537552cffe6c7e832ad (diff)
Merge branch 'fixes-2.6.39' into for-2.6.40
Diffstat (limited to 'arch/mips')
-rw-r--r--arch/mips/Kconfig4
-rw-r--r--arch/mips/alchemy/common/irq.c98
-rw-r--r--arch/mips/alchemy/devboards/bcsr.c18
-rw-r--r--arch/mips/ar7/irq.c42
-rw-r--r--arch/mips/ath79/irq.c24
-rw-r--r--arch/mips/bcm63xx/irq.c77
-rw-r--r--arch/mips/dec/ioasic-irq.c60
-rw-r--r--arch/mips/dec/kn02-irq.c23
-rw-r--r--arch/mips/emma/markeins/irq.c67
-rw-r--r--arch/mips/include/asm/irq.h64
-rw-r--r--arch/mips/include/asm/pmc-sierra/msp71xx/cpu-feature-overrides.h21
-rw-r--r--arch/mips/include/asm/pmc-sierra/msp71xx/msp_gpio_macros.h343
-rw-r--r--arch/mips/include/asm/pmc-sierra/msp71xx/msp_regs.h17
-rw-r--r--arch/mips/include/asm/pmc-sierra/msp71xx/msp_usb.h144
-rw-r--r--arch/mips/include/asm/spinlock.h22
-rw-r--r--arch/mips/include/asm/unistd.h24
-rw-r--r--arch/mips/jazz/irq.c14
-rw-r--r--arch/mips/jz4740/board-qi_lb60.c32
-rw-r--r--arch/mips/jz4740/gpio.c111
-rw-r--r--arch/mips/jz4740/irq.c32
-rw-r--r--arch/mips/kernel/i8259.c37
-rw-r--r--arch/mips/kernel/irq-gic.c43
-rw-r--r--arch/mips/kernel/irq-gt641xx.c26
-rw-r--r--arch/mips/kernel/irq-msc01.c51
-rw-r--r--arch/mips/kernel/irq-rm7000.c18
-rw-r--r--arch/mips/kernel/irq-rm9000.c49
-rw-r--r--arch/mips/kernel/irq.c49
-rw-r--r--arch/mips/kernel/irq_cpu.c46
-rw-r--r--arch/mips/kernel/irq_txx9.c28
-rw-r--r--arch/mips/kernel/scall32-o32.S4
-rw-r--r--arch/mips/kernel/scall64-64.S4
-rw-r--r--arch/mips/kernel/scall64-n32.S4
-rw-r--r--arch/mips/kernel/scall64-o32.S4
-rw-r--r--arch/mips/kernel/smtc.c13
-rw-r--r--arch/mips/lasat/interrupt.c16
-rw-r--r--arch/mips/loongson/common/bonito-irq.c16
-rw-r--r--arch/mips/mipssim/sim_smtc.c3
-rw-r--r--arch/mips/mti-malta/malta-smtc.c10
-rw-r--r--arch/mips/pmc-sierra/Kconfig15
-rw-r--r--arch/mips/pmc-sierra/msp71xx/Makefile8
-rw-r--r--arch/mips/pmc-sierra/msp71xx/msp_eth.c187
-rw-r--r--arch/mips/pmc-sierra/msp71xx/msp_irq.c56
-rw-r--r--arch/mips/pmc-sierra/msp71xx/msp_irq_cic.c239
-rw-r--r--arch/mips/pmc-sierra/msp71xx/msp_irq_per.c135
-rw-r--r--arch/mips/pmc-sierra/msp71xx/msp_irq_slp.c18
-rw-r--r--arch/mips/pmc-sierra/msp71xx/msp_setup.c10
-rw-r--r--arch/mips/pmc-sierra/msp71xx/msp_smp.c77
-rw-r--r--arch/mips/pmc-sierra/msp71xx/msp_smtc.c105
-rw-r--r--arch/mips/pmc-sierra/msp71xx/msp_time.c16
-rw-r--r--arch/mips/pmc-sierra/msp71xx/msp_usb.c239
-rw-r--r--arch/mips/pnx833x/common/interrupts.c98
-rw-r--r--arch/mips/pnx8550/common/int.c18
-rw-r--r--arch/mips/powertv/asic/irq_asic.c13
-rw-r--r--arch/mips/rb532/irq.c32
-rw-r--r--arch/mips/sgi-ip22/ip22-int.c60
-rw-r--r--arch/mips/sgi-ip27/ip27-irq.c38
-rw-r--r--arch/mips/sgi-ip27/ip27-timer.c11
-rw-r--r--arch/mips/sgi-ip32/ip32-irq.c134
-rw-r--r--arch/mips/sibyte/bcm1480/irq.c55
-rw-r--r--arch/mips/sibyte/sb1250/irq.c53
-rw-r--r--arch/mips/sni/a20r.c23
-rw-r--r--arch/mips/sni/pcimt.c21
-rw-r--r--arch/mips/sni/pcit.c21
-rw-r--r--arch/mips/sni/rm200.c42
-rw-r--r--arch/mips/txx9/generic/irq_tx4939.c28
-rw-r--r--arch/mips/txx9/jmr3927/irq.c14
-rw-r--r--arch/mips/txx9/rbtx4927/irq.c58
-rw-r--r--arch/mips/txx9/rbtx4938/irq.c54
-rw-r--r--arch/mips/txx9/rbtx4939/irq.c14
-rw-r--r--arch/mips/vr41xx/common/icu.c72
-rw-r--r--arch/mips/vr41xx/common/irq.c19
71 files changed, 2316 insertions, 1325 deletions
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 9905e2e85de4..83aa5fb8e8f1 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -22,6 +22,7 @@ config MIPS
22 select HAVE_DMA_API_DEBUG 22 select HAVE_DMA_API_DEBUG
23 select HAVE_GENERIC_HARDIRQS 23 select HAVE_GENERIC_HARDIRQS
24 select GENERIC_IRQ_PROBE 24 select GENERIC_IRQ_PROBE
25 select GENERIC_IRQ_SHOW
25 select HAVE_ARCH_JUMP_LABEL 26 select HAVE_ARCH_JUMP_LABEL
26 27
27menu "Machine selection" 28menu "Machine selection"
@@ -862,6 +863,9 @@ config GPIO_TXX9
862config CFE 863config CFE
863 bool 864 bool
864 865
866config ARCH_DMA_ADDR_T_64BIT
867 def_bool (HIGHMEM && 64BIT_PHYS_ADDR) || 64BIT
868
865config DMA_COHERENT 869config DMA_COHERENT
866 bool 870 bool
867 871
diff --git a/arch/mips/alchemy/common/irq.c b/arch/mips/alchemy/common/irq.c
index 9f78ada83b3c..55dd7c888517 100644
--- a/arch/mips/alchemy/common/irq.c
+++ b/arch/mips/alchemy/common/irq.c
@@ -39,7 +39,7 @@
39#include <asm/mach-pb1x00/pb1000.h> 39#include <asm/mach-pb1x00/pb1000.h>
40#endif 40#endif
41 41
42static int au1x_ic_settype(unsigned int irq, unsigned int flow_type); 42static int au1x_ic_settype(struct irq_data *d, unsigned int flow_type);
43 43
44/* NOTE on interrupt priorities: The original writers of this code said: 44/* NOTE on interrupt priorities: The original writers of this code said:
45 * 45 *
@@ -218,17 +218,17 @@ struct au1xxx_irqmap au1200_irqmap[] __initdata = {
218}; 218};
219 219
220 220
221static void au1x_ic0_unmask(unsigned int irq_nr) 221static void au1x_ic0_unmask(struct irq_data *d)
222{ 222{
223 unsigned int bit = irq_nr - AU1000_INTC0_INT_BASE; 223 unsigned int bit = d->irq - AU1000_INTC0_INT_BASE;
224 au_writel(1 << bit, IC0_MASKSET); 224 au_writel(1 << bit, IC0_MASKSET);
225 au_writel(1 << bit, IC0_WAKESET); 225 au_writel(1 << bit, IC0_WAKESET);
226 au_sync(); 226 au_sync();
227} 227}
228 228
229static void au1x_ic1_unmask(unsigned int irq_nr) 229static void au1x_ic1_unmask(struct irq_data *d)
230{ 230{
231 unsigned int bit = irq_nr - AU1000_INTC1_INT_BASE; 231 unsigned int bit = d->irq - AU1000_INTC1_INT_BASE;
232 au_writel(1 << bit, IC1_MASKSET); 232 au_writel(1 << bit, IC1_MASKSET);
233 au_writel(1 << bit, IC1_WAKESET); 233 au_writel(1 << bit, IC1_WAKESET);
234 234
@@ -236,31 +236,31 @@ static void au1x_ic1_unmask(unsigned int irq_nr)
236 * nowhere in the current kernel sources is it disabled. --mlau 236 * nowhere in the current kernel sources is it disabled. --mlau
237 */ 237 */
238#if defined(CONFIG_MIPS_PB1000) 238#if defined(CONFIG_MIPS_PB1000)
239 if (irq_nr == AU1000_GPIO15_INT) 239 if (d->irq == AU1000_GPIO15_INT)
240 au_writel(0x4000, PB1000_MDR); /* enable int */ 240 au_writel(0x4000, PB1000_MDR); /* enable int */
241#endif 241#endif
242 au_sync(); 242 au_sync();
243} 243}
244 244
245static void au1x_ic0_mask(unsigned int irq_nr) 245static void au1x_ic0_mask(struct irq_data *d)
246{ 246{
247 unsigned int bit = irq_nr - AU1000_INTC0_INT_BASE; 247 unsigned int bit = d->irq - AU1000_INTC0_INT_BASE;
248 au_writel(1 << bit, IC0_MASKCLR); 248 au_writel(1 << bit, IC0_MASKCLR);
249 au_writel(1 << bit, IC0_WAKECLR); 249 au_writel(1 << bit, IC0_WAKECLR);
250 au_sync(); 250 au_sync();
251} 251}
252 252
253static void au1x_ic1_mask(unsigned int irq_nr) 253static void au1x_ic1_mask(struct irq_data *d)
254{ 254{
255 unsigned int bit = irq_nr - AU1000_INTC1_INT_BASE; 255 unsigned int bit = d->irq - AU1000_INTC1_INT_BASE;
256 au_writel(1 << bit, IC1_MASKCLR); 256 au_writel(1 << bit, IC1_MASKCLR);
257 au_writel(1 << bit, IC1_WAKECLR); 257 au_writel(1 << bit, IC1_WAKECLR);
258 au_sync(); 258 au_sync();
259} 259}
260 260
261static void au1x_ic0_ack(unsigned int irq_nr) 261static void au1x_ic0_ack(struct irq_data *d)
262{ 262{
263 unsigned int bit = irq_nr - AU1000_INTC0_INT_BASE; 263 unsigned int bit = d->irq - AU1000_INTC0_INT_BASE;
264 264
265 /* 265 /*
266 * This may assume that we don't get interrupts from 266 * This may assume that we don't get interrupts from
@@ -271,9 +271,9 @@ static void au1x_ic0_ack(unsigned int irq_nr)
271 au_sync(); 271 au_sync();
272} 272}
273 273
274static void au1x_ic1_ack(unsigned int irq_nr) 274static void au1x_ic1_ack(struct irq_data *d)
275{ 275{
276 unsigned int bit = irq_nr - AU1000_INTC1_INT_BASE; 276 unsigned int bit = d->irq - AU1000_INTC1_INT_BASE;
277 277
278 /* 278 /*
279 * This may assume that we don't get interrupts from 279 * This may assume that we don't get interrupts from
@@ -284,9 +284,9 @@ static void au1x_ic1_ack(unsigned int irq_nr)
284 au_sync(); 284 au_sync();
285} 285}
286 286
287static void au1x_ic0_maskack(unsigned int irq_nr) 287static void au1x_ic0_maskack(struct irq_data *d)
288{ 288{
289 unsigned int bit = irq_nr - AU1000_INTC0_INT_BASE; 289 unsigned int bit = d->irq - AU1000_INTC0_INT_BASE;
290 290
291 au_writel(1 << bit, IC0_WAKECLR); 291 au_writel(1 << bit, IC0_WAKECLR);
292 au_writel(1 << bit, IC0_MASKCLR); 292 au_writel(1 << bit, IC0_MASKCLR);
@@ -295,9 +295,9 @@ static void au1x_ic0_maskack(unsigned int irq_nr)
295 au_sync(); 295 au_sync();
296} 296}
297 297
298static void au1x_ic1_maskack(unsigned int irq_nr) 298static void au1x_ic1_maskack(struct irq_data *d)
299{ 299{
300 unsigned int bit = irq_nr - AU1000_INTC1_INT_BASE; 300 unsigned int bit = d->irq - AU1000_INTC1_INT_BASE;
301 301
302 au_writel(1 << bit, IC1_WAKECLR); 302 au_writel(1 << bit, IC1_WAKECLR);
303 au_writel(1 << bit, IC1_MASKCLR); 303 au_writel(1 << bit, IC1_MASKCLR);
@@ -306,9 +306,9 @@ static void au1x_ic1_maskack(unsigned int irq_nr)
306 au_sync(); 306 au_sync();
307} 307}
308 308
309static int au1x_ic1_setwake(unsigned int irq, unsigned int on) 309static int au1x_ic1_setwake(struct irq_data *d, unsigned int on)
310{ 310{
311 int bit = irq - AU1000_INTC1_INT_BASE; 311 int bit = d->irq - AU1000_INTC1_INT_BASE;
312 unsigned long wakemsk, flags; 312 unsigned long wakemsk, flags;
313 313
314 /* only GPIO 0-7 can act as wakeup source. Fortunately these 314 /* only GPIO 0-7 can act as wakeup source. Fortunately these
@@ -336,28 +336,30 @@ static int au1x_ic1_setwake(unsigned int irq, unsigned int on)
336 */ 336 */
337static struct irq_chip au1x_ic0_chip = { 337static struct irq_chip au1x_ic0_chip = {
338 .name = "Alchemy-IC0", 338 .name = "Alchemy-IC0",
339 .ack = au1x_ic0_ack, 339 .irq_ack = au1x_ic0_ack,
340 .mask = au1x_ic0_mask, 340 .irq_mask = au1x_ic0_mask,
341 .mask_ack = au1x_ic0_maskack, 341 .irq_mask_ack = au1x_ic0_maskack,
342 .unmask = au1x_ic0_unmask, 342 .irq_unmask = au1x_ic0_unmask,
343 .set_type = au1x_ic_settype, 343 .irq_set_type = au1x_ic_settype,
344}; 344};
345 345
346static struct irq_chip au1x_ic1_chip = { 346static struct irq_chip au1x_ic1_chip = {
347 .name = "Alchemy-IC1", 347 .name = "Alchemy-IC1",
348 .ack = au1x_ic1_ack, 348 .irq_ack = au1x_ic1_ack,
349 .mask = au1x_ic1_mask, 349 .irq_mask = au1x_ic1_mask,
350 .mask_ack = au1x_ic1_maskack, 350 .irq_mask_ack = au1x_ic1_maskack,
351 .unmask = au1x_ic1_unmask, 351 .irq_unmask = au1x_ic1_unmask,
352 .set_type = au1x_ic_settype, 352 .irq_set_type = au1x_ic_settype,
353 .set_wake = au1x_ic1_setwake, 353 .irq_set_wake = au1x_ic1_setwake,
354}; 354};
355 355
356static int au1x_ic_settype(unsigned int irq, unsigned int flow_type) 356static int au1x_ic_settype(struct irq_data *d, unsigned int flow_type)
357{ 357{
358 struct irq_chip *chip; 358 struct irq_chip *chip;
359 unsigned long icr[6]; 359 unsigned long icr[6];
360 unsigned int bit, ic; 360 unsigned int bit, ic, irq = d->irq;
361 irq_flow_handler_t handler = NULL;
362 unsigned char *name = NULL;
361 int ret; 363 int ret;
362 364
363 if (irq >= AU1000_INTC1_INT_BASE) { 365 if (irq >= AU1000_INTC1_INT_BASE) {
@@ -387,47 +389,47 @@ static int au1x_ic_settype(unsigned int irq, unsigned int flow_type)
387 au_writel(1 << bit, icr[5]); 389 au_writel(1 << bit, icr[5]);
388 au_writel(1 << bit, icr[4]); 390 au_writel(1 << bit, icr[4]);
389 au_writel(1 << bit, icr[0]); 391 au_writel(1 << bit, icr[0]);
390 set_irq_chip_and_handler_name(irq, chip, 392 handler = handle_edge_irq;
391 handle_edge_irq, "riseedge"); 393 name = "riseedge";
392 break; 394 break;
393 case IRQ_TYPE_EDGE_FALLING: /* 0:1:0 */ 395 case IRQ_TYPE_EDGE_FALLING: /* 0:1:0 */
394 au_writel(1 << bit, icr[5]); 396 au_writel(1 << bit, icr[5]);
395 au_writel(1 << bit, icr[1]); 397 au_writel(1 << bit, icr[1]);
396 au_writel(1 << bit, icr[3]); 398 au_writel(1 << bit, icr[3]);
397 set_irq_chip_and_handler_name(irq, chip, 399 handler = handle_edge_irq;
398 handle_edge_irq, "falledge"); 400 name = "falledge";
399 break; 401 break;
400 case IRQ_TYPE_EDGE_BOTH: /* 0:1:1 */ 402 case IRQ_TYPE_EDGE_BOTH: /* 0:1:1 */
401 au_writel(1 << bit, icr[5]); 403 au_writel(1 << bit, icr[5]);
402 au_writel(1 << bit, icr[1]); 404 au_writel(1 << bit, icr[1]);
403 au_writel(1 << bit, icr[0]); 405 au_writel(1 << bit, icr[0]);
404 set_irq_chip_and_handler_name(irq, chip, 406 handler = handle_edge_irq;
405 handle_edge_irq, "bothedge"); 407 name = "bothedge";
406 break; 408 break;
407 case IRQ_TYPE_LEVEL_HIGH: /* 1:0:1 */ 409 case IRQ_TYPE_LEVEL_HIGH: /* 1:0:1 */
408 au_writel(1 << bit, icr[2]); 410 au_writel(1 << bit, icr[2]);
409 au_writel(1 << bit, icr[4]); 411 au_writel(1 << bit, icr[4]);
410 au_writel(1 << bit, icr[0]); 412 au_writel(1 << bit, icr[0]);
411 set_irq_chip_and_handler_name(irq, chip, 413 handler = handle_level_irq;
412 handle_level_irq, "hilevel"); 414 name = "hilevel";
413 break; 415 break;
414 case IRQ_TYPE_LEVEL_LOW: /* 1:1:0 */ 416 case IRQ_TYPE_LEVEL_LOW: /* 1:1:0 */
415 au_writel(1 << bit, icr[2]); 417 au_writel(1 << bit, icr[2]);
416 au_writel(1 << bit, icr[1]); 418 au_writel(1 << bit, icr[1]);
417 au_writel(1 << bit, icr[3]); 419 au_writel(1 << bit, icr[3]);
418 set_irq_chip_and_handler_name(irq, chip, 420 handler = handle_level_irq;
419 handle_level_irq, "lowlevel"); 421 name = "lowlevel";
420 break; 422 break;
421 case IRQ_TYPE_NONE: /* 0:0:0 */ 423 case IRQ_TYPE_NONE: /* 0:0:0 */
422 au_writel(1 << bit, icr[5]); 424 au_writel(1 << bit, icr[5]);
423 au_writel(1 << bit, icr[4]); 425 au_writel(1 << bit, icr[4]);
424 au_writel(1 << bit, icr[3]); 426 au_writel(1 << bit, icr[3]);
425 /* set at least chip so we can call set_irq_type() on it */
426 set_irq_chip(irq, chip);
427 break; 427 break;
428 default: 428 default:
429 ret = -EINVAL; 429 ret = -EINVAL;
430 } 430 }
431 __irq_set_chip_handler_name_locked(d->irq, chip, handler, name);
432
431 au_sync(); 433 au_sync();
432 434
433 return ret; 435 return ret;
@@ -504,11 +506,11 @@ static void __init au1000_init_irq(struct au1xxx_irqmap *map)
504 */ 506 */
505 for (i = AU1000_INTC0_INT_BASE; 507 for (i = AU1000_INTC0_INT_BASE;
506 (i < AU1000_INTC0_INT_BASE + 32); i++) 508 (i < AU1000_INTC0_INT_BASE + 32); i++)
507 au1x_ic_settype(i, IRQ_TYPE_NONE); 509 au1x_ic_settype(irq_get_irq_data(i), IRQ_TYPE_NONE);
508 510
509 for (i = AU1000_INTC1_INT_BASE; 511 for (i = AU1000_INTC1_INT_BASE;
510 (i < AU1000_INTC1_INT_BASE + 32); i++) 512 (i < AU1000_INTC1_INT_BASE + 32); i++)
511 au1x_ic_settype(i, IRQ_TYPE_NONE); 513 au1x_ic_settype(irq_get_irq_data(i), IRQ_TYPE_NONE);
512 514
513 /* 515 /*
514 * Initialize IC0, which is fixed per processor. 516 * Initialize IC0, which is fixed per processor.
@@ -526,7 +528,7 @@ static void __init au1000_init_irq(struct au1xxx_irqmap *map)
526 au_writel(1 << bit, IC0_ASSIGNSET); 528 au_writel(1 << bit, IC0_ASSIGNSET);
527 } 529 }
528 530
529 au1x_ic_settype(irq_nr, map->im_type); 531 au1x_ic_settype(irq_get_irq_data(irq_nr), map->im_type);
530 ++map; 532 ++map;
531 } 533 }
532 534
diff --git a/arch/mips/alchemy/devboards/bcsr.c b/arch/mips/alchemy/devboards/bcsr.c
index c52af8821da0..f91c43a7d5dc 100644
--- a/arch/mips/alchemy/devboards/bcsr.c
+++ b/arch/mips/alchemy/devboards/bcsr.c
@@ -97,26 +97,26 @@ static void bcsr_csc_handler(unsigned int irq, struct irq_desc *d)
97 * CPLD generates tons of spurious interrupts (at least on my DB1200). 97 * CPLD generates tons of spurious interrupts (at least on my DB1200).
98 * -- mlau 98 * -- mlau
99 */ 99 */
100static void bcsr_irq_mask(unsigned int irq_nr) 100static void bcsr_irq_mask(struct irq_data *d)
101{ 101{
102 unsigned short v = 1 << (irq_nr - bcsr_csc_base); 102 unsigned short v = 1 << (d->irq - bcsr_csc_base);
103 __raw_writew(v, bcsr_virt + BCSR_REG_INTCLR); 103 __raw_writew(v, bcsr_virt + BCSR_REG_INTCLR);
104 __raw_writew(v, bcsr_virt + BCSR_REG_MASKCLR); 104 __raw_writew(v, bcsr_virt + BCSR_REG_MASKCLR);
105 wmb(); 105 wmb();
106} 106}
107 107
108static void bcsr_irq_maskack(unsigned int irq_nr) 108static void bcsr_irq_maskack(struct irq_data *d)
109{ 109{
110 unsigned short v = 1 << (irq_nr - bcsr_csc_base); 110 unsigned short v = 1 << (d->irq - bcsr_csc_base);
111 __raw_writew(v, bcsr_virt + BCSR_REG_INTCLR); 111 __raw_writew(v, bcsr_virt + BCSR_REG_INTCLR);
112 __raw_writew(v, bcsr_virt + BCSR_REG_MASKCLR); 112 __raw_writew(v, bcsr_virt + BCSR_REG_MASKCLR);
113 __raw_writew(v, bcsr_virt + BCSR_REG_INTSTAT); /* ack */ 113 __raw_writew(v, bcsr_virt + BCSR_REG_INTSTAT); /* ack */
114 wmb(); 114 wmb();
115} 115}
116 116
117static void bcsr_irq_unmask(unsigned int irq_nr) 117static void bcsr_irq_unmask(struct irq_data *d)
118{ 118{
119 unsigned short v = 1 << (irq_nr - bcsr_csc_base); 119 unsigned short v = 1 << (d->irq - bcsr_csc_base);
120 __raw_writew(v, bcsr_virt + BCSR_REG_INTSET); 120 __raw_writew(v, bcsr_virt + BCSR_REG_INTSET);
121 __raw_writew(v, bcsr_virt + BCSR_REG_MASKSET); 121 __raw_writew(v, bcsr_virt + BCSR_REG_MASKSET);
122 wmb(); 122 wmb();
@@ -124,9 +124,9 @@ static void bcsr_irq_unmask(unsigned int irq_nr)
124 124
125static struct irq_chip bcsr_irq_type = { 125static struct irq_chip bcsr_irq_type = {
126 .name = "CPLD", 126 .name = "CPLD",
127 .mask = bcsr_irq_mask, 127 .irq_mask = bcsr_irq_mask,
128 .mask_ack = bcsr_irq_maskack, 128 .irq_mask_ack = bcsr_irq_maskack,
129 .unmask = bcsr_irq_unmask, 129 .irq_unmask = bcsr_irq_unmask,
130}; 130};
131 131
132void __init bcsr_init_irq(int csc_start, int csc_end, int hook_irq) 132void __init bcsr_init_irq(int csc_start, int csc_end, int hook_irq)
diff --git a/arch/mips/ar7/irq.c b/arch/mips/ar7/irq.c
index 4ec2642c568f..a6484b60642f 100644
--- a/arch/mips/ar7/irq.c
+++ b/arch/mips/ar7/irq.c
@@ -49,51 +49,51 @@
49 49
50static int ar7_irq_base; 50static int ar7_irq_base;
51 51
52static void ar7_unmask_irq(unsigned int irq) 52static void ar7_unmask_irq(struct irq_data *d)
53{ 53{
54 writel(1 << ((irq - ar7_irq_base) % 32), 54 writel(1 << ((d->irq - ar7_irq_base) % 32),
55 REG(ESR_OFFSET(irq - ar7_irq_base))); 55 REG(ESR_OFFSET(d->irq - ar7_irq_base)));
56} 56}
57 57
58static void ar7_mask_irq(unsigned int irq) 58static void ar7_mask_irq(struct irq_data *d)
59{ 59{
60 writel(1 << ((irq - ar7_irq_base) % 32), 60 writel(1 << ((d->irq - ar7_irq_base) % 32),
61 REG(ECR_OFFSET(irq - ar7_irq_base))); 61 REG(ECR_OFFSET(d->irq - ar7_irq_base)));
62} 62}
63 63
64static void ar7_ack_irq(unsigned int irq) 64static void ar7_ack_irq(struct irq_data *d)
65{ 65{
66 writel(1 << ((irq - ar7_irq_base) % 32), 66 writel(1 << ((d->irq - ar7_irq_base) % 32),
67 REG(CR_OFFSET(irq - ar7_irq_base))); 67 REG(CR_OFFSET(d->irq - ar7_irq_base)));
68} 68}
69 69
70static void ar7_unmask_sec_irq(unsigned int irq) 70static void ar7_unmask_sec_irq(struct irq_data *d)
71{ 71{
72 writel(1 << (irq - ar7_irq_base - 40), REG(SEC_ESR_OFFSET)); 72 writel(1 << (d->irq - ar7_irq_base - 40), REG(SEC_ESR_OFFSET));
73} 73}
74 74
75static void ar7_mask_sec_irq(unsigned int irq) 75static void ar7_mask_sec_irq(struct irq_data *d)
76{ 76{
77 writel(1 << (irq - ar7_irq_base - 40), REG(SEC_ECR_OFFSET)); 77 writel(1 << (d->irq - ar7_irq_base - 40), REG(SEC_ECR_OFFSET));
78} 78}
79 79
80static void ar7_ack_sec_irq(unsigned int irq) 80static void ar7_ack_sec_irq(struct irq_data *d)
81{ 81{
82 writel(1 << (irq - ar7_irq_base - 40), REG(SEC_CR_OFFSET)); 82 writel(1 << (d->irq - ar7_irq_base - 40), REG(SEC_CR_OFFSET));
83} 83}
84 84
85static struct irq_chip ar7_irq_type = { 85static struct irq_chip ar7_irq_type = {
86 .name = "AR7", 86 .name = "AR7",
87 .unmask = ar7_unmask_irq, 87 .irq_unmask = ar7_unmask_irq,
88 .mask = ar7_mask_irq, 88 .irq_mask = ar7_mask_irq,
89 .ack = ar7_ack_irq 89 .irq_ack = ar7_ack_irq
90}; 90};
91 91
92static struct irq_chip ar7_sec_irq_type = { 92static struct irq_chip ar7_sec_irq_type = {
93 .name = "AR7", 93 .name = "AR7",
94 .unmask = ar7_unmask_sec_irq, 94 .irq_unmask = ar7_unmask_sec_irq,
95 .mask = ar7_mask_sec_irq, 95 .irq_mask = ar7_mask_sec_irq,
96 .ack = ar7_ack_sec_irq, 96 .irq_ack = ar7_ack_sec_irq,
97}; 97};
98 98
99static struct irqaction ar7_cascade_action = { 99static struct irqaction ar7_cascade_action = {
diff --git a/arch/mips/ath79/irq.c b/arch/mips/ath79/irq.c
index 1bf7f719ba53..7c02bc948a31 100644
--- a/arch/mips/ath79/irq.c
+++ b/arch/mips/ath79/irq.c
@@ -62,13 +62,12 @@ static void ath79_misc_irq_handler(unsigned int irq, struct irq_desc *desc)
62 spurious_interrupt(); 62 spurious_interrupt();
63} 63}
64 64
65static void ar71xx_misc_irq_unmask(unsigned int irq) 65static void ar71xx_misc_irq_unmask(struct irq_data *d)
66{ 66{
67 unsigned int irq = d->irq - ATH79_MISC_IRQ_BASE;
67 void __iomem *base = ath79_reset_base; 68 void __iomem *base = ath79_reset_base;
68 u32 t; 69 u32 t;
69 70
70 irq -= ATH79_MISC_IRQ_BASE;
71
72 t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE); 71 t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
73 __raw_writel(t | (1 << irq), base + AR71XX_RESET_REG_MISC_INT_ENABLE); 72 __raw_writel(t | (1 << irq), base + AR71XX_RESET_REG_MISC_INT_ENABLE);
74 73
@@ -76,13 +75,12 @@ static void ar71xx_misc_irq_unmask(unsigned int irq)
76 __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE); 75 __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
77} 76}
78 77
79static void ar71xx_misc_irq_mask(unsigned int irq) 78static void ar71xx_misc_irq_mask(struct irq_data *d)
80{ 79{
80 unsigned int irq = d->irq - ATH79_MISC_IRQ_BASE;
81 void __iomem *base = ath79_reset_base; 81 void __iomem *base = ath79_reset_base;
82 u32 t; 82 u32 t;
83 83
84 irq -= ATH79_MISC_IRQ_BASE;
85
86 t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE); 84 t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
87 __raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_MISC_INT_ENABLE); 85 __raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_MISC_INT_ENABLE);
88 86
@@ -90,13 +88,12 @@ static void ar71xx_misc_irq_mask(unsigned int irq)
90 __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE); 88 __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
91} 89}
92 90
93static void ar724x_misc_irq_ack(unsigned int irq) 91static void ar724x_misc_irq_ack(struct irq_data *d)
94{ 92{
93 unsigned int irq = d->irq - ATH79_MISC_IRQ_BASE;
95 void __iomem *base = ath79_reset_base; 94 void __iomem *base = ath79_reset_base;
96 u32 t; 95 u32 t;
97 96
98 irq -= ATH79_MISC_IRQ_BASE;
99
100 t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS); 97 t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS);
101 __raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_MISC_INT_STATUS); 98 __raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_MISC_INT_STATUS);
102 99
@@ -106,8 +103,8 @@ static void ar724x_misc_irq_ack(unsigned int irq)
106 103
107static struct irq_chip ath79_misc_irq_chip = { 104static struct irq_chip ath79_misc_irq_chip = {
108 .name = "MISC", 105 .name = "MISC",
109 .unmask = ar71xx_misc_irq_unmask, 106 .irq_unmask = ar71xx_misc_irq_unmask,
110 .mask = ar71xx_misc_irq_mask, 107 .irq_mask = ar71xx_misc_irq_mask,
111}; 108};
112 109
113static void __init ath79_misc_irq_init(void) 110static void __init ath79_misc_irq_init(void)
@@ -119,15 +116,14 @@ static void __init ath79_misc_irq_init(void)
119 __raw_writel(0, base + AR71XX_RESET_REG_MISC_INT_STATUS); 116 __raw_writel(0, base + AR71XX_RESET_REG_MISC_INT_STATUS);
120 117
121 if (soc_is_ar71xx() || soc_is_ar913x()) 118 if (soc_is_ar71xx() || soc_is_ar913x())
122 ath79_misc_irq_chip.mask_ack = ar71xx_misc_irq_mask; 119 ath79_misc_irq_chip.irq_mask_ack = ar71xx_misc_irq_mask;
123 else if (soc_is_ar724x()) 120 else if (soc_is_ar724x())
124 ath79_misc_irq_chip.ack = ar724x_misc_irq_ack; 121 ath79_misc_irq_chip.irq_ack = ar724x_misc_irq_ack;
125 else 122 else
126 BUG(); 123 BUG();
127 124
128 for (i = ATH79_MISC_IRQ_BASE; 125 for (i = ATH79_MISC_IRQ_BASE;
129 i < ATH79_MISC_IRQ_BASE + ATH79_MISC_IRQ_COUNT; i++) { 126 i < ATH79_MISC_IRQ_BASE + ATH79_MISC_IRQ_COUNT; i++) {
130 irq_desc[i].status = IRQ_DISABLED;
131 set_irq_chip_and_handler(i, &ath79_misc_irq_chip, 127 set_irq_chip_and_handler(i, &ath79_misc_irq_chip,
132 handle_level_irq); 128 handle_level_irq);
133 } 129 }
diff --git a/arch/mips/bcm63xx/irq.c b/arch/mips/bcm63xx/irq.c
index 3be87f2422f0..1691531aa34d 100644
--- a/arch/mips/bcm63xx/irq.c
+++ b/arch/mips/bcm63xx/irq.c
@@ -76,88 +76,80 @@ asmlinkage void plat_irq_dispatch(void)
76 * internal IRQs operations: only mask/unmask on PERF irq mask 76 * internal IRQs operations: only mask/unmask on PERF irq mask
77 * register. 77 * register.
78 */ 78 */
79static inline void bcm63xx_internal_irq_mask(unsigned int irq) 79static inline void bcm63xx_internal_irq_mask(struct irq_data *d)
80{ 80{
81 unsigned int irq = d->irq - IRQ_INTERNAL_BASE;
81 u32 mask; 82 u32 mask;
82 83
83 irq -= IRQ_INTERNAL_BASE;
84 mask = bcm_perf_readl(PERF_IRQMASK_REG); 84 mask = bcm_perf_readl(PERF_IRQMASK_REG);
85 mask &= ~(1 << irq); 85 mask &= ~(1 << irq);
86 bcm_perf_writel(mask, PERF_IRQMASK_REG); 86 bcm_perf_writel(mask, PERF_IRQMASK_REG);
87} 87}
88 88
89static void bcm63xx_internal_irq_unmask(unsigned int irq) 89static void bcm63xx_internal_irq_unmask(struct irq_data *d)
90{ 90{
91 unsigned int irq = d->irq - IRQ_INTERNAL_BASE;
91 u32 mask; 92 u32 mask;
92 93
93 irq -= IRQ_INTERNAL_BASE;
94 mask = bcm_perf_readl(PERF_IRQMASK_REG); 94 mask = bcm_perf_readl(PERF_IRQMASK_REG);
95 mask |= (1 << irq); 95 mask |= (1 << irq);
96 bcm_perf_writel(mask, PERF_IRQMASK_REG); 96 bcm_perf_writel(mask, PERF_IRQMASK_REG);
97} 97}
98 98
99static unsigned int bcm63xx_internal_irq_startup(unsigned int irq)
100{
101 bcm63xx_internal_irq_unmask(irq);
102 return 0;
103}
104
105/* 99/*
106 * external IRQs operations: mask/unmask and clear on PERF external 100 * external IRQs operations: mask/unmask and clear on PERF external
107 * irq control register. 101 * irq control register.
108 */ 102 */
109static void bcm63xx_external_irq_mask(unsigned int irq) 103static void bcm63xx_external_irq_mask(struct irq_data *d)
110{ 104{
105 unsigned int irq = d->irq - IRQ_EXT_BASE;
111 u32 reg; 106 u32 reg;
112 107
113 irq -= IRQ_EXT_BASE;
114 reg = bcm_perf_readl(PERF_EXTIRQ_CFG_REG); 108 reg = bcm_perf_readl(PERF_EXTIRQ_CFG_REG);
115 reg &= ~EXTIRQ_CFG_MASK(irq); 109 reg &= ~EXTIRQ_CFG_MASK(irq);
116 bcm_perf_writel(reg, PERF_EXTIRQ_CFG_REG); 110 bcm_perf_writel(reg, PERF_EXTIRQ_CFG_REG);
117} 111}
118 112
119static void bcm63xx_external_irq_unmask(unsigned int irq) 113static void bcm63xx_external_irq_unmask(struct irq_data *d)
120{ 114{
115 unsigned int irq = d->irq - IRQ_EXT_BASE;
121 u32 reg; 116 u32 reg;
122 117
123 irq -= IRQ_EXT_BASE;
124 reg = bcm_perf_readl(PERF_EXTIRQ_CFG_REG); 118 reg = bcm_perf_readl(PERF_EXTIRQ_CFG_REG);
125 reg |= EXTIRQ_CFG_MASK(irq); 119 reg |= EXTIRQ_CFG_MASK(irq);
126 bcm_perf_writel(reg, PERF_EXTIRQ_CFG_REG); 120 bcm_perf_writel(reg, PERF_EXTIRQ_CFG_REG);
127} 121}
128 122
129static void bcm63xx_external_irq_clear(unsigned int irq) 123static void bcm63xx_external_irq_clear(struct irq_data *d)
130{ 124{
125 unsigned int irq = d->irq - IRQ_EXT_BASE;
131 u32 reg; 126 u32 reg;
132 127
133 irq -= IRQ_EXT_BASE;
134 reg = bcm_perf_readl(PERF_EXTIRQ_CFG_REG); 128 reg = bcm_perf_readl(PERF_EXTIRQ_CFG_REG);
135 reg |= EXTIRQ_CFG_CLEAR(irq); 129 reg |= EXTIRQ_CFG_CLEAR(irq);
136 bcm_perf_writel(reg, PERF_EXTIRQ_CFG_REG); 130 bcm_perf_writel(reg, PERF_EXTIRQ_CFG_REG);
137} 131}
138 132
139static unsigned int bcm63xx_external_irq_startup(unsigned int irq) 133static unsigned int bcm63xx_external_irq_startup(struct irq_data *d)
140{ 134{
141 set_c0_status(0x100 << (irq - IRQ_MIPS_BASE)); 135 set_c0_status(0x100 << (d->irq - IRQ_MIPS_BASE));
142 irq_enable_hazard(); 136 irq_enable_hazard();
143 bcm63xx_external_irq_unmask(irq); 137 bcm63xx_external_irq_unmask(d);
144 return 0; 138 return 0;
145} 139}
146 140
147static void bcm63xx_external_irq_shutdown(unsigned int irq) 141static void bcm63xx_external_irq_shutdown(struct irq_data *d)
148{ 142{
149 bcm63xx_external_irq_mask(irq); 143 bcm63xx_external_irq_mask(d);
150 clear_c0_status(0x100 << (irq - IRQ_MIPS_BASE)); 144 clear_c0_status(0x100 << (d->irq - IRQ_MIPS_BASE));
151 irq_disable_hazard(); 145 irq_disable_hazard();
152} 146}
153 147
154static int bcm63xx_external_irq_set_type(unsigned int irq, 148static int bcm63xx_external_irq_set_type(struct irq_data *d,
155 unsigned int flow_type) 149 unsigned int flow_type)
156{ 150{
151 unsigned int irq = d->irq - IRQ_EXT_BASE;
157 u32 reg; 152 u32 reg;
158 struct irq_desc *desc = irq_desc + irq;
159
160 irq -= IRQ_EXT_BASE;
161 153
162 flow_type &= IRQ_TYPE_SENSE_MASK; 154 flow_type &= IRQ_TYPE_SENSE_MASK;
163 155
@@ -199,37 +191,32 @@ static int bcm63xx_external_irq_set_type(unsigned int irq,
199 } 191 }
200 bcm_perf_writel(reg, PERF_EXTIRQ_CFG_REG); 192 bcm_perf_writel(reg, PERF_EXTIRQ_CFG_REG);
201 193
202 if (flow_type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) { 194 irqd_set_trigger_type(d, flow_type);
203 desc->status |= IRQ_LEVEL; 195 if (flow_type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
204 desc->handle_irq = handle_level_irq; 196 __irq_set_handler_locked(d->irq, handle_level_irq);
205 } else { 197 else
206 desc->handle_irq = handle_edge_irq; 198 __irq_set_handler_locked(d->irq, handle_edge_irq);
207 }
208 199
209 return 0; 200 return IRQ_SET_MASK_OK_NOCOPY;
210} 201}
211 202
212static struct irq_chip bcm63xx_internal_irq_chip = { 203static struct irq_chip bcm63xx_internal_irq_chip = {
213 .name = "bcm63xx_ipic", 204 .name = "bcm63xx_ipic",
214 .startup = bcm63xx_internal_irq_startup, 205 .irq_mask = bcm63xx_internal_irq_mask,
215 .shutdown = bcm63xx_internal_irq_mask, 206 .irq_unmask = bcm63xx_internal_irq_unmask,
216
217 .mask = bcm63xx_internal_irq_mask,
218 .mask_ack = bcm63xx_internal_irq_mask,
219 .unmask = bcm63xx_internal_irq_unmask,
220}; 207};
221 208
222static struct irq_chip bcm63xx_external_irq_chip = { 209static struct irq_chip bcm63xx_external_irq_chip = {
223 .name = "bcm63xx_epic", 210 .name = "bcm63xx_epic",
224 .startup = bcm63xx_external_irq_startup, 211 .irq_startup = bcm63xx_external_irq_startup,
225 .shutdown = bcm63xx_external_irq_shutdown, 212 .irq_shutdown = bcm63xx_external_irq_shutdown,
226 213
227 .ack = bcm63xx_external_irq_clear, 214 .irq_ack = bcm63xx_external_irq_clear,
228 215
229 .mask = bcm63xx_external_irq_mask, 216 .irq_mask = bcm63xx_external_irq_mask,
230 .unmask = bcm63xx_external_irq_unmask, 217 .irq_unmask = bcm63xx_external_irq_unmask,
231 218
232 .set_type = bcm63xx_external_irq_set_type, 219 .irq_set_type = bcm63xx_external_irq_set_type,
233}; 220};
234 221
235static struct irqaction cpu_ip2_cascade_action = { 222static struct irqaction cpu_ip2_cascade_action = {
diff --git a/arch/mips/dec/ioasic-irq.c b/arch/mips/dec/ioasic-irq.c
index cb41954fc321..8d9a5fc607e4 100644
--- a/arch/mips/dec/ioasic-irq.c
+++ b/arch/mips/dec/ioasic-irq.c
@@ -17,80 +17,48 @@
17#include <asm/dec/ioasic_addrs.h> 17#include <asm/dec/ioasic_addrs.h>
18#include <asm/dec/ioasic_ints.h> 18#include <asm/dec/ioasic_ints.h>
19 19
20
21static int ioasic_irq_base; 20static int ioasic_irq_base;
22 21
23 22static void unmask_ioasic_irq(struct irq_data *d)
24static inline void unmask_ioasic_irq(unsigned int irq)
25{ 23{
26 u32 simr; 24 u32 simr;
27 25
28 simr = ioasic_read(IO_REG_SIMR); 26 simr = ioasic_read(IO_REG_SIMR);
29 simr |= (1 << (irq - ioasic_irq_base)); 27 simr |= (1 << (d->irq - ioasic_irq_base));
30 ioasic_write(IO_REG_SIMR, simr); 28 ioasic_write(IO_REG_SIMR, simr);
31} 29}
32 30
33static inline void mask_ioasic_irq(unsigned int irq) 31static void mask_ioasic_irq(struct irq_data *d)
34{ 32{
35 u32 simr; 33 u32 simr;
36 34
37 simr = ioasic_read(IO_REG_SIMR); 35 simr = ioasic_read(IO_REG_SIMR);
38 simr &= ~(1 << (irq - ioasic_irq_base)); 36 simr &= ~(1 << (d->irq - ioasic_irq_base));
39 ioasic_write(IO_REG_SIMR, simr); 37 ioasic_write(IO_REG_SIMR, simr);
40} 38}
41 39
42static inline void clear_ioasic_irq(unsigned int irq) 40static void ack_ioasic_irq(struct irq_data *d)
43{ 41{
44 u32 sir; 42 mask_ioasic_irq(d);
45
46 sir = ~(1 << (irq - ioasic_irq_base));
47 ioasic_write(IO_REG_SIR, sir);
48}
49
50static inline void ack_ioasic_irq(unsigned int irq)
51{
52 mask_ioasic_irq(irq);
53 fast_iob(); 43 fast_iob();
54} 44}
55 45
56static inline void end_ioasic_irq(unsigned int irq)
57{
58 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
59 unmask_ioasic_irq(irq);
60}
61
62static struct irq_chip ioasic_irq_type = { 46static struct irq_chip ioasic_irq_type = {
63 .name = "IO-ASIC", 47 .name = "IO-ASIC",
64 .ack = ack_ioasic_irq, 48 .irq_ack = ack_ioasic_irq,
65 .mask = mask_ioasic_irq, 49 .irq_mask = mask_ioasic_irq,
66 .mask_ack = ack_ioasic_irq, 50 .irq_mask_ack = ack_ioasic_irq,
67 .unmask = unmask_ioasic_irq, 51 .irq_unmask = unmask_ioasic_irq,
68}; 52};
69 53
70
71#define unmask_ioasic_dma_irq unmask_ioasic_irq
72
73#define mask_ioasic_dma_irq mask_ioasic_irq
74
75#define ack_ioasic_dma_irq ack_ioasic_irq
76
77static inline void end_ioasic_dma_irq(unsigned int irq)
78{
79 clear_ioasic_irq(irq);
80 fast_iob();
81 end_ioasic_irq(irq);
82}
83
84static struct irq_chip ioasic_dma_irq_type = { 54static struct irq_chip ioasic_dma_irq_type = {
85 .name = "IO-ASIC-DMA", 55 .name = "IO-ASIC-DMA",
86 .ack = ack_ioasic_dma_irq, 56 .irq_ack = ack_ioasic_irq,
87 .mask = mask_ioasic_dma_irq, 57 .irq_mask = mask_ioasic_irq,
88 .mask_ack = ack_ioasic_dma_irq, 58 .irq_mask_ack = ack_ioasic_irq,
89 .unmask = unmask_ioasic_dma_irq, 59 .irq_unmask = unmask_ioasic_irq,
90 .end = end_ioasic_dma_irq,
91}; 60};
92 61
93
94void __init init_ioasic_irqs(int base) 62void __init init_ioasic_irqs(int base)
95{ 63{
96 int i; 64 int i;
diff --git a/arch/mips/dec/kn02-irq.c b/arch/mips/dec/kn02-irq.c
index ed90a8deabcc..ef31d98c4fb8 100644
--- a/arch/mips/dec/kn02-irq.c
+++ b/arch/mips/dec/kn02-irq.c
@@ -27,43 +27,40 @@
27 */ 27 */
28u32 cached_kn02_csr; 28u32 cached_kn02_csr;
29 29
30
31static int kn02_irq_base; 30static int kn02_irq_base;
32 31
33 32static void unmask_kn02_irq(struct irq_data *d)
34static inline void unmask_kn02_irq(unsigned int irq)
35{ 33{
36 volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE + 34 volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE +
37 KN02_CSR); 35 KN02_CSR);
38 36
39 cached_kn02_csr |= (1 << (irq - kn02_irq_base + 16)); 37 cached_kn02_csr |= (1 << (d->irq - kn02_irq_base + 16));
40 *csr = cached_kn02_csr; 38 *csr = cached_kn02_csr;
41} 39}
42 40
43static inline void mask_kn02_irq(unsigned int irq) 41static void mask_kn02_irq(struct irq_data *d)
44{ 42{
45 volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE + 43 volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE +
46 KN02_CSR); 44 KN02_CSR);
47 45
48 cached_kn02_csr &= ~(1 << (irq - kn02_irq_base + 16)); 46 cached_kn02_csr &= ~(1 << (d->irq - kn02_irq_base + 16));
49 *csr = cached_kn02_csr; 47 *csr = cached_kn02_csr;
50} 48}
51 49
52static void ack_kn02_irq(unsigned int irq) 50static void ack_kn02_irq(struct irq_data *d)
53{ 51{
54 mask_kn02_irq(irq); 52 mask_kn02_irq(d);
55 iob(); 53 iob();
56} 54}
57 55
58static struct irq_chip kn02_irq_type = { 56static struct irq_chip kn02_irq_type = {
59 .name = "KN02-CSR", 57 .name = "KN02-CSR",
60 .ack = ack_kn02_irq, 58 .irq_ack = ack_kn02_irq,
61 .mask = mask_kn02_irq, 59 .irq_mask = mask_kn02_irq,
62 .mask_ack = ack_kn02_irq, 60 .irq_mask_ack = ack_kn02_irq,
63 .unmask = unmask_kn02_irq, 61 .irq_unmask = unmask_kn02_irq,
64}; 62};
65 63
66
67void __init init_kn02_irqs(int base) 64void __init init_kn02_irqs(int base)
68{ 65{
69 volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE + 66 volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE +
diff --git a/arch/mips/emma/markeins/irq.c b/arch/mips/emma/markeins/irq.c
index 3a96799eb65f..9b1207ae2256 100644
--- a/arch/mips/emma/markeins/irq.c
+++ b/arch/mips/emma/markeins/irq.c
@@ -34,13 +34,10 @@
34 34
35#include <asm/emma/emma2rh.h> 35#include <asm/emma/emma2rh.h>
36 36
37static void emma2rh_irq_enable(unsigned int irq) 37static void emma2rh_irq_enable(struct irq_data *d)
38{ 38{
39 u32 reg_value; 39 unsigned int irq = d->irq - EMMA2RH_IRQ_BASE;
40 u32 reg_bitmask; 40 u32 reg_value, reg_bitmask, reg_index;
41 u32 reg_index;
42
43 irq -= EMMA2RH_IRQ_BASE;
44 41
45 reg_index = EMMA2RH_BHIF_INT_EN_0 + 42 reg_index = EMMA2RH_BHIF_INT_EN_0 +
46 (EMMA2RH_BHIF_INT_EN_1 - EMMA2RH_BHIF_INT_EN_0) * (irq / 32); 43 (EMMA2RH_BHIF_INT_EN_1 - EMMA2RH_BHIF_INT_EN_0) * (irq / 32);
@@ -49,13 +46,10 @@ static void emma2rh_irq_enable(unsigned int irq)
49 emma2rh_out32(reg_index, reg_value | reg_bitmask); 46 emma2rh_out32(reg_index, reg_value | reg_bitmask);
50} 47}
51 48
52static void emma2rh_irq_disable(unsigned int irq) 49static void emma2rh_irq_disable(struct irq_data *d)
53{ 50{
54 u32 reg_value; 51 unsigned int irq = d->irq - EMMA2RH_IRQ_BASE;
55 u32 reg_bitmask; 52 u32 reg_value, reg_bitmask, reg_index;
56 u32 reg_index;
57
58 irq -= EMMA2RH_IRQ_BASE;
59 53
60 reg_index = EMMA2RH_BHIF_INT_EN_0 + 54 reg_index = EMMA2RH_BHIF_INT_EN_0 +
61 (EMMA2RH_BHIF_INT_EN_1 - EMMA2RH_BHIF_INT_EN_0) * (irq / 32); 55 (EMMA2RH_BHIF_INT_EN_1 - EMMA2RH_BHIF_INT_EN_0) * (irq / 32);
@@ -66,10 +60,8 @@ static void emma2rh_irq_disable(unsigned int irq)
66 60
67struct irq_chip emma2rh_irq_controller = { 61struct irq_chip emma2rh_irq_controller = {
68 .name = "emma2rh_irq", 62 .name = "emma2rh_irq",
69 .ack = emma2rh_irq_disable, 63 .irq_mask = emma2rh_irq_disable,
70 .mask = emma2rh_irq_disable, 64 .irq_unmask = emma2rh_irq_enable,
71 .mask_ack = emma2rh_irq_disable,
72 .unmask = emma2rh_irq_enable,
73}; 65};
74 66
75void emma2rh_irq_init(void) 67void emma2rh_irq_init(void)
@@ -82,23 +74,21 @@ void emma2rh_irq_init(void)
82 handle_level_irq, "level"); 74 handle_level_irq, "level");
83} 75}
84 76
85static void emma2rh_sw_irq_enable(unsigned int irq) 77static void emma2rh_sw_irq_enable(struct irq_data *d)
86{ 78{
79 unsigned int irq = d->irq - EMMA2RH_SW_IRQ_BASE;
87 u32 reg; 80 u32 reg;
88 81
89 irq -= EMMA2RH_SW_IRQ_BASE;
90
91 reg = emma2rh_in32(EMMA2RH_BHIF_SW_INT_EN); 82 reg = emma2rh_in32(EMMA2RH_BHIF_SW_INT_EN);
92 reg |= 1 << irq; 83 reg |= 1 << irq;
93 emma2rh_out32(EMMA2RH_BHIF_SW_INT_EN, reg); 84 emma2rh_out32(EMMA2RH_BHIF_SW_INT_EN, reg);
94} 85}
95 86
96static void emma2rh_sw_irq_disable(unsigned int irq) 87static void emma2rh_sw_irq_disable(struct irq_data *d)
97{ 88{
89 unsigned int irq = d->irq - EMMA2RH_SW_IRQ_BASE;
98 u32 reg; 90 u32 reg;
99 91
100 irq -= EMMA2RH_SW_IRQ_BASE;
101
102 reg = emma2rh_in32(EMMA2RH_BHIF_SW_INT_EN); 92 reg = emma2rh_in32(EMMA2RH_BHIF_SW_INT_EN);
103 reg &= ~(1 << irq); 93 reg &= ~(1 << irq);
104 emma2rh_out32(EMMA2RH_BHIF_SW_INT_EN, reg); 94 emma2rh_out32(EMMA2RH_BHIF_SW_INT_EN, reg);
@@ -106,10 +96,8 @@ static void emma2rh_sw_irq_disable(unsigned int irq)
106 96
107struct irq_chip emma2rh_sw_irq_controller = { 97struct irq_chip emma2rh_sw_irq_controller = {
108 .name = "emma2rh_sw_irq", 98 .name = "emma2rh_sw_irq",
109 .ack = emma2rh_sw_irq_disable, 99 .irq_mask = emma2rh_sw_irq_disable,
110 .mask = emma2rh_sw_irq_disable, 100 .irq_unmask = emma2rh_sw_irq_enable,
111 .mask_ack = emma2rh_sw_irq_disable,
112 .unmask = emma2rh_sw_irq_enable,
113}; 101};
114 102
115void emma2rh_sw_irq_init(void) 103void emma2rh_sw_irq_init(void)
@@ -122,39 +110,38 @@ void emma2rh_sw_irq_init(void)
122 handle_level_irq, "level"); 110 handle_level_irq, "level");
123} 111}
124 112
125static void emma2rh_gpio_irq_enable(unsigned int irq) 113static void emma2rh_gpio_irq_enable(struct irq_data *d)
126{ 114{
115 unsigned int irq = d->irq - EMMA2RH_GPIO_IRQ_BASE;
127 u32 reg; 116 u32 reg;
128 117
129 irq -= EMMA2RH_GPIO_IRQ_BASE;
130
131 reg = emma2rh_in32(EMMA2RH_GPIO_INT_MASK); 118 reg = emma2rh_in32(EMMA2RH_GPIO_INT_MASK);
132 reg |= 1 << irq; 119 reg |= 1 << irq;
133 emma2rh_out32(EMMA2RH_GPIO_INT_MASK, reg); 120 emma2rh_out32(EMMA2RH_GPIO_INT_MASK, reg);
134} 121}
135 122
136static void emma2rh_gpio_irq_disable(unsigned int irq) 123static void emma2rh_gpio_irq_disable(struct irq_data *d)
137{ 124{
125 unsigned int irq = d->irq - EMMA2RH_GPIO_IRQ_BASE;
138 u32 reg; 126 u32 reg;
139 127
140 irq -= EMMA2RH_GPIO_IRQ_BASE;
141
142 reg = emma2rh_in32(EMMA2RH_GPIO_INT_MASK); 128 reg = emma2rh_in32(EMMA2RH_GPIO_INT_MASK);
143 reg &= ~(1 << irq); 129 reg &= ~(1 << irq);
144 emma2rh_out32(EMMA2RH_GPIO_INT_MASK, reg); 130 emma2rh_out32(EMMA2RH_GPIO_INT_MASK, reg);
145} 131}
146 132
147static void emma2rh_gpio_irq_ack(unsigned int irq) 133static void emma2rh_gpio_irq_ack(struct irq_data *d)
148{ 134{
149 irq -= EMMA2RH_GPIO_IRQ_BASE; 135 unsigned int irq = d->irq - EMMA2RH_GPIO_IRQ_BASE;
136
150 emma2rh_out32(EMMA2RH_GPIO_INT_ST, ~(1 << irq)); 137 emma2rh_out32(EMMA2RH_GPIO_INT_ST, ~(1 << irq));
151} 138}
152 139
153static void emma2rh_gpio_irq_mask_ack(unsigned int irq) 140static void emma2rh_gpio_irq_mask_ack(struct irq_data *d)
154{ 141{
142 unsigned int irq = d->irq - EMMA2RH_GPIO_IRQ_BASE;
155 u32 reg; 143 u32 reg;
156 144
157 irq -= EMMA2RH_GPIO_IRQ_BASE;
158 emma2rh_out32(EMMA2RH_GPIO_INT_ST, ~(1 << irq)); 145 emma2rh_out32(EMMA2RH_GPIO_INT_ST, ~(1 << irq));
159 146
160 reg = emma2rh_in32(EMMA2RH_GPIO_INT_MASK); 147 reg = emma2rh_in32(EMMA2RH_GPIO_INT_MASK);
@@ -164,10 +151,10 @@ static void emma2rh_gpio_irq_mask_ack(unsigned int irq)
164 151
165struct irq_chip emma2rh_gpio_irq_controller = { 152struct irq_chip emma2rh_gpio_irq_controller = {
166 .name = "emma2rh_gpio_irq", 153 .name = "emma2rh_gpio_irq",
167 .ack = emma2rh_gpio_irq_ack, 154 .irq_ack = emma2rh_gpio_irq_ack,
168 .mask = emma2rh_gpio_irq_disable, 155 .irq_mask = emma2rh_gpio_irq_disable,
169 .mask_ack = emma2rh_gpio_irq_mask_ack, 156 .irq_mask_ack = emma2rh_gpio_irq_mask_ack,
170 .unmask = emma2rh_gpio_irq_enable, 157 .irq_unmask = emma2rh_gpio_irq_enable,
171}; 158};
172 159
173void emma2rh_gpio_irq_init(void) 160void emma2rh_gpio_irq_init(void)
diff --git a/arch/mips/include/asm/irq.h b/arch/mips/include/asm/irq.h
index b003ed52ed17..0ec01294b063 100644
--- a/arch/mips/include/asm/irq.h
+++ b/arch/mips/include/asm/irq.h
@@ -55,9 +55,9 @@ static inline void smtc_im_ack_irq(unsigned int irq)
55#ifdef CONFIG_MIPS_MT_SMTC_IRQAFF 55#ifdef CONFIG_MIPS_MT_SMTC_IRQAFF
56#include <linux/cpumask.h> 56#include <linux/cpumask.h>
57 57
58extern int plat_set_irq_affinity(unsigned int irq, 58extern int plat_set_irq_affinity(struct irq_data *d,
59 const struct cpumask *affinity); 59 const struct cpumask *affinity, bool force);
60extern void smtc_forward_irq(unsigned int irq); 60extern void smtc_forward_irq(struct irq_data *d);
61 61
62/* 62/*
63 * IRQ affinity hook invoked at the beginning of interrupt dispatch 63 * IRQ affinity hook invoked at the beginning of interrupt dispatch
@@ -70,51 +70,53 @@ extern void smtc_forward_irq(unsigned int irq);
70 * cpumask implementations, this version is optimistically assuming 70 * cpumask implementations, this version is optimistically assuming
71 * that cpumask.h macro overhead is reasonable during interrupt dispatch. 71 * that cpumask.h macro overhead is reasonable during interrupt dispatch.
72 */ 72 */
73#define IRQ_AFFINITY_HOOK(irq) \ 73static inline int handle_on_other_cpu(unsigned int irq)
74do { \ 74{
75 if (!cpumask_test_cpu(smp_processor_id(), irq_desc[irq].affinity)) {\ 75 struct irq_data *d = irq_get_irq_data(irq);
76 smtc_forward_irq(irq); \ 76
77 irq_exit(); \ 77 if (cpumask_test_cpu(smp_processor_id(), d->affinity))
78 return; \ 78 return 0;
79 } \ 79 smtc_forward_irq(d);
80} while (0) 80 return 1;
81}
81 82
82#else /* Not doing SMTC affinity */ 83#else /* Not doing SMTC affinity */
83 84
84#define IRQ_AFFINITY_HOOK(irq) do { } while (0) 85static inline int handle_on_other_cpu(unsigned int irq) { return 0; }
85 86
86#endif /* CONFIG_MIPS_MT_SMTC_IRQAFF */ 87#endif /* CONFIG_MIPS_MT_SMTC_IRQAFF */
87 88
88#ifdef CONFIG_MIPS_MT_SMTC_IM_BACKSTOP 89#ifdef CONFIG_MIPS_MT_SMTC_IM_BACKSTOP
89 90
91static inline void smtc_im_backstop(unsigned int irq)
92{
93 if (irq_hwmask[irq] & 0x0000ff00)
94 write_c0_tccontext(read_c0_tccontext() &
95 ~(irq_hwmask[irq] & 0x0000ff00));
96}
97
90/* 98/*
91 * Clear interrupt mask handling "backstop" if irq_hwmask 99 * Clear interrupt mask handling "backstop" if irq_hwmask
92 * entry so indicates. This implies that the ack() or end() 100 * entry so indicates. This implies that the ack() or end()
93 * functions will take over re-enabling the low-level mask. 101 * functions will take over re-enabling the low-level mask.
94 * Otherwise it will be done on return from exception. 102 * Otherwise it will be done on return from exception.
95 */ 103 */
96#define __DO_IRQ_SMTC_HOOK(irq) \ 104static inline int smtc_handle_on_other_cpu(unsigned int irq)
97do { \ 105{
98 IRQ_AFFINITY_HOOK(irq); \ 106 int ret = handle_on_other_cpu(irq);
99 if (irq_hwmask[irq] & 0x0000ff00) \ 107
100 write_c0_tccontext(read_c0_tccontext() & \ 108 if (!ret)
101 ~(irq_hwmask[irq] & 0x0000ff00)); \ 109 smtc_im_backstop(irq);
102} while (0) 110 return ret;
103 111}
104#define __NO_AFFINITY_IRQ_SMTC_HOOK(irq) \
105do { \
106 if (irq_hwmask[irq] & 0x0000ff00) \
107 write_c0_tccontext(read_c0_tccontext() & \
108 ~(irq_hwmask[irq] & 0x0000ff00)); \
109} while (0)
110 112
111#else 113#else
112 114
113#define __DO_IRQ_SMTC_HOOK(irq) \ 115static inline void smtc_im_backstop(unsigned int irq) { }
114do { \ 116static inline int smtc_handle_on_other_cpu(unsigned int irq)
115 IRQ_AFFINITY_HOOK(irq); \ 117{
116} while (0) 118 return handle_on_other_cpu(irq);
117#define __NO_AFFINITY_IRQ_SMTC_HOOK(irq) do { } while (0) 119}
118 120
119#endif 121#endif
120 122
diff --git a/arch/mips/include/asm/pmc-sierra/msp71xx/cpu-feature-overrides.h b/arch/mips/include/asm/pmc-sierra/msp71xx/cpu-feature-overrides.h
new file mode 100644
index 000000000000..a80801b094bd
--- /dev/null
+++ b/arch/mips/include/asm/pmc-sierra/msp71xx/cpu-feature-overrides.h
@@ -0,0 +1,21 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2003, 04, 07 Ralf Baechle (ralf@linux-mips.org)
7 */
8#ifndef __ASM_MACH_MSP71XX_CPU_FEATURE_OVERRIDES_H
9#define __ASM_MACH_MSP71XX_CPU_FEATURE_OVERRIDES_H
10
11#define cpu_has_mips16 1
12#define cpu_has_dsp 1
13#define cpu_has_mipsmt 1
14#define cpu_has_fpu 0
15
16#define cpu_has_mips32r1 0
17#define cpu_has_mips32r2 1
18#define cpu_has_mips64r1 0
19#define cpu_has_mips64r2 0
20
21#endif /* __ASM_MACH_MSP71XX_CPU_FEATURE_OVERRIDES_H */
diff --git a/arch/mips/include/asm/pmc-sierra/msp71xx/msp_gpio_macros.h b/arch/mips/include/asm/pmc-sierra/msp71xx/msp_gpio_macros.h
new file mode 100644
index 000000000000..156f320c69e7
--- /dev/null
+++ b/arch/mips/include/asm/pmc-sierra/msp71xx/msp_gpio_macros.h
@@ -0,0 +1,343 @@
1/*
2 *
3 * Macros for external SMP-safe access to the PMC MSP71xx reference
4 * board GPIO pins
5 *
6 * Copyright 2010 PMC-Sierra, Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
14 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
15 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
16 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
19 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
20 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
23 *
24 * You should have received a copy of the GNU General Public License along
25 * with this program; if not, write to the Free Software Foundation, Inc.,
26 * 675 Mass Ave, Cambridge, MA 02139, USA.
27 */
28
29#ifndef __MSP_GPIO_MACROS_H__
30#define __MSP_GPIO_MACROS_H__
31
32#include <msp_regops.h>
33#include <msp_regs.h>
34
35#ifdef CONFIG_PMC_MSP7120_GW
36#define MSP_NUM_GPIOS 20
37#else
38#define MSP_NUM_GPIOS 28
39#endif
40
41/* -- GPIO Enumerations -- */
42enum msp_gpio_data {
43 MSP_GPIO_LO = 0,
44 MSP_GPIO_HI = 1,
45 MSP_GPIO_NONE, /* Special - Means pin is out of range */
46 MSP_GPIO_TOGGLE, /* Special - Sets pin to opposite */
47};
48
49enum msp_gpio_mode {
50 MSP_GPIO_INPUT = 0x0,
51 /* MSP_GPIO_ INTERRUPT = 0x1, Not supported yet */
52 MSP_GPIO_UART_INPUT = 0x2, /* Only GPIO 4 or 5 */
53 MSP_GPIO_OUTPUT = 0x8,
54 MSP_GPIO_UART_OUTPUT = 0x9, /* Only GPIO 2 or 3 */
55 MSP_GPIO_PERIF_TIMERA = 0x9, /* Only GPIO 0 or 1 */
56 MSP_GPIO_PERIF_TIMERB = 0xa, /* Only GPIO 0 or 1 */
57 MSP_GPIO_UNKNOWN = 0xb, /* No such GPIO or mode */
58};
59
60/* -- Static Tables -- */
61
62/* Maps pins to data register */
63static volatile u32 * const MSP_GPIO_DATA_REGISTER[] = {
64 /* GPIO 0 and 1 on the first register */
65 GPIO_DATA1_REG, GPIO_DATA1_REG,
66 /* GPIO 2, 3, 4, and 5 on the second register */
67 GPIO_DATA2_REG, GPIO_DATA2_REG, GPIO_DATA2_REG, GPIO_DATA2_REG,
68 /* GPIO 6, 7, 8, and 9 on the third register */
69 GPIO_DATA3_REG, GPIO_DATA3_REG, GPIO_DATA3_REG, GPIO_DATA3_REG,
70 /* GPIO 10, 11, 12, 13, 14, and 15 on the fourth register */
71 GPIO_DATA4_REG, GPIO_DATA4_REG, GPIO_DATA4_REG, GPIO_DATA4_REG,
72 GPIO_DATA4_REG, GPIO_DATA4_REG,
73 /* GPIO 16 - 23 on the first strange EXTENDED register */
74 EXTENDED_GPIO1_REG, EXTENDED_GPIO1_REG, EXTENDED_GPIO1_REG,
75 EXTENDED_GPIO1_REG, EXTENDED_GPIO1_REG, EXTENDED_GPIO1_REG,
76 EXTENDED_GPIO1_REG, EXTENDED_GPIO1_REG,
77 /* GPIO 24 - 27 on the second strange EXTENDED register */
78 EXTENDED_GPIO2_REG, EXTENDED_GPIO2_REG, EXTENDED_GPIO2_REG,
79 EXTENDED_GPIO2_REG,
80};
81
82/* Maps pins to mode register */
83static volatile u32 * const MSP_GPIO_MODE_REGISTER[] = {
84 /* GPIO 0 and 1 on the first register */
85 GPIO_CFG1_REG, GPIO_CFG1_REG,
86 /* GPIO 2, 3, 4, and 5 on the second register */
87 GPIO_CFG2_REG, GPIO_CFG2_REG, GPIO_CFG2_REG, GPIO_CFG2_REG,
88 /* GPIO 6, 7, 8, and 9 on the third register */
89 GPIO_CFG3_REG, GPIO_CFG3_REG, GPIO_CFG3_REG, GPIO_CFG3_REG,
90 /* GPIO 10, 11, 12, 13, 14, and 15 on the fourth register */
91 GPIO_CFG4_REG, GPIO_CFG4_REG, GPIO_CFG4_REG, GPIO_CFG4_REG,
92 GPIO_CFG4_REG, GPIO_CFG4_REG,
93 /* GPIO 16 - 23 on the first strange EXTENDED register */
94 EXTENDED_GPIO1_REG, EXTENDED_GPIO1_REG, EXTENDED_GPIO1_REG,
95 EXTENDED_GPIO1_REG, EXTENDED_GPIO1_REG, EXTENDED_GPIO1_REG,
96 EXTENDED_GPIO1_REG, EXTENDED_GPIO1_REG,
97 /* GPIO 24 - 27 on the second strange EXTENDED register */
98 EXTENDED_GPIO2_REG, EXTENDED_GPIO2_REG, EXTENDED_GPIO2_REG,
99 EXTENDED_GPIO2_REG,
100};
101
102/* Maps 'basic' pins to relative offset from 0 per register */
103static int MSP_GPIO_OFFSET[] = {
104 /* GPIO 0 and 1 on the first register */
105 0, 0,
106 /* GPIO 2, 3, 4, and 5 on the second register */
107 2, 2, 2, 2,
108 /* GPIO 6, 7, 8, and 9 on the third register */
109 6, 6, 6, 6,
110 /* GPIO 10, 11, 12, 13, 14, and 15 on the fourth register */
111 10, 10, 10, 10, 10, 10,
112};
113
114/* Maps MODE to allowed pin mask */
115static unsigned int MSP_GPIO_MODE_ALLOWED[] = {
116 0xffffffff, /* Mode 0 - INPUT */
117 0x00000, /* Mode 1 - INTERRUPT */
118 0x00030, /* Mode 2 - UART_INPUT (GPIO 4, 5)*/
119 0, 0, 0, 0, 0, /* Modes 3, 4, 5, 6, and 7 are reserved */
120 0xffffffff, /* Mode 8 - OUTPUT */
121 0x0000f, /* Mode 9 - UART_OUTPUT/
122 PERF_TIMERA (GPIO 0, 1, 2, 3) */
123 0x00003, /* Mode a - PERF_TIMERB (GPIO 0, 1) */
124 0x00000, /* Mode b - Not really a mode! */
125};
126
127/* -- Bit masks -- */
128
129/* This gives you the 'register relative offset gpio' number */
130#define OFFSET_GPIO_NUMBER(gpio) (gpio - MSP_GPIO_OFFSET[gpio])
131
132/* These take the 'register relative offset gpio' number */
133#define BASIC_DATA_REG_MASK(ogpio) (1 << ogpio)
134#define BASIC_MODE_REG_VALUE(mode, ogpio) \
135 (mode << BASIC_MODE_REG_SHIFT(ogpio))
136#define BASIC_MODE_REG_MASK(ogpio) \
137 BASIC_MODE_REG_VALUE(0xf, ogpio)
138#define BASIC_MODE_REG_SHIFT(ogpio) (ogpio * 4)
139#define BASIC_MODE_REG_FROM_REG(data, ogpio) \
140 ((data & BASIC_MODE_REG_MASK(ogpio)) >> BASIC_MODE_REG_SHIFT(ogpio))
141
142/* These take the actual GPIO number (0 through 15) */
143#define BASIC_DATA_MASK(gpio) \
144 BASIC_DATA_REG_MASK(OFFSET_GPIO_NUMBER(gpio))
145#define BASIC_MODE_MASK(gpio) \
146 BASIC_MODE_REG_MASK(OFFSET_GPIO_NUMBER(gpio))
147#define BASIC_MODE(mode, gpio) \
148 BASIC_MODE_REG_VALUE(mode, OFFSET_GPIO_NUMBER(gpio))
149#define BASIC_MODE_SHIFT(gpio) \
150 BASIC_MODE_REG_SHIFT(OFFSET_GPIO_NUMBER(gpio))
151#define BASIC_MODE_FROM_REG(data, gpio) \
152 BASIC_MODE_REG_FROM_REG(data, OFFSET_GPIO_NUMBER(gpio))
153
154/*
155 * Each extended GPIO register is 32 bits long and is responsible for up to
156 * eight GPIOs. The least significant 16 bits contain the set and clear bit
157 * pair for each of the GPIOs. The most significant 16 bits contain the
158 * disable and enable bit pair for each of the GPIOs. For example, the
159 * extended GPIO reg for GPIOs 16-23 is as follows:
160 *
161 * 31: GPIO23_DISABLE
162 * ...
163 * 19: GPIO17_DISABLE
164 * 18: GPIO17_ENABLE
165 * 17: GPIO16_DISABLE
166 * 16: GPIO16_ENABLE
167 * ...
168 * 3: GPIO17_SET
169 * 2: GPIO17_CLEAR
170 * 1: GPIO16_SET
171 * 0: GPIO16_CLEAR
172 */
173
174/* This gives the 'register relative offset gpio' number */
175#define EXTENDED_OFFSET_GPIO(gpio) (gpio < 24 ? gpio - 16 : gpio - 24)
176
177/* These take the 'register relative offset gpio' number */
178#define EXTENDED_REG_DISABLE(ogpio) (0x2 << ((ogpio * 2) + 16))
179#define EXTENDED_REG_ENABLE(ogpio) (0x1 << ((ogpio * 2) + 16))
180#define EXTENDED_REG_SET(ogpio) (0x2 << (ogpio * 2))
181#define EXTENDED_REG_CLR(ogpio) (0x1 << (ogpio * 2))
182
183/* These take the actual GPIO number (16 through 27) */
184#define EXTENDED_DISABLE(gpio) \
185 EXTENDED_REG_DISABLE(EXTENDED_OFFSET_GPIO(gpio))
186#define EXTENDED_ENABLE(gpio) \
187 EXTENDED_REG_ENABLE(EXTENDED_OFFSET_GPIO(gpio))
188#define EXTENDED_SET(gpio) \
189 EXTENDED_REG_SET(EXTENDED_OFFSET_GPIO(gpio))
190#define EXTENDED_CLR(gpio) \
191 EXTENDED_REG_CLR(EXTENDED_OFFSET_GPIO(gpio))
192
193#define EXTENDED_FULL_MASK (0xffffffff)
194
195/* -- API inline-functions -- */
196
197/*
198 * Gets the current value of the specified pin
199 */
200static inline enum msp_gpio_data msp_gpio_pin_get(unsigned int gpio)
201{
202 u32 pinhi_mask = 0, pinhi_mask2 = 0;
203
204 if (gpio >= MSP_NUM_GPIOS)
205 return MSP_GPIO_NONE;
206
207 if (gpio < 16) {
208 pinhi_mask = BASIC_DATA_MASK(gpio);
209 } else {
210 /*
211 * Two cases are possible with the EXTENDED register:
212 * - In output mode (ENABLED flag set), check the CLR bit
213 * - In input mode (ENABLED flag not set), check the SET bit
214 */
215 pinhi_mask = EXTENDED_ENABLE(gpio) | EXTENDED_CLR(gpio);
216 pinhi_mask2 = EXTENDED_SET(gpio);
217 }
218 if (((*MSP_GPIO_DATA_REGISTER[gpio] & pinhi_mask) == pinhi_mask) ||
219 (*MSP_GPIO_DATA_REGISTER[gpio] & pinhi_mask2))
220 return MSP_GPIO_HI;
221 else
222 return MSP_GPIO_LO;
223}
224
225/* Sets the specified pin to the specified value */
226static inline void msp_gpio_pin_set(enum msp_gpio_data data, unsigned int gpio)
227{
228 if (gpio >= MSP_NUM_GPIOS)
229 return;
230
231 if (gpio < 16) {
232 if (data == MSP_GPIO_TOGGLE)
233 toggle_reg32(MSP_GPIO_DATA_REGISTER[gpio],
234 BASIC_DATA_MASK(gpio));
235 else if (data == MSP_GPIO_HI)
236 set_reg32(MSP_GPIO_DATA_REGISTER[gpio],
237 BASIC_DATA_MASK(gpio));
238 else
239 clear_reg32(MSP_GPIO_DATA_REGISTER[gpio],
240 BASIC_DATA_MASK(gpio));
241 } else {
242 if (data == MSP_GPIO_TOGGLE) {
243 /* Special ugly case:
244 * We have to read the CLR bit.
245 * If set, we write the CLR bit.
246 * If not, we write the SET bit.
247 */
248 u32 tmpdata;
249
250 custom_read_reg32(MSP_GPIO_DATA_REGISTER[gpio],
251 tmpdata);
252 if (tmpdata & EXTENDED_CLR(gpio))
253 tmpdata = EXTENDED_CLR(gpio);
254 else
255 tmpdata = EXTENDED_SET(gpio);
256 custom_write_reg32(MSP_GPIO_DATA_REGISTER[gpio],
257 tmpdata);
258 } else {
259 u32 newdata;
260
261 if (data == MSP_GPIO_HI)
262 newdata = EXTENDED_SET(gpio);
263 else
264 newdata = EXTENDED_CLR(gpio);
265 set_value_reg32(MSP_GPIO_DATA_REGISTER[gpio],
266 EXTENDED_FULL_MASK, newdata);
267 }
268 }
269}
270
271/* Sets the specified pin to the specified value */
272static inline void msp_gpio_pin_hi(unsigned int gpio)
273{
274 msp_gpio_pin_set(MSP_GPIO_HI, gpio);
275}
276
277/* Sets the specified pin to the specified value */
278static inline void msp_gpio_pin_lo(unsigned int gpio)
279{
280 msp_gpio_pin_set(MSP_GPIO_LO, gpio);
281}
282
283/* Sets the specified pin to the opposite value */
284static inline void msp_gpio_pin_toggle(unsigned int gpio)
285{
286 msp_gpio_pin_set(MSP_GPIO_TOGGLE, gpio);
287}
288
289/* Gets the mode of the specified pin */
290static inline enum msp_gpio_mode msp_gpio_pin_get_mode(unsigned int gpio)
291{
292 enum msp_gpio_mode retval = MSP_GPIO_UNKNOWN;
293 uint32_t data;
294
295 if (gpio >= MSP_NUM_GPIOS)
296 return retval;
297
298 data = *MSP_GPIO_MODE_REGISTER[gpio];
299
300 if (gpio < 16) {
301 retval = BASIC_MODE_FROM_REG(data, gpio);
302 } else {
303 /* Extended pins can only be either INPUT or OUTPUT */
304 if (data & EXTENDED_ENABLE(gpio))
305 retval = MSP_GPIO_OUTPUT;
306 else
307 retval = MSP_GPIO_INPUT;
308 }
309
310 return retval;
311}
312
313/*
314 * Sets the specified mode on the requested pin
315 * Returns 0 on success, or -1 if that mode is not allowed on this pin
316 */
317static inline int msp_gpio_pin_mode(enum msp_gpio_mode mode, unsigned int gpio)
318{
319 u32 modemask, newmode;
320
321 if ((1 << gpio) & ~MSP_GPIO_MODE_ALLOWED[mode])
322 return -1;
323
324 if (gpio >= MSP_NUM_GPIOS)
325 return -1;
326
327 if (gpio < 16) {
328 modemask = BASIC_MODE_MASK(gpio);
329 newmode = BASIC_MODE(mode, gpio);
330 } else {
331 modemask = EXTENDED_FULL_MASK;
332 if (mode == MSP_GPIO_INPUT)
333 newmode = EXTENDED_DISABLE(gpio);
334 else
335 newmode = EXTENDED_ENABLE(gpio);
336 }
337 /* Do the set atomically */
338 set_value_reg32(MSP_GPIO_MODE_REGISTER[gpio], modemask, newmode);
339
340 return 0;
341}
342
343#endif /* __MSP_GPIO_MACROS_H__ */
diff --git a/arch/mips/include/asm/pmc-sierra/msp71xx/msp_regs.h b/arch/mips/include/asm/pmc-sierra/msp71xx/msp_regs.h
index 603eb737b4a8..692c1b658b92 100644
--- a/arch/mips/include/asm/pmc-sierra/msp71xx/msp_regs.h
+++ b/arch/mips/include/asm/pmc-sierra/msp71xx/msp_regs.h
@@ -91,12 +91,10 @@
91 /* MAC C device registers */ 91 /* MAC C device registers */
92#define MSP_ADSL2_BASE (MSP_MSB_BASE + 0xA80000) 92#define MSP_ADSL2_BASE (MSP_MSB_BASE + 0xA80000)
93 /* ADSL2 device registers */ 93 /* ADSL2 device registers */
94#define MSP_USB_BASE (MSP_MSB_BASE + 0xB40000) 94#define MSP_USB0_BASE (MSP_MSB_BASE + 0xB00000)
95 /* USB device registers */ 95 /* USB0 device registers */
96#define MSP_USB_BASE_START (MSP_MSB_BASE + 0xB40100) 96#define MSP_USB1_BASE (MSP_MSB_BASE + 0x300000)
97 /* USB device registers */ 97 /* USB1 device registers */
98#define MSP_USB_BASE_END (MSP_MSB_BASE + 0xB401FF)
99 /* USB device registers */
100#define MSP_CPUIF_BASE (MSP_MSB_BASE + 0xC00000) 98#define MSP_CPUIF_BASE (MSP_MSB_BASE + 0xC00000)
101 /* CPU interface registers */ 99 /* CPU interface registers */
102 100
@@ -319,8 +317,11 @@
319#define CPU_ERR2_REG regptr(MSP_SLP_BASE + 0x184) 317#define CPU_ERR2_REG regptr(MSP_SLP_BASE + 0x184)
320 /* CPU/SLP Error status 1 */ 318 /* CPU/SLP Error status 1 */
321 319
322#define EXTENDED_GPIO_REG regptr(MSP_SLP_BASE + 0x188) 320/* Extended GPIO registers */
323 /* Extended GPIO register */ 321#define EXTENDED_GPIO1_REG regptr(MSP_SLP_BASE + 0x188)
322#define EXTENDED_GPIO2_REG regptr(MSP_SLP_BASE + 0x18c)
323#define EXTENDED_GPIO_REG EXTENDED_GPIO1_REG
324 /* Backward-compatibility */
324 325
325/* System Error registers */ 326/* System Error registers */
326#define SLP_ERR_STS_REG regptr(MSP_SLP_BASE + 0x190) 327#define SLP_ERR_STS_REG regptr(MSP_SLP_BASE + 0x190)
diff --git a/arch/mips/include/asm/pmc-sierra/msp71xx/msp_usb.h b/arch/mips/include/asm/pmc-sierra/msp71xx/msp_usb.h
new file mode 100644
index 000000000000..4c9348df9df2
--- /dev/null
+++ b/arch/mips/include/asm/pmc-sierra/msp71xx/msp_usb.h
@@ -0,0 +1,144 @@
1/******************************************************************
2 * Copyright (c) 2000-2007 PMC-Sierra INC.
3 *
4 * This program is free software; you can redistribute it
5 * and/or modify it under the terms of the GNU General
6 * Public License as published by the Free Software
7 * Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * This program is distributed in the hope that it will be
11 * useful, but WITHOUT ANY WARRANTY; without even the implied
12 * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
13 * PURPOSE. See the GNU General Public License for more
14 * details.
15 *
16 * You should have received a copy of the GNU General Public
17 * License along with this program; if not, write to the Free
18 * Software Foundation, Inc., 675 Mass Ave, Cambridge, MA
19 * 02139, USA.
20 *
21 * PMC-SIERRA INC. DISCLAIMS ANY LIABILITY OF ANY KIND
22 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS
23 * SOFTWARE.
24 */
25#ifndef MSP_USB_H_
26#define MSP_USB_H_
27
28#ifdef CONFIG_MSP_HAS_DUAL_USB
29#define NUM_USB_DEVS 2
30#else
31#define NUM_USB_DEVS 1
32#endif
33
34/* Register spaces for USB host 0 */
35#define MSP_USB0_MAB_START (MSP_USB0_BASE + 0x0)
36#define MSP_USB0_MAB_END (MSP_USB0_BASE + 0x17)
37#define MSP_USB0_ID_START (MSP_USB0_BASE + 0x40000)
38#define MSP_USB0_ID_END (MSP_USB0_BASE + 0x4008f)
39#define MSP_USB0_HS_START (MSP_USB0_BASE + 0x40100)
40#define MSP_USB0_HS_END (MSP_USB0_BASE + 0x401FF)
41
42/* Register spaces for USB host 1 */
43#define MSP_USB1_MAB_START (MSP_USB1_BASE + 0x0)
44#define MSP_USB1_MAB_END (MSP_USB1_BASE + 0x17)
45#define MSP_USB1_ID_START (MSP_USB1_BASE + 0x40000)
46#define MSP_USB1_ID_END (MSP_USB1_BASE + 0x4008f)
47#define MSP_USB1_HS_START (MSP_USB1_BASE + 0x40100)
48#define MSP_USB1_HS_END (MSP_USB1_BASE + 0x401ff)
49
50/* USB Identification registers */
51struct msp_usbid_regs {
52 u32 id; /* 0x0: Identification register */
53 u32 hwgen; /* 0x4: General HW params */
54 u32 hwhost; /* 0x8: Host HW params */
55 u32 hwdev; /* 0xc: Device HW params */
56 u32 hwtxbuf; /* 0x10: Tx buffer HW params */
57 u32 hwrxbuf; /* 0x14: Rx buffer HW params */
58 u32 reserved[26];
59 u32 timer0_load; /* 0x80: General-purpose timer 0 load*/
60 u32 timer0_ctrl; /* 0x84: General-purpose timer 0 control */
61 u32 timer1_load; /* 0x88: General-purpose timer 1 load*/
62 u32 timer1_ctrl; /* 0x8c: General-purpose timer 1 control */
63};
64
65/* MSBus to AMBA registers */
66struct msp_mab_regs {
67 u32 isr; /* 0x0: Interrupt status */
68 u32 imr; /* 0x4: Interrupt mask */
69 u32 thcr0; /* 0x8: Transaction header capture 0 */
70 u32 thcr1; /* 0xc: Transaction header capture 1 */
71 u32 int_stat; /* 0x10: Interrupt status summary */
72 u32 phy_cfg; /* 0x14: USB phy config */
73};
74
75/* EHCI registers */
76struct msp_usbhs_regs {
77 u32 hciver; /* 0x0: Version and offset to operational regs */
78 u32 hcsparams; /* 0x4: Host control structural parameters */
79 u32 hccparams; /* 0x8: Host control capability parameters */
80 u32 reserved0[5];
81 u32 dciver; /* 0x20: Device interface version */
82 u32 dccparams; /* 0x24: Device control capability parameters */
83 u32 reserved1[6];
84 u32 cmd; /* 0x40: USB command */
85 u32 sts; /* 0x44: USB status */
86 u32 int_ena; /* 0x48: USB interrupt enable */
87 u32 frindex; /* 0x4c: Frame index */
88 u32 reserved3;
89 union {
90 struct {
91 u32 flb_addr; /* 0x54: Frame list base address */
92 u32 next_async_addr; /* 0x58: next asynchronous addr */
93 u32 ttctrl; /* 0x5c: embedded transaction translator
94 async buffer status */
95 u32 burst_size; /* 0x60: Controller burst size */
96 u32 tx_fifo_ctrl; /* 0x64: Tx latency FIFO tuning */
97 u32 reserved0[4];
98 u32 endpt_nak; /* 0x78: Endpoint NAK */
99 u32 endpt_nak_ena; /* 0x7c: Endpoint NAK enable */
100 u32 cfg_flag; /* 0x80: Config flag */
101 u32 port_sc1; /* 0x84: Port status & control 1 */
102 u32 reserved1[7];
103 u32 otgsc; /* 0xa4: OTG status & control */
104 u32 mode; /* 0xa8: USB controller mode */
105 } host;
106
107 struct {
108 u32 dev_addr; /* 0x54: Device address */
109 u32 endpt_list_addr; /* 0x58: Endpoint list address */
110 u32 reserved0[7];
111 u32 endpt_nak; /* 0x74 */
112 u32 endpt_nak_ctrl; /* 0x78 */
113 u32 cfg_flag; /* 0x80 */
114 u32 port_sc1; /* 0x84: Port status & control 1 */
115 u32 reserved[7];
116 u32 otgsc; /* 0xa4: OTG status & control */
117 u32 mode; /* 0xa8: USB controller mode */
118 u32 endpt_setup_stat; /* 0xac */
119 u32 endpt_prime; /* 0xb0 */
120 u32 endpt_flush; /* 0xb4 */
121 u32 endpt_stat; /* 0xb8 */
122 u32 endpt_complete; /* 0xbc */
123 u32 endpt_ctrl0; /* 0xc0 */
124 u32 endpt_ctrl1; /* 0xc4 */
125 u32 endpt_ctrl2; /* 0xc8 */
126 u32 endpt_ctrl3; /* 0xcc */
127 } device;
128 } u;
129};
130/*
131 * Container for the more-generic platform_device.
132 * This exists mainly as a way to map the non-standard register
133 * spaces and make them accessible to the USB ISR.
134 */
135struct mspusb_device {
136 struct msp_mab_regs __iomem *mab_regs;
137 struct msp_usbid_regs __iomem *usbid_regs;
138 struct msp_usbhs_regs __iomem *usbhs_regs;
139 struct platform_device dev;
140};
141
142#define to_mspusb_device(x) container_of((x), struct mspusb_device, dev)
143#define TO_HOST_ID(x) ((x) & 0x3)
144#endif /*MSP_USB_H_*/
diff --git a/arch/mips/include/asm/spinlock.h b/arch/mips/include/asm/spinlock.h
index 396e402fbe2c..ca61e846ab0f 100644
--- a/arch/mips/include/asm/spinlock.h
+++ b/arch/mips/include/asm/spinlock.h
@@ -245,16 +245,16 @@ static inline void arch_read_lock(arch_rwlock_t *rw)
245 __asm__ __volatile__( 245 __asm__ __volatile__(
246 " .set noreorder # arch_read_lock \n" 246 " .set noreorder # arch_read_lock \n"
247 "1: ll %1, %2 \n" 247 "1: ll %1, %2 \n"
248 " bltz %1, 2f \n" 248 " bltz %1, 3f \n"
249 " addu %1, 1 \n" 249 " addu %1, 1 \n"
250 " sc %1, %0 \n" 250 "2: sc %1, %0 \n"
251 " beqz %1, 1b \n" 251 " beqz %1, 1b \n"
252 " nop \n" 252 " nop \n"
253 " .subsection 2 \n" 253 " .subsection 2 \n"
254 "2: ll %1, %2 \n" 254 "3: ll %1, %2 \n"
255 " bltz %1, 2b \n" 255 " bltz %1, 3b \n"
256 " addu %1, 1 \n" 256 " addu %1, 1 \n"
257 " b 1b \n" 257 " b 2b \n"
258 " nop \n" 258 " nop \n"
259 " .previous \n" 259 " .previous \n"
260 " .set reorder \n" 260 " .set reorder \n"
@@ -324,16 +324,16 @@ static inline void arch_write_lock(arch_rwlock_t *rw)
324 __asm__ __volatile__( 324 __asm__ __volatile__(
325 " .set noreorder # arch_write_lock \n" 325 " .set noreorder # arch_write_lock \n"
326 "1: ll %1, %2 \n" 326 "1: ll %1, %2 \n"
327 " bnez %1, 2f \n" 327 " bnez %1, 3f \n"
328 " lui %1, 0x8000 \n" 328 " lui %1, 0x8000 \n"
329 " sc %1, %0 \n" 329 "2: sc %1, %0 \n"
330 " beqz %1, 2f \n" 330 " beqz %1, 3f \n"
331 " nop \n" 331 " nop \n"
332 " .subsection 2 \n" 332 " .subsection 2 \n"
333 "2: ll %1, %2 \n" 333 "3: ll %1, %2 \n"
334 " bnez %1, 2b \n" 334 " bnez %1, 3b \n"
335 " lui %1, 0x8000 \n" 335 " lui %1, 0x8000 \n"
336 " b 1b \n" 336 " b 2b \n"
337 " nop \n" 337 " nop \n"
338 " .previous \n" 338 " .previous \n"
339 " .set reorder \n" 339 " .set reorder \n"
diff --git a/arch/mips/include/asm/unistd.h b/arch/mips/include/asm/unistd.h
index 550725b881d5..dae22c1d2c82 100644
--- a/arch/mips/include/asm/unistd.h
+++ b/arch/mips/include/asm/unistd.h
@@ -359,16 +359,20 @@
359#define __NR_fanotify_init (__NR_Linux + 336) 359#define __NR_fanotify_init (__NR_Linux + 336)
360#define __NR_fanotify_mark (__NR_Linux + 337) 360#define __NR_fanotify_mark (__NR_Linux + 337)
361#define __NR_prlimit64 (__NR_Linux + 338) 361#define __NR_prlimit64 (__NR_Linux + 338)
362#define __NR_name_to_handle_at (__NR_Linux + 339)
363#define __NR_open_by_handle_at (__NR_Linux + 340)
364#define __NR_clock_adjtime (__NR_Linux + 341)
365#define __NR_syncfs (__NR_Linux + 342)
362 366
363/* 367/*
364 * Offset of the last Linux o32 flavoured syscall 368 * Offset of the last Linux o32 flavoured syscall
365 */ 369 */
366#define __NR_Linux_syscalls 338 370#define __NR_Linux_syscalls 342
367 371
368#endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */ 372#endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */
369 373
370#define __NR_O32_Linux 4000 374#define __NR_O32_Linux 4000
371#define __NR_O32_Linux_syscalls 338 375#define __NR_O32_Linux_syscalls 342
372 376
373#if _MIPS_SIM == _MIPS_SIM_ABI64 377#if _MIPS_SIM == _MIPS_SIM_ABI64
374 378
@@ -674,16 +678,20 @@
674#define __NR_fanotify_init (__NR_Linux + 295) 678#define __NR_fanotify_init (__NR_Linux + 295)
675#define __NR_fanotify_mark (__NR_Linux + 296) 679#define __NR_fanotify_mark (__NR_Linux + 296)
676#define __NR_prlimit64 (__NR_Linux + 297) 680#define __NR_prlimit64 (__NR_Linux + 297)
681#define __NR_name_to_handle_at (__NR_Linux + 298)
682#define __NR_open_by_handle_at (__NR_Linux + 299)
683#define __NR_clock_adjtime (__NR_Linux + 300)
684#define __NR_syncfs (__NR_Linux + 301)
677 685
678/* 686/*
679 * Offset of the last Linux 64-bit flavoured syscall 687 * Offset of the last Linux 64-bit flavoured syscall
680 */ 688 */
681#define __NR_Linux_syscalls 297 689#define __NR_Linux_syscalls 301
682 690
683#endif /* _MIPS_SIM == _MIPS_SIM_ABI64 */ 691#endif /* _MIPS_SIM == _MIPS_SIM_ABI64 */
684 692
685#define __NR_64_Linux 5000 693#define __NR_64_Linux 5000
686#define __NR_64_Linux_syscalls 297 694#define __NR_64_Linux_syscalls 301
687 695
688#if _MIPS_SIM == _MIPS_SIM_NABI32 696#if _MIPS_SIM == _MIPS_SIM_NABI32
689 697
@@ -994,16 +1002,20 @@
994#define __NR_fanotify_init (__NR_Linux + 300) 1002#define __NR_fanotify_init (__NR_Linux + 300)
995#define __NR_fanotify_mark (__NR_Linux + 301) 1003#define __NR_fanotify_mark (__NR_Linux + 301)
996#define __NR_prlimit64 (__NR_Linux + 302) 1004#define __NR_prlimit64 (__NR_Linux + 302)
1005#define __NR_name_to_handle_at (__NR_Linux + 303)
1006#define __NR_open_by_handle_at (__NR_Linux + 304)
1007#define __NR_clock_adjtime (__NR_Linux + 305)
1008#define __NR_clock_adjtime (__NR_Linux + 306)
997 1009
998/* 1010/*
999 * Offset of the last N32 flavoured syscall 1011 * Offset of the last N32 flavoured syscall
1000 */ 1012 */
1001#define __NR_Linux_syscalls 302 1013#define __NR_Linux_syscalls 306
1002 1014
1003#endif /* _MIPS_SIM == _MIPS_SIM_NABI32 */ 1015#endif /* _MIPS_SIM == _MIPS_SIM_NABI32 */
1004 1016
1005#define __NR_N32_Linux 6000 1017#define __NR_N32_Linux 6000
1006#define __NR_N32_Linux_syscalls 302 1018#define __NR_N32_Linux_syscalls 306
1007 1019
1008#ifdef __KERNEL__ 1020#ifdef __KERNEL__
1009 1021
diff --git a/arch/mips/jazz/irq.c b/arch/mips/jazz/irq.c
index 35b3e2f0af04..40f7c6b1e260 100644
--- a/arch/mips/jazz/irq.c
+++ b/arch/mips/jazz/irq.c
@@ -23,9 +23,9 @@
23 23
24static DEFINE_RAW_SPINLOCK(r4030_lock); 24static DEFINE_RAW_SPINLOCK(r4030_lock);
25 25
26static void enable_r4030_irq(unsigned int irq) 26static void enable_r4030_irq(struct irq_data *d)
27{ 27{
28 unsigned int mask = 1 << (irq - JAZZ_IRQ_START); 28 unsigned int mask = 1 << (d->irq - JAZZ_IRQ_START);
29 unsigned long flags; 29 unsigned long flags;
30 30
31 raw_spin_lock_irqsave(&r4030_lock, flags); 31 raw_spin_lock_irqsave(&r4030_lock, flags);
@@ -34,9 +34,9 @@ static void enable_r4030_irq(unsigned int irq)
34 raw_spin_unlock_irqrestore(&r4030_lock, flags); 34 raw_spin_unlock_irqrestore(&r4030_lock, flags);
35} 35}
36 36
37void disable_r4030_irq(unsigned int irq) 37void disable_r4030_irq(struct irq_data *d)
38{ 38{
39 unsigned int mask = ~(1 << (irq - JAZZ_IRQ_START)); 39 unsigned int mask = ~(1 << (d->irq - JAZZ_IRQ_START));
40 unsigned long flags; 40 unsigned long flags;
41 41
42 raw_spin_lock_irqsave(&r4030_lock, flags); 42 raw_spin_lock_irqsave(&r4030_lock, flags);
@@ -47,10 +47,8 @@ void disable_r4030_irq(unsigned int irq)
47 47
48static struct irq_chip r4030_irq_type = { 48static struct irq_chip r4030_irq_type = {
49 .name = "R4030", 49 .name = "R4030",
50 .ack = disable_r4030_irq, 50 .irq_mask = disable_r4030_irq,
51 .mask = disable_r4030_irq, 51 .irq_unmask = enable_r4030_irq,
52 .mask_ack = disable_r4030_irq,
53 .unmask = enable_r4030_irq,
54}; 52};
55 53
56void __init init_r4030_ints(void) 54void __init init_r4030_ints(void)
diff --git a/arch/mips/jz4740/board-qi_lb60.c b/arch/mips/jz4740/board-qi_lb60.c
index 2c0e107966ad..bc18daaa8f84 100644
--- a/arch/mips/jz4740/board-qi_lb60.c
+++ b/arch/mips/jz4740/board-qi_lb60.c
@@ -23,6 +23,7 @@
23#include <linux/spi/spi_gpio.h> 23#include <linux/spi/spi_gpio.h>
24#include <linux/power_supply.h> 24#include <linux/power_supply.h>
25#include <linux/power/jz4740-battery.h> 25#include <linux/power/jz4740-battery.h>
26#include <linux/power/gpio-charger.h>
26 27
27#include <asm/mach-jz4740/jz4740_fb.h> 28#include <asm/mach-jz4740/jz4740_fb.h>
28#include <asm/mach-jz4740/jz4740_mmc.h> 29#include <asm/mach-jz4740/jz4740_mmc.h>
@@ -49,14 +50,14 @@ static bool is_avt2;
49 50
50/* NAND */ 51/* NAND */
51static struct nand_ecclayout qi_lb60_ecclayout_1gb = { 52static struct nand_ecclayout qi_lb60_ecclayout_1gb = {
52/* .eccbytes = 36, 53 .eccbytes = 36,
53 .eccpos = { 54 .eccpos = {
54 6, 7, 8, 9, 10, 11, 12, 13, 55 6, 7, 8, 9, 10, 11, 12, 13,
55 14, 15, 16, 17, 18, 19, 20, 21, 56 14, 15, 16, 17, 18, 19, 20, 21,
56 22, 23, 24, 25, 26, 27, 28, 29, 57 22, 23, 24, 25, 26, 27, 28, 29,
57 30, 31, 32, 33, 34, 35, 36, 37, 58 30, 31, 32, 33, 34, 35, 36, 37,
58 38, 39, 40, 41 59 38, 39, 40, 41
59 },*/ 60 },
60 .oobfree = { 61 .oobfree = {
61 { .offset = 2, .length = 4 }, 62 { .offset = 2, .length = 4 },
62 { .offset = 42, .length = 22 } 63 { .offset = 42, .length = 22 }
@@ -85,7 +86,7 @@ static struct mtd_partition qi_lb60_partitions_1gb[] = {
85}; 86};
86 87
87static struct nand_ecclayout qi_lb60_ecclayout_2gb = { 88static struct nand_ecclayout qi_lb60_ecclayout_2gb = {
88/* .eccbytes = 72, 89 .eccbytes = 72,
89 .eccpos = { 90 .eccpos = {
90 12, 13, 14, 15, 16, 17, 18, 19, 91 12, 13, 14, 15, 16, 17, 18, 19,
91 20, 21, 22, 23, 24, 25, 26, 27, 92 20, 21, 22, 23, 24, 25, 26, 27,
@@ -96,7 +97,7 @@ static struct nand_ecclayout qi_lb60_ecclayout_2gb = {
96 60, 61, 62, 63, 64, 65, 66, 67, 97 60, 61, 62, 63, 64, 65, 66, 67,
97 68, 69, 70, 71, 72, 73, 74, 75, 98 68, 69, 70, 71, 72, 73, 74, 75,
98 76, 77, 78, 79, 80, 81, 82, 83 99 76, 77, 78, 79, 80, 81, 82, 83
99 },*/ 100 },
100 .oobfree = { 101 .oobfree = {
101 { .offset = 2, .length = 10 }, 102 { .offset = 2, .length = 10 },
102 { .offset = 84, .length = 44 }, 103 { .offset = 84, .length = 44 },
@@ -396,6 +397,28 @@ static struct platform_device qi_lb60_pwm_beeper = {
396 }, 397 },
397}; 398};
398 399
400/* charger */
401static char *qi_lb60_batteries[] = {
402 "battery",
403};
404
405static struct gpio_charger_platform_data qi_lb60_charger_pdata = {
406 .name = "usb",
407 .type = POWER_SUPPLY_TYPE_USB,
408 .gpio = JZ_GPIO_PORTD(28),
409 .gpio_active_low = 1,
410 .supplied_to = qi_lb60_batteries,
411 .num_supplicants = ARRAY_SIZE(qi_lb60_batteries),
412};
413
414static struct platform_device qi_lb60_charger_device = {
415 .name = "gpio-charger",
416 .dev = {
417 .platform_data = &qi_lb60_charger_pdata,
418 },
419};
420
421
399static struct platform_device *jz_platform_devices[] __initdata = { 422static struct platform_device *jz_platform_devices[] __initdata = {
400 &jz4740_udc_device, 423 &jz4740_udc_device,
401 &jz4740_mmc_device, 424 &jz4740_mmc_device,
@@ -410,6 +433,7 @@ static struct platform_device *jz_platform_devices[] __initdata = {
410 &jz4740_adc_device, 433 &jz4740_adc_device,
411 &qi_lb60_gpio_keys, 434 &qi_lb60_gpio_keys,
412 &qi_lb60_pwm_beeper, 435 &qi_lb60_pwm_beeper,
436 &qi_lb60_charger_device,
413}; 437};
414 438
415static void __init board_gpio_setup(void) 439static void __init board_gpio_setup(void)
diff --git a/arch/mips/jz4740/gpio.c b/arch/mips/jz4740/gpio.c
index 88e6aeda5bf1..bd2fc29b95e0 100644
--- a/arch/mips/jz4740/gpio.c
+++ b/arch/mips/jz4740/gpio.c
@@ -86,7 +86,6 @@ struct jz_gpio_chip {
86 spinlock_t lock; 86 spinlock_t lock;
87 87
88 struct gpio_chip gpio_chip; 88 struct gpio_chip gpio_chip;
89 struct irq_chip irq_chip;
90 struct sys_device sysdev; 89 struct sys_device sysdev;
91}; 90};
92 91
@@ -102,9 +101,9 @@ static inline struct jz_gpio_chip *gpio_chip_to_jz_gpio_chip(struct gpio_chip *g
102 return container_of(gpio_chip, struct jz_gpio_chip, gpio_chip); 101 return container_of(gpio_chip, struct jz_gpio_chip, gpio_chip);
103} 102}
104 103
105static inline struct jz_gpio_chip *irq_to_jz_gpio_chip(unsigned int irq) 104static inline struct jz_gpio_chip *irq_to_jz_gpio_chip(struct irq_data *data)
106{ 105{
107 return get_irq_chip_data(irq); 106 return irq_data_get_irq_chip_data(data);
108} 107}
109 108
110static inline void jz_gpio_write_bit(unsigned int gpio, unsigned int reg) 109static inline void jz_gpio_write_bit(unsigned int gpio, unsigned int reg)
@@ -325,62 +324,52 @@ static void jz_gpio_irq_demux_handler(unsigned int irq, struct irq_desc *desc)
325 generic_handle_irq(gpio_irq); 324 generic_handle_irq(gpio_irq);
326}; 325};
327 326
328static inline void jz_gpio_set_irq_bit(unsigned int irq, unsigned int reg) 327static inline void jz_gpio_set_irq_bit(struct irq_data *data, unsigned int reg)
329{ 328{
330 struct jz_gpio_chip *chip = irq_to_jz_gpio_chip(irq); 329 struct jz_gpio_chip *chip = irq_to_jz_gpio_chip(data);
331 writel(IRQ_TO_BIT(irq), chip->base + reg); 330 writel(IRQ_TO_BIT(data->irq), chip->base + reg);
332} 331}
333 332
334static void jz_gpio_irq_mask(unsigned int irq) 333static void jz_gpio_irq_mask(struct irq_data *data)
335{ 334{
336 jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_MASK_SET); 335 jz_gpio_set_irq_bit(data, JZ_REG_GPIO_MASK_SET);
337}; 336};
338 337
339static void jz_gpio_irq_unmask(unsigned int irq) 338static void jz_gpio_irq_unmask(struct irq_data *data)
340{ 339{
341 struct jz_gpio_chip *chip = irq_to_jz_gpio_chip(irq); 340 struct jz_gpio_chip *chip = irq_to_jz_gpio_chip(data);
342 341
343 jz_gpio_check_trigger_both(chip, irq); 342 jz_gpio_check_trigger_both(chip, data->irq);
344 343
345 jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_MASK_CLEAR); 344 jz_gpio_set_irq_bit(data, JZ_REG_GPIO_MASK_CLEAR);
346}; 345};
347 346
348/* TODO: Check if function is gpio */ 347/* TODO: Check if function is gpio */
349static unsigned int jz_gpio_irq_startup(unsigned int irq) 348static unsigned int jz_gpio_irq_startup(struct irq_data *data)
350{ 349{
351 struct irq_desc *desc = irq_to_desc(irq); 350 jz_gpio_set_irq_bit(data, JZ_REG_GPIO_SELECT_SET);
352 351 jz_gpio_irq_unmask(data);
353 jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_SELECT_SET);
354
355 desc->status &= ~IRQ_MASKED;
356 jz_gpio_irq_unmask(irq);
357
358 return 0; 352 return 0;
359} 353}
360 354
361static void jz_gpio_irq_shutdown(unsigned int irq) 355static void jz_gpio_irq_shutdown(struct irq_data *data)
362{ 356{
363 struct irq_desc *desc = irq_to_desc(irq); 357 jz_gpio_irq_mask(data);
364
365 jz_gpio_irq_mask(irq);
366 desc->status |= IRQ_MASKED;
367 358
368 /* Set direction to input */ 359 /* Set direction to input */
369 jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_DIRECTION_CLEAR); 360 jz_gpio_set_irq_bit(data, JZ_REG_GPIO_DIRECTION_CLEAR);
370 jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_SELECT_CLEAR); 361 jz_gpio_set_irq_bit(data, JZ_REG_GPIO_SELECT_CLEAR);
371} 362}
372 363
373static void jz_gpio_irq_ack(unsigned int irq) 364static void jz_gpio_irq_ack(struct irq_data *data)
374{ 365{
375 jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_FLAG_CLEAR); 366 jz_gpio_set_irq_bit(data, JZ_REG_GPIO_FLAG_CLEAR);
376}; 367};
377 368
378static int jz_gpio_irq_set_type(unsigned int irq, unsigned int flow_type) 369static int jz_gpio_irq_set_type(struct irq_data *data, unsigned int flow_type)
379{ 370{
380 struct jz_gpio_chip *chip = irq_to_jz_gpio_chip(irq); 371 struct jz_gpio_chip *chip = irq_to_jz_gpio_chip(data);
381 struct irq_desc *desc = irq_to_desc(irq); 372 unsigned int irq = data->irq;
382
383 jz_gpio_irq_mask(irq);
384 373
385 if (flow_type == IRQ_TYPE_EDGE_BOTH) { 374 if (flow_type == IRQ_TYPE_EDGE_BOTH) {
386 uint32_t value = readl(chip->base + JZ_REG_GPIO_PIN); 375 uint32_t value = readl(chip->base + JZ_REG_GPIO_PIN);
@@ -395,45 +384,54 @@ static int jz_gpio_irq_set_type(unsigned int irq, unsigned int flow_type)
395 384
396 switch (flow_type) { 385 switch (flow_type) {
397 case IRQ_TYPE_EDGE_RISING: 386 case IRQ_TYPE_EDGE_RISING:
398 jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_DIRECTION_SET); 387 jz_gpio_set_irq_bit(data, JZ_REG_GPIO_DIRECTION_SET);
399 jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_TRIGGER_SET); 388 jz_gpio_set_irq_bit(data, JZ_REG_GPIO_TRIGGER_SET);
400 break; 389 break;
401 case IRQ_TYPE_EDGE_FALLING: 390 case IRQ_TYPE_EDGE_FALLING:
402 jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_DIRECTION_CLEAR); 391 jz_gpio_set_irq_bit(data, JZ_REG_GPIO_DIRECTION_CLEAR);
403 jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_TRIGGER_SET); 392 jz_gpio_set_irq_bit(data, JZ_REG_GPIO_TRIGGER_SET);
404 break; 393 break;
405 case IRQ_TYPE_LEVEL_HIGH: 394 case IRQ_TYPE_LEVEL_HIGH:
406 jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_DIRECTION_SET); 395 jz_gpio_set_irq_bit(data, JZ_REG_GPIO_DIRECTION_SET);
407 jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_TRIGGER_CLEAR); 396 jz_gpio_set_irq_bit(data, JZ_REG_GPIO_TRIGGER_CLEAR);
408 break; 397 break;
409 case IRQ_TYPE_LEVEL_LOW: 398 case IRQ_TYPE_LEVEL_LOW:
410 jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_DIRECTION_CLEAR); 399 jz_gpio_set_irq_bit(data, JZ_REG_GPIO_DIRECTION_CLEAR);
411 jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_TRIGGER_CLEAR); 400 jz_gpio_set_irq_bit(data, JZ_REG_GPIO_TRIGGER_CLEAR);
412 break; 401 break;
413 default: 402 default:
414 return -EINVAL; 403 return -EINVAL;
415 } 404 }
416 405
417 if (!(desc->status & IRQ_MASKED))
418 jz_gpio_irq_unmask(irq);
419
420 return 0; 406 return 0;
421} 407}
422 408
423static int jz_gpio_irq_set_wake(unsigned int irq, unsigned int on) 409static int jz_gpio_irq_set_wake(struct irq_data *data, unsigned int on)
424{ 410{
425 struct jz_gpio_chip *chip = irq_to_jz_gpio_chip(irq); 411 struct jz_gpio_chip *chip = irq_to_jz_gpio_chip(data);
426 spin_lock(&chip->lock); 412 spin_lock(&chip->lock);
427 if (on) 413 if (on)
428 chip->wakeup |= IRQ_TO_BIT(irq); 414 chip->wakeup |= IRQ_TO_BIT(data->irq);
429 else 415 else
430 chip->wakeup &= ~IRQ_TO_BIT(irq); 416 chip->wakeup &= ~IRQ_TO_BIT(data->irq);
431 spin_unlock(&chip->lock); 417 spin_unlock(&chip->lock);
432 418
433 set_irq_wake(chip->irq, on); 419 set_irq_wake(chip->irq, on);
434 return 0; 420 return 0;
435} 421}
436 422
423static struct irq_chip jz_gpio_irq_chip = {
424 .name = "GPIO",
425 .irq_mask = jz_gpio_irq_mask,
426 .irq_unmask = jz_gpio_irq_unmask,
427 .irq_ack = jz_gpio_irq_ack,
428 .irq_startup = jz_gpio_irq_startup,
429 .irq_shutdown = jz_gpio_irq_shutdown,
430 .irq_set_type = jz_gpio_irq_set_type,
431 .irq_set_wake = jz_gpio_irq_set_wake,
432 .flags = IRQCHIP_SET_TYPE_MASKED,
433};
434
437/* 435/*
438 * This lock class tells lockdep that GPIO irqs are in a different 436 * This lock class tells lockdep that GPIO irqs are in a different
439 * category than their parents, so it won't report false recursion. 437 * category than their parents, so it won't report false recursion.
@@ -452,16 +450,6 @@ static struct lock_class_key gpio_lock_class;
452 .base = JZ4740_GPIO_BASE_ ## _bank, \ 450 .base = JZ4740_GPIO_BASE_ ## _bank, \
453 .ngpio = JZ4740_GPIO_NUM_ ## _bank, \ 451 .ngpio = JZ4740_GPIO_NUM_ ## _bank, \
454 }, \ 452 }, \
455 .irq_chip = { \
456 .name = "GPIO Bank " # _bank, \
457 .mask = jz_gpio_irq_mask, \
458 .unmask = jz_gpio_irq_unmask, \
459 .ack = jz_gpio_irq_ack, \
460 .startup = jz_gpio_irq_startup, \
461 .shutdown = jz_gpio_irq_shutdown, \
462 .set_type = jz_gpio_irq_set_type, \
463 .set_wake = jz_gpio_irq_set_wake, \
464 }, \
465} 453}
466 454
467static struct jz_gpio_chip jz4740_gpio_chips[] = { 455static struct jz_gpio_chip jz4740_gpio_chips[] = {
@@ -526,9 +514,10 @@ static int jz4740_gpio_chip_init(struct jz_gpio_chip *chip, unsigned int id)
526 set_irq_chained_handler(chip->irq, jz_gpio_irq_demux_handler); 514 set_irq_chained_handler(chip->irq, jz_gpio_irq_demux_handler);
527 515
528 for (irq = chip->irq_base; irq < chip->irq_base + chip->gpio_chip.ngpio; ++irq) { 516 for (irq = chip->irq_base; irq < chip->irq_base + chip->gpio_chip.ngpio; ++irq) {
529 lockdep_set_class(&irq_desc[irq].lock, &gpio_lock_class); 517 irq_set_lockdep_class(irq, &gpio_lock_class);
530 set_irq_chip_data(irq, chip); 518 set_irq_chip_data(irq, chip);
531 set_irq_chip_and_handler(irq, &chip->irq_chip, handle_level_irq); 519 set_irq_chip_and_handler(irq, &jz_gpio_irq_chip,
520 handle_level_irq);
532 } 521 }
533 522
534 return 0; 523 return 0;
diff --git a/arch/mips/jz4740/irq.c b/arch/mips/jz4740/irq.c
index 7d33ff83580f..dcc5593a9389 100644
--- a/arch/mips/jz4740/irq.c
+++ b/arch/mips/jz4740/irq.c
@@ -43,32 +43,37 @@ static uint32_t jz_intc_saved;
43 43
44#define IRQ_BIT(x) BIT((x) - JZ4740_IRQ_BASE) 44#define IRQ_BIT(x) BIT((x) - JZ4740_IRQ_BASE)
45 45
46static void intc_irq_unmask(unsigned int irq) 46static inline unsigned long intc_irq_bit(struct irq_data *data)
47{ 47{
48 writel(IRQ_BIT(irq), jz_intc_base + JZ_REG_INTC_CLEAR_MASK); 48 return (unsigned long)irq_data_get_irq_chip_data(data);
49} 49}
50 50
51static void intc_irq_mask(unsigned int irq) 51static void intc_irq_unmask(struct irq_data *data)
52{ 52{
53 writel(IRQ_BIT(irq), jz_intc_base + JZ_REG_INTC_SET_MASK); 53 writel(intc_irq_bit(data), jz_intc_base + JZ_REG_INTC_CLEAR_MASK);
54} 54}
55 55
56static int intc_irq_set_wake(unsigned int irq, unsigned int on) 56static void intc_irq_mask(struct irq_data *data)
57{
58 writel(intc_irq_bit(data), jz_intc_base + JZ_REG_INTC_SET_MASK);
59}
60
61static int intc_irq_set_wake(struct irq_data *data, unsigned int on)
57{ 62{
58 if (on) 63 if (on)
59 jz_intc_wakeup |= IRQ_BIT(irq); 64 jz_intc_wakeup |= intc_irq_bit(data);
60 else 65 else
61 jz_intc_wakeup &= ~IRQ_BIT(irq); 66 jz_intc_wakeup &= ~intc_irq_bit(data);
62 67
63 return 0; 68 return 0;
64} 69}
65 70
66static struct irq_chip intc_irq_type = { 71static struct irq_chip intc_irq_type = {
67 .name = "INTC", 72 .name = "INTC",
68 .mask = intc_irq_mask, 73 .irq_mask = intc_irq_mask,
69 .mask_ack = intc_irq_mask, 74 .irq_mask_ack = intc_irq_mask,
70 .unmask = intc_irq_unmask, 75 .irq_unmask = intc_irq_unmask,
71 .set_wake = intc_irq_set_wake, 76 .irq_set_wake = intc_irq_set_wake,
72}; 77};
73 78
74static irqreturn_t jz4740_cascade(int irq, void *data) 79static irqreturn_t jz4740_cascade(int irq, void *data)
@@ -95,8 +100,11 @@ void __init arch_init_irq(void)
95 100
96 jz_intc_base = ioremap(JZ4740_INTC_BASE_ADDR, 0x14); 101 jz_intc_base = ioremap(JZ4740_INTC_BASE_ADDR, 0x14);
97 102
103 /* Mask all irqs */
104 writel(0xffffffff, jz_intc_base + JZ_REG_INTC_SET_MASK);
105
98 for (i = JZ4740_IRQ_BASE; i < JZ4740_IRQ_BASE + 32; i++) { 106 for (i = JZ4740_IRQ_BASE; i < JZ4740_IRQ_BASE + 32; i++) {
99 intc_irq_mask(i); 107 set_irq_chip_data(i, (void *)IRQ_BIT(i));
100 set_irq_chip_and_handler(i, &intc_irq_type, handle_level_irq); 108 set_irq_chip_and_handler(i, &intc_irq_type, handle_level_irq);
101 } 109 }
102 110
diff --git a/arch/mips/kernel/i8259.c b/arch/mips/kernel/i8259.c
index c58176cc796b..e221662bb80c 100644
--- a/arch/mips/kernel/i8259.c
+++ b/arch/mips/kernel/i8259.c
@@ -31,19 +31,19 @@
31 31
32static int i8259A_auto_eoi = -1; 32static int i8259A_auto_eoi = -1;
33DEFINE_RAW_SPINLOCK(i8259A_lock); 33DEFINE_RAW_SPINLOCK(i8259A_lock);
34static void disable_8259A_irq(unsigned int irq); 34static void disable_8259A_irq(struct irq_data *d);
35static void enable_8259A_irq(unsigned int irq); 35static void enable_8259A_irq(struct irq_data *d);
36static void mask_and_ack_8259A(unsigned int irq); 36static void mask_and_ack_8259A(struct irq_data *d);
37static void init_8259A(int auto_eoi); 37static void init_8259A(int auto_eoi);
38 38
39static struct irq_chip i8259A_chip = { 39static struct irq_chip i8259A_chip = {
40 .name = "XT-PIC", 40 .name = "XT-PIC",
41 .mask = disable_8259A_irq, 41 .irq_mask = disable_8259A_irq,
42 .disable = disable_8259A_irq, 42 .irq_disable = disable_8259A_irq,
43 .unmask = enable_8259A_irq, 43 .irq_unmask = enable_8259A_irq,
44 .mask_ack = mask_and_ack_8259A, 44 .irq_mask_ack = mask_and_ack_8259A,
45#ifdef CONFIG_MIPS_MT_SMTC_IRQAFF 45#ifdef CONFIG_MIPS_MT_SMTC_IRQAFF
46 .set_affinity = plat_set_irq_affinity, 46 .irq_set_affinity = plat_set_irq_affinity,
47#endif /* CONFIG_MIPS_MT_SMTC_IRQAFF */ 47#endif /* CONFIG_MIPS_MT_SMTC_IRQAFF */
48}; 48};
49 49
@@ -59,12 +59,11 @@ static unsigned int cached_irq_mask = 0xffff;
59#define cached_master_mask (cached_irq_mask) 59#define cached_master_mask (cached_irq_mask)
60#define cached_slave_mask (cached_irq_mask >> 8) 60#define cached_slave_mask (cached_irq_mask >> 8)
61 61
62static void disable_8259A_irq(unsigned int irq) 62static void disable_8259A_irq(struct irq_data *d)
63{ 63{
64 unsigned int mask; 64 unsigned int mask, irq = d->irq - I8259A_IRQ_BASE;
65 unsigned long flags; 65 unsigned long flags;
66 66
67 irq -= I8259A_IRQ_BASE;
68 mask = 1 << irq; 67 mask = 1 << irq;
69 raw_spin_lock_irqsave(&i8259A_lock, flags); 68 raw_spin_lock_irqsave(&i8259A_lock, flags);
70 cached_irq_mask |= mask; 69 cached_irq_mask |= mask;
@@ -75,12 +74,11 @@ static void disable_8259A_irq(unsigned int irq)
75 raw_spin_unlock_irqrestore(&i8259A_lock, flags); 74 raw_spin_unlock_irqrestore(&i8259A_lock, flags);
76} 75}
77 76
78static void enable_8259A_irq(unsigned int irq) 77static void enable_8259A_irq(struct irq_data *d)
79{ 78{
80 unsigned int mask; 79 unsigned int mask, irq = d->irq - I8259A_IRQ_BASE;
81 unsigned long flags; 80 unsigned long flags;
82 81
83 irq -= I8259A_IRQ_BASE;
84 mask = ~(1 << irq); 82 mask = ~(1 << irq);
85 raw_spin_lock_irqsave(&i8259A_lock, flags); 83 raw_spin_lock_irqsave(&i8259A_lock, flags);
86 cached_irq_mask &= mask; 84 cached_irq_mask &= mask;
@@ -145,12 +143,11 @@ static inline int i8259A_irq_real(unsigned int irq)
145 * first, _then_ send the EOI, and the order of EOI 143 * first, _then_ send the EOI, and the order of EOI
146 * to the two 8259s is important! 144 * to the two 8259s is important!
147 */ 145 */
148static void mask_and_ack_8259A(unsigned int irq) 146static void mask_and_ack_8259A(struct irq_data *d)
149{ 147{
150 unsigned int irqmask; 148 unsigned int irqmask, irq = d->irq - I8259A_IRQ_BASE;
151 unsigned long flags; 149 unsigned long flags;
152 150
153 irq -= I8259A_IRQ_BASE;
154 irqmask = 1 << irq; 151 irqmask = 1 << irq;
155 raw_spin_lock_irqsave(&i8259A_lock, flags); 152 raw_spin_lock_irqsave(&i8259A_lock, flags);
156 /* 153 /*
@@ -290,9 +287,9 @@ static void init_8259A(int auto_eoi)
290 * In AEOI mode we just have to mask the interrupt 287 * In AEOI mode we just have to mask the interrupt
291 * when acking. 288 * when acking.
292 */ 289 */
293 i8259A_chip.mask_ack = disable_8259A_irq; 290 i8259A_chip.irq_mask_ack = disable_8259A_irq;
294 else 291 else
295 i8259A_chip.mask_ack = mask_and_ack_8259A; 292 i8259A_chip.irq_mask_ack = mask_and_ack_8259A;
296 293
297 udelay(100); /* wait for 8259A to initialize */ 294 udelay(100); /* wait for 8259A to initialize */
298 295
diff --git a/arch/mips/kernel/irq-gic.c b/arch/mips/kernel/irq-gic.c
index 1774271af848..43cd9628251a 100644
--- a/arch/mips/kernel/irq-gic.c
+++ b/arch/mips/kernel/irq-gic.c
@@ -87,17 +87,10 @@ unsigned int gic_get_int(void)
87 return i; 87 return i;
88} 88}
89 89
90static unsigned int gic_irq_startup(unsigned int irq) 90static void gic_irq_ack(struct irq_data *d)
91{ 91{
92 irq -= _irqbase; 92 unsigned int irq = d->irq - _irqbase;
93 pr_debug("CPU%d: %s: irq%d\n", smp_processor_id(), __func__, irq);
94 GIC_SET_INTR_MASK(irq);
95 return 0;
96}
97 93
98static void gic_irq_ack(unsigned int irq)
99{
100 irq -= _irqbase;
101 pr_debug("CPU%d: %s: irq%d\n", smp_processor_id(), __func__, irq); 94 pr_debug("CPU%d: %s: irq%d\n", smp_processor_id(), __func__, irq);
102 GIC_CLR_INTR_MASK(irq); 95 GIC_CLR_INTR_MASK(irq);
103 96
@@ -105,16 +98,16 @@ static void gic_irq_ack(unsigned int irq)
105 GICWRITE(GIC_REG(SHARED, GIC_SH_WEDGE), irq); 98 GICWRITE(GIC_REG(SHARED, GIC_SH_WEDGE), irq);
106} 99}
107 100
108static void gic_mask_irq(unsigned int irq) 101static void gic_mask_irq(struct irq_data *d)
109{ 102{
110 irq -= _irqbase; 103 unsigned int irq = d->irq - _irqbase;
111 pr_debug("CPU%d: %s: irq%d\n", smp_processor_id(), __func__, irq); 104 pr_debug("CPU%d: %s: irq%d\n", smp_processor_id(), __func__, irq);
112 GIC_CLR_INTR_MASK(irq); 105 GIC_CLR_INTR_MASK(irq);
113} 106}
114 107
115static void gic_unmask_irq(unsigned int irq) 108static void gic_unmask_irq(struct irq_data *d)
116{ 109{
117 irq -= _irqbase; 110 unsigned int irq = d->irq - _irqbase;
118 pr_debug("CPU%d: %s: irq%d\n", smp_processor_id(), __func__, irq); 111 pr_debug("CPU%d: %s: irq%d\n", smp_processor_id(), __func__, irq);
119 GIC_SET_INTR_MASK(irq); 112 GIC_SET_INTR_MASK(irq);
120} 113}
@@ -123,13 +116,14 @@ static void gic_unmask_irq(unsigned int irq)
123 116
124static DEFINE_SPINLOCK(gic_lock); 117static DEFINE_SPINLOCK(gic_lock);
125 118
126static int gic_set_affinity(unsigned int irq, const struct cpumask *cpumask) 119static int gic_set_affinity(struct irq_data *d, const struct cpumask *cpumask,
120 bool force)
127{ 121{
122 unsigned int irq = d->irq - _irqbase;
128 cpumask_t tmp = CPU_MASK_NONE; 123 cpumask_t tmp = CPU_MASK_NONE;
129 unsigned long flags; 124 unsigned long flags;
130 int i; 125 int i;
131 126
132 irq -= _irqbase;
133 pr_debug("%s(%d) called\n", __func__, irq); 127 pr_debug("%s(%d) called\n", __func__, irq);
134 cpumask_and(&tmp, cpumask, cpu_online_mask); 128 cpumask_and(&tmp, cpumask, cpu_online_mask);
135 if (cpus_empty(tmp)) 129 if (cpus_empty(tmp))
@@ -147,23 +141,22 @@ static int gic_set_affinity(unsigned int irq, const struct cpumask *cpumask)
147 set_bit(irq, pcpu_masks[first_cpu(tmp)].pcpu_mask); 141 set_bit(irq, pcpu_masks[first_cpu(tmp)].pcpu_mask);
148 142
149 } 143 }
150 cpumask_copy(irq_desc[irq].affinity, cpumask); 144 cpumask_copy(d->affinity, cpumask);
151 spin_unlock_irqrestore(&gic_lock, flags); 145 spin_unlock_irqrestore(&gic_lock, flags);
152 146
153 return 0; 147 return IRQ_SET_MASK_OK_NOCOPY;
154} 148}
155#endif 149#endif
156 150
157static struct irq_chip gic_irq_controller = { 151static struct irq_chip gic_irq_controller = {
158 .name = "MIPS GIC", 152 .name = "MIPS GIC",
159 .startup = gic_irq_startup, 153 .irq_ack = gic_irq_ack,
160 .ack = gic_irq_ack, 154 .irq_mask = gic_mask_irq,
161 .mask = gic_mask_irq, 155 .irq_mask_ack = gic_mask_irq,
162 .mask_ack = gic_mask_irq, 156 .irq_unmask = gic_unmask_irq,
163 .unmask = gic_unmask_irq, 157 .irq_eoi = gic_unmask_irq,
164 .eoi = gic_unmask_irq,
165#ifdef CONFIG_SMP 158#ifdef CONFIG_SMP
166 .set_affinity = gic_set_affinity, 159 .irq_set_affinity = gic_set_affinity,
167#endif 160#endif
168}; 161};
169 162
diff --git a/arch/mips/kernel/irq-gt641xx.c b/arch/mips/kernel/irq-gt641xx.c
index 42ef81461bfc..7fd176fa367a 100644
--- a/arch/mips/kernel/irq-gt641xx.c
+++ b/arch/mips/kernel/irq-gt641xx.c
@@ -29,64 +29,64 @@
29 29
30static DEFINE_RAW_SPINLOCK(gt641xx_irq_lock); 30static DEFINE_RAW_SPINLOCK(gt641xx_irq_lock);
31 31
32static void ack_gt641xx_irq(unsigned int irq) 32static void ack_gt641xx_irq(struct irq_data *d)
33{ 33{
34 unsigned long flags; 34 unsigned long flags;
35 u32 cause; 35 u32 cause;
36 36
37 raw_spin_lock_irqsave(&gt641xx_irq_lock, flags); 37 raw_spin_lock_irqsave(&gt641xx_irq_lock, flags);
38 cause = GT_READ(GT_INTRCAUSE_OFS); 38 cause = GT_READ(GT_INTRCAUSE_OFS);
39 cause &= ~GT641XX_IRQ_TO_BIT(irq); 39 cause &= ~GT641XX_IRQ_TO_BIT(d->irq);
40 GT_WRITE(GT_INTRCAUSE_OFS, cause); 40 GT_WRITE(GT_INTRCAUSE_OFS, cause);
41 raw_spin_unlock_irqrestore(&gt641xx_irq_lock, flags); 41 raw_spin_unlock_irqrestore(&gt641xx_irq_lock, flags);
42} 42}
43 43
44static void mask_gt641xx_irq(unsigned int irq) 44static void mask_gt641xx_irq(struct irq_data *d)
45{ 45{
46 unsigned long flags; 46 unsigned long flags;
47 u32 mask; 47 u32 mask;
48 48
49 raw_spin_lock_irqsave(&gt641xx_irq_lock, flags); 49 raw_spin_lock_irqsave(&gt641xx_irq_lock, flags);
50 mask = GT_READ(GT_INTRMASK_OFS); 50 mask = GT_READ(GT_INTRMASK_OFS);
51 mask &= ~GT641XX_IRQ_TO_BIT(irq); 51 mask &= ~GT641XX_IRQ_TO_BIT(d->irq);
52 GT_WRITE(GT_INTRMASK_OFS, mask); 52 GT_WRITE(GT_INTRMASK_OFS, mask);
53 raw_spin_unlock_irqrestore(&gt641xx_irq_lock, flags); 53 raw_spin_unlock_irqrestore(&gt641xx_irq_lock, flags);
54} 54}
55 55
56static void mask_ack_gt641xx_irq(unsigned int irq) 56static void mask_ack_gt641xx_irq(struct irq_data *d)
57{ 57{
58 unsigned long flags; 58 unsigned long flags;
59 u32 cause, mask; 59 u32 cause, mask;
60 60
61 raw_spin_lock_irqsave(&gt641xx_irq_lock, flags); 61 raw_spin_lock_irqsave(&gt641xx_irq_lock, flags);
62 mask = GT_READ(GT_INTRMASK_OFS); 62 mask = GT_READ(GT_INTRMASK_OFS);
63 mask &= ~GT641XX_IRQ_TO_BIT(irq); 63 mask &= ~GT641XX_IRQ_TO_BIT(d->irq);
64 GT_WRITE(GT_INTRMASK_OFS, mask); 64 GT_WRITE(GT_INTRMASK_OFS, mask);
65 65
66 cause = GT_READ(GT_INTRCAUSE_OFS); 66 cause = GT_READ(GT_INTRCAUSE_OFS);
67 cause &= ~GT641XX_IRQ_TO_BIT(irq); 67 cause &= ~GT641XX_IRQ_TO_BIT(d->irq);
68 GT_WRITE(GT_INTRCAUSE_OFS, cause); 68 GT_WRITE(GT_INTRCAUSE_OFS, cause);
69 raw_spin_unlock_irqrestore(&gt641xx_irq_lock, flags); 69 raw_spin_unlock_irqrestore(&gt641xx_irq_lock, flags);
70} 70}
71 71
72static void unmask_gt641xx_irq(unsigned int irq) 72static void unmask_gt641xx_irq(struct irq_data *d)
73{ 73{
74 unsigned long flags; 74 unsigned long flags;
75 u32 mask; 75 u32 mask;
76 76
77 raw_spin_lock_irqsave(&gt641xx_irq_lock, flags); 77 raw_spin_lock_irqsave(&gt641xx_irq_lock, flags);
78 mask = GT_READ(GT_INTRMASK_OFS); 78 mask = GT_READ(GT_INTRMASK_OFS);
79 mask |= GT641XX_IRQ_TO_BIT(irq); 79 mask |= GT641XX_IRQ_TO_BIT(d->irq);
80 GT_WRITE(GT_INTRMASK_OFS, mask); 80 GT_WRITE(GT_INTRMASK_OFS, mask);
81 raw_spin_unlock_irqrestore(&gt641xx_irq_lock, flags); 81 raw_spin_unlock_irqrestore(&gt641xx_irq_lock, flags);
82} 82}
83 83
84static struct irq_chip gt641xx_irq_chip = { 84static struct irq_chip gt641xx_irq_chip = {
85 .name = "GT641xx", 85 .name = "GT641xx",
86 .ack = ack_gt641xx_irq, 86 .irq_ack = ack_gt641xx_irq,
87 .mask = mask_gt641xx_irq, 87 .irq_mask = mask_gt641xx_irq,
88 .mask_ack = mask_ack_gt641xx_irq, 88 .irq_mask_ack = mask_ack_gt641xx_irq,
89 .unmask = unmask_gt641xx_irq, 89 .irq_unmask = unmask_gt641xx_irq,
90}; 90};
91 91
92void gt641xx_irq_dispatch(void) 92void gt641xx_irq_dispatch(void)
diff --git a/arch/mips/kernel/irq-msc01.c b/arch/mips/kernel/irq-msc01.c
index 6a8cd28133d5..fc800cd9947e 100644
--- a/arch/mips/kernel/irq-msc01.c
+++ b/arch/mips/kernel/irq-msc01.c
@@ -28,8 +28,10 @@ static unsigned long _icctrl_msc;
28static unsigned int irq_base; 28static unsigned int irq_base;
29 29
30/* mask off an interrupt */ 30/* mask off an interrupt */
31static inline void mask_msc_irq(unsigned int irq) 31static inline void mask_msc_irq(struct irq_data *d)
32{ 32{
33 unsigned int irq = d->irq;
34
33 if (irq < (irq_base + 32)) 35 if (irq < (irq_base + 32))
34 MSCIC_WRITE(MSC01_IC_DISL, 1<<(irq - irq_base)); 36 MSCIC_WRITE(MSC01_IC_DISL, 1<<(irq - irq_base));
35 else 37 else
@@ -37,8 +39,10 @@ static inline void mask_msc_irq(unsigned int irq)
37} 39}
38 40
39/* unmask an interrupt */ 41/* unmask an interrupt */
40static inline void unmask_msc_irq(unsigned int irq) 42static inline void unmask_msc_irq(struct irq_data *d)
41{ 43{
44 unsigned int irq = d->irq;
45
42 if (irq < (irq_base + 32)) 46 if (irq < (irq_base + 32))
43 MSCIC_WRITE(MSC01_IC_ENAL, 1<<(irq - irq_base)); 47 MSCIC_WRITE(MSC01_IC_ENAL, 1<<(irq - irq_base));
44 else 48 else
@@ -48,9 +52,11 @@ static inline void unmask_msc_irq(unsigned int irq)
48/* 52/*
49 * Masks and ACKs an IRQ 53 * Masks and ACKs an IRQ
50 */ 54 */
51static void level_mask_and_ack_msc_irq(unsigned int irq) 55static void level_mask_and_ack_msc_irq(struct irq_data *d)
52{ 56{
53 mask_msc_irq(irq); 57 unsigned int irq = d->irq;
58
59 mask_msc_irq(d);
54 if (!cpu_has_veic) 60 if (!cpu_has_veic)
55 MSCIC_WRITE(MSC01_IC_EOI, 0); 61 MSCIC_WRITE(MSC01_IC_EOI, 0);
56 /* This actually needs to be a call into platform code */ 62 /* This actually needs to be a call into platform code */
@@ -60,9 +66,11 @@ static void level_mask_and_ack_msc_irq(unsigned int irq)
60/* 66/*
61 * Masks and ACKs an IRQ 67 * Masks and ACKs an IRQ
62 */ 68 */
63static void edge_mask_and_ack_msc_irq(unsigned int irq) 69static void edge_mask_and_ack_msc_irq(struct irq_data *d)
64{ 70{
65 mask_msc_irq(irq); 71 unsigned int irq = d->irq;
72
73 mask_msc_irq(d);
66 if (!cpu_has_veic) 74 if (!cpu_has_veic)
67 MSCIC_WRITE(MSC01_IC_EOI, 0); 75 MSCIC_WRITE(MSC01_IC_EOI, 0);
68 else { 76 else {
@@ -75,15 +83,6 @@ static void edge_mask_and_ack_msc_irq(unsigned int irq)
75} 83}
76 84
77/* 85/*
78 * End IRQ processing
79 */
80static void end_msc_irq(unsigned int irq)
81{
82 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
83 unmask_msc_irq(irq);
84}
85
86/*
87 * Interrupt handler for interrupts coming from SOC-it. 86 * Interrupt handler for interrupts coming from SOC-it.
88 */ 87 */
89void ll_msc_irq(void) 88void ll_msc_irq(void)
@@ -107,22 +106,20 @@ static void msc_bind_eic_interrupt(int irq, int set)
107 106
108static struct irq_chip msc_levelirq_type = { 107static struct irq_chip msc_levelirq_type = {
109 .name = "SOC-it-Level", 108 .name = "SOC-it-Level",
110 .ack = level_mask_and_ack_msc_irq, 109 .irq_ack = level_mask_and_ack_msc_irq,
111 .mask = mask_msc_irq, 110 .irq_mask = mask_msc_irq,
112 .mask_ack = level_mask_and_ack_msc_irq, 111 .irq_mask_ack = level_mask_and_ack_msc_irq,
113 .unmask = unmask_msc_irq, 112 .irq_unmask = unmask_msc_irq,
114 .eoi = unmask_msc_irq, 113 .irq_eoi = unmask_msc_irq,
115 .end = end_msc_irq,
116}; 114};
117 115
118static struct irq_chip msc_edgeirq_type = { 116static struct irq_chip msc_edgeirq_type = {
119 .name = "SOC-it-Edge", 117 .name = "SOC-it-Edge",
120 .ack = edge_mask_and_ack_msc_irq, 118 .irq_ack = edge_mask_and_ack_msc_irq,
121 .mask = mask_msc_irq, 119 .irq_mask = mask_msc_irq,
122 .mask_ack = edge_mask_and_ack_msc_irq, 120 .irq_mask_ack = edge_mask_and_ack_msc_irq,
123 .unmask = unmask_msc_irq, 121 .irq_unmask = unmask_msc_irq,
124 .eoi = unmask_msc_irq, 122 .irq_eoi = unmask_msc_irq,
125 .end = end_msc_irq,
126}; 123};
127 124
128 125
diff --git a/arch/mips/kernel/irq-rm7000.c b/arch/mips/kernel/irq-rm7000.c
index 9731e8b47862..fd24fd98b041 100644
--- a/arch/mips/kernel/irq-rm7000.c
+++ b/arch/mips/kernel/irq-rm7000.c
@@ -18,23 +18,23 @@
18#include <asm/mipsregs.h> 18#include <asm/mipsregs.h>
19#include <asm/system.h> 19#include <asm/system.h>
20 20
21static inline void unmask_rm7k_irq(unsigned int irq) 21static inline void unmask_rm7k_irq(struct irq_data *d)
22{ 22{
23 set_c0_intcontrol(0x100 << (irq - RM7K_CPU_IRQ_BASE)); 23 set_c0_intcontrol(0x100 << (d->irq - RM7K_CPU_IRQ_BASE));
24} 24}
25 25
26static inline void mask_rm7k_irq(unsigned int irq) 26static inline void mask_rm7k_irq(struct irq_data *d)
27{ 27{
28 clear_c0_intcontrol(0x100 << (irq - RM7K_CPU_IRQ_BASE)); 28 clear_c0_intcontrol(0x100 << (d->irq - RM7K_CPU_IRQ_BASE));
29} 29}
30 30
31static struct irq_chip rm7k_irq_controller = { 31static struct irq_chip rm7k_irq_controller = {
32 .name = "RM7000", 32 .name = "RM7000",
33 .ack = mask_rm7k_irq, 33 .irq_ack = mask_rm7k_irq,
34 .mask = mask_rm7k_irq, 34 .irq_mask = mask_rm7k_irq,
35 .mask_ack = mask_rm7k_irq, 35 .irq_mask_ack = mask_rm7k_irq,
36 .unmask = unmask_rm7k_irq, 36 .irq_unmask = unmask_rm7k_irq,
37 .eoi = unmask_rm7k_irq 37 .irq_eoi = unmask_rm7k_irq
38}; 38};
39 39
40void __init rm7k_cpu_irq_init(void) 40void __init rm7k_cpu_irq_init(void)
diff --git a/arch/mips/kernel/irq-rm9000.c b/arch/mips/kernel/irq-rm9000.c
index b7e4025b58a8..ca463ec9bad5 100644
--- a/arch/mips/kernel/irq-rm9000.c
+++ b/arch/mips/kernel/irq-rm9000.c
@@ -19,22 +19,22 @@
19#include <asm/mipsregs.h> 19#include <asm/mipsregs.h>
20#include <asm/system.h> 20#include <asm/system.h>
21 21
22static inline void unmask_rm9k_irq(unsigned int irq) 22static inline void unmask_rm9k_irq(struct irq_data *d)
23{ 23{
24 set_c0_intcontrol(0x1000 << (irq - RM9K_CPU_IRQ_BASE)); 24 set_c0_intcontrol(0x1000 << (d->irq - RM9K_CPU_IRQ_BASE));
25} 25}
26 26
27static inline void mask_rm9k_irq(unsigned int irq) 27static inline void mask_rm9k_irq(struct irq_data *d)
28{ 28{
29 clear_c0_intcontrol(0x1000 << (irq - RM9K_CPU_IRQ_BASE)); 29 clear_c0_intcontrol(0x1000 << (d->irq - RM9K_CPU_IRQ_BASE));
30} 30}
31 31
32static inline void rm9k_cpu_irq_enable(unsigned int irq) 32static inline void rm9k_cpu_irq_enable(struct irq_data *d)
33{ 33{
34 unsigned long flags; 34 unsigned long flags;
35 35
36 local_irq_save(flags); 36 local_irq_save(flags);
37 unmask_rm9k_irq(irq); 37 unmask_rm9k_irq(d);
38 local_irq_restore(flags); 38 local_irq_restore(flags);
39} 39}
40 40
@@ -43,50 +43,47 @@ static inline void rm9k_cpu_irq_enable(unsigned int irq)
43 */ 43 */
44static void local_rm9k_perfcounter_irq_startup(void *args) 44static void local_rm9k_perfcounter_irq_startup(void *args)
45{ 45{
46 unsigned int irq = (unsigned int) args; 46 rm9k_cpu_irq_enable(args);
47
48 rm9k_cpu_irq_enable(irq);
49} 47}
50 48
51static unsigned int rm9k_perfcounter_irq_startup(unsigned int irq) 49static unsigned int rm9k_perfcounter_irq_startup(struct irq_data *d)
52{ 50{
53 on_each_cpu(local_rm9k_perfcounter_irq_startup, (void *) irq, 1); 51 on_each_cpu(local_rm9k_perfcounter_irq_startup, d, 1);
54 52
55 return 0; 53 return 0;
56} 54}
57 55
58static void local_rm9k_perfcounter_irq_shutdown(void *args) 56static void local_rm9k_perfcounter_irq_shutdown(void *args)
59{ 57{
60 unsigned int irq = (unsigned int) args;
61 unsigned long flags; 58 unsigned long flags;
62 59
63 local_irq_save(flags); 60 local_irq_save(flags);
64 mask_rm9k_irq(irq); 61 mask_rm9k_irq(args);
65 local_irq_restore(flags); 62 local_irq_restore(flags);
66} 63}
67 64
68static void rm9k_perfcounter_irq_shutdown(unsigned int irq) 65static void rm9k_perfcounter_irq_shutdown(struct irq_data *d)
69{ 66{
70 on_each_cpu(local_rm9k_perfcounter_irq_shutdown, (void *) irq, 1); 67 on_each_cpu(local_rm9k_perfcounter_irq_shutdown, d, 1);
71} 68}
72 69
73static struct irq_chip rm9k_irq_controller = { 70static struct irq_chip rm9k_irq_controller = {
74 .name = "RM9000", 71 .name = "RM9000",
75 .ack = mask_rm9k_irq, 72 .irq_ack = mask_rm9k_irq,
76 .mask = mask_rm9k_irq, 73 .irq_mask = mask_rm9k_irq,
77 .mask_ack = mask_rm9k_irq, 74 .irq_mask_ack = mask_rm9k_irq,
78 .unmask = unmask_rm9k_irq, 75 .irq_unmask = unmask_rm9k_irq,
79 .eoi = unmask_rm9k_irq 76 .irq_eoi = unmask_rm9k_irq
80}; 77};
81 78
82static struct irq_chip rm9k_perfcounter_irq = { 79static struct irq_chip rm9k_perfcounter_irq = {
83 .name = "RM9000", 80 .name = "RM9000",
84 .startup = rm9k_perfcounter_irq_startup, 81 .irq_startup = rm9k_perfcounter_irq_startup,
85 .shutdown = rm9k_perfcounter_irq_shutdown, 82 .irq_shutdown = rm9k_perfcounter_irq_shutdown,
86 .ack = mask_rm9k_irq, 83 .irq_ack = mask_rm9k_irq,
87 .mask = mask_rm9k_irq, 84 .irq_mask = mask_rm9k_irq,
88 .mask_ack = mask_rm9k_irq, 85 .irq_mask_ack = mask_rm9k_irq,
89 .unmask = unmask_rm9k_irq, 86 .irq_unmask = unmask_rm9k_irq,
90}; 87};
91 88
92unsigned int rm9000_perfcount_irq; 89unsigned int rm9000_perfcount_irq;
diff --git a/arch/mips/kernel/irq.c b/arch/mips/kernel/irq.c
index 4f93db58a79e..1b68ebe1b458 100644
--- a/arch/mips/kernel/irq.c
+++ b/arch/mips/kernel/irq.c
@@ -81,48 +81,9 @@ void ack_bad_irq(unsigned int irq)
81 81
82atomic_t irq_err_count; 82atomic_t irq_err_count;
83 83
84/* 84int arch_show_interrupts(struct seq_file *p, int prec)
85 * Generic, controller-independent functions:
86 */
87
88int show_interrupts(struct seq_file *p, void *v)
89{ 85{
90 int i = *(loff_t *) v, j; 86 seq_printf(p, "%*s: %10u\n", prec, "ERR", atomic_read(&irq_err_count));
91 struct irqaction * action;
92 unsigned long flags;
93
94 if (i == 0) {
95 seq_printf(p, " ");
96 for_each_online_cpu(j)
97 seq_printf(p, "CPU%d ", j);
98 seq_putc(p, '\n');
99 }
100
101 if (i < NR_IRQS) {
102 raw_spin_lock_irqsave(&irq_desc[i].lock, flags);
103 action = irq_desc[i].action;
104 if (!action)
105 goto skip;
106 seq_printf(p, "%3d: ", i);
107#ifndef CONFIG_SMP
108 seq_printf(p, "%10u ", kstat_irqs(i));
109#else
110 for_each_online_cpu(j)
111 seq_printf(p, "%10u ", kstat_irqs_cpu(i, j));
112#endif
113 seq_printf(p, " %14s", irq_desc[i].chip->name);
114 seq_printf(p, " %s", action->name);
115
116 for (action=action->next; action; action = action->next)
117 seq_printf(p, ", %s", action->name);
118
119 seq_putc(p, '\n');
120skip:
121 raw_spin_unlock_irqrestore(&irq_desc[i].lock, flags);
122 } else if (i == NR_IRQS) {
123 seq_putc(p, '\n');
124 seq_printf(p, "ERR: %10u\n", atomic_read(&irq_err_count));
125 }
126 return 0; 87 return 0;
127} 88}
128 89
@@ -183,8 +144,8 @@ void __irq_entry do_IRQ(unsigned int irq)
183{ 144{
184 irq_enter(); 145 irq_enter();
185 check_stack_overflow(); 146 check_stack_overflow();
186 __DO_IRQ_SMTC_HOOK(irq); 147 if (!smtc_handle_on_other_cpu(irq))
187 generic_handle_irq(irq); 148 generic_handle_irq(irq);
188 irq_exit(); 149 irq_exit();
189} 150}
190 151
@@ -197,7 +158,7 @@ void __irq_entry do_IRQ(unsigned int irq)
197void __irq_entry do_IRQ_no_affinity(unsigned int irq) 158void __irq_entry do_IRQ_no_affinity(unsigned int irq)
198{ 159{
199 irq_enter(); 160 irq_enter();
200 __NO_AFFINITY_IRQ_SMTC_HOOK(irq); 161 smtc_im_backstop(irq);
201 generic_handle_irq(irq); 162 generic_handle_irq(irq);
202 irq_exit(); 163 irq_exit();
203} 164}
diff --git a/arch/mips/kernel/irq_cpu.c b/arch/mips/kernel/irq_cpu.c
index 0262abe09121..fd945c56bc33 100644
--- a/arch/mips/kernel/irq_cpu.c
+++ b/arch/mips/kernel/irq_cpu.c
@@ -37,42 +37,38 @@
37#include <asm/mipsmtregs.h> 37#include <asm/mipsmtregs.h>
38#include <asm/system.h> 38#include <asm/system.h>
39 39
40static inline void unmask_mips_irq(unsigned int irq) 40static inline void unmask_mips_irq(struct irq_data *d)
41{ 41{
42 set_c0_status(0x100 << (irq - MIPS_CPU_IRQ_BASE)); 42 set_c0_status(0x100 << (d->irq - MIPS_CPU_IRQ_BASE));
43 irq_enable_hazard(); 43 irq_enable_hazard();
44} 44}
45 45
46static inline void mask_mips_irq(unsigned int irq) 46static inline void mask_mips_irq(struct irq_data *d)
47{ 47{
48 clear_c0_status(0x100 << (irq - MIPS_CPU_IRQ_BASE)); 48 clear_c0_status(0x100 << (d->irq - MIPS_CPU_IRQ_BASE));
49 irq_disable_hazard(); 49 irq_disable_hazard();
50} 50}
51 51
52static struct irq_chip mips_cpu_irq_controller = { 52static struct irq_chip mips_cpu_irq_controller = {
53 .name = "MIPS", 53 .name = "MIPS",
54 .ack = mask_mips_irq, 54 .irq_ack = mask_mips_irq,
55 .mask = mask_mips_irq, 55 .irq_mask = mask_mips_irq,
56 .mask_ack = mask_mips_irq, 56 .irq_mask_ack = mask_mips_irq,
57 .unmask = unmask_mips_irq, 57 .irq_unmask = unmask_mips_irq,
58 .eoi = unmask_mips_irq, 58 .irq_eoi = unmask_mips_irq,
59}; 59};
60 60
61/* 61/*
62 * Basically the same as above but taking care of all the MT stuff 62 * Basically the same as above but taking care of all the MT stuff
63 */ 63 */
64 64
65#define unmask_mips_mt_irq unmask_mips_irq 65static unsigned int mips_mt_cpu_irq_startup(struct irq_data *d)
66#define mask_mips_mt_irq mask_mips_irq
67
68static unsigned int mips_mt_cpu_irq_startup(unsigned int irq)
69{ 66{
70 unsigned int vpflags = dvpe(); 67 unsigned int vpflags = dvpe();
71 68
72 clear_c0_cause(0x100 << (irq - MIPS_CPU_IRQ_BASE)); 69 clear_c0_cause(0x100 << (d->irq - MIPS_CPU_IRQ_BASE));
73 evpe(vpflags); 70 evpe(vpflags);
74 unmask_mips_mt_irq(irq); 71 unmask_mips_irq(d);
75
76 return 0; 72 return 0;
77} 73}
78 74
@@ -80,22 +76,22 @@ static unsigned int mips_mt_cpu_irq_startup(unsigned int irq)
80 * While we ack the interrupt interrupts are disabled and thus we don't need 76 * While we ack the interrupt interrupts are disabled and thus we don't need
81 * to deal with concurrency issues. Same for mips_cpu_irq_end. 77 * to deal with concurrency issues. Same for mips_cpu_irq_end.
82 */ 78 */
83static void mips_mt_cpu_irq_ack(unsigned int irq) 79static void mips_mt_cpu_irq_ack(struct irq_data *d)
84{ 80{
85 unsigned int vpflags = dvpe(); 81 unsigned int vpflags = dvpe();
86 clear_c0_cause(0x100 << (irq - MIPS_CPU_IRQ_BASE)); 82 clear_c0_cause(0x100 << (d->irq - MIPS_CPU_IRQ_BASE));
87 evpe(vpflags); 83 evpe(vpflags);
88 mask_mips_mt_irq(irq); 84 mask_mips_irq(d);
89} 85}
90 86
91static struct irq_chip mips_mt_cpu_irq_controller = { 87static struct irq_chip mips_mt_cpu_irq_controller = {
92 .name = "MIPS", 88 .name = "MIPS",
93 .startup = mips_mt_cpu_irq_startup, 89 .irq_startup = mips_mt_cpu_irq_startup,
94 .ack = mips_mt_cpu_irq_ack, 90 .irq_ack = mips_mt_cpu_irq_ack,
95 .mask = mask_mips_mt_irq, 91 .irq_mask = mask_mips_irq,
96 .mask_ack = mips_mt_cpu_irq_ack, 92 .irq_mask_ack = mips_mt_cpu_irq_ack,
97 .unmask = unmask_mips_mt_irq, 93 .irq_unmask = unmask_mips_irq,
98 .eoi = unmask_mips_mt_irq, 94 .irq_eoi = unmask_mips_irq,
99}; 95};
100 96
101void __init mips_cpu_irq_init(void) 97void __init mips_cpu_irq_init(void)
diff --git a/arch/mips/kernel/irq_txx9.c b/arch/mips/kernel/irq_txx9.c
index 95a96f69172d..526e1581549a 100644
--- a/arch/mips/kernel/irq_txx9.c
+++ b/arch/mips/kernel/irq_txx9.c
@@ -63,9 +63,9 @@ static struct {
63 unsigned char mode; 63 unsigned char mode;
64} txx9irq[TXx9_MAX_IR] __read_mostly; 64} txx9irq[TXx9_MAX_IR] __read_mostly;
65 65
66static void txx9_irq_unmask(unsigned int irq) 66static void txx9_irq_unmask(struct irq_data *d)
67{ 67{
68 unsigned int irq_nr = irq - TXX9_IRQ_BASE; 68 unsigned int irq_nr = d->irq - TXX9_IRQ_BASE;
69 u32 __iomem *ilrp = &txx9_ircptr->ilr[(irq_nr % 16 ) / 2]; 69 u32 __iomem *ilrp = &txx9_ircptr->ilr[(irq_nr % 16 ) / 2];
70 int ofs = irq_nr / 16 * 16 + (irq_nr & 1) * 8; 70 int ofs = irq_nr / 16 * 16 + (irq_nr & 1) * 8;
71 71
@@ -79,9 +79,9 @@ static void txx9_irq_unmask(unsigned int irq)
79#endif 79#endif
80} 80}
81 81
82static inline void txx9_irq_mask(unsigned int irq) 82static inline void txx9_irq_mask(struct irq_data *d)
83{ 83{
84 unsigned int irq_nr = irq - TXX9_IRQ_BASE; 84 unsigned int irq_nr = d->irq - TXX9_IRQ_BASE;
85 u32 __iomem *ilrp = &txx9_ircptr->ilr[(irq_nr % 16) / 2]; 85 u32 __iomem *ilrp = &txx9_ircptr->ilr[(irq_nr % 16) / 2];
86 int ofs = irq_nr / 16 * 16 + (irq_nr & 1) * 8; 86 int ofs = irq_nr / 16 * 16 + (irq_nr & 1) * 8;
87 87
@@ -99,19 +99,19 @@ static inline void txx9_irq_mask(unsigned int irq)
99#endif 99#endif
100} 100}
101 101
102static void txx9_irq_mask_ack(unsigned int irq) 102static void txx9_irq_mask_ack(struct irq_data *d)
103{ 103{
104 unsigned int irq_nr = irq - TXX9_IRQ_BASE; 104 unsigned int irq_nr = d->irq - TXX9_IRQ_BASE;
105 105
106 txx9_irq_mask(irq); 106 txx9_irq_mask(d);
107 /* clear edge detection */ 107 /* clear edge detection */
108 if (unlikely(TXx9_IRCR_EDGE(txx9irq[irq_nr].mode))) 108 if (unlikely(TXx9_IRCR_EDGE(txx9irq[irq_nr].mode)))
109 __raw_writel(TXx9_IRSCR_EIClrE | irq_nr, &txx9_ircptr->scr); 109 __raw_writel(TXx9_IRSCR_EIClrE | irq_nr, &txx9_ircptr->scr);
110} 110}
111 111
112static int txx9_irq_set_type(unsigned int irq, unsigned int flow_type) 112static int txx9_irq_set_type(struct irq_data *d, unsigned int flow_type)
113{ 113{
114 unsigned int irq_nr = irq - TXX9_IRQ_BASE; 114 unsigned int irq_nr = d->irq - TXX9_IRQ_BASE;
115 u32 cr; 115 u32 cr;
116 u32 __iomem *crp; 116 u32 __iomem *crp;
117 int ofs; 117 int ofs;
@@ -139,11 +139,11 @@ static int txx9_irq_set_type(unsigned int irq, unsigned int flow_type)
139 139
140static struct irq_chip txx9_irq_chip = { 140static struct irq_chip txx9_irq_chip = {
141 .name = "TXX9", 141 .name = "TXX9",
142 .ack = txx9_irq_mask_ack, 142 .irq_ack = txx9_irq_mask_ack,
143 .mask = txx9_irq_mask, 143 .irq_mask = txx9_irq_mask,
144 .mask_ack = txx9_irq_mask_ack, 144 .irq_mask_ack = txx9_irq_mask_ack,
145 .unmask = txx9_irq_unmask, 145 .irq_unmask = txx9_irq_unmask,
146 .set_type = txx9_irq_set_type, 146 .irq_set_type = txx9_irq_set_type,
147}; 147};
148 148
149void __init txx9_irq_init(unsigned long baseaddr) 149void __init txx9_irq_init(unsigned long baseaddr)
diff --git a/arch/mips/kernel/scall32-o32.S b/arch/mips/kernel/scall32-o32.S
index fbaabad0e6e2..7f5468b38d4c 100644
--- a/arch/mips/kernel/scall32-o32.S
+++ b/arch/mips/kernel/scall32-o32.S
@@ -586,6 +586,10 @@ einval: li v0, -ENOSYS
586 sys sys_fanotify_init 2 586 sys sys_fanotify_init 2
587 sys sys_fanotify_mark 6 587 sys sys_fanotify_mark 6
588 sys sys_prlimit64 4 588 sys sys_prlimit64 4
589 sys sys_name_to_handle_at 5
590 sys sys_open_by_handle_at 3 /* 4340 */
591 sys sys_clock_adjtime 2
592 sys sys_syncfs 1
589 .endm 593 .endm
590 594
591 /* We pre-compute the number of _instruction_ bytes needed to 595 /* We pre-compute the number of _instruction_ bytes needed to
diff --git a/arch/mips/kernel/scall64-64.S b/arch/mips/kernel/scall64-64.S
index 3f4179283207..a2e1fcbc41dc 100644
--- a/arch/mips/kernel/scall64-64.S
+++ b/arch/mips/kernel/scall64-64.S
@@ -425,4 +425,8 @@ sys_call_table:
425 PTR sys_fanotify_init /* 5295 */ 425 PTR sys_fanotify_init /* 5295 */
426 PTR sys_fanotify_mark 426 PTR sys_fanotify_mark
427 PTR sys_prlimit64 427 PTR sys_prlimit64
428 PTR sys_name_to_handle_at
429 PTR sys_open_by_handle_at
430 PTR sys_clock_adjtime /* 5300 */
431 PTR sys_syncfs
428 .size sys_call_table,.-sys_call_table 432 .size sys_call_table,.-sys_call_table
diff --git a/arch/mips/kernel/scall64-n32.S b/arch/mips/kernel/scall64-n32.S
index f08ece6d8acc..b2c7624995b8 100644
--- a/arch/mips/kernel/scall64-n32.S
+++ b/arch/mips/kernel/scall64-n32.S
@@ -425,4 +425,8 @@ EXPORT(sysn32_call_table)
425 PTR sys_fanotify_init /* 6300 */ 425 PTR sys_fanotify_init /* 6300 */
426 PTR sys_fanotify_mark 426 PTR sys_fanotify_mark
427 PTR sys_prlimit64 427 PTR sys_prlimit64
428 PTR sys_name_to_handle_at
429 PTR sys_open_by_handle_at
430 PTR compat_sys_clock_adjtime /* 6305 */
431 PTR sys_syncfs
428 .size sysn32_call_table,.-sysn32_call_table 432 .size sysn32_call_table,.-sysn32_call_table
diff --git a/arch/mips/kernel/scall64-o32.S b/arch/mips/kernel/scall64-o32.S
index 78d768a3e19d..049a9c8c49a0 100644
--- a/arch/mips/kernel/scall64-o32.S
+++ b/arch/mips/kernel/scall64-o32.S
@@ -543,4 +543,8 @@ sys_call_table:
543 PTR sys_fanotify_init 543 PTR sys_fanotify_init
544 PTR sys_32_fanotify_mark 544 PTR sys_32_fanotify_mark
545 PTR sys_prlimit64 545 PTR sys_prlimit64
546 PTR sys_name_to_handle_at
547 PTR compat_sys_open_by_handle_at /* 4340 */
548 PTR compat_sys_clock_adjtime
549 PTR sys_syncfs
546 .size sys_call_table,.-sys_call_table 550 .size sys_call_table,.-sys_call_table
diff --git a/arch/mips/kernel/smtc.c b/arch/mips/kernel/smtc.c
index 39c08254b0f1..f7e2c7807d7b 100644
--- a/arch/mips/kernel/smtc.c
+++ b/arch/mips/kernel/smtc.c
@@ -677,8 +677,9 @@ void smtc_set_irq_affinity(unsigned int irq, cpumask_t affinity)
677 */ 677 */
678} 678}
679 679
680void smtc_forward_irq(unsigned int irq) 680void smtc_forward_irq(struct irq_data *d)
681{ 681{
682 unsigned int irq = d->irq;
682 int target; 683 int target;
683 684
684 /* 685 /*
@@ -692,7 +693,7 @@ void smtc_forward_irq(unsigned int irq)
692 * and efficiency, we just pick the easiest one to find. 693 * and efficiency, we just pick the easiest one to find.
693 */ 694 */
694 695
695 target = cpumask_first(irq_desc[irq].affinity); 696 target = cpumask_first(d->affinity);
696 697
697 /* 698 /*
698 * We depend on the platform code to have correctly processed 699 * We depend on the platform code to have correctly processed
@@ -707,12 +708,10 @@ void smtc_forward_irq(unsigned int irq)
707 */ 708 */
708 709
709 /* If no one is eligible, service locally */ 710 /* If no one is eligible, service locally */
710 if (target >= NR_CPUS) { 711 if (target >= NR_CPUS)
711 do_IRQ_no_affinity(irq); 712 do_IRQ_no_affinity(irq);
712 return; 713 else
713 } 714 smtc_send_ipi(target, IRQ_AFFINITY_IPI, irq);
714
715 smtc_send_ipi(target, IRQ_AFFINITY_IPI, irq);
716} 715}
717 716
718#endif /* CONFIG_MIPS_MT_SMTC_IRQAFF */ 717#endif /* CONFIG_MIPS_MT_SMTC_IRQAFF */
diff --git a/arch/mips/lasat/interrupt.c b/arch/mips/lasat/interrupt.c
index 1353fb135ed3..670e3e70d198 100644
--- a/arch/mips/lasat/interrupt.c
+++ b/arch/mips/lasat/interrupt.c
@@ -32,24 +32,24 @@ static volatile int *lasat_int_status;
32static volatile int *lasat_int_mask; 32static volatile int *lasat_int_mask;
33static volatile int lasat_int_mask_shift; 33static volatile int lasat_int_mask_shift;
34 34
35void disable_lasat_irq(unsigned int irq_nr) 35void disable_lasat_irq(struct irq_data *d)
36{ 36{
37 irq_nr -= LASAT_IRQ_BASE; 37 unsigned int irq_nr = d->irq - LASAT_IRQ_BASE;
38
38 *lasat_int_mask &= ~(1 << irq_nr) << lasat_int_mask_shift; 39 *lasat_int_mask &= ~(1 << irq_nr) << lasat_int_mask_shift;
39} 40}
40 41
41void enable_lasat_irq(unsigned int irq_nr) 42void enable_lasat_irq(struct irq_data *d)
42{ 43{
43 irq_nr -= LASAT_IRQ_BASE; 44 unsigned int irq_nr = d->irq - LASAT_IRQ_BASE;
45
44 *lasat_int_mask |= (1 << irq_nr) << lasat_int_mask_shift; 46 *lasat_int_mask |= (1 << irq_nr) << lasat_int_mask_shift;
45} 47}
46 48
47static struct irq_chip lasat_irq_type = { 49static struct irq_chip lasat_irq_type = {
48 .name = "Lasat", 50 .name = "Lasat",
49 .ack = disable_lasat_irq, 51 .irq_mask = disable_lasat_irq,
50 .mask = disable_lasat_irq, 52 .irq_unmask = enable_lasat_irq,
51 .mask_ack = disable_lasat_irq,
52 .unmask = enable_lasat_irq,
53}; 53};
54 54
55static inline int ls1bit32(unsigned int x) 55static inline int ls1bit32(unsigned int x)
diff --git a/arch/mips/loongson/common/bonito-irq.c b/arch/mips/loongson/common/bonito-irq.c
index 2dc2a4cc632a..1549361696ad 100644
--- a/arch/mips/loongson/common/bonito-irq.c
+++ b/arch/mips/loongson/common/bonito-irq.c
@@ -16,24 +16,22 @@
16 16
17#include <loongson.h> 17#include <loongson.h>
18 18
19static inline void bonito_irq_enable(unsigned int irq) 19static inline void bonito_irq_enable(struct irq_data *d)
20{ 20{
21 LOONGSON_INTENSET = (1 << (irq - LOONGSON_IRQ_BASE)); 21 LOONGSON_INTENSET = (1 << (d->irq - LOONGSON_IRQ_BASE));
22 mmiowb(); 22 mmiowb();
23} 23}
24 24
25static inline void bonito_irq_disable(unsigned int irq) 25static inline void bonito_irq_disable(struct irq_data *d)
26{ 26{
27 LOONGSON_INTENCLR = (1 << (irq - LOONGSON_IRQ_BASE)); 27 LOONGSON_INTENCLR = (1 << (d->irq - LOONGSON_IRQ_BASE));
28 mmiowb(); 28 mmiowb();
29} 29}
30 30
31static struct irq_chip bonito_irq_type = { 31static struct irq_chip bonito_irq_type = {
32 .name = "bonito_irq", 32 .name = "bonito_irq",
33 .ack = bonito_irq_disable, 33 .irq_mask = bonito_irq_disable,
34 .mask = bonito_irq_disable, 34 .irq_unmask = bonito_irq_enable,
35 .mask_ack = bonito_irq_disable,
36 .unmask = bonito_irq_enable,
37}; 35};
38 36
39static struct irqaction __maybe_unused dma_timeout_irqaction = { 37static struct irqaction __maybe_unused dma_timeout_irqaction = {
diff --git a/arch/mips/mipssim/sim_smtc.c b/arch/mips/mipssim/sim_smtc.c
index 5da30b6a65b7..30df47258c2c 100644
--- a/arch/mips/mipssim/sim_smtc.c
+++ b/arch/mips/mipssim/sim_smtc.c
@@ -27,6 +27,7 @@
27#include <asm/atomic.h> 27#include <asm/atomic.h>
28#include <asm/cpu.h> 28#include <asm/cpu.h>
29#include <asm/processor.h> 29#include <asm/processor.h>
30#include <asm/smtc.h>
30#include <asm/system.h> 31#include <asm/system.h>
31#include <asm/mmu_context.h> 32#include <asm/mmu_context.h>
32#include <asm/smtc_ipi.h> 33#include <asm/smtc_ipi.h>
@@ -57,8 +58,6 @@ static inline void ssmtc_send_ipi_mask(const struct cpumask *mask,
57 */ 58 */
58static void __cpuinit ssmtc_init_secondary(void) 59static void __cpuinit ssmtc_init_secondary(void)
59{ 60{
60 void smtc_init_secondary(void);
61
62 smtc_init_secondary(); 61 smtc_init_secondary();
63} 62}
64 63
diff --git a/arch/mips/mti-malta/malta-smtc.c b/arch/mips/mti-malta/malta-smtc.c
index 192cfd2a539c..e67891521ac1 100644
--- a/arch/mips/mti-malta/malta-smtc.c
+++ b/arch/mips/mti-malta/malta-smtc.c
@@ -34,7 +34,6 @@ static void msmtc_send_ipi_mask(const struct cpumask *mask, unsigned int action)
34 */ 34 */
35static void __cpuinit msmtc_init_secondary(void) 35static void __cpuinit msmtc_init_secondary(void)
36{ 36{
37 void smtc_init_secondary(void);
38 int myvpe; 37 int myvpe;
39 38
40 /* Don't enable Malta I/O interrupts (IP2) for secondary VPEs */ 39 /* Don't enable Malta I/O interrupts (IP2) for secondary VPEs */
@@ -114,7 +113,8 @@ struct plat_smp_ops msmtc_smp_ops = {
114 */ 113 */
115 114
116 115
117int plat_set_irq_affinity(unsigned int irq, const struct cpumask *affinity) 116int plat_set_irq_affinity(struct irq_data *d, const struct cpumask *affinity,
117 bool force)
118{ 118{
119 cpumask_t tmask; 119 cpumask_t tmask;
120 int cpu = 0; 120 int cpu = 0;
@@ -144,7 +144,7 @@ int plat_set_irq_affinity(unsigned int irq, const struct cpumask *affinity)
144 if ((cpu_data[cpu].vpe_id != 0) || !cpu_online(cpu)) 144 if ((cpu_data[cpu].vpe_id != 0) || !cpu_online(cpu))
145 cpu_clear(cpu, tmask); 145 cpu_clear(cpu, tmask);
146 } 146 }
147 cpumask_copy(irq_desc[irq].affinity, &tmask); 147 cpumask_copy(d->affinity, &tmask);
148 148
149 if (cpus_empty(tmask)) 149 if (cpus_empty(tmask))
150 /* 150 /*
@@ -155,8 +155,8 @@ int plat_set_irq_affinity(unsigned int irq, const struct cpumask *affinity)
155 "IRQ affinity leaves no legal CPU for IRQ %d\n", irq); 155 "IRQ affinity leaves no legal CPU for IRQ %d\n", irq);
156 156
157 /* Do any generic SMTC IRQ affinity setup */ 157 /* Do any generic SMTC IRQ affinity setup */
158 smtc_set_irq_affinity(irq, tmask); 158 smtc_set_irq_affinity(d->irq, tmask);
159 159
160 return 0; 160 return IRQ_SET_MASK_OK_NOCOPY;
161} 161}
162#endif /* CONFIG_MIPS_MT_SMTC_IRQAFF */ 162#endif /* CONFIG_MIPS_MT_SMTC_IRQAFF */
diff --git a/arch/mips/pmc-sierra/Kconfig b/arch/mips/pmc-sierra/Kconfig
index 8d798497c614..bbd76082fa8c 100644
--- a/arch/mips/pmc-sierra/Kconfig
+++ b/arch/mips/pmc-sierra/Kconfig
@@ -23,6 +23,8 @@ config PMC_MSP7120_GW
23 select SYS_SUPPORTS_MULTITHREADING 23 select SYS_SUPPORTS_MULTITHREADING
24 select IRQ_MSP_CIC 24 select IRQ_MSP_CIC
25 select HW_HAS_PCI 25 select HW_HAS_PCI
26 select MSP_HAS_USB
27 select MSP_ETH
26 28
27config PMC_MSP7120_FPGA 29config PMC_MSP7120_FPGA
28 bool "PMC-Sierra MSP7120 FPGA" 30 bool "PMC-Sierra MSP7120 FPGA"
@@ -35,3 +37,16 @@ endchoice
35config HYPERTRANSPORT 37config HYPERTRANSPORT
36 bool "Hypertransport Support for PMC-Sierra Yosemite" 38 bool "Hypertransport Support for PMC-Sierra Yosemite"
37 depends on PMC_YOSEMITE 39 depends on PMC_YOSEMITE
40
41config MSP_HAS_USB
42 boolean
43 depends on PMC_MSP
44
45config MSP_ETH
46 boolean
47 select MSP_HAS_MAC
48 depends on PMC_MSP
49
50config MSP_HAS_MAC
51 boolean
52 depends on PMC_MSP
diff --git a/arch/mips/pmc-sierra/msp71xx/Makefile b/arch/mips/pmc-sierra/msp71xx/Makefile
index e107f79b1491..cefba7733b73 100644
--- a/arch/mips/pmc-sierra/msp71xx/Makefile
+++ b/arch/mips/pmc-sierra/msp71xx/Makefile
@@ -6,7 +6,9 @@ obj-y += msp_prom.o msp_setup.o msp_irq.o \
6obj-$(CONFIG_HAVE_GPIO_LIB) += gpio.o gpio_extended.o 6obj-$(CONFIG_HAVE_GPIO_LIB) += gpio.o gpio_extended.o
7obj-$(CONFIG_PMC_MSP7120_GW) += msp_hwbutton.o 7obj-$(CONFIG_PMC_MSP7120_GW) += msp_hwbutton.o
8obj-$(CONFIG_IRQ_MSP_SLP) += msp_irq_slp.o 8obj-$(CONFIG_IRQ_MSP_SLP) += msp_irq_slp.o
9obj-$(CONFIG_IRQ_MSP_CIC) += msp_irq_cic.o 9obj-$(CONFIG_IRQ_MSP_CIC) += msp_irq_cic.o msp_irq_per.o
10obj-$(CONFIG_PCI) += msp_pci.o 10obj-$(CONFIG_PCI) += msp_pci.o
11obj-$(CONFIG_MSPETH) += msp_eth.o 11obj-$(CONFIG_MSP_HAS_MAC) += msp_eth.o
12obj-$(CONFIG_USB_MSP71XX) += msp_usb.o 12obj-$(CONFIG_MSP_HAS_USB) += msp_usb.o
13obj-$(CONFIG_MIPS_MT_SMP) += msp_smp.o
14obj-$(CONFIG_MIPS_MT_SMTC) += msp_smtc.o
diff --git a/arch/mips/pmc-sierra/msp71xx/msp_eth.c b/arch/mips/pmc-sierra/msp71xx/msp_eth.c
new file mode 100644
index 000000000000..c584df393de2
--- /dev/null
+++ b/arch/mips/pmc-sierra/msp71xx/msp_eth.c
@@ -0,0 +1,187 @@
1/*
2 * The setup file for ethernet related hardware on PMC-Sierra MSP processors.
3 *
4 * Copyright 2010 PMC-Sierra, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 *
11 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
12 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
14 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
15 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
16 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
17 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
18 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
19 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
20 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
21 *
22 * You should have received a copy of the GNU General Public License along
23 * with this program; if not, write to the Free Software Foundation, Inc.,
24 * 675 Mass Ave, Cambridge, MA 02139, USA.
25 */
26
27#include <linux/init.h>
28#include <linux/kernel.h>
29#include <linux/ioport.h>
30#include <linux/platform_device.h>
31#include <linux/delay.h>
32#include <msp_regs.h>
33#include <msp_int.h>
34#include <msp_gpio_macros.h>
35
36
37#define MSP_ETHERNET_GPIO0 14
38#define MSP_ETHERNET_GPIO1 15
39#define MSP_ETHERNET_GPIO2 16
40
41#ifdef CONFIG_MSP_HAS_TSMAC
42#define MSP_TSMAC_SIZE 0x10020
43#define MSP_TSMAC_ID "pmc_tsmac"
44
45static struct resource msp_tsmac0_resources[] = {
46 [0] = {
47 .start = MSP_MAC0_BASE,
48 .end = MSP_MAC0_BASE + MSP_TSMAC_SIZE - 1,
49 .flags = IORESOURCE_MEM,
50 },
51 [1] = {
52 .start = MSP_INT_MAC0,
53 .end = MSP_INT_MAC0,
54 .flags = IORESOURCE_IRQ,
55 },
56};
57
58static struct resource msp_tsmac1_resources[] = {
59 [0] = {
60 .start = MSP_MAC1_BASE,
61 .end = MSP_MAC1_BASE + MSP_TSMAC_SIZE - 1,
62 .flags = IORESOURCE_MEM,
63 },
64 [1] = {
65 .start = MSP_INT_MAC1,
66 .end = MSP_INT_MAC1,
67 .flags = IORESOURCE_IRQ,
68 },
69};
70static struct resource msp_tsmac2_resources[] = {
71 [0] = {
72 .start = MSP_MAC2_BASE,
73 .end = MSP_MAC2_BASE + MSP_TSMAC_SIZE - 1,
74 .flags = IORESOURCE_MEM,
75 },
76 [1] = {
77 .start = MSP_INT_SAR,
78 .end = MSP_INT_SAR,
79 .flags = IORESOURCE_IRQ,
80 },
81};
82
83
84static struct platform_device tsmac_device[] = {
85 [0] = {
86 .name = MSP_TSMAC_ID,
87 .id = 0,
88 .num_resources = ARRAY_SIZE(msp_tsmac0_resources),
89 .resource = msp_tsmac0_resources,
90 },
91 [1] = {
92 .name = MSP_TSMAC_ID,
93 .id = 1,
94 .num_resources = ARRAY_SIZE(msp_tsmac1_resources),
95 .resource = msp_tsmac1_resources,
96 },
97 [2] = {
98 .name = MSP_TSMAC_ID,
99 .id = 2,
100 .num_resources = ARRAY_SIZE(msp_tsmac2_resources),
101 .resource = msp_tsmac2_resources,
102 },
103};
104#define msp_eth_devs tsmac_device
105
106#else
107/* If it is not TSMAC assume MSP_ETH (100Mbps) */
108#define MSP_ETH_ID "pmc_mspeth"
109#define MSP_ETH_SIZE 0xE0
110static struct resource msp_eth0_resources[] = {
111 [0] = {
112 .start = MSP_MAC0_BASE,
113 .end = MSP_MAC0_BASE + MSP_ETH_SIZE - 1,
114 .flags = IORESOURCE_MEM,
115 },
116 [1] = {
117 .start = MSP_INT_MAC0,
118 .end = MSP_INT_MAC0,
119 .flags = IORESOURCE_IRQ,
120 },
121};
122
123static struct resource msp_eth1_resources[] = {
124 [0] = {
125 .start = MSP_MAC1_BASE,
126 .end = MSP_MAC1_BASE + MSP_ETH_SIZE - 1,
127 .flags = IORESOURCE_MEM,
128 },
129 [1] = {
130 .start = MSP_INT_MAC1,
131 .end = MSP_INT_MAC1,
132 .flags = IORESOURCE_IRQ,
133 },
134};
135
136
137
138static struct platform_device mspeth_device[] = {
139 [0] = {
140 .name = MSP_ETH_ID,
141 .id = 0,
142 .num_resources = ARRAY_SIZE(msp_eth0_resources),
143 .resource = msp_eth0_resources,
144 },
145 [1] = {
146 .name = MSP_ETH_ID,
147 .id = 1,
148 .num_resources = ARRAY_SIZE(msp_eth1_resources),
149 .resource = msp_eth1_resources,
150 },
151
152};
153#define msp_eth_devs mspeth_device
154
155#endif
156int __init msp_eth_setup(void)
157{
158 int i, ret = 0;
159
160 /* Configure the GPIO and take the ethernet PHY out of reset */
161 msp_gpio_pin_mode(MSP_GPIO_OUTPUT, MSP_ETHERNET_GPIO0);
162 msp_gpio_pin_hi(MSP_ETHERNET_GPIO0);
163
164#ifdef CONFIG_MSP_HAS_TSMAC
165 /* 3 phys on boards with TSMAC */
166 msp_gpio_pin_mode(MSP_GPIO_OUTPUT, MSP_ETHERNET_GPIO1);
167 msp_gpio_pin_hi(MSP_ETHERNET_GPIO1);
168
169 msp_gpio_pin_mode(MSP_GPIO_OUTPUT, MSP_ETHERNET_GPIO2);
170 msp_gpio_pin_hi(MSP_ETHERNET_GPIO2);
171#endif
172 for (i = 0; i < ARRAY_SIZE(msp_eth_devs); i++) {
173 ret = platform_device_register(&msp_eth_devs[i]);
174 printk(KERN_INFO "device: %d, return value = %d\n", i, ret);
175 if (ret) {
176 platform_device_unregister(&msp_eth_devs[i]);
177 break;
178 }
179 }
180
181 if (ret)
182 printk(KERN_WARNING "Could not initialize "
183 "MSPETH device structures.\n");
184
185 return ret;
186}
187subsys_initcall(msp_eth_setup);
diff --git a/arch/mips/pmc-sierra/msp71xx/msp_irq.c b/arch/mips/pmc-sierra/msp71xx/msp_irq.c
index 734d598a2e3a..4531c4a514bc 100644
--- a/arch/mips/pmc-sierra/msp71xx/msp_irq.c
+++ b/arch/mips/pmc-sierra/msp71xx/msp_irq.c
@@ -19,8 +19,6 @@
19 19
20#include <msp_int.h> 20#include <msp_int.h>
21 21
22extern void msp_int_handle(void);
23
24/* SLP bases systems */ 22/* SLP bases systems */
25extern void msp_slp_irq_init(void); 23extern void msp_slp_irq_init(void);
26extern void msp_slp_irq_dispatch(void); 24extern void msp_slp_irq_dispatch(void);
@@ -29,6 +27,18 @@ extern void msp_slp_irq_dispatch(void);
29extern void msp_cic_irq_init(void); 27extern void msp_cic_irq_init(void);
30extern void msp_cic_irq_dispatch(void); 28extern void msp_cic_irq_dispatch(void);
31 29
30/* VSMP support init */
31extern void msp_vsmp_int_init(void);
32
33/* vectored interrupt implementation */
34
35/* SW0/1 interrupts are used for SMP/SMTC */
36static inline void mac0_int_dispatch(void) { do_IRQ(MSP_INT_MAC0); }
37static inline void mac1_int_dispatch(void) { do_IRQ(MSP_INT_MAC1); }
38static inline void mac2_int_dispatch(void) { do_IRQ(MSP_INT_SAR); }
39static inline void usb_int_dispatch(void) { do_IRQ(MSP_INT_USB); }
40static inline void sec_int_dispatch(void) { do_IRQ(MSP_INT_SEC); }
41
32/* 42/*
33 * The PMC-Sierra MSP interrupts are arranged in a 3 level cascaded 43 * The PMC-Sierra MSP interrupts are arranged in a 3 level cascaded
34 * hierarchical system. The first level are the direct MIPS interrupts 44 * hierarchical system. The first level are the direct MIPS interrupts
@@ -96,29 +106,57 @@ asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
96 do_IRQ(MSP_INT_SW1); 106 do_IRQ(MSP_INT_SW1);
97} 107}
98 108
99static struct irqaction cascade_msp = { 109static struct irqaction cic_cascade_msp = {
100 .handler = no_action, 110 .handler = no_action,
101 .name = "MSP cascade" 111 .name = "MSP CIC cascade"
102}; 112};
103 113
114static struct irqaction per_cascade_msp = {
115 .handler = no_action,
116 .name = "MSP PER cascade"
117};
104 118
105void __init arch_init_irq(void) 119void __init arch_init_irq(void)
106{ 120{
121 /* assume we'll be using vectored interrupt mode except in UP mode*/
122#ifdef CONFIG_MIPS_MT
123 BUG_ON(!cpu_has_vint);
124#endif
107 /* initialize the 1st-level CPU based interrupt controller */ 125 /* initialize the 1st-level CPU based interrupt controller */
108 mips_cpu_irq_init(); 126 mips_cpu_irq_init();
109 127
110#ifdef CONFIG_IRQ_MSP_CIC 128#ifdef CONFIG_IRQ_MSP_CIC
111 msp_cic_irq_init(); 129 msp_cic_irq_init();
112 130#ifdef CONFIG_MIPS_MT
131 set_vi_handler(MSP_INT_CIC, msp_cic_irq_dispatch);
132 set_vi_handler(MSP_INT_MAC0, mac0_int_dispatch);
133 set_vi_handler(MSP_INT_MAC1, mac1_int_dispatch);
134 set_vi_handler(MSP_INT_SAR, mac2_int_dispatch);
135 set_vi_handler(MSP_INT_USB, usb_int_dispatch);
136 set_vi_handler(MSP_INT_SEC, sec_int_dispatch);
137#ifdef CONFIG_MIPS_MT_SMP
138 msp_vsmp_int_init();
139#elif defined CONFIG_MIPS_MT_SMTC
140 /*Set hwmask for all platform devices */
141 irq_hwmask[MSP_INT_MAC0] = C_IRQ0;
142 irq_hwmask[MSP_INT_MAC1] = C_IRQ1;
143 irq_hwmask[MSP_INT_USB] = C_IRQ2;
144 irq_hwmask[MSP_INT_SAR] = C_IRQ3;
145 irq_hwmask[MSP_INT_SEC] = C_IRQ5;
146
147#endif /* CONFIG_MIPS_MT_SMP */
148#endif /* CONFIG_MIPS_MT */
113 /* setup the cascaded interrupts */ 149 /* setup the cascaded interrupts */
114 setup_irq(MSP_INT_CIC, &cascade_msp); 150 setup_irq(MSP_INT_CIC, &cic_cascade_msp);
115 setup_irq(MSP_INT_PER, &cascade_msp); 151 setup_irq(MSP_INT_PER, &per_cascade_msp);
152
116#else 153#else
117 /* setup the 2nd-level SLP register based interrupt controller */ 154 /* setup the 2nd-level SLP register based interrupt controller */
155 /* VSMP /SMTC support support is not enabled for SLP */
118 msp_slp_irq_init(); 156 msp_slp_irq_init();
119 157
120 /* setup the cascaded SLP/PER interrupts */ 158 /* setup the cascaded SLP/PER interrupts */
121 setup_irq(MSP_INT_SLP, &cascade_msp); 159 setup_irq(MSP_INT_SLP, &cic_cascade_msp);
122 setup_irq(MSP_INT_PER, &cascade_msp); 160 setup_irq(MSP_INT_PER, &per_cascade_msp);
123#endif 161#endif
124} 162}
diff --git a/arch/mips/pmc-sierra/msp71xx/msp_irq_cic.c b/arch/mips/pmc-sierra/msp71xx/msp_irq_cic.c
index 07e71ff2433f..352f29d9226f 100644
--- a/arch/mips/pmc-sierra/msp71xx/msp_irq_cic.c
+++ b/arch/mips/pmc-sierra/msp71xx/msp_irq_cic.c
@@ -1,8 +1,7 @@
1/* 1/*
2 * This file define the irq handler for MSP SLM subsystem interrupts. 2 * Copyright 2010 PMC-Sierra, Inc, derived from irq_cpu.c
3 * 3 *
4 * Copyright 2005-2007 PMC-Sierra, Inc, derived from irq_cpu.c 4 * This file define the irq handler for MSP CIC subsystem interrupts.
5 * Author: Andrew Hughes, Andrew_Hughes@pmc-sierra.com
6 * 5 *
7 * This program is free software; you can redistribute it and/or modify it 6 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the 7 * under the terms of the GNU General Public License as published by the
@@ -16,119 +15,203 @@
16#include <linux/bitops.h> 15#include <linux/bitops.h>
17#include <linux/irq.h> 16#include <linux/irq.h>
18 17
18#include <asm/mipsregs.h>
19#include <asm/system.h> 19#include <asm/system.h>
20 20
21#include <msp_cic_int.h> 21#include <msp_cic_int.h>
22#include <msp_regs.h> 22#include <msp_regs.h>
23 23
24/* 24/*
25 * NOTE: We are only enabling support for VPE0 right now. 25 * External API
26 */ 26 */
27extern void msp_per_irq_init(void);
28extern void msp_per_irq_dispatch(void);
27 29
28static inline void unmask_msp_cic_irq(unsigned int irq) 30
31/*
32 * Convenience Macro. Should be somewhere generic.
33 */
34#define get_current_vpe() \
35 ((read_c0_tcbind() >> TCBIND_CURVPE_SHIFT) & TCBIND_CURVPE)
36
37#ifdef CONFIG_SMP
38
39#define LOCK_VPE(flags, mtflags) \
40do { \
41 local_irq_save(flags); \
42 mtflags = dmt(); \
43} while (0)
44
45#define UNLOCK_VPE(flags, mtflags) \
46do { \
47 emt(mtflags); \
48 local_irq_restore(flags);\
49} while (0)
50
51#define LOCK_CORE(flags, mtflags) \
52do { \
53 local_irq_save(flags); \
54 mtflags = dvpe(); \
55} while (0)
56
57#define UNLOCK_CORE(flags, mtflags) \
58do { \
59 evpe(mtflags); \
60 local_irq_restore(flags);\
61} while (0)
62
63#else
64
65#define LOCK_VPE(flags, mtflags)
66#define UNLOCK_VPE(flags, mtflags)
67#endif
68
69/* ensure writes to cic are completed */
70static inline void cic_wmb(void)
29{ 71{
72 const volatile void __iomem *cic_mem = CIC_VPE0_MSK_REG;
73 volatile u32 dummy_read;
30 74
31 /* check for PER interrupt range */ 75 wmb();
32 if (irq < MSP_PER_INTBASE) 76 dummy_read = __raw_readl(cic_mem);
33 *CIC_VPE0_MSK_REG |= (1 << (irq - MSP_CIC_INTBASE)); 77 dummy_read++;
34 else
35 *PER_INT_MSK_REG |= (1 << (irq - MSP_PER_INTBASE));
36} 78}
37 79
38static inline void mask_msp_cic_irq(unsigned int irq) 80static void unmask_cic_irq(struct irq_data *d)
39{ 81{
40 /* check for PER interrupt range */ 82 volatile u32 *cic_msk_reg = CIC_VPE0_MSK_REG;
41 if (irq < MSP_PER_INTBASE) 83 int vpe;
42 *CIC_VPE0_MSK_REG &= ~(1 << (irq - MSP_CIC_INTBASE)); 84#ifdef CONFIG_SMP
43 else 85 unsigned int mtflags;
44 *PER_INT_MSK_REG &= ~(1 << (irq - MSP_PER_INTBASE)); 86 unsigned long flags;
87
88 /*
89 * Make sure we have IRQ affinity. It may have changed while
90 * we were processing the IRQ.
91 */
92 if (!cpumask_test_cpu(smp_processor_id(), d->affinity))
93 return;
94#endif
95
96 vpe = get_current_vpe();
97 LOCK_VPE(flags, mtflags);
98 cic_msk_reg[vpe] |= (1 << (d->irq - MSP_CIC_INTBASE));
99 UNLOCK_VPE(flags, mtflags);
100 cic_wmb();
45} 101}
46 102
47/* 103static void mask_cic_irq(struct irq_data *d)
48 * While we ack the interrupt interrupts are disabled and thus we don't need
49 * to deal with concurrency issues. Same for msp_cic_irq_end.
50 */
51static inline void ack_msp_cic_irq(unsigned int irq)
52{ 104{
53 mask_msp_cic_irq(irq); 105 volatile u32 *cic_msk_reg = CIC_VPE0_MSK_REG;
54 106 int vpe = get_current_vpe();
107#ifdef CONFIG_SMP
108 unsigned long flags, mtflags;
109#endif
110 LOCK_VPE(flags, mtflags);
111 cic_msk_reg[vpe] &= ~(1 << (d->irq - MSP_CIC_INTBASE));
112 UNLOCK_VPE(flags, mtflags);
113 cic_wmb();
114}
115static void msp_cic_irq_ack(struct irq_data *d)
116{
117 mask_cic_irq(d);
55 /* 118 /*
56 * only really necessary for 18, 16-14 and sometimes 3:0 (since 119 * Only really necessary for 18, 16-14 and sometimes 3:0
57 * these can be edge sensitive) but it doesn't hurt for the others. 120 * (since these can be edge sensitive) but it doesn't
58 */ 121 * hurt for the others
59 122 */
60 /* check for PER interrupt range */ 123 *CIC_STS_REG = (1 << (d->irq - MSP_CIC_INTBASE));
61 if (irq < MSP_PER_INTBASE) 124 smtc_im_ack_irq(d->irq);
62 *CIC_STS_REG = (1 << (irq - MSP_CIC_INTBASE));
63 else
64 *PER_INT_STS_REG = (1 << (irq - MSP_PER_INTBASE));
65} 125}
66 126
127/*Note: Limiting to VSMP . Not tested in SMTC */
128
129#ifdef CONFIG_MIPS_MT_SMP
130static int msp_cic_irq_set_affinity(struct irq_data *d,
131 const struct cpumask *cpumask, bool force)
132{
133 int cpu;
134 unsigned long flags;
135 unsigned int mtflags;
136 unsigned long imask = (1 << (irq - MSP_CIC_INTBASE));
137 volatile u32 *cic_mask = (volatile u32 *)CIC_VPE0_MSK_REG;
138
139 /* timer balancing should be disabled in kernel code */
140 BUG_ON(irq == MSP_INT_VPE0_TIMER || irq == MSP_INT_VPE1_TIMER);
141
142 LOCK_CORE(flags, mtflags);
143 /* enable if any of each VPE's TCs require this IRQ */
144 for_each_online_cpu(cpu) {
145 if (cpumask_test_cpu(cpu, cpumask))
146 cic_mask[cpu] |= imask;
147 else
148 cic_mask[cpu] &= ~imask;
149
150 }
151
152 UNLOCK_CORE(flags, mtflags);
153 return 0;
154
155}
156#endif
157
67static struct irq_chip msp_cic_irq_controller = { 158static struct irq_chip msp_cic_irq_controller = {
68 .name = "MSP_CIC", 159 .name = "MSP_CIC",
69 .ack = ack_msp_cic_irq, 160 .irq_mask = mask_cic_irq,
70 .mask = ack_msp_cic_irq, 161 .irq_mask_ack = msp_cic_irq_ack,
71 .mask_ack = ack_msp_cic_irq, 162 .irq_unmask = unmask_cic_irq,
72 .unmask = unmask_msp_cic_irq, 163 .irq_ack = msp_cic_irq_ack,
164#ifdef CONFIG_MIPS_MT_SMP
165 .irq_set_affinity = msp_cic_irq_set_affinity,
166#endif
73}; 167};
74 168
75
76void __init msp_cic_irq_init(void) 169void __init msp_cic_irq_init(void)
77{ 170{
78 int i; 171 int i;
79
80 /* Mask/clear interrupts. */ 172 /* Mask/clear interrupts. */
81 *CIC_VPE0_MSK_REG = 0x00000000; 173 *CIC_VPE0_MSK_REG = 0x00000000;
82 *PER_INT_MSK_REG = 0x00000000; 174 *CIC_VPE1_MSK_REG = 0x00000000;
83 *CIC_STS_REG = 0xFFFFFFFF; 175 *CIC_STS_REG = 0xFFFFFFFF;
84 *PER_INT_STS_REG = 0xFFFFFFFF;
85
86#if defined(CONFIG_PMC_MSP7120_GW) || \
87 defined(CONFIG_PMC_MSP7120_EVAL)
88 /* 176 /*
89 * The MSP7120 RG and EVBD boards use IRQ[6:4] for PCI. 177 * The MSP7120 RG and EVBD boards use IRQ[6:4] for PCI.
90 * These inputs map to EXT_INT_POL[6:4] inside the CIC. 178 * These inputs map to EXT_INT_POL[6:4] inside the CIC.
91 * They are to be active low, level sensitive. 179 * They are to be active low, level sensitive.
92 */ 180 */
93 *CIC_EXT_CFG_REG &= 0xFFFF8F8F; 181 *CIC_EXT_CFG_REG &= 0xFFFF8F8F;
94#endif
95 182
96 /* initialize all the IRQ descriptors */ 183 /* initialize all the IRQ descriptors */
97 for (i = MSP_CIC_INTBASE; i < MSP_PER_INTBASE + 32; i++) 184 for (i = MSP_CIC_INTBASE ; i < MSP_CIC_INTBASE + 32 ; i++) {
98 set_irq_chip_and_handler(i, &msp_cic_irq_controller, 185 set_irq_chip_and_handler(i, &msp_cic_irq_controller,
99 handle_level_irq); 186 handle_level_irq);
187#ifdef CONFIG_MIPS_MT_SMTC
188 /* Mask of CIC interrupt */
189 irq_hwmask[i] = C_IRQ4;
190#endif
191 }
192
193 /* Initialize the PER interrupt sub-system */
194 msp_per_irq_init();
100} 195}
101 196
197/* CIC masked by CIC vector processing before dispatch called */
102void msp_cic_irq_dispatch(void) 198void msp_cic_irq_dispatch(void)
103{ 199{
104 u32 pending; 200 volatile u32 *cic_msk_reg = (volatile u32 *)CIC_VPE0_MSK_REG;
105 int intbase; 201 u32 cic_mask;
106 202 u32 pending;
107 intbase = MSP_CIC_INTBASE; 203 int cic_status = *CIC_STS_REG;
108 pending = *CIC_STS_REG & *CIC_VPE0_MSK_REG; 204 cic_mask = cic_msk_reg[get_current_vpe()];
109 205 pending = cic_status & cic_mask;
110 /* check for PER interrupt */ 206 if (pending & (1 << (MSP_INT_VPE0_TIMER - MSP_CIC_INTBASE))) {
111 if (pending == (1 << (MSP_INT_PER - MSP_CIC_INTBASE))) {
112 intbase = MSP_PER_INTBASE;
113 pending = *PER_INT_STS_REG & *PER_INT_MSK_REG;
114 }
115
116 /* check for spurious interrupt */
117 if (pending == 0x00000000) {
118 printk(KERN_ERR
119 "Spurious %s interrupt? status %08x, mask %08x\n",
120 (intbase == MSP_CIC_INTBASE) ? "CIC" : "PER",
121 (intbase == MSP_CIC_INTBASE) ?
122 *CIC_STS_REG : *PER_INT_STS_REG,
123 (intbase == MSP_CIC_INTBASE) ?
124 *CIC_VPE0_MSK_REG : *PER_INT_MSK_REG);
125 return;
126 }
127
128 /* check for the timer and dispatch it first */
129 if ((intbase == MSP_CIC_INTBASE) &&
130 (pending & (1 << (MSP_INT_VPE0_TIMER - MSP_CIC_INTBASE))))
131 do_IRQ(MSP_INT_VPE0_TIMER); 207 do_IRQ(MSP_INT_VPE0_TIMER);
132 else 208 } else if (pending & (1 << (MSP_INT_VPE1_TIMER - MSP_CIC_INTBASE))) {
133 do_IRQ(ffs(pending) + intbase - 1); 209 do_IRQ(MSP_INT_VPE1_TIMER);
210 } else if (pending & (1 << (MSP_INT_PER - MSP_CIC_INTBASE))) {
211 msp_per_irq_dispatch();
212 } else if (pending) {
213 do_IRQ(ffs(pending) + MSP_CIC_INTBASE - 1);
214 } else{
215 spurious_interrupt();
216 }
134} 217}
diff --git a/arch/mips/pmc-sierra/msp71xx/msp_irq_per.c b/arch/mips/pmc-sierra/msp71xx/msp_irq_per.c
new file mode 100644
index 000000000000..f9b9dcdfa9dd
--- /dev/null
+++ b/arch/mips/pmc-sierra/msp71xx/msp_irq_per.c
@@ -0,0 +1,135 @@
1/*
2 * Copyright 2010 PMC-Sierra, Inc, derived from irq_cpu.c
3 *
4 * This file define the irq handler for MSP PER subsystem interrupts.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12#include <linux/init.h>
13#include <linux/interrupt.h>
14#include <linux/kernel.h>
15#include <linux/spinlock.h>
16#include <linux/bitops.h>
17
18#include <asm/mipsregs.h>
19#include <asm/system.h>
20
21#include <msp_cic_int.h>
22#include <msp_regs.h>
23
24
25/*
26 * Convenience Macro. Should be somewhere generic.
27 */
28#define get_current_vpe() \
29 ((read_c0_tcbind() >> TCBIND_CURVPE_SHIFT) & TCBIND_CURVPE)
30
31#ifdef CONFIG_SMP
32/*
33 * The PER registers must be protected from concurrent access.
34 */
35
36static DEFINE_SPINLOCK(per_lock);
37#endif
38
39/* ensure writes to per are completed */
40
41static inline void per_wmb(void)
42{
43 const volatile void __iomem *per_mem = PER_INT_MSK_REG;
44 volatile u32 dummy_read;
45
46 wmb();
47 dummy_read = __raw_readl(per_mem);
48 dummy_read++;
49}
50
51static inline void unmask_per_irq(struct irq_data *d)
52{
53#ifdef CONFIG_SMP
54 unsigned long flags;
55 spin_lock_irqsave(&per_lock, flags);
56 *PER_INT_MSK_REG |= (1 << (d->irq - MSP_PER_INTBASE));
57 spin_unlock_irqrestore(&per_lock, flags);
58#else
59 *PER_INT_MSK_REG |= (1 << (d->irq - MSP_PER_INTBASE));
60#endif
61 per_wmb();
62}
63
64static inline void mask_per_irq(struct irq_data *d)
65{
66#ifdef CONFIG_SMP
67 unsigned long flags;
68 spin_lock_irqsave(&per_lock, flags);
69 *PER_INT_MSK_REG &= ~(1 << (d->irq - MSP_PER_INTBASE));
70 spin_unlock_irqrestore(&per_lock, flags);
71#else
72 *PER_INT_MSK_REG &= ~(1 << (d->irq - MSP_PER_INTBASE));
73#endif
74 per_wmb();
75}
76
77static inline void msp_per_irq_ack(struct irq_data *d)
78{
79 mask_per_irq(d);
80 /*
81 * In the PER interrupt controller, only bits 11 and 10
82 * are write-to-clear, (SPI TX complete, SPI RX complete).
83 * It does nothing for any others.
84 */
85 *PER_INT_STS_REG = (1 << (d->irq - MSP_PER_INTBASE));
86}
87
88#ifdef CONFIG_SMP
89static int msp_per_irq_set_affinity(struct irq_data *d,
90 const struct cpumask *affinity, bool force)
91{
92 /* WTF is this doing ????? */
93 unmask_per_irq(d);
94 return 0;
95}
96#endif
97
98static struct irq_chip msp_per_irq_controller = {
99 .name = "MSP_PER",
100 .irq_enable = unmask_per_irq.
101 .irq_disable = mask_per_irq,
102 .irq_ack = msp_per_irq_ack,
103#ifdef CONFIG_SMP
104 .irq_set_affinity = msp_per_irq_set_affinity,
105#endif
106};
107
108void __init msp_per_irq_init(void)
109{
110 int i;
111 /* Mask/clear interrupts. */
112 *PER_INT_MSK_REG = 0x00000000;
113 *PER_INT_STS_REG = 0xFFFFFFFF;
114 /* initialize all the IRQ descriptors */
115 for (i = MSP_PER_INTBASE; i < MSP_PER_INTBASE + 32; i++) {
116 irq_set_chip(i, &msp_per_irq_controller);
117#ifdef CONFIG_MIPS_MT_SMTC
118 irq_hwmask[i] = C_IRQ4;
119#endif
120 }
121}
122
123void msp_per_irq_dispatch(void)
124{
125 u32 per_mask = *PER_INT_MSK_REG;
126 u32 per_status = *PER_INT_STS_REG;
127 u32 pending;
128
129 pending = per_status & per_mask;
130 if (pending) {
131 do_IRQ(ffs(pending) + MSP_PER_INTBASE - 1);
132 } else {
133 spurious_interrupt();
134 }
135}
diff --git a/arch/mips/pmc-sierra/msp71xx/msp_irq_slp.c b/arch/mips/pmc-sierra/msp71xx/msp_irq_slp.c
index 61f390232346..8f51e4adc438 100644
--- a/arch/mips/pmc-sierra/msp71xx/msp_irq_slp.c
+++ b/arch/mips/pmc-sierra/msp71xx/msp_irq_slp.c
@@ -21,8 +21,10 @@
21#include <msp_slp_int.h> 21#include <msp_slp_int.h>
22#include <msp_regs.h> 22#include <msp_regs.h>
23 23
24static inline void unmask_msp_slp_irq(unsigned int irq) 24static inline void unmask_msp_slp_irq(struct irq_data *d)
25{ 25{
26 unsigned int irq = d->irq;
27
26 /* check for PER interrupt range */ 28 /* check for PER interrupt range */
27 if (irq < MSP_PER_INTBASE) 29 if (irq < MSP_PER_INTBASE)
28 *SLP_INT_MSK_REG |= (1 << (irq - MSP_SLP_INTBASE)); 30 *SLP_INT_MSK_REG |= (1 << (irq - MSP_SLP_INTBASE));
@@ -30,8 +32,10 @@ static inline void unmask_msp_slp_irq(unsigned int irq)
30 *PER_INT_MSK_REG |= (1 << (irq - MSP_PER_INTBASE)); 32 *PER_INT_MSK_REG |= (1 << (irq - MSP_PER_INTBASE));
31} 33}
32 34
33static inline void mask_msp_slp_irq(unsigned int irq) 35static inline void mask_msp_slp_irq(struct irq_data *d)
34{ 36{
37 unsigned int irq = d->irq;
38
35 /* check for PER interrupt range */ 39 /* check for PER interrupt range */
36 if (irq < MSP_PER_INTBASE) 40 if (irq < MSP_PER_INTBASE)
37 *SLP_INT_MSK_REG &= ~(1 << (irq - MSP_SLP_INTBASE)); 41 *SLP_INT_MSK_REG &= ~(1 << (irq - MSP_SLP_INTBASE));
@@ -43,8 +47,10 @@ static inline void mask_msp_slp_irq(unsigned int irq)
43 * While we ack the interrupt interrupts are disabled and thus we don't need 47 * While we ack the interrupt interrupts are disabled and thus we don't need
44 * to deal with concurrency issues. Same for msp_slp_irq_end. 48 * to deal with concurrency issues. Same for msp_slp_irq_end.
45 */ 49 */
46static inline void ack_msp_slp_irq(unsigned int irq) 50static inline void ack_msp_slp_irq(struct irq_data *d)
47{ 51{
52 unsigned int irq = d->irq;
53
48 /* check for PER interrupt range */ 54 /* check for PER interrupt range */
49 if (irq < MSP_PER_INTBASE) 55 if (irq < MSP_PER_INTBASE)
50 *SLP_INT_STS_REG = (1 << (irq - MSP_SLP_INTBASE)); 56 *SLP_INT_STS_REG = (1 << (irq - MSP_SLP_INTBASE));
@@ -54,9 +60,9 @@ static inline void ack_msp_slp_irq(unsigned int irq)
54 60
55static struct irq_chip msp_slp_irq_controller = { 61static struct irq_chip msp_slp_irq_controller = {
56 .name = "MSP_SLP", 62 .name = "MSP_SLP",
57 .ack = ack_msp_slp_irq, 63 .irq_ack = ack_msp_slp_irq,
58 .mask = mask_msp_slp_irq, 64 .irq_mask = mask_msp_slp_irq,
59 .unmask = unmask_msp_slp_irq, 65 .irq_unmask = unmask_msp_slp_irq,
60}; 66};
61 67
62void __init msp_slp_irq_init(void) 68void __init msp_slp_irq_init(void)
diff --git a/arch/mips/pmc-sierra/msp71xx/msp_setup.c b/arch/mips/pmc-sierra/msp71xx/msp_setup.c
index a54e85b3cf29..fb37a10e0309 100644
--- a/arch/mips/pmc-sierra/msp71xx/msp_setup.c
+++ b/arch/mips/pmc-sierra/msp71xx/msp_setup.c
@@ -146,6 +146,8 @@ void __init plat_mem_setup(void)
146 pm_power_off = msp_power_off; 146 pm_power_off = msp_power_off;
147} 147}
148 148
149extern struct plat_smp_ops msp_smtc_smp_ops;
150
149void __init prom_init(void) 151void __init prom_init(void)
150{ 152{
151 unsigned long family; 153 unsigned long family;
@@ -226,6 +228,14 @@ void __init prom_init(void)
226 */ 228 */
227 msp_serial_setup(); 229 msp_serial_setup();
228 230
231#ifdef CONFIG_MIPS_MT_SMP
232 register_smp_ops(&vsmp_smp_ops);
233#endif
234
235#ifdef CONFIG_MIPS_MT_SMTC
236 register_smp_ops(&msp_smtc_smp_ops);
237#endif
238
229#ifdef CONFIG_PMCTWILED 239#ifdef CONFIG_PMCTWILED
230 /* 240 /*
231 * Setup LED states before the subsys_initcall loads other 241 * Setup LED states before the subsys_initcall loads other
diff --git a/arch/mips/pmc-sierra/msp71xx/msp_smp.c b/arch/mips/pmc-sierra/msp71xx/msp_smp.c
new file mode 100644
index 000000000000..43a9e26e1c69
--- /dev/null
+++ b/arch/mips/pmc-sierra/msp71xx/msp_smp.c
@@ -0,0 +1,77 @@
1/*
2 * Copyright (C) 2000, 2001, 2004 MIPS Technologies, Inc.
3 * Copyright (C) 2001 Ralf Baechle
4 * Copyright (C) 2010 PMC-Sierra, Inc.
5 *
6 * VSMP support for MSP platforms . Derived from malta vsmp support.
7 *
8 * This program is free software; you can distribute it and/or modify it
9 * under the terms of the GNU General Public License (Version 2) as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 * for more details.
16 *
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, write to the Free Software Foundation, Inc.,
19 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
20 *
21 */
22#include <linux/smp.h>
23#include <linux/interrupt.h>
24
25#ifdef CONFIG_MIPS_MT_SMP
26#define MIPS_CPU_IPI_RESCHED_IRQ 0 /* SW int 0 for resched */
27#define MIPS_CPU_IPI_CALL_IRQ 1 /* SW int 1 for call */
28
29
30static void ipi_resched_dispatch(void)
31{
32 do_IRQ(MIPS_CPU_IPI_RESCHED_IRQ);
33}
34
35static void ipi_call_dispatch(void)
36{
37 do_IRQ(MIPS_CPU_IPI_CALL_IRQ);
38}
39
40static irqreturn_t ipi_resched_interrupt(int irq, void *dev_id)
41{
42 return IRQ_HANDLED;
43}
44
45static irqreturn_t ipi_call_interrupt(int irq, void *dev_id)
46{
47 smp_call_function_interrupt();
48
49 return IRQ_HANDLED;
50}
51
52static struct irqaction irq_resched = {
53 .handler = ipi_resched_interrupt,
54 .flags = IRQF_DISABLED | IRQF_PERCPU,
55 .name = "IPI_resched"
56};
57
58static struct irqaction irq_call = {
59 .handler = ipi_call_interrupt,
60 .flags = IRQF_DISABLED | IRQF_PERCPU,
61 .name = "IPI_call"
62};
63
64void __init arch_init_ipiirq(int irq, struct irqaction *action)
65{
66 setup_irq(irq, action);
67 set_irq_handler(irq, handle_percpu_irq);
68}
69
70void __init msp_vsmp_int_init(void)
71{
72 set_vi_handler(MIPS_CPU_IPI_RESCHED_IRQ, ipi_resched_dispatch);
73 set_vi_handler(MIPS_CPU_IPI_CALL_IRQ, ipi_call_dispatch);
74 arch_init_ipiirq(MIPS_CPU_IPI_RESCHED_IRQ, &irq_resched);
75 arch_init_ipiirq(MIPS_CPU_IPI_CALL_IRQ, &irq_call);
76}
77#endif /* CONFIG_MIPS_MT_SMP */
diff --git a/arch/mips/pmc-sierra/msp71xx/msp_smtc.c b/arch/mips/pmc-sierra/msp71xx/msp_smtc.c
new file mode 100644
index 000000000000..c8dcc1c01e18
--- /dev/null
+++ b/arch/mips/pmc-sierra/msp71xx/msp_smtc.c
@@ -0,0 +1,105 @@
1/*
2 * MSP71xx Platform-specific hooks for SMP operation
3 */
4#include <linux/irq.h>
5#include <linux/init.h>
6
7#include <asm/mipsmtregs.h>
8#include <asm/mipsregs.h>
9#include <asm/smtc.h>
10#include <asm/smtc_ipi.h>
11
12/* VPE/SMP Prototype implements platform interfaces directly */
13
14/*
15 * Cause the specified action to be performed on a targeted "CPU"
16 */
17
18static void msp_smtc_send_ipi_single(int cpu, unsigned int action)
19{
20 /* "CPU" may be TC of same VPE, VPE of same CPU, or different CPU */
21 smtc_send_ipi(cpu, LINUX_SMP_IPI, action);
22}
23
24static void msp_smtc_send_ipi_mask(const struct cpumask *mask,
25 unsigned int action)
26{
27 unsigned int i;
28
29 for_each_cpu(i, mask)
30 msp_smtc_send_ipi_single(i, action);
31}
32
33/*
34 * Post-config but pre-boot cleanup entry point
35 */
36static void __cpuinit msp_smtc_init_secondary(void)
37{
38 int myvpe;
39
40 /* Don't enable Malta I/O interrupts (IP2) for secondary VPEs */
41 myvpe = read_c0_tcbind() & TCBIND_CURVPE;
42 if (myvpe > 0)
43 change_c0_status(ST0_IM, STATUSF_IP0 | STATUSF_IP1 |
44 STATUSF_IP6 | STATUSF_IP7);
45 smtc_init_secondary();
46}
47
48/*
49 * Platform "CPU" startup hook
50 */
51static void __cpuinit msp_smtc_boot_secondary(int cpu,
52 struct task_struct *idle)
53{
54 smtc_boot_secondary(cpu, idle);
55}
56
57/*
58 * SMP initialization finalization entry point
59 */
60static void __cpuinit msp_smtc_smp_finish(void)
61{
62 smtc_smp_finish();
63}
64
65/*
66 * Hook for after all CPUs are online
67 */
68
69static void msp_smtc_cpus_done(void)
70{
71}
72
73/*
74 * Platform SMP pre-initialization
75 *
76 * As noted above, we can assume a single CPU for now
77 * but it may be multithreaded.
78 */
79
80static void __init msp_smtc_smp_setup(void)
81{
82 /*
83 * we won't get the definitive value until
84 * we've run smtc_prepare_cpus later, but
85 */
86
87 if (read_c0_config3() & (1 << 2))
88 smp_num_siblings = smtc_build_cpu_map(0);
89}
90
91static void __init msp_smtc_prepare_cpus(unsigned int max_cpus)
92{
93 smtc_prepare_cpus(max_cpus);
94}
95
96struct plat_smp_ops msp_smtc_smp_ops = {
97 .send_ipi_single = msp_smtc_send_ipi_single,
98 .send_ipi_mask = msp_smtc_send_ipi_mask,
99 .init_secondary = msp_smtc_init_secondary,
100 .smp_finish = msp_smtc_smp_finish,
101 .cpus_done = msp_smtc_cpus_done,
102 .boot_secondary = msp_smtc_boot_secondary,
103 .smp_setup = msp_smtc_smp_setup,
104 .prepare_cpus = msp_smtc_prepare_cpus,
105};
diff --git a/arch/mips/pmc-sierra/msp71xx/msp_time.c b/arch/mips/pmc-sierra/msp71xx/msp_time.c
index 01df84ce31e2..8b42f307a7a7 100644
--- a/arch/mips/pmc-sierra/msp71xx/msp_time.c
+++ b/arch/mips/pmc-sierra/msp71xx/msp_time.c
@@ -29,6 +29,7 @@
29#include <linux/module.h> 29#include <linux/module.h>
30#include <linux/ptrace.h> 30#include <linux/ptrace.h>
31 31
32#include <asm/cevt-r4k.h>
32#include <asm/mipsregs.h> 33#include <asm/mipsregs.h>
33#include <asm/time.h> 34#include <asm/time.h>
34 35
@@ -36,6 +37,12 @@
36#include <msp_int.h> 37#include <msp_int.h>
37#include <msp_regs.h> 38#include <msp_regs.h>
38 39
40#define get_current_vpe() \
41 ((read_c0_tcbind() >> TCBIND_CURVPE_SHIFT) & TCBIND_CURVPE)
42
43static struct irqaction timer_vpe1;
44static int tim_installed;
45
39void __init plat_time_init(void) 46void __init plat_time_init(void)
40{ 47{
41 char *endp, *s; 48 char *endp, *s;
@@ -83,5 +90,12 @@ void __init plat_time_init(void)
83 90
84unsigned int __cpuinit get_c0_compare_int(void) 91unsigned int __cpuinit get_c0_compare_int(void)
85{ 92{
86 return MSP_INT_VPE0_TIMER; 93 /* MIPS_MT modes may want timer for second VPE */
94 if ((get_current_vpe()) && !tim_installed) {
95 memcpy(&timer_vpe1, &c0_compare_irqaction, sizeof(timer_vpe1));
96 setup_irq(MSP_INT_VPE1_TIMER, &timer_vpe1);
97 tim_installed++;
98 }
99
100 return get_current_vpe() ? MSP_INT_VPE1_TIMER : MSP_INT_VPE0_TIMER;
87} 101}
diff --git a/arch/mips/pmc-sierra/msp71xx/msp_usb.c b/arch/mips/pmc-sierra/msp71xx/msp_usb.c
index 0ee01e359dd8..9a1aef89bd4c 100644
--- a/arch/mips/pmc-sierra/msp71xx/msp_usb.c
+++ b/arch/mips/pmc-sierra/msp71xx/msp_usb.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * The setup file for USB related hardware on PMC-Sierra MSP processors. 2 * The setup file for USB related hardware on PMC-Sierra MSP processors.
3 * 3 *
4 * Copyright 2006-2007 PMC-Sierra, Inc. 4 * Copyright 2006 PMC-Sierra, Inc.
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify it 6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the 7 * under the terms of the GNU General Public License as published by the
@@ -23,8 +23,8 @@
23 * with this program; if not, write to the Free Software Foundation, Inc., 23 * with this program; if not, write to the Free Software Foundation, Inc.,
24 * 675 Mass Ave, Cambridge, MA 02139, USA. 24 * 675 Mass Ave, Cambridge, MA 02139, USA.
25 */ 25 */
26#if defined(CONFIG_USB_EHCI_HCD) || defined(CONFIG_USB_GADGET)
26 27
27#include <linux/dma-mapping.h>
28#include <linux/init.h> 28#include <linux/init.h>
29#include <linux/ioport.h> 29#include <linux/ioport.h>
30#include <linux/platform_device.h> 30#include <linux/platform_device.h>
@@ -34,40 +34,56 @@
34#include <msp_regs.h> 34#include <msp_regs.h>
35#include <msp_int.h> 35#include <msp_int.h>
36#include <msp_prom.h> 36#include <msp_prom.h>
37#include <msp_usb.h>
38
37 39
38#if defined(CONFIG_USB_EHCI_HCD) 40#if defined(CONFIG_USB_EHCI_HCD)
39static struct resource msp_usbhost_resources [] = { 41static struct resource msp_usbhost0_resources[] = {
40 [0] = { 42 [0] = { /* EHCI-HS operational and capabilities registers */
41 .start = MSP_USB_BASE_START, 43 .start = MSP_USB0_HS_START,
42 .end = MSP_USB_BASE_END, 44 .end = MSP_USB0_HS_END,
43 .flags = IORESOURCE_MEM, 45 .flags = IORESOURCE_MEM,
44 }, 46 },
45 [1] = { 47 [1] = {
46 .start = MSP_INT_USB, 48 .start = MSP_INT_USB,
47 .end = MSP_INT_USB, 49 .end = MSP_INT_USB,
48 .flags = IORESOURCE_IRQ, 50 .flags = IORESOURCE_IRQ,
51 },
52 [2] = { /* MSBus-to-AMBA bridge register space */
53 .start = MSP_USB0_MAB_START,
54 .end = MSP_USB0_MAB_END,
55 .flags = IORESOURCE_MEM,
56 },
57 [3] = { /* Identification and general hardware parameters */
58 .start = MSP_USB0_ID_START,
59 .end = MSP_USB0_ID_END,
60 .flags = IORESOURCE_MEM,
49 }, 61 },
50}; 62};
51 63
52static u64 msp_usbhost_dma_mask = DMA_BIT_MASK(32); 64static u64 msp_usbhost0_dma_mask = 0xffffffffUL;
53 65
54static struct platform_device msp_usbhost_device = { 66static struct mspusb_device msp_usbhost0_device = {
55 .name = "pmcmsp-ehci",
56 .id = 0,
57 .dev = { 67 .dev = {
58 .dma_mask = &msp_usbhost_dma_mask, 68 .name = "pmcmsp-ehci",
59 .coherent_dma_mask = DMA_BIT_MASK(32), 69 .id = 0,
70 .dev = {
71 .dma_mask = &msp_usbhost0_dma_mask,
72 .coherent_dma_mask = 0xffffffffUL,
73 },
74 .num_resources = ARRAY_SIZE(msp_usbhost0_resources),
75 .resource = msp_usbhost0_resources,
60 }, 76 },
61 .num_resources = ARRAY_SIZE(msp_usbhost_resources),
62 .resource = msp_usbhost_resources,
63}; 77};
64#endif /* CONFIG_USB_EHCI_HCD */
65 78
66#if defined(CONFIG_USB_GADGET) 79/* MSP7140/MSP82XX has two USB2 hosts. */
67static struct resource msp_usbdev_resources [] = { 80#ifdef CONFIG_MSP_HAS_DUAL_USB
68 [0] = { 81static u64 msp_usbhost1_dma_mask = 0xffffffffUL;
69 .start = MSP_USB_BASE, 82
70 .end = MSP_USB_BASE_END, 83static struct resource msp_usbhost1_resources[] = {
84 [0] = { /* EHCI-HS operational and capabilities registers */
85 .start = MSP_USB1_HS_START,
86 .end = MSP_USB1_HS_END,
71 .flags = IORESOURCE_MEM, 87 .flags = IORESOURCE_MEM,
72 }, 88 },
73 [1] = { 89 [1] = {
@@ -75,76 +91,173 @@ static struct resource msp_usbdev_resources [] = {
75 .end = MSP_INT_USB, 91 .end = MSP_INT_USB,
76 .flags = IORESOURCE_IRQ, 92 .flags = IORESOURCE_IRQ,
77 }, 93 },
94 [2] = { /* MSBus-to-AMBA bridge register space */
95 .start = MSP_USB1_MAB_START,
96 .end = MSP_USB1_MAB_END,
97 .flags = IORESOURCE_MEM,
98 },
99 [3] = { /* Identification and general hardware parameters */
100 .start = MSP_USB1_ID_START,
101 .end = MSP_USB1_ID_END,
102 .flags = IORESOURCE_MEM,
103 },
104};
105
106static struct mspusb_device msp_usbhost1_device = {
107 .dev = {
108 .name = "pmcmsp-ehci",
109 .id = 1,
110 .dev = {
111 .dma_mask = &msp_usbhost1_dma_mask,
112 .coherent_dma_mask = 0xffffffffUL,
113 },
114 .num_resources = ARRAY_SIZE(msp_usbhost1_resources),
115 .resource = msp_usbhost1_resources,
116 },
78}; 117};
118#endif /* CONFIG_MSP_HAS_DUAL_USB */
119#endif /* CONFIG_USB_EHCI_HCD */
79 120
80static u64 msp_usbdev_dma_mask = DMA_BIT_MASK(32); 121#if defined(CONFIG_USB_GADGET)
122static struct resource msp_usbdev0_resources[] = {
123 [0] = { /* EHCI-HS operational and capabilities registers */
124 .start = MSP_USB0_HS_START,
125 .end = MSP_USB0_HS_END,
126 .flags = IORESOURCE_MEM,
127 },
128 [1] = {
129 .start = MSP_INT_USB,
130 .end = MSP_INT_USB,
131 .flags = IORESOURCE_IRQ,
132 },
133 [2] = { /* MSBus-to-AMBA bridge register space */
134 .start = MSP_USB0_MAB_START,
135 .end = MSP_USB0_MAB_END,
136 .flags = IORESOURCE_MEM,
137 },
138 [3] = { /* Identification and general hardware parameters */
139 .start = MSP_USB0_ID_START,
140 .end = MSP_USB0_ID_END,
141 .flags = IORESOURCE_MEM,
142 },
143};
81 144
82static struct platform_device msp_usbdev_device = { 145static u64 msp_usbdev_dma_mask = 0xffffffffUL;
83 .name = "msp71xx_udc", 146
84 .id = 0, 147/* This may need to be converted to a mspusb_device, too. */
148static struct mspusb_device msp_usbdev0_device = {
85 .dev = { 149 .dev = {
86 .dma_mask = &msp_usbdev_dma_mask, 150 .name = "msp71xx_udc",
87 .coherent_dma_mask = DMA_BIT_MASK(32), 151 .id = 0,
152 .dev = {
153 .dma_mask = &msp_usbdev_dma_mask,
154 .coherent_dma_mask = 0xffffffffUL,
155 },
156 .num_resources = ARRAY_SIZE(msp_usbdev0_resources),
157 .resource = msp_usbdev0_resources,
88 }, 158 },
89 .num_resources = ARRAY_SIZE(msp_usbdev_resources),
90 .resource = msp_usbdev_resources,
91}; 159};
92#endif /* CONFIG_USB_GADGET */
93 160
94#if defined(CONFIG_USB_EHCI_HCD) || defined(CONFIG_USB_GADGET) 161#ifdef CONFIG_MSP_HAS_DUAL_USB
95static struct platform_device *msp_devs[1]; 162static struct resource msp_usbdev1_resources[] = {
96#endif 163 [0] = { /* EHCI-HS operational and capabilities registers */
164 .start = MSP_USB1_HS_START,
165 .end = MSP_USB1_HS_END,
166 .flags = IORESOURCE_MEM,
167 },
168 [1] = {
169 .start = MSP_INT_USB,
170 .end = MSP_INT_USB,
171 .flags = IORESOURCE_IRQ,
172 },
173 [2] = { /* MSBus-to-AMBA bridge register space */
174 .start = MSP_USB1_MAB_START,
175 .end = MSP_USB1_MAB_END,
176 .flags = IORESOURCE_MEM,
177 },
178 [3] = { /* Identification and general hardware parameters */
179 .start = MSP_USB1_ID_START,
180 .end = MSP_USB1_ID_END,
181 .flags = IORESOURCE_MEM,
182 },
183};
97 184
185/* This may need to be converted to a mspusb_device, too. */
186static struct mspusb_device msp_usbdev1_device = {
187 .dev = {
188 .name = "msp71xx_udc",
189 .id = 0,
190 .dev = {
191 .dma_mask = &msp_usbdev_dma_mask,
192 .coherent_dma_mask = 0xffffffffUL,
193 },
194 .num_resources = ARRAY_SIZE(msp_usbdev1_resources),
195 .resource = msp_usbdev1_resources,
196 },
197};
198
199#endif /* CONFIG_MSP_HAS_DUAL_USB */
200#endif /* CONFIG_USB_GADGET */
98 201
99static int __init msp_usb_setup(void) 202static int __init msp_usb_setup(void)
100{ 203{
101#if defined(CONFIG_USB_EHCI_HCD) || defined(CONFIG_USB_GADGET) 204 char *strp;
102 char *strp; 205 char envstr[32];
103 char envstr[32]; 206 struct platform_device *msp_devs[NUM_USB_DEVS];
104 unsigned int val = 0; 207 unsigned int val;
105 int result = 0;
106 208
209 /* construct environment name usbmode */
210 /* set usbmode <host/device> as pmon environment var */
107 /* 211 /*
108 * construct environment name usbmode 212 * Could this perhaps be integrated into the "features" env var?
109 * set usbmode <host/device> as pmon environment var 213 * Use the features key "U", and follow with "H" for host-mode,
214 * "D" for device-mode. If it works for Ethernet, why not USB...
215 * -- hammtrev, 2007/03/22
110 */ 216 */
111 snprintf((char *)&envstr[0], sizeof(envstr), "usbmode"); 217 snprintf((char *)&envstr[0], sizeof(envstr), "usbmode");
112 218
113#if defined(CONFIG_USB_EHCI_HCD) 219 /* set default host mode */
114 /* default to host mode */
115 val = 1; 220 val = 1;
116#endif
117 221
118 /* get environment string */ 222 /* get environment string */
119 strp = prom_getenv((char *)&envstr[0]); 223 strp = prom_getenv((char *)&envstr[0]);
120 if (strp) { 224 if (strp) {
225 /* compare string */
121 if (!strcmp(strp, "device")) 226 if (!strcmp(strp, "device"))
122 val = 0; 227 val = 0;
123 } 228 }
124 229
125 if (val) { 230 if (val) {
126#if defined(CONFIG_USB_EHCI_HCD) 231#if defined(CONFIG_USB_EHCI_HCD)
127 /* get host mode device */ 232 msp_devs[0] = &msp_usbhost0_device.dev;
128 msp_devs[0] = &msp_usbhost_device; 233 ppfinit("platform add USB HOST done %s.\n", msp_devs[0]->name);
129 ppfinit("platform add USB HOST done %s.\n", 234#ifdef CONFIG_MSP_HAS_DUAL_USB
130 msp_devs[0]->name); 235 msp_devs[1] = &msp_usbhost1_device.dev;
131 236 ppfinit("platform add USB HOST done %s.\n", msp_devs[1]->name);
132 result = platform_add_devices(msp_devs, ARRAY_SIZE(msp_devs)); 237#endif
133#endif /* CONFIG_USB_EHCI_HCD */ 238#else
134 } 239 ppfinit("%s: echi_hcd not supported\n", __FILE__);
240#endif /* CONFIG_USB_EHCI_HCD */
241 } else {
135#if defined(CONFIG_USB_GADGET) 242#if defined(CONFIG_USB_GADGET)
136 else {
137 /* get device mode structure */ 243 /* get device mode structure */
138 msp_devs[0] = &msp_usbdev_device; 244 msp_devs[0] = &msp_usbdev0_device.dev;
139 ppfinit("platform add USB DEVICE done %s.\n", 245 ppfinit("platform add USB DEVICE done %s.\n"
140 msp_devs[0]->name); 246 , msp_devs[0]->name);
141 247#ifdef CONFIG_MSP_HAS_DUAL_USB
142 result = platform_add_devices(msp_devs, ARRAY_SIZE(msp_devs)); 248 msp_devs[1] = &msp_usbdev1_device.dev;
249 ppfinit("platform add USB DEVICE done %s.\n"
250 , msp_devs[1]->name);
251#endif
252#else
253 ppfinit("%s: usb_gadget not supported\n", __FILE__);
254#endif /* CONFIG_USB_GADGET */
143 } 255 }
144#endif /* CONFIG_USB_GADGET */ 256 /* add device */
145#endif /* CONFIG_USB_EHCI_HCD || CONFIG_USB_GADGET */ 257 platform_add_devices(msp_devs, ARRAY_SIZE(msp_devs));
146 258
147 return result; 259 return 0;
148} 260}
149 261
150subsys_initcall(msp_usb_setup); 262subsys_initcall(msp_usb_setup);
263#endif /* CONFIG_USB_EHCI_HCD || CONFIG_USB_GADGET */
diff --git a/arch/mips/pnx833x/common/interrupts.c b/arch/mips/pnx833x/common/interrupts.c
index 941916f8aaff..b226bcb0a2f4 100644
--- a/arch/mips/pnx833x/common/interrupts.c
+++ b/arch/mips/pnx833x/common/interrupts.c
@@ -152,10 +152,6 @@ static inline void pnx833x_hard_disable_pic_irq(unsigned int irq)
152 PNX833X_PIC_INT_REG(irq) = 0; 152 PNX833X_PIC_INT_REG(irq) = 0;
153} 153}
154 154
155static int irqflags[PNX833X_PIC_NUM_IRQ]; /* initialized by zeroes */
156#define IRQFLAG_STARTED 1
157#define IRQFLAG_DISABLED 2
158
159static DEFINE_RAW_SPINLOCK(pnx833x_irq_lock); 155static DEFINE_RAW_SPINLOCK(pnx833x_irq_lock);
160 156
161static unsigned int pnx833x_startup_pic_irq(unsigned int irq) 157static unsigned int pnx833x_startup_pic_irq(unsigned int irq)
@@ -164,108 +160,54 @@ static unsigned int pnx833x_startup_pic_irq(unsigned int irq)
164 unsigned int pic_irq = irq - PNX833X_PIC_IRQ_BASE; 160 unsigned int pic_irq = irq - PNX833X_PIC_IRQ_BASE;
165 161
166 raw_spin_lock_irqsave(&pnx833x_irq_lock, flags); 162 raw_spin_lock_irqsave(&pnx833x_irq_lock, flags);
167
168 irqflags[pic_irq] = IRQFLAG_STARTED; /* started, not disabled */
169 pnx833x_hard_enable_pic_irq(pic_irq); 163 pnx833x_hard_enable_pic_irq(pic_irq);
170
171 raw_spin_unlock_irqrestore(&pnx833x_irq_lock, flags); 164 raw_spin_unlock_irqrestore(&pnx833x_irq_lock, flags);
172 return 0; 165 return 0;
173} 166}
174 167
175static void pnx833x_shutdown_pic_irq(unsigned int irq) 168static void pnx833x_enable_pic_irq(struct irq_data *d)
176{
177 unsigned long flags;
178 unsigned int pic_irq = irq - PNX833X_PIC_IRQ_BASE;
179
180 raw_spin_lock_irqsave(&pnx833x_irq_lock, flags);
181
182 irqflags[pic_irq] = 0; /* not started */
183 pnx833x_hard_disable_pic_irq(pic_irq);
184
185 raw_spin_unlock_irqrestore(&pnx833x_irq_lock, flags);
186}
187
188static void pnx833x_enable_pic_irq(unsigned int irq)
189{ 169{
190 unsigned long flags; 170 unsigned long flags;
191 unsigned int pic_irq = irq - PNX833X_PIC_IRQ_BASE; 171 unsigned int pic_irq = d->irq - PNX833X_PIC_IRQ_BASE;
192 172
193 raw_spin_lock_irqsave(&pnx833x_irq_lock, flags); 173 raw_spin_lock_irqsave(&pnx833x_irq_lock, flags);
194 174 pnx833x_hard_enable_pic_irq(pic_irq);
195 irqflags[pic_irq] &= ~IRQFLAG_DISABLED;
196 if (irqflags[pic_irq] == IRQFLAG_STARTED)
197 pnx833x_hard_enable_pic_irq(pic_irq);
198
199 raw_spin_unlock_irqrestore(&pnx833x_irq_lock, flags); 175 raw_spin_unlock_irqrestore(&pnx833x_irq_lock, flags);
200} 176}
201 177
202static void pnx833x_disable_pic_irq(unsigned int irq) 178static void pnx833x_disable_pic_irq(struct irq_data *d)
203{ 179{
204 unsigned long flags; 180 unsigned long flags;
205 unsigned int pic_irq = irq - PNX833X_PIC_IRQ_BASE; 181 unsigned int pic_irq = d->irq - PNX833X_PIC_IRQ_BASE;
206 182
207 raw_spin_lock_irqsave(&pnx833x_irq_lock, flags); 183 raw_spin_lock_irqsave(&pnx833x_irq_lock, flags);
208
209 irqflags[pic_irq] |= IRQFLAG_DISABLED;
210 pnx833x_hard_disable_pic_irq(pic_irq); 184 pnx833x_hard_disable_pic_irq(pic_irq);
211
212 raw_spin_unlock_irqrestore(&pnx833x_irq_lock, flags); 185 raw_spin_unlock_irqrestore(&pnx833x_irq_lock, flags);
213} 186}
214 187
215static void pnx833x_ack_pic_irq(unsigned int irq)
216{
217}
218
219static void pnx833x_end_pic_irq(unsigned int irq)
220{
221}
222
223static DEFINE_RAW_SPINLOCK(pnx833x_gpio_pnx833x_irq_lock); 188static DEFINE_RAW_SPINLOCK(pnx833x_gpio_pnx833x_irq_lock);
224 189
225static unsigned int pnx833x_startup_gpio_irq(unsigned int irq) 190static void pnx833x_enable_gpio_irq(struct irq_data *d)
226{
227 int pin = irq - PNX833X_GPIO_IRQ_BASE;
228 unsigned long flags;
229 raw_spin_lock_irqsave(&pnx833x_gpio_pnx833x_irq_lock, flags);
230 pnx833x_gpio_enable_irq(pin);
231 raw_spin_unlock_irqrestore(&pnx833x_gpio_pnx833x_irq_lock, flags);
232 return 0;
233}
234
235static void pnx833x_enable_gpio_irq(unsigned int irq)
236{ 191{
237 int pin = irq - PNX833X_GPIO_IRQ_BASE; 192 int pin = d->irq - PNX833X_GPIO_IRQ_BASE;
238 unsigned long flags; 193 unsigned long flags;
239 raw_spin_lock_irqsave(&pnx833x_gpio_pnx833x_irq_lock, flags); 194 raw_spin_lock_irqsave(&pnx833x_gpio_pnx833x_irq_lock, flags);
240 pnx833x_gpio_enable_irq(pin); 195 pnx833x_gpio_enable_irq(pin);
241 raw_spin_unlock_irqrestore(&pnx833x_gpio_pnx833x_irq_lock, flags); 196 raw_spin_unlock_irqrestore(&pnx833x_gpio_pnx833x_irq_lock, flags);
242} 197}
243 198
244static void pnx833x_disable_gpio_irq(unsigned int irq) 199static void pnx833x_disable_gpio_irq(struct irq_data *d)
245{ 200{
246 int pin = irq - PNX833X_GPIO_IRQ_BASE; 201 int pin = d->irq - PNX833X_GPIO_IRQ_BASE;
247 unsigned long flags; 202 unsigned long flags;
248 raw_spin_lock_irqsave(&pnx833x_gpio_pnx833x_irq_lock, flags); 203 raw_spin_lock_irqsave(&pnx833x_gpio_pnx833x_irq_lock, flags);
249 pnx833x_gpio_disable_irq(pin); 204 pnx833x_gpio_disable_irq(pin);
250 raw_spin_unlock_irqrestore(&pnx833x_gpio_pnx833x_irq_lock, flags); 205 raw_spin_unlock_irqrestore(&pnx833x_gpio_pnx833x_irq_lock, flags);
251} 206}
252 207
253static void pnx833x_ack_gpio_irq(unsigned int irq) 208static int pnx833x_set_type_gpio_irq(struct irq_data *d, unsigned int flow_type)
254{
255}
256
257static void pnx833x_end_gpio_irq(unsigned int irq)
258{
259 int pin = irq - PNX833X_GPIO_IRQ_BASE;
260 unsigned long flags;
261 raw_spin_lock_irqsave(&pnx833x_gpio_pnx833x_irq_lock, flags);
262 pnx833x_gpio_clear_irq(pin);
263 raw_spin_unlock_irqrestore(&pnx833x_gpio_pnx833x_irq_lock, flags);
264}
265
266static int pnx833x_set_type_gpio_irq(unsigned int irq, unsigned int flow_type)
267{ 209{
268 int pin = irq - PNX833X_GPIO_IRQ_BASE; 210 int pin = d->irq - PNX833X_GPIO_IRQ_BASE;
269 int gpio_mode; 211 int gpio_mode;
270 212
271 switch (flow_type) { 213 switch (flow_type) {
@@ -296,23 +238,15 @@ static int pnx833x_set_type_gpio_irq(unsigned int irq, unsigned int flow_type)
296 238
297static struct irq_chip pnx833x_pic_irq_type = { 239static struct irq_chip pnx833x_pic_irq_type = {
298 .name = "PNX-PIC", 240 .name = "PNX-PIC",
299 .startup = pnx833x_startup_pic_irq, 241 .irq_enable = pnx833x_enable_pic_irq,
300 .shutdown = pnx833x_shutdown_pic_irq, 242 .irq_disable = pnx833x_disable_pic_irq,
301 .enable = pnx833x_enable_pic_irq,
302 .disable = pnx833x_disable_pic_irq,
303 .ack = pnx833x_ack_pic_irq,
304 .end = pnx833x_end_pic_irq
305}; 243};
306 244
307static struct irq_chip pnx833x_gpio_irq_type = { 245static struct irq_chip pnx833x_gpio_irq_type = {
308 .name = "PNX-GPIO", 246 .name = "PNX-GPIO",
309 .startup = pnx833x_startup_gpio_irq, 247 .irq_enable = pnx833x_enable_gpio_irq,
310 .shutdown = pnx833x_disable_gpio_irq, 248 .irq_disable = pnx833x_disable_gpio_irq,
311 .enable = pnx833x_enable_gpio_irq, 249 .irq_set_type = pnx833x_set_type_gpio_irq,
312 .disable = pnx833x_disable_gpio_irq,
313 .ack = pnx833x_ack_gpio_irq,
314 .end = pnx833x_end_gpio_irq,
315 .set_type = pnx833x_set_type_gpio_irq
316}; 250};
317 251
318void __init arch_init_irq(void) 252void __init arch_init_irq(void)
diff --git a/arch/mips/pnx8550/common/int.c b/arch/mips/pnx8550/common/int.c
index cfed5051dc6d..dbdc35c3531d 100644
--- a/arch/mips/pnx8550/common/int.c
+++ b/arch/mips/pnx8550/common/int.c
@@ -114,8 +114,10 @@ static inline void unmask_gic_int(unsigned int irq_nr)
114 PNX8550_GIC_REQ(irq_nr) = (1<<26 | 1<<16) | (1<<28) | gic_prio[irq_nr]; 114 PNX8550_GIC_REQ(irq_nr) = (1<<26 | 1<<16) | (1<<28) | gic_prio[irq_nr];
115} 115}
116 116
117static inline void mask_irq(unsigned int irq_nr) 117static inline void mask_irq(struct irq_data *d)
118{ 118{
119 unsigned int irq_nr = d->irq;
120
119 if ((PNX8550_INT_CP0_MIN <= irq_nr) && (irq_nr <= PNX8550_INT_CP0_MAX)) { 121 if ((PNX8550_INT_CP0_MIN <= irq_nr) && (irq_nr <= PNX8550_INT_CP0_MAX)) {
120 modify_cp0_intmask(1 << irq_nr, 0); 122 modify_cp0_intmask(1 << irq_nr, 0);
121 } else if ((PNX8550_INT_GIC_MIN <= irq_nr) && 123 } else if ((PNX8550_INT_GIC_MIN <= irq_nr) &&
@@ -129,8 +131,10 @@ static inline void mask_irq(unsigned int irq_nr)
129 } 131 }
130} 132}
131 133
132static inline void unmask_irq(unsigned int irq_nr) 134static inline void unmask_irq(struct irq_data *d)
133{ 135{
136 unsigned int irq_nr = d->irq;
137
134 if ((PNX8550_INT_CP0_MIN <= irq_nr) && (irq_nr <= PNX8550_INT_CP0_MAX)) { 138 if ((PNX8550_INT_CP0_MIN <= irq_nr) && (irq_nr <= PNX8550_INT_CP0_MAX)) {
135 modify_cp0_intmask(0, 1 << irq_nr); 139 modify_cp0_intmask(0, 1 << irq_nr);
136 } else if ((PNX8550_INT_GIC_MIN <= irq_nr) && 140 } else if ((PNX8550_INT_GIC_MIN <= irq_nr) &&
@@ -157,10 +161,8 @@ int pnx8550_set_gic_priority(int irq, int priority)
157 161
158static struct irq_chip level_irq_type = { 162static struct irq_chip level_irq_type = {
159 .name = "PNX Level IRQ", 163 .name = "PNX Level IRQ",
160 .ack = mask_irq, 164 .irq_mask = mask_irq,
161 .mask = mask_irq, 165 .irq_unmask = unmask_irq,
162 .mask_ack = mask_irq,
163 .unmask = unmask_irq,
164}; 166};
165 167
166static struct irqaction gic_action = { 168static struct irqaction gic_action = {
@@ -180,10 +182,8 @@ void __init arch_init_irq(void)
180 int i; 182 int i;
181 int configPR; 183 int configPR;
182 184
183 for (i = 0; i < PNX8550_INT_CP0_TOTINT; i++) { 185 for (i = 0; i < PNX8550_INT_CP0_TOTINT; i++)
184 set_irq_chip_and_handler(i, &level_irq_type, handle_level_irq); 186 set_irq_chip_and_handler(i, &level_irq_type, handle_level_irq);
185 mask_irq(i); /* mask the irq just in case */
186 }
187 187
188 /* init of GIC/IPC interrupts */ 188 /* init of GIC/IPC interrupts */
189 /* should be done before cp0 since cp0 init enables the GIC int */ 189 /* should be done before cp0 since cp0 init enables the GIC int */
diff --git a/arch/mips/powertv/asic/irq_asic.c b/arch/mips/powertv/asic/irq_asic.c
index e55382434155..6f1c8ef6a719 100644
--- a/arch/mips/powertv/asic/irq_asic.c
+++ b/arch/mips/powertv/asic/irq_asic.c
@@ -21,9 +21,10 @@
21 21
22#include <asm/mach-powertv/asic_regs.h> 22#include <asm/mach-powertv/asic_regs.h>
23 23
24static inline void unmask_asic_irq(unsigned int irq) 24static inline void unmask_asic_irq(struct irq_data *d)
25{ 25{
26 unsigned long enable_bit; 26 unsigned long enable_bit;
27 unsigned int irq = d->irq;
27 28
28 enable_bit = (1 << (irq & 0x1f)); 29 enable_bit = (1 << (irq & 0x1f));
29 30
@@ -45,9 +46,10 @@ static inline void unmask_asic_irq(unsigned int irq)
45 } 46 }
46} 47}
47 48
48static inline void mask_asic_irq(unsigned int irq) 49static inline void mask_asic_irq(struct irq_data *d)
49{ 50{
50 unsigned long disable_mask; 51 unsigned long disable_mask;
52 unsigned int irq = d->irq;
51 53
52 disable_mask = ~(1 << (irq & 0x1f)); 54 disable_mask = ~(1 << (irq & 0x1f));
53 55
@@ -71,11 +73,8 @@ static inline void mask_asic_irq(unsigned int irq)
71 73
72static struct irq_chip asic_irq_chip = { 74static struct irq_chip asic_irq_chip = {
73 .name = "ASIC Level", 75 .name = "ASIC Level",
74 .ack = mask_asic_irq, 76 .irq_mask = mask_asic_irq,
75 .mask = mask_asic_irq, 77 .irq_unmask = unmask_asic_irq,
76 .mask_ack = mask_asic_irq,
77 .unmask = unmask_asic_irq,
78 .eoi = unmask_asic_irq,
79}; 78};
80 79
81void __init asic_irq_init(void) 80void __init asic_irq_init(void)
diff --git a/arch/mips/rb532/irq.c b/arch/mips/rb532/irq.c
index ea6cec3c1e0d..b32a768da894 100644
--- a/arch/mips/rb532/irq.c
+++ b/arch/mips/rb532/irq.c
@@ -111,10 +111,10 @@ static inline void ack_local_irq(unsigned int ip)
111 clear_c0_cause(ipnum); 111 clear_c0_cause(ipnum);
112} 112}
113 113
114static void rb532_enable_irq(unsigned int irq_nr) 114static void rb532_enable_irq(struct irq_data *d)
115{ 115{
116 unsigned int group, intr_bit, irq_nr = d->irq;
116 int ip = irq_nr - GROUP0_IRQ_BASE; 117 int ip = irq_nr - GROUP0_IRQ_BASE;
117 unsigned int group, intr_bit;
118 volatile unsigned int *addr; 118 volatile unsigned int *addr;
119 119
120 if (ip < 0) 120 if (ip < 0)
@@ -132,10 +132,10 @@ static void rb532_enable_irq(unsigned int irq_nr)
132 } 132 }
133} 133}
134 134
135static void rb532_disable_irq(unsigned int irq_nr) 135static void rb532_disable_irq(struct irq_data *d)
136{ 136{
137 unsigned int group, intr_bit, mask, irq_nr = d->irq;
137 int ip = irq_nr - GROUP0_IRQ_BASE; 138 int ip = irq_nr - GROUP0_IRQ_BASE;
138 unsigned int group, intr_bit, mask;
139 volatile unsigned int *addr; 139 volatile unsigned int *addr;
140 140
141 if (ip < 0) { 141 if (ip < 0) {
@@ -163,18 +163,18 @@ static void rb532_disable_irq(unsigned int irq_nr)
163 } 163 }
164} 164}
165 165
166static void rb532_mask_and_ack_irq(unsigned int irq_nr) 166static void rb532_mask_and_ack_irq(struct irq_data *d)
167{ 167{
168 rb532_disable_irq(irq_nr); 168 rb532_disable_irq(d);
169 ack_local_irq(group_to_ip(irq_to_group(irq_nr))); 169 ack_local_irq(group_to_ip(irq_to_group(d->irq)));
170} 170}
171 171
172static int rb532_set_type(unsigned int irq_nr, unsigned type) 172static int rb532_set_type(struct irq_data *d, unsigned type)
173{ 173{
174 int gpio = irq_nr - GPIO_MAPPED_IRQ_BASE; 174 int gpio = d->irq - GPIO_MAPPED_IRQ_BASE;
175 int group = irq_to_group(irq_nr); 175 int group = irq_to_group(d->irq);
176 176
177 if (group != GPIO_MAPPED_IRQ_GROUP || irq_nr > (GROUP4_IRQ_BASE + 13)) 177 if (group != GPIO_MAPPED_IRQ_GROUP || d->irq > (GROUP4_IRQ_BASE + 13))
178 return (type == IRQ_TYPE_LEVEL_HIGH) ? 0 : -EINVAL; 178 return (type == IRQ_TYPE_LEVEL_HIGH) ? 0 : -EINVAL;
179 179
180 switch (type) { 180 switch (type) {
@@ -193,11 +193,11 @@ static int rb532_set_type(unsigned int irq_nr, unsigned type)
193 193
194static struct irq_chip rc32434_irq_type = { 194static struct irq_chip rc32434_irq_type = {
195 .name = "RB532", 195 .name = "RB532",
196 .ack = rb532_disable_irq, 196 .irq_ack = rb532_disable_irq,
197 .mask = rb532_disable_irq, 197 .irq_mask = rb532_disable_irq,
198 .mask_ack = rb532_mask_and_ack_irq, 198 .irq_mask_ack = rb532_mask_and_ack_irq,
199 .unmask = rb532_enable_irq, 199 .irq_unmask = rb532_enable_irq,
200 .set_type = rb532_set_type, 200 .irq_set_type = rb532_set_type,
201}; 201};
202 202
203void __init arch_init_irq(void) 203void __init arch_init_irq(void)
diff --git a/arch/mips/sgi-ip22/ip22-int.c b/arch/mips/sgi-ip22/ip22-int.c
index 383f11d7f442..e6e64750e90a 100644
--- a/arch/mips/sgi-ip22/ip22-int.c
+++ b/arch/mips/sgi-ip22/ip22-int.c
@@ -31,88 +31,80 @@ static char lc3msk_to_irqnr[256];
31 31
32extern int ip22_eisa_init(void); 32extern int ip22_eisa_init(void);
33 33
34static void enable_local0_irq(unsigned int irq) 34static void enable_local0_irq(struct irq_data *d)
35{ 35{
36 /* don't allow mappable interrupt to be enabled from setup_irq, 36 /* don't allow mappable interrupt to be enabled from setup_irq,
37 * we have our own way to do so */ 37 * we have our own way to do so */
38 if (irq != SGI_MAP_0_IRQ) 38 if (d->irq != SGI_MAP_0_IRQ)
39 sgint->imask0 |= (1 << (irq - SGINT_LOCAL0)); 39 sgint->imask0 |= (1 << (d->irq - SGINT_LOCAL0));
40} 40}
41 41
42static void disable_local0_irq(unsigned int irq) 42static void disable_local0_irq(struct irq_data *d)
43{ 43{
44 sgint->imask0 &= ~(1 << (irq - SGINT_LOCAL0)); 44 sgint->imask0 &= ~(1 << (d->irq - SGINT_LOCAL0));
45} 45}
46 46
47static struct irq_chip ip22_local0_irq_type = { 47static struct irq_chip ip22_local0_irq_type = {
48 .name = "IP22 local 0", 48 .name = "IP22 local 0",
49 .ack = disable_local0_irq, 49 .irq_mask = disable_local0_irq,
50 .mask = disable_local0_irq, 50 .irq_unmask = enable_local0_irq,
51 .mask_ack = disable_local0_irq,
52 .unmask = enable_local0_irq,
53}; 51};
54 52
55static void enable_local1_irq(unsigned int irq) 53static void enable_local1_irq(struct irq_data *d)
56{ 54{
57 /* don't allow mappable interrupt to be enabled from setup_irq, 55 /* don't allow mappable interrupt to be enabled from setup_irq,
58 * we have our own way to do so */ 56 * we have our own way to do so */
59 if (irq != SGI_MAP_1_IRQ) 57 if (d->irq != SGI_MAP_1_IRQ)
60 sgint->imask1 |= (1 << (irq - SGINT_LOCAL1)); 58 sgint->imask1 |= (1 << (d->irq - SGINT_LOCAL1));
61} 59}
62 60
63static void disable_local1_irq(unsigned int irq) 61static void disable_local1_irq(struct irq_data *d)
64{ 62{
65 sgint->imask1 &= ~(1 << (irq - SGINT_LOCAL1)); 63 sgint->imask1 &= ~(1 << (d->irq - SGINT_LOCAL1));
66} 64}
67 65
68static struct irq_chip ip22_local1_irq_type = { 66static struct irq_chip ip22_local1_irq_type = {
69 .name = "IP22 local 1", 67 .name = "IP22 local 1",
70 .ack = disable_local1_irq, 68 .irq_mask = disable_local1_irq,
71 .mask = disable_local1_irq, 69 .irq_unmask = enable_local1_irq,
72 .mask_ack = disable_local1_irq,
73 .unmask = enable_local1_irq,
74}; 70};
75 71
76static void enable_local2_irq(unsigned int irq) 72static void enable_local2_irq(struct irq_data *d)
77{ 73{
78 sgint->imask0 |= (1 << (SGI_MAP_0_IRQ - SGINT_LOCAL0)); 74 sgint->imask0 |= (1 << (SGI_MAP_0_IRQ - SGINT_LOCAL0));
79 sgint->cmeimask0 |= (1 << (irq - SGINT_LOCAL2)); 75 sgint->cmeimask0 |= (1 << (d->irq - SGINT_LOCAL2));
80} 76}
81 77
82static void disable_local2_irq(unsigned int irq) 78static void disable_local2_irq(struct irq_data *d)
83{ 79{
84 sgint->cmeimask0 &= ~(1 << (irq - SGINT_LOCAL2)); 80 sgint->cmeimask0 &= ~(1 << (d->irq - SGINT_LOCAL2));
85 if (!sgint->cmeimask0) 81 if (!sgint->cmeimask0)
86 sgint->imask0 &= ~(1 << (SGI_MAP_0_IRQ - SGINT_LOCAL0)); 82 sgint->imask0 &= ~(1 << (SGI_MAP_0_IRQ - SGINT_LOCAL0));
87} 83}
88 84
89static struct irq_chip ip22_local2_irq_type = { 85static struct irq_chip ip22_local2_irq_type = {
90 .name = "IP22 local 2", 86 .name = "IP22 local 2",
91 .ack = disable_local2_irq, 87 .irq_mask = disable_local2_irq,
92 .mask = disable_local2_irq, 88 .irq_unmask = enable_local2_irq,
93 .mask_ack = disable_local2_irq,
94 .unmask = enable_local2_irq,
95}; 89};
96 90
97static void enable_local3_irq(unsigned int irq) 91static void enable_local3_irq(struct irq_data *d)
98{ 92{
99 sgint->imask1 |= (1 << (SGI_MAP_1_IRQ - SGINT_LOCAL1)); 93 sgint->imask1 |= (1 << (SGI_MAP_1_IRQ - SGINT_LOCAL1));
100 sgint->cmeimask1 |= (1 << (irq - SGINT_LOCAL3)); 94 sgint->cmeimask1 |= (1 << (d->irq - SGINT_LOCAL3));
101} 95}
102 96
103static void disable_local3_irq(unsigned int irq) 97static void disable_local3_irq(struct irq_data *d)
104{ 98{
105 sgint->cmeimask1 &= ~(1 << (irq - SGINT_LOCAL3)); 99 sgint->cmeimask1 &= ~(1 << (d->irq - SGINT_LOCAL3));
106 if (!sgint->cmeimask1) 100 if (!sgint->cmeimask1)
107 sgint->imask1 &= ~(1 << (SGI_MAP_1_IRQ - SGINT_LOCAL1)); 101 sgint->imask1 &= ~(1 << (SGI_MAP_1_IRQ - SGINT_LOCAL1));
108} 102}
109 103
110static struct irq_chip ip22_local3_irq_type = { 104static struct irq_chip ip22_local3_irq_type = {
111 .name = "IP22 local 3", 105 .name = "IP22 local 3",
112 .ack = disable_local3_irq, 106 .irq_mask = disable_local3_irq,
113 .mask = disable_local3_irq, 107 .irq_unmask = enable_local3_irq,
114 .mask_ack = disable_local3_irq,
115 .unmask = enable_local3_irq,
116}; 108};
117 109
118static void indy_local0_irqdispatch(void) 110static void indy_local0_irqdispatch(void)
diff --git a/arch/mips/sgi-ip27/ip27-irq.c b/arch/mips/sgi-ip27/ip27-irq.c
index 6a123ea72de5..f2d09d7700dd 100644
--- a/arch/mips/sgi-ip27/ip27-irq.c
+++ b/arch/mips/sgi-ip27/ip27-irq.c
@@ -240,7 +240,7 @@ static int intr_disconnect_level(int cpu, int bit)
240} 240}
241 241
242/* Startup one of the (PCI ...) IRQs routes over a bridge. */ 242/* Startup one of the (PCI ...) IRQs routes over a bridge. */
243static unsigned int startup_bridge_irq(unsigned int irq) 243static unsigned int startup_bridge_irq(struct irq_data *d)
244{ 244{
245 struct bridge_controller *bc; 245 struct bridge_controller *bc;
246 bridgereg_t device; 246 bridgereg_t device;
@@ -248,16 +248,16 @@ static unsigned int startup_bridge_irq(unsigned int irq)
248 int pin, swlevel; 248 int pin, swlevel;
249 cpuid_t cpu; 249 cpuid_t cpu;
250 250
251 pin = SLOT_FROM_PCI_IRQ(irq); 251 pin = SLOT_FROM_PCI_IRQ(d->irq);
252 bc = IRQ_TO_BRIDGE(irq); 252 bc = IRQ_TO_BRIDGE(d->irq);
253 bridge = bc->base; 253 bridge = bc->base;
254 254
255 pr_debug("bridge_startup(): irq= 0x%x pin=%d\n", irq, pin); 255 pr_debug("bridge_startup(): irq= 0x%x pin=%d\n", d->irq, pin);
256 /* 256 /*
257 * "map" irq to a swlevel greater than 6 since the first 6 bits 257 * "map" irq to a swlevel greater than 6 since the first 6 bits
258 * of INT_PEND0 are taken 258 * of INT_PEND0 are taken
259 */ 259 */
260 swlevel = find_level(&cpu, irq); 260 swlevel = find_level(&cpu, d->irq);
261 bridge->b_int_addr[pin].addr = (0x20000 | swlevel | (bc->nasid << 8)); 261 bridge->b_int_addr[pin].addr = (0x20000 | swlevel | (bc->nasid << 8));
262 bridge->b_int_enable |= (1 << pin); 262 bridge->b_int_enable |= (1 << pin);
263 bridge->b_int_enable |= 0x7ffffe00; /* more stuff in int_enable */ 263 bridge->b_int_enable |= 0x7ffffe00; /* more stuff in int_enable */
@@ -288,53 +288,51 @@ static unsigned int startup_bridge_irq(unsigned int irq)
288} 288}
289 289
290/* Shutdown one of the (PCI ...) IRQs routes over a bridge. */ 290/* Shutdown one of the (PCI ...) IRQs routes over a bridge. */
291static void shutdown_bridge_irq(unsigned int irq) 291static void shutdown_bridge_irq(struct irq_data *d)
292{ 292{
293 struct bridge_controller *bc = IRQ_TO_BRIDGE(irq); 293 struct bridge_controller *bc = IRQ_TO_BRIDGE(d->irq);
294 bridge_t *bridge = bc->base; 294 bridge_t *bridge = bc->base;
295 int pin, swlevel; 295 int pin, swlevel;
296 cpuid_t cpu; 296 cpuid_t cpu;
297 297
298 pr_debug("bridge_shutdown: irq 0x%x\n", irq); 298 pr_debug("bridge_shutdown: irq 0x%x\n", d->irq);
299 pin = SLOT_FROM_PCI_IRQ(irq); 299 pin = SLOT_FROM_PCI_IRQ(d->irq);
300 300
301 /* 301 /*
302 * map irq to a swlevel greater than 6 since the first 6 bits 302 * map irq to a swlevel greater than 6 since the first 6 bits
303 * of INT_PEND0 are taken 303 * of INT_PEND0 are taken
304 */ 304 */
305 swlevel = find_level(&cpu, irq); 305 swlevel = find_level(&cpu, d->irq);
306 intr_disconnect_level(cpu, swlevel); 306 intr_disconnect_level(cpu, swlevel);
307 307
308 bridge->b_int_enable &= ~(1 << pin); 308 bridge->b_int_enable &= ~(1 << pin);
309 bridge->b_wid_tflush; 309 bridge->b_wid_tflush;
310} 310}
311 311
312static inline void enable_bridge_irq(unsigned int irq) 312static inline void enable_bridge_irq(struct irq_data *d)
313{ 313{
314 cpuid_t cpu; 314 cpuid_t cpu;
315 int swlevel; 315 int swlevel;
316 316
317 swlevel = find_level(&cpu, irq); /* Criminal offence */ 317 swlevel = find_level(&cpu, d->irq); /* Criminal offence */
318 intr_connect_level(cpu, swlevel); 318 intr_connect_level(cpu, swlevel);
319} 319}
320 320
321static inline void disable_bridge_irq(unsigned int irq) 321static inline void disable_bridge_irq(struct irq_data *d)
322{ 322{
323 cpuid_t cpu; 323 cpuid_t cpu;
324 int swlevel; 324 int swlevel;
325 325
326 swlevel = find_level(&cpu, irq); /* Criminal offence */ 326 swlevel = find_level(&cpu, d->irq); /* Criminal offence */
327 intr_disconnect_level(cpu, swlevel); 327 intr_disconnect_level(cpu, swlevel);
328} 328}
329 329
330static struct irq_chip bridge_irq_type = { 330static struct irq_chip bridge_irq_type = {
331 .name = "bridge", 331 .name = "bridge",
332 .startup = startup_bridge_irq, 332 .irq_startup = startup_bridge_irq,
333 .shutdown = shutdown_bridge_irq, 333 .irq_shutdown = shutdown_bridge_irq,
334 .ack = disable_bridge_irq, 334 .irq_mask = disable_bridge_irq,
335 .mask = disable_bridge_irq, 335 .irq_unmask = enable_bridge_irq,
336 .mask_ack = disable_bridge_irq,
337 .unmask = enable_bridge_irq,
338}; 336};
339 337
340void __devinit register_bridge_irq(unsigned int irq) 338void __devinit register_bridge_irq(unsigned int irq)
diff --git a/arch/mips/sgi-ip27/ip27-timer.c b/arch/mips/sgi-ip27/ip27-timer.c
index d6802d6d1f82..c01f558a2a09 100644
--- a/arch/mips/sgi-ip27/ip27-timer.c
+++ b/arch/mips/sgi-ip27/ip27-timer.c
@@ -36,21 +36,18 @@
36#include <asm/sn/sn0/hubio.h> 36#include <asm/sn/sn0/hubio.h>
37#include <asm/pci/bridge.h> 37#include <asm/pci/bridge.h>
38 38
39static void enable_rt_irq(unsigned int irq) 39static void enable_rt_irq(struct irq_data *d)
40{ 40{
41} 41}
42 42
43static void disable_rt_irq(unsigned int irq) 43static void disable_rt_irq(struct irq_data *d)
44{ 44{
45} 45}
46 46
47static struct irq_chip rt_irq_type = { 47static struct irq_chip rt_irq_type = {
48 .name = "SN HUB RT timer", 48 .name = "SN HUB RT timer",
49 .ack = disable_rt_irq, 49 .irq_mask = disable_rt_irq,
50 .mask = disable_rt_irq, 50 .irq_unmask = enable_rt_irq,
51 .mask_ack = disable_rt_irq,
52 .unmask = enable_rt_irq,
53 .eoi = enable_rt_irq,
54}; 51};
55 52
56static int rt_next_event(unsigned long delta, struct clock_event_device *evt) 53static int rt_next_event(unsigned long delta, struct clock_event_device *evt)
diff --git a/arch/mips/sgi-ip32/ip32-irq.c b/arch/mips/sgi-ip32/ip32-irq.c
index eb40824b172a..e0a3ce4a8d48 100644
--- a/arch/mips/sgi-ip32/ip32-irq.c
+++ b/arch/mips/sgi-ip32/ip32-irq.c
@@ -130,70 +130,48 @@ static struct irqaction cpuerr_irq = {
130 130
131static uint64_t crime_mask; 131static uint64_t crime_mask;
132 132
133static inline void crime_enable_irq(unsigned int irq) 133static inline void crime_enable_irq(struct irq_data *d)
134{ 134{
135 unsigned int bit = irq - CRIME_IRQ_BASE; 135 unsigned int bit = d->irq - CRIME_IRQ_BASE;
136 136
137 crime_mask |= 1 << bit; 137 crime_mask |= 1 << bit;
138 crime->imask = crime_mask; 138 crime->imask = crime_mask;
139} 139}
140 140
141static inline void crime_disable_irq(unsigned int irq) 141static inline void crime_disable_irq(struct irq_data *d)
142{ 142{
143 unsigned int bit = irq - CRIME_IRQ_BASE; 143 unsigned int bit = d->irq - CRIME_IRQ_BASE;
144 144
145 crime_mask &= ~(1 << bit); 145 crime_mask &= ~(1 << bit);
146 crime->imask = crime_mask; 146 crime->imask = crime_mask;
147 flush_crime_bus(); 147 flush_crime_bus();
148} 148}
149 149
150static void crime_level_mask_and_ack_irq(unsigned int irq)
151{
152 crime_disable_irq(irq);
153}
154
155static void crime_level_end_irq(unsigned int irq)
156{
157 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
158 crime_enable_irq(irq);
159}
160
161static struct irq_chip crime_level_interrupt = { 150static struct irq_chip crime_level_interrupt = {
162 .name = "IP32 CRIME", 151 .name = "IP32 CRIME",
163 .ack = crime_level_mask_and_ack_irq, 152 .irq_mask = crime_disable_irq,
164 .mask = crime_disable_irq, 153 .irq_unmask = crime_enable_irq,
165 .mask_ack = crime_level_mask_and_ack_irq,
166 .unmask = crime_enable_irq,
167 .end = crime_level_end_irq,
168}; 154};
169 155
170static void crime_edge_mask_and_ack_irq(unsigned int irq) 156static void crime_edge_mask_and_ack_irq(struct irq_data *d)
171{ 157{
172 unsigned int bit = irq - CRIME_IRQ_BASE; 158 unsigned int bit = d->irq - CRIME_IRQ_BASE;
173 uint64_t crime_int; 159 uint64_t crime_int;
174 160
175 /* Edge triggered interrupts must be cleared. */ 161 /* Edge triggered interrupts must be cleared. */
176
177 crime_int = crime->hard_int; 162 crime_int = crime->hard_int;
178 crime_int &= ~(1 << bit); 163 crime_int &= ~(1 << bit);
179 crime->hard_int = crime_int; 164 crime->hard_int = crime_int;
180 165
181 crime_disable_irq(irq); 166 crime_disable_irq(d);
182}
183
184static void crime_edge_end_irq(unsigned int irq)
185{
186 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
187 crime_enable_irq(irq);
188} 167}
189 168
190static struct irq_chip crime_edge_interrupt = { 169static struct irq_chip crime_edge_interrupt = {
191 .name = "IP32 CRIME", 170 .name = "IP32 CRIME",
192 .ack = crime_edge_mask_and_ack_irq, 171 .irq_ack = crime_edge_mask_and_ack_irq,
193 .mask = crime_disable_irq, 172 .irq_mask = crime_disable_irq,
194 .mask_ack = crime_edge_mask_and_ack_irq, 173 .irq_mask_ack = crime_edge_mask_and_ack_irq,
195 .unmask = crime_enable_irq, 174 .irq_unmask = crime_enable_irq,
196 .end = crime_edge_end_irq,
197}; 175};
198 176
199/* 177/*
@@ -204,37 +182,28 @@ static struct irq_chip crime_edge_interrupt = {
204 182
205static unsigned long macepci_mask; 183static unsigned long macepci_mask;
206 184
207static void enable_macepci_irq(unsigned int irq) 185static void enable_macepci_irq(struct irq_data *d)
208{ 186{
209 macepci_mask |= MACEPCI_CONTROL_INT(irq - MACEPCI_SCSI0_IRQ); 187 macepci_mask |= MACEPCI_CONTROL_INT(d->irq - MACEPCI_SCSI0_IRQ);
210 mace->pci.control = macepci_mask; 188 mace->pci.control = macepci_mask;
211 crime_mask |= 1 << (irq - CRIME_IRQ_BASE); 189 crime_mask |= 1 << (d->irq - CRIME_IRQ_BASE);
212 crime->imask = crime_mask; 190 crime->imask = crime_mask;
213} 191}
214 192
215static void disable_macepci_irq(unsigned int irq) 193static void disable_macepci_irq(struct irq_data *d)
216{ 194{
217 crime_mask &= ~(1 << (irq - CRIME_IRQ_BASE)); 195 crime_mask &= ~(1 << (d->irq - CRIME_IRQ_BASE));
218 crime->imask = crime_mask; 196 crime->imask = crime_mask;
219 flush_crime_bus(); 197 flush_crime_bus();
220 macepci_mask &= ~MACEPCI_CONTROL_INT(irq - MACEPCI_SCSI0_IRQ); 198 macepci_mask &= ~MACEPCI_CONTROL_INT(d->irq - MACEPCI_SCSI0_IRQ);
221 mace->pci.control = macepci_mask; 199 mace->pci.control = macepci_mask;
222 flush_mace_bus(); 200 flush_mace_bus();
223} 201}
224 202
225static void end_macepci_irq(unsigned int irq)
226{
227 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
228 enable_macepci_irq(irq);
229}
230
231static struct irq_chip ip32_macepci_interrupt = { 203static struct irq_chip ip32_macepci_interrupt = {
232 .name = "IP32 MACE PCI", 204 .name = "IP32 MACE PCI",
233 .ack = disable_macepci_irq, 205 .irq_mask = disable_macepci_irq,
234 .mask = disable_macepci_irq, 206 .irq_unmask = enable_macepci_irq,
235 .mask_ack = disable_macepci_irq,
236 .unmask = enable_macepci_irq,
237 .end = end_macepci_irq,
238}; 207};
239 208
240/* This is used for MACE ISA interrupts. That means bits 4-6 in the 209/* This is used for MACE ISA interrupts. That means bits 4-6 in the
@@ -276,13 +245,13 @@ static struct irq_chip ip32_macepci_interrupt = {
276 245
277static unsigned long maceisa_mask; 246static unsigned long maceisa_mask;
278 247
279static void enable_maceisa_irq(unsigned int irq) 248static void enable_maceisa_irq(struct irq_data *d)
280{ 249{
281 unsigned int crime_int = 0; 250 unsigned int crime_int = 0;
282 251
283 pr_debug("maceisa enable: %u\n", irq); 252 pr_debug("maceisa enable: %u\n", d->irq);
284 253
285 switch (irq) { 254 switch (d->irq) {
286 case MACEISA_AUDIO_SW_IRQ ... MACEISA_AUDIO3_MERR_IRQ: 255 case MACEISA_AUDIO_SW_IRQ ... MACEISA_AUDIO3_MERR_IRQ:
287 crime_int = MACE_AUDIO_INT; 256 crime_int = MACE_AUDIO_INT;
288 break; 257 break;
@@ -296,15 +265,15 @@ static void enable_maceisa_irq(unsigned int irq)
296 pr_debug("crime_int %08x enabled\n", crime_int); 265 pr_debug("crime_int %08x enabled\n", crime_int);
297 crime_mask |= crime_int; 266 crime_mask |= crime_int;
298 crime->imask = crime_mask; 267 crime->imask = crime_mask;
299 maceisa_mask |= 1 << (irq - MACEISA_AUDIO_SW_IRQ); 268 maceisa_mask |= 1 << (d->irq - MACEISA_AUDIO_SW_IRQ);
300 mace->perif.ctrl.imask = maceisa_mask; 269 mace->perif.ctrl.imask = maceisa_mask;
301} 270}
302 271
303static void disable_maceisa_irq(unsigned int irq) 272static void disable_maceisa_irq(struct irq_data *d)
304{ 273{
305 unsigned int crime_int = 0; 274 unsigned int crime_int = 0;
306 275
307 maceisa_mask &= ~(1 << (irq - MACEISA_AUDIO_SW_IRQ)); 276 maceisa_mask &= ~(1 << (d->irq - MACEISA_AUDIO_SW_IRQ));
308 if (!(maceisa_mask & MACEISA_AUDIO_INT)) 277 if (!(maceisa_mask & MACEISA_AUDIO_INT))
309 crime_int |= MACE_AUDIO_INT; 278 crime_int |= MACE_AUDIO_INT;
310 if (!(maceisa_mask & MACEISA_MISC_INT)) 279 if (!(maceisa_mask & MACEISA_MISC_INT))
@@ -318,76 +287,57 @@ static void disable_maceisa_irq(unsigned int irq)
318 flush_mace_bus(); 287 flush_mace_bus();
319} 288}
320 289
321static void mask_and_ack_maceisa_irq(unsigned int irq) 290static void mask_and_ack_maceisa_irq(struct irq_data *d)
322{ 291{
323 unsigned long mace_int; 292 unsigned long mace_int;
324 293
325 /* edge triggered */ 294 /* edge triggered */
326 mace_int = mace->perif.ctrl.istat; 295 mace_int = mace->perif.ctrl.istat;
327 mace_int &= ~(1 << (irq - MACEISA_AUDIO_SW_IRQ)); 296 mace_int &= ~(1 << (d->irq - MACEISA_AUDIO_SW_IRQ));
328 mace->perif.ctrl.istat = mace_int; 297 mace->perif.ctrl.istat = mace_int;
329 298
330 disable_maceisa_irq(irq); 299 disable_maceisa_irq(d);
331}
332
333static void end_maceisa_irq(unsigned irq)
334{
335 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
336 enable_maceisa_irq(irq);
337} 300}
338 301
339static struct irq_chip ip32_maceisa_level_interrupt = { 302static struct irq_chip ip32_maceisa_level_interrupt = {
340 .name = "IP32 MACE ISA", 303 .name = "IP32 MACE ISA",
341 .ack = disable_maceisa_irq, 304 .irq_mask = disable_maceisa_irq,
342 .mask = disable_maceisa_irq, 305 .irq_unmask = enable_maceisa_irq,
343 .mask_ack = disable_maceisa_irq,
344 .unmask = enable_maceisa_irq,
345 .end = end_maceisa_irq,
346}; 306};
347 307
348static struct irq_chip ip32_maceisa_edge_interrupt = { 308static struct irq_chip ip32_maceisa_edge_interrupt = {
349 .name = "IP32 MACE ISA", 309 .name = "IP32 MACE ISA",
350 .ack = mask_and_ack_maceisa_irq, 310 .irq_ack = mask_and_ack_maceisa_irq,
351 .mask = disable_maceisa_irq, 311 .irq_mask = disable_maceisa_irq,
352 .mask_ack = mask_and_ack_maceisa_irq, 312 .irq_mask_ack = mask_and_ack_maceisa_irq,
353 .unmask = enable_maceisa_irq, 313 .irq_unmask = enable_maceisa_irq,
354 .end = end_maceisa_irq,
355}; 314};
356 315
357/* This is used for regular non-ISA, non-PCI MACE interrupts. That means 316/* This is used for regular non-ISA, non-PCI MACE interrupts. That means
358 * bits 0-3 and 7 in the CRIME register. 317 * bits 0-3 and 7 in the CRIME register.
359 */ 318 */
360 319
361static void enable_mace_irq(unsigned int irq) 320static void enable_mace_irq(struct irq_data *d)
362{ 321{
363 unsigned int bit = irq - CRIME_IRQ_BASE; 322 unsigned int bit = d->irq - CRIME_IRQ_BASE;
364 323
365 crime_mask |= (1 << bit); 324 crime_mask |= (1 << bit);
366 crime->imask = crime_mask; 325 crime->imask = crime_mask;
367} 326}
368 327
369static void disable_mace_irq(unsigned int irq) 328static void disable_mace_irq(struct irq_data *d)
370{ 329{
371 unsigned int bit = irq - CRIME_IRQ_BASE; 330 unsigned int bit = d->irq - CRIME_IRQ_BASE;
372 331
373 crime_mask &= ~(1 << bit); 332 crime_mask &= ~(1 << bit);
374 crime->imask = crime_mask; 333 crime->imask = crime_mask;
375 flush_crime_bus(); 334 flush_crime_bus();
376} 335}
377 336
378static void end_mace_irq(unsigned int irq)
379{
380 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
381 enable_mace_irq(irq);
382}
383
384static struct irq_chip ip32_mace_interrupt = { 337static struct irq_chip ip32_mace_interrupt = {
385 .name = "IP32 MACE", 338 .name = "IP32 MACE",
386 .ack = disable_mace_irq, 339 .irq_mask = disable_mace_irq,
387 .mask = disable_mace_irq, 340 .irq_unmask = enable_mace_irq,
388 .mask_ack = disable_mace_irq,
389 .unmask = enable_mace_irq,
390 .end = end_mace_irq,
391}; 341};
392 342
393static void ip32_unknown_interrupt(void) 343static void ip32_unknown_interrupt(void)
diff --git a/arch/mips/sibyte/bcm1480/irq.c b/arch/mips/sibyte/bcm1480/irq.c
index 044bbe462c2c..89e8188a4665 100644
--- a/arch/mips/sibyte/bcm1480/irq.c
+++ b/arch/mips/sibyte/bcm1480/irq.c
@@ -44,31 +44,10 @@
44 * for interrupt lines 44 * for interrupt lines
45 */ 45 */
46 46
47
48static void end_bcm1480_irq(unsigned int irq);
49static void enable_bcm1480_irq(unsigned int irq);
50static void disable_bcm1480_irq(unsigned int irq);
51static void ack_bcm1480_irq(unsigned int irq);
52#ifdef CONFIG_SMP
53static int bcm1480_set_affinity(unsigned int irq, const struct cpumask *mask);
54#endif
55
56#ifdef CONFIG_PCI 47#ifdef CONFIG_PCI
57extern unsigned long ht_eoi_space; 48extern unsigned long ht_eoi_space;
58#endif 49#endif
59 50
60static struct irq_chip bcm1480_irq_type = {
61 .name = "BCM1480-IMR",
62 .ack = ack_bcm1480_irq,
63 .mask = disable_bcm1480_irq,
64 .mask_ack = ack_bcm1480_irq,
65 .unmask = enable_bcm1480_irq,
66 .end = end_bcm1480_irq,
67#ifdef CONFIG_SMP
68 .set_affinity = bcm1480_set_affinity
69#endif
70};
71
72/* Store the CPU id (not the logical number) */ 51/* Store the CPU id (not the logical number) */
73int bcm1480_irq_owner[BCM1480_NR_IRQS]; 52int bcm1480_irq_owner[BCM1480_NR_IRQS];
74 53
@@ -109,12 +88,13 @@ void bcm1480_unmask_irq(int cpu, int irq)
109} 88}
110 89
111#ifdef CONFIG_SMP 90#ifdef CONFIG_SMP
112static int bcm1480_set_affinity(unsigned int irq, const struct cpumask *mask) 91static int bcm1480_set_affinity(struct irq_data *d, const struct cpumask *mask,
92 bool force)
113{ 93{
94 unsigned int irq_dirty, irq = d->irq;
114 int i = 0, old_cpu, cpu, int_on, k; 95 int i = 0, old_cpu, cpu, int_on, k;
115 u64 cur_ints; 96 u64 cur_ints;
116 unsigned long flags; 97 unsigned long flags;
117 unsigned int irq_dirty;
118 98
119 i = cpumask_first(mask); 99 i = cpumask_first(mask);
120 100
@@ -156,21 +136,25 @@ static int bcm1480_set_affinity(unsigned int irq, const struct cpumask *mask)
156 136
157/*****************************************************************************/ 137/*****************************************************************************/
158 138
159static void disable_bcm1480_irq(unsigned int irq) 139static void disable_bcm1480_irq(struct irq_data *d)
160{ 140{
141 unsigned int irq = d->irq;
142
161 bcm1480_mask_irq(bcm1480_irq_owner[irq], irq); 143 bcm1480_mask_irq(bcm1480_irq_owner[irq], irq);
162} 144}
163 145
164static void enable_bcm1480_irq(unsigned int irq) 146static void enable_bcm1480_irq(struct irq_data *d)
165{ 147{
148 unsigned int irq = d->irq;
149
166 bcm1480_unmask_irq(bcm1480_irq_owner[irq], irq); 150 bcm1480_unmask_irq(bcm1480_irq_owner[irq], irq);
167} 151}
168 152
169 153
170static void ack_bcm1480_irq(unsigned int irq) 154static void ack_bcm1480_irq(struct irq_data *d)
171{ 155{
156 unsigned int irq_dirty, irq = d->irq;
172 u64 pending; 157 u64 pending;
173 unsigned int irq_dirty;
174 int k; 158 int k;
175 159
176 /* 160 /*
@@ -217,14 +201,15 @@ static void ack_bcm1480_irq(unsigned int irq)
217 bcm1480_mask_irq(bcm1480_irq_owner[irq], irq); 201 bcm1480_mask_irq(bcm1480_irq_owner[irq], irq);
218} 202}
219 203
220 204static struct irq_chip bcm1480_irq_type = {
221static void end_bcm1480_irq(unsigned int irq) 205 .name = "BCM1480-IMR",
222{ 206 .irq_mask_ack = ack_bcm1480_irq,
223 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) { 207 .irq_mask = disable_bcm1480_irq,
224 bcm1480_unmask_irq(bcm1480_irq_owner[irq], irq); 208 .irq_unmask = enable_bcm1480_irq,
225 } 209#ifdef CONFIG_SMP
226} 210 .irq_set_affinity = bcm1480_set_affinity
227 211#endif
212};
228 213
229void __init init_bcm1480_irqs(void) 214void __init init_bcm1480_irqs(void)
230{ 215{
diff --git a/arch/mips/sibyte/sb1250/irq.c b/arch/mips/sibyte/sb1250/irq.c
index 12ac04a658ee..fd269ea8d8a8 100644
--- a/arch/mips/sibyte/sb1250/irq.c
+++ b/arch/mips/sibyte/sb1250/irq.c
@@ -43,31 +43,10 @@
43 * for interrupt lines 43 * for interrupt lines
44 */ 44 */
45 45
46
47static void end_sb1250_irq(unsigned int irq);
48static void enable_sb1250_irq(unsigned int irq);
49static void disable_sb1250_irq(unsigned int irq);
50static void ack_sb1250_irq(unsigned int irq);
51#ifdef CONFIG_SMP
52static int sb1250_set_affinity(unsigned int irq, const struct cpumask *mask);
53#endif
54
55#ifdef CONFIG_SIBYTE_HAS_LDT 46#ifdef CONFIG_SIBYTE_HAS_LDT
56extern unsigned long ldt_eoi_space; 47extern unsigned long ldt_eoi_space;
57#endif 48#endif
58 49
59static struct irq_chip sb1250_irq_type = {
60 .name = "SB1250-IMR",
61 .ack = ack_sb1250_irq,
62 .mask = disable_sb1250_irq,
63 .mask_ack = ack_sb1250_irq,
64 .unmask = enable_sb1250_irq,
65 .end = end_sb1250_irq,
66#ifdef CONFIG_SMP
67 .set_affinity = sb1250_set_affinity
68#endif
69};
70
71/* Store the CPU id (not the logical number) */ 50/* Store the CPU id (not the logical number) */
72int sb1250_irq_owner[SB1250_NR_IRQS]; 51int sb1250_irq_owner[SB1250_NR_IRQS];
73 52
@@ -102,9 +81,11 @@ void sb1250_unmask_irq(int cpu, int irq)
102} 81}
103 82
104#ifdef CONFIG_SMP 83#ifdef CONFIG_SMP
105static int sb1250_set_affinity(unsigned int irq, const struct cpumask *mask) 84static int sb1250_set_affinity(struct irq_data *d, const struct cpumask *mask,
85 bool force)
106{ 86{
107 int i = 0, old_cpu, cpu, int_on; 87 int i = 0, old_cpu, cpu, int_on;
88 unsigned int irq = d->irq;
108 u64 cur_ints; 89 u64 cur_ints;
109 unsigned long flags; 90 unsigned long flags;
110 91
@@ -142,21 +123,17 @@ static int sb1250_set_affinity(unsigned int irq, const struct cpumask *mask)
142} 123}
143#endif 124#endif
144 125
145/*****************************************************************************/ 126static void enable_sb1250_irq(struct irq_data *d)
146
147static void disable_sb1250_irq(unsigned int irq)
148{ 127{
149 sb1250_mask_irq(sb1250_irq_owner[irq], irq); 128 unsigned int irq = d->irq;
150}
151 129
152static void enable_sb1250_irq(unsigned int irq)
153{
154 sb1250_unmask_irq(sb1250_irq_owner[irq], irq); 130 sb1250_unmask_irq(sb1250_irq_owner[irq], irq);
155} 131}
156 132
157 133
158static void ack_sb1250_irq(unsigned int irq) 134static void ack_sb1250_irq(struct irq_data *d)
159{ 135{
136 unsigned int irq = d->irq;
160#ifdef CONFIG_SIBYTE_HAS_LDT 137#ifdef CONFIG_SIBYTE_HAS_LDT
161 u64 pending; 138 u64 pending;
162 139
@@ -199,14 +176,14 @@ static void ack_sb1250_irq(unsigned int irq)
199 sb1250_mask_irq(sb1250_irq_owner[irq], irq); 176 sb1250_mask_irq(sb1250_irq_owner[irq], irq);
200} 177}
201 178
202 179static struct irq_chip sb1250_irq_type = {
203static void end_sb1250_irq(unsigned int irq) 180 .name = "SB1250-IMR",
204{ 181 .irq_mask_ack = ack_sb1250_irq,
205 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) { 182 .irq_unmask = enable_sb1250_irq,
206 sb1250_unmask_irq(sb1250_irq_owner[irq], irq); 183#ifdef CONFIG_SMP
207 } 184 .irq_set_affinity = sb1250_set_affinity
208} 185#endif
209 186};
210 187
211void __init init_sb1250_irqs(void) 188void __init init_sb1250_irqs(void)
212{ 189{
diff --git a/arch/mips/sni/a20r.c b/arch/mips/sni/a20r.c
index bbe7187879fa..72b94155778d 100644
--- a/arch/mips/sni/a20r.c
+++ b/arch/mips/sni/a20r.c
@@ -168,33 +168,22 @@ static u32 a20r_ack_hwint(void)
168 return status; 168 return status;
169} 169}
170 170
171static inline void unmask_a20r_irq(unsigned int irq) 171static inline void unmask_a20r_irq(struct irq_data *d)
172{ 172{
173 set_c0_status(0x100 << (irq - SNI_A20R_IRQ_BASE)); 173 set_c0_status(0x100 << (d->irq - SNI_A20R_IRQ_BASE));
174 irq_enable_hazard(); 174 irq_enable_hazard();
175} 175}
176 176
177static inline void mask_a20r_irq(unsigned int irq) 177static inline void mask_a20r_irq(struct irq_data *d)
178{ 178{
179 clear_c0_status(0x100 << (irq - SNI_A20R_IRQ_BASE)); 179 clear_c0_status(0x100 << (d->irq - SNI_A20R_IRQ_BASE));
180 irq_disable_hazard(); 180 irq_disable_hazard();
181} 181}
182 182
183static void end_a20r_irq(unsigned int irq)
184{
185 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
186 a20r_ack_hwint();
187 unmask_a20r_irq(irq);
188 }
189}
190
191static struct irq_chip a20r_irq_type = { 183static struct irq_chip a20r_irq_type = {
192 .name = "A20R", 184 .name = "A20R",
193 .ack = mask_a20r_irq, 185 .irq_mask = mask_a20r_irq,
194 .mask = mask_a20r_irq, 186 .irq_unmask = unmask_a20r_irq,
195 .mask_ack = mask_a20r_irq,
196 .unmask = unmask_a20r_irq,
197 .end = end_a20r_irq,
198}; 187};
199 188
200/* 189/*
diff --git a/arch/mips/sni/pcimt.c b/arch/mips/sni/pcimt.c
index 8c92c73bc717..cfcc68abc5b2 100644
--- a/arch/mips/sni/pcimt.c
+++ b/arch/mips/sni/pcimt.c
@@ -194,33 +194,24 @@ static struct pci_controller sni_controller = {
194 .io_map_base = SNI_PORT_BASE 194 .io_map_base = SNI_PORT_BASE
195}; 195};
196 196
197static void enable_pcimt_irq(unsigned int irq) 197static void enable_pcimt_irq(struct irq_data *d)
198{ 198{
199 unsigned int mask = 1 << (irq - PCIMT_IRQ_INT2); 199 unsigned int mask = 1 << (d->irq - PCIMT_IRQ_INT2);
200 200
201 *(volatile u8 *) PCIMT_IRQSEL |= mask; 201 *(volatile u8 *) PCIMT_IRQSEL |= mask;
202} 202}
203 203
204void disable_pcimt_irq(unsigned int irq) 204void disable_pcimt_irq(struct irq_data *d)
205{ 205{
206 unsigned int mask = ~(1 << (irq - PCIMT_IRQ_INT2)); 206 unsigned int mask = ~(1 << (d->irq - PCIMT_IRQ_INT2));
207 207
208 *(volatile u8 *) PCIMT_IRQSEL &= mask; 208 *(volatile u8 *) PCIMT_IRQSEL &= mask;
209} 209}
210 210
211static void end_pcimt_irq(unsigned int irq)
212{
213 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
214 enable_pcimt_irq(irq);
215}
216
217static struct irq_chip pcimt_irq_type = { 211static struct irq_chip pcimt_irq_type = {
218 .name = "PCIMT", 212 .name = "PCIMT",
219 .ack = disable_pcimt_irq, 213 .irq_mask = disable_pcimt_irq,
220 .mask = disable_pcimt_irq, 214 .irq_unmask = enable_pcimt_irq,
221 .mask_ack = disable_pcimt_irq,
222 .unmask = enable_pcimt_irq,
223 .end = end_pcimt_irq,
224}; 215};
225 216
226/* 217/*
diff --git a/arch/mips/sni/pcit.c b/arch/mips/sni/pcit.c
index dc9874553bec..0846e99a6efe 100644
--- a/arch/mips/sni/pcit.c
+++ b/arch/mips/sni/pcit.c
@@ -156,33 +156,24 @@ static struct pci_controller sni_pcit_controller = {
156 .io_map_base = SNI_PORT_BASE 156 .io_map_base = SNI_PORT_BASE
157}; 157};
158 158
159static void enable_pcit_irq(unsigned int irq) 159static void enable_pcit_irq(struct irq_data *d)
160{ 160{
161 u32 mask = 1 << (irq - SNI_PCIT_INT_START + 24); 161 u32 mask = 1 << (d->irq - SNI_PCIT_INT_START + 24);
162 162
163 *(volatile u32 *)SNI_PCIT_INT_REG |= mask; 163 *(volatile u32 *)SNI_PCIT_INT_REG |= mask;
164} 164}
165 165
166void disable_pcit_irq(unsigned int irq) 166void disable_pcit_irq(struct irq_data *d)
167{ 167{
168 u32 mask = 1 << (irq - SNI_PCIT_INT_START + 24); 168 u32 mask = 1 << (d->irq - SNI_PCIT_INT_START + 24);
169 169
170 *(volatile u32 *)SNI_PCIT_INT_REG &= ~mask; 170 *(volatile u32 *)SNI_PCIT_INT_REG &= ~mask;
171} 171}
172 172
173void end_pcit_irq(unsigned int irq)
174{
175 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
176 enable_pcit_irq(irq);
177}
178
179static struct irq_chip pcit_irq_type = { 173static struct irq_chip pcit_irq_type = {
180 .name = "PCIT", 174 .name = "PCIT",
181 .ack = disable_pcit_irq, 175 .irq_mask = disable_pcit_irq,
182 .mask = disable_pcit_irq, 176 .irq_unmask = enable_pcit_irq,
183 .mask_ack = disable_pcit_irq,
184 .unmask = enable_pcit_irq,
185 .end = end_pcit_irq,
186}; 177};
187 178
188static void pcit_hwint1(void) 179static void pcit_hwint1(void)
diff --git a/arch/mips/sni/rm200.c b/arch/mips/sni/rm200.c
index 0e6f42c2bbc8..f05d8e593300 100644
--- a/arch/mips/sni/rm200.c
+++ b/arch/mips/sni/rm200.c
@@ -155,12 +155,11 @@ static __iomem u8 *rm200_pic_slave;
155#define cached_master_mask (rm200_cached_irq_mask) 155#define cached_master_mask (rm200_cached_irq_mask)
156#define cached_slave_mask (rm200_cached_irq_mask >> 8) 156#define cached_slave_mask (rm200_cached_irq_mask >> 8)
157 157
158static void sni_rm200_disable_8259A_irq(unsigned int irq) 158static void sni_rm200_disable_8259A_irq(struct irq_data *d)
159{ 159{
160 unsigned int mask; 160 unsigned int mask, irq = d->irq - RM200_I8259A_IRQ_BASE;
161 unsigned long flags; 161 unsigned long flags;
162 162
163 irq -= RM200_I8259A_IRQ_BASE;
164 mask = 1 << irq; 163 mask = 1 << irq;
165 raw_spin_lock_irqsave(&sni_rm200_i8259A_lock, flags); 164 raw_spin_lock_irqsave(&sni_rm200_i8259A_lock, flags);
166 rm200_cached_irq_mask |= mask; 165 rm200_cached_irq_mask |= mask;
@@ -171,12 +170,11 @@ static void sni_rm200_disable_8259A_irq(unsigned int irq)
171 raw_spin_unlock_irqrestore(&sni_rm200_i8259A_lock, flags); 170 raw_spin_unlock_irqrestore(&sni_rm200_i8259A_lock, flags);
172} 171}
173 172
174static void sni_rm200_enable_8259A_irq(unsigned int irq) 173static void sni_rm200_enable_8259A_irq(struct irq_data *d)
175{ 174{
176 unsigned int mask; 175 unsigned int mask, irq = d->irq - RM200_I8259A_IRQ_BASE;
177 unsigned long flags; 176 unsigned long flags;
178 177
179 irq -= RM200_I8259A_IRQ_BASE;
180 mask = ~(1 << irq); 178 mask = ~(1 << irq);
181 raw_spin_lock_irqsave(&sni_rm200_i8259A_lock, flags); 179 raw_spin_lock_irqsave(&sni_rm200_i8259A_lock, flags);
182 rm200_cached_irq_mask &= mask; 180 rm200_cached_irq_mask &= mask;
@@ -210,12 +208,11 @@ static inline int sni_rm200_i8259A_irq_real(unsigned int irq)
210 * first, _then_ send the EOI, and the order of EOI 208 * first, _then_ send the EOI, and the order of EOI
211 * to the two 8259s is important! 209 * to the two 8259s is important!
212 */ 210 */
213void sni_rm200_mask_and_ack_8259A(unsigned int irq) 211void sni_rm200_mask_and_ack_8259A(struct irq_data *d)
214{ 212{
215 unsigned int irqmask; 213 unsigned int irqmask, irq = d->irq - RM200_I8259A_IRQ_BASE;
216 unsigned long flags; 214 unsigned long flags;
217 215
218 irq -= RM200_I8259A_IRQ_BASE;
219 irqmask = 1 << irq; 216 irqmask = 1 << irq;
220 raw_spin_lock_irqsave(&sni_rm200_i8259A_lock, flags); 217 raw_spin_lock_irqsave(&sni_rm200_i8259A_lock, flags);
221 /* 218 /*
@@ -285,9 +282,9 @@ spurious_8259A_irq:
285 282
286static struct irq_chip sni_rm200_i8259A_chip = { 283static struct irq_chip sni_rm200_i8259A_chip = {
287 .name = "RM200-XT-PIC", 284 .name = "RM200-XT-PIC",
288 .mask = sni_rm200_disable_8259A_irq, 285 .irq_mask = sni_rm200_disable_8259A_irq,
289 .unmask = sni_rm200_enable_8259A_irq, 286 .irq_unmask = sni_rm200_enable_8259A_irq,
290 .mask_ack = sni_rm200_mask_and_ack_8259A, 287 .irq_mask_ack = sni_rm200_mask_and_ack_8259A,
291}; 288};
292 289
293/* 290/*
@@ -429,33 +426,24 @@ void __init sni_rm200_i8259_irqs(void)
429#define SNI_RM200_INT_START 24 426#define SNI_RM200_INT_START 24
430#define SNI_RM200_INT_END 28 427#define SNI_RM200_INT_END 28
431 428
432static void enable_rm200_irq(unsigned int irq) 429static void enable_rm200_irq(struct irq_data *d)
433{ 430{
434 unsigned int mask = 1 << (irq - SNI_RM200_INT_START); 431 unsigned int mask = 1 << (d->irq - SNI_RM200_INT_START);
435 432
436 *(volatile u8 *)SNI_RM200_INT_ENA_REG &= ~mask; 433 *(volatile u8 *)SNI_RM200_INT_ENA_REG &= ~mask;
437} 434}
438 435
439void disable_rm200_irq(unsigned int irq) 436void disable_rm200_irq(struct irq_data *d)
440{ 437{
441 unsigned int mask = 1 << (irq - SNI_RM200_INT_START); 438 unsigned int mask = 1 << (d->irq - SNI_RM200_INT_START);
442 439
443 *(volatile u8 *)SNI_RM200_INT_ENA_REG |= mask; 440 *(volatile u8 *)SNI_RM200_INT_ENA_REG |= mask;
444} 441}
445 442
446void end_rm200_irq(unsigned int irq)
447{
448 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
449 enable_rm200_irq(irq);
450}
451
452static struct irq_chip rm200_irq_type = { 443static struct irq_chip rm200_irq_type = {
453 .name = "RM200", 444 .name = "RM200",
454 .ack = disable_rm200_irq, 445 .irq_mask = disable_rm200_irq,
455 .mask = disable_rm200_irq, 446 .irq_unmask = enable_rm200_irq,
456 .mask_ack = disable_rm200_irq,
457 .unmask = enable_rm200_irq,
458 .end = end_rm200_irq,
459}; 447};
460 448
461static void sni_rm200_hwint(void) 449static void sni_rm200_hwint(void)
diff --git a/arch/mips/txx9/generic/irq_tx4939.c b/arch/mips/txx9/generic/irq_tx4939.c
index 3886ad77cbad..93b6edbedd64 100644
--- a/arch/mips/txx9/generic/irq_tx4939.c
+++ b/arch/mips/txx9/generic/irq_tx4939.c
@@ -50,9 +50,9 @@ static struct {
50 unsigned char mode; 50 unsigned char mode;
51} tx4939irq[TX4939_NUM_IR] __read_mostly; 51} tx4939irq[TX4939_NUM_IR] __read_mostly;
52 52
53static void tx4939_irq_unmask(unsigned int irq) 53static void tx4939_irq_unmask(struct irq_data *d)
54{ 54{
55 unsigned int irq_nr = irq - TXX9_IRQ_BASE; 55 unsigned int irq_nr = d->irq - TXX9_IRQ_BASE;
56 u32 __iomem *lvlp; 56 u32 __iomem *lvlp;
57 int ofs; 57 int ofs;
58 if (irq_nr < 32) { 58 if (irq_nr < 32) {
@@ -68,9 +68,9 @@ static void tx4939_irq_unmask(unsigned int irq)
68 lvlp); 68 lvlp);
69} 69}
70 70
71static inline void tx4939_irq_mask(unsigned int irq) 71static inline void tx4939_irq_mask(struct irq_data *d)
72{ 72{
73 unsigned int irq_nr = irq - TXX9_IRQ_BASE; 73 unsigned int irq_nr = d->irq - TXX9_IRQ_BASE;
74 u32 __iomem *lvlp; 74 u32 __iomem *lvlp;
75 int ofs; 75 int ofs;
76 if (irq_nr < 32) { 76 if (irq_nr < 32) {
@@ -87,11 +87,11 @@ static inline void tx4939_irq_mask(unsigned int irq)
87 mmiowb(); 87 mmiowb();
88} 88}
89 89
90static void tx4939_irq_mask_ack(unsigned int irq) 90static void tx4939_irq_mask_ack(struct irq_data *d)
91{ 91{
92 unsigned int irq_nr = irq - TXX9_IRQ_BASE; 92 unsigned int irq_nr = d->irq - TXX9_IRQ_BASE;
93 93
94 tx4939_irq_mask(irq); 94 tx4939_irq_mask(d);
95 if (TXx9_IRCR_EDGE(tx4939irq[irq_nr].mode)) { 95 if (TXx9_IRCR_EDGE(tx4939irq[irq_nr].mode)) {
96 irq_nr--; 96 irq_nr--;
97 /* clear edge detection */ 97 /* clear edge detection */
@@ -101,9 +101,9 @@ static void tx4939_irq_mask_ack(unsigned int irq)
101 } 101 }
102} 102}
103 103
104static int tx4939_irq_set_type(unsigned int irq, unsigned int flow_type) 104static int tx4939_irq_set_type(struct irq_data *d, unsigned int flow_type)
105{ 105{
106 unsigned int irq_nr = irq - TXX9_IRQ_BASE; 106 unsigned int irq_nr = d->irq - TXX9_IRQ_BASE;
107 u32 cr; 107 u32 cr;
108 u32 __iomem *crp; 108 u32 __iomem *crp;
109 int ofs; 109 int ofs;
@@ -145,11 +145,11 @@ static int tx4939_irq_set_type(unsigned int irq, unsigned int flow_type)
145 145
146static struct irq_chip tx4939_irq_chip = { 146static struct irq_chip tx4939_irq_chip = {
147 .name = "TX4939", 147 .name = "TX4939",
148 .ack = tx4939_irq_mask_ack, 148 .irq_ack = tx4939_irq_mask_ack,
149 .mask = tx4939_irq_mask, 149 .irq_mask = tx4939_irq_mask,
150 .mask_ack = tx4939_irq_mask_ack, 150 .irq_mask_ack = tx4939_irq_mask_ack,
151 .unmask = tx4939_irq_unmask, 151 .irq_unmask = tx4939_irq_unmask,
152 .set_type = tx4939_irq_set_type, 152 .irq_set_type = tx4939_irq_set_type,
153}; 153};
154 154
155static int tx4939_irq_set_pri(int irc_irq, int new_pri) 155static int tx4939_irq_set_pri(int irc_irq, int new_pri)
diff --git a/arch/mips/txx9/jmr3927/irq.c b/arch/mips/txx9/jmr3927/irq.c
index 0a7f8e3b9fd7..92a5c1b400f0 100644
--- a/arch/mips/txx9/jmr3927/irq.c
+++ b/arch/mips/txx9/jmr3927/irq.c
@@ -47,20 +47,20 @@
47 * CP0_STATUS is a thread's resource (saved/restored on context switch). 47 * CP0_STATUS is a thread's resource (saved/restored on context switch).
48 * So disable_irq/enable_irq MUST handle IOC/IRC registers. 48 * So disable_irq/enable_irq MUST handle IOC/IRC registers.
49 */ 49 */
50static void mask_irq_ioc(unsigned int irq) 50static void mask_irq_ioc(struct irq_data *d)
51{ 51{
52 /* 0: mask */ 52 /* 0: mask */
53 unsigned int irq_nr = irq - JMR3927_IRQ_IOC; 53 unsigned int irq_nr = d->irq - JMR3927_IRQ_IOC;
54 unsigned char imask = jmr3927_ioc_reg_in(JMR3927_IOC_INTM_ADDR); 54 unsigned char imask = jmr3927_ioc_reg_in(JMR3927_IOC_INTM_ADDR);
55 unsigned int bit = 1 << irq_nr; 55 unsigned int bit = 1 << irq_nr;
56 jmr3927_ioc_reg_out(imask & ~bit, JMR3927_IOC_INTM_ADDR); 56 jmr3927_ioc_reg_out(imask & ~bit, JMR3927_IOC_INTM_ADDR);
57 /* flush write buffer */ 57 /* flush write buffer */
58 (void)jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR); 58 (void)jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR);
59} 59}
60static void unmask_irq_ioc(unsigned int irq) 60static void unmask_irq_ioc(struct irq_data *d)
61{ 61{
62 /* 0: mask */ 62 /* 0: mask */
63 unsigned int irq_nr = irq - JMR3927_IRQ_IOC; 63 unsigned int irq_nr = d->irq - JMR3927_IRQ_IOC;
64 unsigned char imask = jmr3927_ioc_reg_in(JMR3927_IOC_INTM_ADDR); 64 unsigned char imask = jmr3927_ioc_reg_in(JMR3927_IOC_INTM_ADDR);
65 unsigned int bit = 1 << irq_nr; 65 unsigned int bit = 1 << irq_nr;
66 jmr3927_ioc_reg_out(imask | bit, JMR3927_IOC_INTM_ADDR); 66 jmr3927_ioc_reg_out(imask | bit, JMR3927_IOC_INTM_ADDR);
@@ -95,10 +95,8 @@ static int jmr3927_irq_dispatch(int pending)
95 95
96static struct irq_chip jmr3927_irq_ioc = { 96static struct irq_chip jmr3927_irq_ioc = {
97 .name = "jmr3927_ioc", 97 .name = "jmr3927_ioc",
98 .ack = mask_irq_ioc, 98 .irq_mask = mask_irq_ioc,
99 .mask = mask_irq_ioc, 99 .irq_unmask = unmask_irq_ioc,
100 .mask_ack = mask_irq_ioc,
101 .unmask = unmask_irq_ioc,
102}; 100};
103 101
104void __init jmr3927_irq_setup(void) 102void __init jmr3927_irq_setup(void)
diff --git a/arch/mips/txx9/rbtx4927/irq.c b/arch/mips/txx9/rbtx4927/irq.c
index c4b54d20efd3..7c0a048b307c 100644
--- a/arch/mips/txx9/rbtx4927/irq.c
+++ b/arch/mips/txx9/rbtx4927/irq.c
@@ -117,18 +117,6 @@
117#include <asm/txx9/generic.h> 117#include <asm/txx9/generic.h>
118#include <asm/txx9/rbtx4927.h> 118#include <asm/txx9/rbtx4927.h>
119 119
120static void toshiba_rbtx4927_irq_ioc_enable(unsigned int irq);
121static void toshiba_rbtx4927_irq_ioc_disable(unsigned int irq);
122
123#define TOSHIBA_RBTX4927_IOC_NAME "RBTX4927-IOC"
124static struct irq_chip toshiba_rbtx4927_irq_ioc_type = {
125 .name = TOSHIBA_RBTX4927_IOC_NAME,
126 .ack = toshiba_rbtx4927_irq_ioc_disable,
127 .mask = toshiba_rbtx4927_irq_ioc_disable,
128 .mask_ack = toshiba_rbtx4927_irq_ioc_disable,
129 .unmask = toshiba_rbtx4927_irq_ioc_enable,
130};
131
132static int toshiba_rbtx4927_irq_nested(int sw_irq) 120static int toshiba_rbtx4927_irq_nested(int sw_irq)
133{ 121{
134 u8 level3; 122 u8 level3;
@@ -139,41 +127,47 @@ static int toshiba_rbtx4927_irq_nested(int sw_irq)
139 return RBTX4927_IRQ_IOC + __fls8(level3); 127 return RBTX4927_IRQ_IOC + __fls8(level3);
140} 128}
141 129
142static void __init toshiba_rbtx4927_irq_ioc_init(void) 130static void toshiba_rbtx4927_irq_ioc_enable(struct irq_data *d)
143{
144 int i;
145
146 /* mask all IOC interrupts */
147 writeb(0, rbtx4927_imask_addr);
148 /* clear SoftInt interrupts */
149 writeb(0, rbtx4927_softint_addr);
150
151 for (i = RBTX4927_IRQ_IOC;
152 i < RBTX4927_IRQ_IOC + RBTX4927_NR_IRQ_IOC; i++)
153 set_irq_chip_and_handler(i, &toshiba_rbtx4927_irq_ioc_type,
154 handle_level_irq);
155 set_irq_chained_handler(RBTX4927_IRQ_IOCINT, handle_simple_irq);
156}
157
158static void toshiba_rbtx4927_irq_ioc_enable(unsigned int irq)
159{ 131{
160 unsigned char v; 132 unsigned char v;
161 133
162 v = readb(rbtx4927_imask_addr); 134 v = readb(rbtx4927_imask_addr);
163 v |= (1 << (irq - RBTX4927_IRQ_IOC)); 135 v |= (1 << (d->irq - RBTX4927_IRQ_IOC));
164 writeb(v, rbtx4927_imask_addr); 136 writeb(v, rbtx4927_imask_addr);
165} 137}
166 138
167static void toshiba_rbtx4927_irq_ioc_disable(unsigned int irq) 139static void toshiba_rbtx4927_irq_ioc_disable(struct irq_data *d)
168{ 140{
169 unsigned char v; 141 unsigned char v;
170 142
171 v = readb(rbtx4927_imask_addr); 143 v = readb(rbtx4927_imask_addr);
172 v &= ~(1 << (irq - RBTX4927_IRQ_IOC)); 144 v &= ~(1 << (d->irq - RBTX4927_IRQ_IOC));
173 writeb(v, rbtx4927_imask_addr); 145 writeb(v, rbtx4927_imask_addr);
174 mmiowb(); 146 mmiowb();
175} 147}
176 148
149#define TOSHIBA_RBTX4927_IOC_NAME "RBTX4927-IOC"
150static struct irq_chip toshiba_rbtx4927_irq_ioc_type = {
151 .name = TOSHIBA_RBTX4927_IOC_NAME,
152 .irq_mask = toshiba_rbtx4927_irq_ioc_disable,
153 .irq_unmask = toshiba_rbtx4927_irq_ioc_enable,
154};
155
156static void __init toshiba_rbtx4927_irq_ioc_init(void)
157{
158 int i;
159
160 /* mask all IOC interrupts */
161 writeb(0, rbtx4927_imask_addr);
162 /* clear SoftInt interrupts */
163 writeb(0, rbtx4927_softint_addr);
164
165 for (i = RBTX4927_IRQ_IOC;
166 i < RBTX4927_IRQ_IOC + RBTX4927_NR_IRQ_IOC; i++)
167 set_irq_chip_and_handler(i, &toshiba_rbtx4927_irq_ioc_type,
168 handle_level_irq);
169 set_irq_chained_handler(RBTX4927_IRQ_IOCINT, handle_simple_irq);
170}
177 171
178static int rbtx4927_irq_dispatch(int pending) 172static int rbtx4927_irq_dispatch(int pending)
179{ 173{
diff --git a/arch/mips/txx9/rbtx4938/irq.c b/arch/mips/txx9/rbtx4938/irq.c
index 67a73a8065ec..2ec4fe1b1670 100644
--- a/arch/mips/txx9/rbtx4938/irq.c
+++ b/arch/mips/txx9/rbtx4938/irq.c
@@ -69,18 +69,6 @@
69#include <asm/txx9/generic.h> 69#include <asm/txx9/generic.h>
70#include <asm/txx9/rbtx4938.h> 70#include <asm/txx9/rbtx4938.h>
71 71
72static void toshiba_rbtx4938_irq_ioc_enable(unsigned int irq);
73static void toshiba_rbtx4938_irq_ioc_disable(unsigned int irq);
74
75#define TOSHIBA_RBTX4938_IOC_NAME "RBTX4938-IOC"
76static struct irq_chip toshiba_rbtx4938_irq_ioc_type = {
77 .name = TOSHIBA_RBTX4938_IOC_NAME,
78 .ack = toshiba_rbtx4938_irq_ioc_disable,
79 .mask = toshiba_rbtx4938_irq_ioc_disable,
80 .mask_ack = toshiba_rbtx4938_irq_ioc_disable,
81 .unmask = toshiba_rbtx4938_irq_ioc_enable,
82};
83
84static int toshiba_rbtx4938_irq_nested(int sw_irq) 72static int toshiba_rbtx4938_irq_nested(int sw_irq)
85{ 73{
86 u8 level3; 74 u8 level3;
@@ -92,41 +80,33 @@ static int toshiba_rbtx4938_irq_nested(int sw_irq)
92 return RBTX4938_IRQ_IOC + __fls8(level3); 80 return RBTX4938_IRQ_IOC + __fls8(level3);
93} 81}
94 82
95static void __init 83static void toshiba_rbtx4938_irq_ioc_enable(struct irq_data *d)
96toshiba_rbtx4938_irq_ioc_init(void)
97{
98 int i;
99
100 for (i = RBTX4938_IRQ_IOC;
101 i < RBTX4938_IRQ_IOC + RBTX4938_NR_IRQ_IOC; i++)
102 set_irq_chip_and_handler(i, &toshiba_rbtx4938_irq_ioc_type,
103 handle_level_irq);
104
105 set_irq_chained_handler(RBTX4938_IRQ_IOCINT, handle_simple_irq);
106}
107
108static void
109toshiba_rbtx4938_irq_ioc_enable(unsigned int irq)
110{ 84{
111 unsigned char v; 85 unsigned char v;
112 86
113 v = readb(rbtx4938_imask_addr); 87 v = readb(rbtx4938_imask_addr);
114 v |= (1 << (irq - RBTX4938_IRQ_IOC)); 88 v |= (1 << (d->irq - RBTX4938_IRQ_IOC));
115 writeb(v, rbtx4938_imask_addr); 89 writeb(v, rbtx4938_imask_addr);
116 mmiowb(); 90 mmiowb();
117} 91}
118 92
119static void 93static void toshiba_rbtx4938_irq_ioc_disable(struct irq_data *d)
120toshiba_rbtx4938_irq_ioc_disable(unsigned int irq)
121{ 94{
122 unsigned char v; 95 unsigned char v;
123 96
124 v = readb(rbtx4938_imask_addr); 97 v = readb(rbtx4938_imask_addr);
125 v &= ~(1 << (irq - RBTX4938_IRQ_IOC)); 98 v &= ~(1 << (d->irq - RBTX4938_IRQ_IOC));
126 writeb(v, rbtx4938_imask_addr); 99 writeb(v, rbtx4938_imask_addr);
127 mmiowb(); 100 mmiowb();
128} 101}
129 102
103#define TOSHIBA_RBTX4938_IOC_NAME "RBTX4938-IOC"
104static struct irq_chip toshiba_rbtx4938_irq_ioc_type = {
105 .name = TOSHIBA_RBTX4938_IOC_NAME,
106 .irq_mask = toshiba_rbtx4938_irq_ioc_disable,
107 .irq_unmask = toshiba_rbtx4938_irq_ioc_enable,
108};
109
130static int rbtx4938_irq_dispatch(int pending) 110static int rbtx4938_irq_dispatch(int pending)
131{ 111{
132 int irq; 112 int irq;
@@ -146,6 +126,18 @@ static int rbtx4938_irq_dispatch(int pending)
146 return irq; 126 return irq;
147} 127}
148 128
129static void __init toshiba_rbtx4938_irq_ioc_init(void)
130{
131 int i;
132
133 for (i = RBTX4938_IRQ_IOC;
134 i < RBTX4938_IRQ_IOC + RBTX4938_NR_IRQ_IOC; i++)
135 set_irq_chip_and_handler(i, &toshiba_rbtx4938_irq_ioc_type,
136 handle_level_irq);
137
138 set_irq_chained_handler(RBTX4938_IRQ_IOCINT, handle_simple_irq);
139}
140
149void __init rbtx4938_irq_setup(void) 141void __init rbtx4938_irq_setup(void)
150{ 142{
151 txx9_irq_dispatch = rbtx4938_irq_dispatch; 143 txx9_irq_dispatch = rbtx4938_irq_dispatch;
diff --git a/arch/mips/txx9/rbtx4939/irq.c b/arch/mips/txx9/rbtx4939/irq.c
index 57fa740a7205..70074632fb99 100644
--- a/arch/mips/txx9/rbtx4939/irq.c
+++ b/arch/mips/txx9/rbtx4939/irq.c
@@ -19,16 +19,16 @@
19 * RBTX4939 IOC controller definition 19 * RBTX4939 IOC controller definition
20 */ 20 */
21 21
22static void rbtx4939_ioc_irq_unmask(unsigned int irq) 22static void rbtx4939_ioc_irq_unmask(struct irq_data *d)
23{ 23{
24 int ioc_nr = irq - RBTX4939_IRQ_IOC; 24 int ioc_nr = d->irq - RBTX4939_IRQ_IOC;
25 25
26 writeb(readb(rbtx4939_ien_addr) | (1 << ioc_nr), rbtx4939_ien_addr); 26 writeb(readb(rbtx4939_ien_addr) | (1 << ioc_nr), rbtx4939_ien_addr);
27} 27}
28 28
29static void rbtx4939_ioc_irq_mask(unsigned int irq) 29static void rbtx4939_ioc_irq_mask(struct irq_data *d)
30{ 30{
31 int ioc_nr = irq - RBTX4939_IRQ_IOC; 31 int ioc_nr = d->irq - RBTX4939_IRQ_IOC;
32 32
33 writeb(readb(rbtx4939_ien_addr) & ~(1 << ioc_nr), rbtx4939_ien_addr); 33 writeb(readb(rbtx4939_ien_addr) & ~(1 << ioc_nr), rbtx4939_ien_addr);
34 mmiowb(); 34 mmiowb();
@@ -36,10 +36,8 @@ static void rbtx4939_ioc_irq_mask(unsigned int irq)
36 36
37static struct irq_chip rbtx4939_ioc_irq_chip = { 37static struct irq_chip rbtx4939_ioc_irq_chip = {
38 .name = "IOC", 38 .name = "IOC",
39 .ack = rbtx4939_ioc_irq_mask, 39 .irq_mask = rbtx4939_ioc_irq_mask,
40 .mask = rbtx4939_ioc_irq_mask, 40 .irq_unmask = rbtx4939_ioc_irq_unmask,
41 .mask_ack = rbtx4939_ioc_irq_mask,
42 .unmask = rbtx4939_ioc_irq_unmask,
43}; 41};
44 42
45 43
diff --git a/arch/mips/vr41xx/common/icu.c b/arch/mips/vr41xx/common/icu.c
index 6153b6a05ccf..f53156bb9aa8 100644
--- a/arch/mips/vr41xx/common/icu.c
+++ b/arch/mips/vr41xx/common/icu.c
@@ -154,7 +154,7 @@ static inline uint16_t icu2_clear(uint8_t offset, uint16_t clear)
154 154
155void vr41xx_enable_piuint(uint16_t mask) 155void vr41xx_enable_piuint(uint16_t mask)
156{ 156{
157 struct irq_desc *desc = irq_desc + PIU_IRQ; 157 struct irq_desc *desc = irq_to_desc(PIU_IRQ);
158 unsigned long flags; 158 unsigned long flags;
159 159
160 if (current_cpu_type() == CPU_VR4111 || 160 if (current_cpu_type() == CPU_VR4111 ||
@@ -169,7 +169,7 @@ EXPORT_SYMBOL(vr41xx_enable_piuint);
169 169
170void vr41xx_disable_piuint(uint16_t mask) 170void vr41xx_disable_piuint(uint16_t mask)
171{ 171{
172 struct irq_desc *desc = irq_desc + PIU_IRQ; 172 struct irq_desc *desc = irq_to_desc(PIU_IRQ);
173 unsigned long flags; 173 unsigned long flags;
174 174
175 if (current_cpu_type() == CPU_VR4111 || 175 if (current_cpu_type() == CPU_VR4111 ||
@@ -184,7 +184,7 @@ EXPORT_SYMBOL(vr41xx_disable_piuint);
184 184
185void vr41xx_enable_aiuint(uint16_t mask) 185void vr41xx_enable_aiuint(uint16_t mask)
186{ 186{
187 struct irq_desc *desc = irq_desc + AIU_IRQ; 187 struct irq_desc *desc = irq_to_desc(AIU_IRQ);
188 unsigned long flags; 188 unsigned long flags;
189 189
190 if (current_cpu_type() == CPU_VR4111 || 190 if (current_cpu_type() == CPU_VR4111 ||
@@ -199,7 +199,7 @@ EXPORT_SYMBOL(vr41xx_enable_aiuint);
199 199
200void vr41xx_disable_aiuint(uint16_t mask) 200void vr41xx_disable_aiuint(uint16_t mask)
201{ 201{
202 struct irq_desc *desc = irq_desc + AIU_IRQ; 202 struct irq_desc *desc = irq_to_desc(AIU_IRQ);
203 unsigned long flags; 203 unsigned long flags;
204 204
205 if (current_cpu_type() == CPU_VR4111 || 205 if (current_cpu_type() == CPU_VR4111 ||
@@ -214,7 +214,7 @@ EXPORT_SYMBOL(vr41xx_disable_aiuint);
214 214
215void vr41xx_enable_kiuint(uint16_t mask) 215void vr41xx_enable_kiuint(uint16_t mask)
216{ 216{
217 struct irq_desc *desc = irq_desc + KIU_IRQ; 217 struct irq_desc *desc = irq_to_desc(KIU_IRQ);
218 unsigned long flags; 218 unsigned long flags;
219 219
220 if (current_cpu_type() == CPU_VR4111 || 220 if (current_cpu_type() == CPU_VR4111 ||
@@ -229,7 +229,7 @@ EXPORT_SYMBOL(vr41xx_enable_kiuint);
229 229
230void vr41xx_disable_kiuint(uint16_t mask) 230void vr41xx_disable_kiuint(uint16_t mask)
231{ 231{
232 struct irq_desc *desc = irq_desc + KIU_IRQ; 232 struct irq_desc *desc = irq_to_desc(KIU_IRQ);
233 unsigned long flags; 233 unsigned long flags;
234 234
235 if (current_cpu_type() == CPU_VR4111 || 235 if (current_cpu_type() == CPU_VR4111 ||
@@ -244,7 +244,7 @@ EXPORT_SYMBOL(vr41xx_disable_kiuint);
244 244
245void vr41xx_enable_macint(uint16_t mask) 245void vr41xx_enable_macint(uint16_t mask)
246{ 246{
247 struct irq_desc *desc = irq_desc + ETHERNET_IRQ; 247 struct irq_desc *desc = irq_to_desc(ETHERNET_IRQ);
248 unsigned long flags; 248 unsigned long flags;
249 249
250 raw_spin_lock_irqsave(&desc->lock, flags); 250 raw_spin_lock_irqsave(&desc->lock, flags);
@@ -256,7 +256,7 @@ EXPORT_SYMBOL(vr41xx_enable_macint);
256 256
257void vr41xx_disable_macint(uint16_t mask) 257void vr41xx_disable_macint(uint16_t mask)
258{ 258{
259 struct irq_desc *desc = irq_desc + ETHERNET_IRQ; 259 struct irq_desc *desc = irq_to_desc(ETHERNET_IRQ);
260 unsigned long flags; 260 unsigned long flags;
261 261
262 raw_spin_lock_irqsave(&desc->lock, flags); 262 raw_spin_lock_irqsave(&desc->lock, flags);
@@ -268,7 +268,7 @@ EXPORT_SYMBOL(vr41xx_disable_macint);
268 268
269void vr41xx_enable_dsiuint(uint16_t mask) 269void vr41xx_enable_dsiuint(uint16_t mask)
270{ 270{
271 struct irq_desc *desc = irq_desc + DSIU_IRQ; 271 struct irq_desc *desc = irq_to_desc(DSIU_IRQ);
272 unsigned long flags; 272 unsigned long flags;
273 273
274 raw_spin_lock_irqsave(&desc->lock, flags); 274 raw_spin_lock_irqsave(&desc->lock, flags);
@@ -280,7 +280,7 @@ EXPORT_SYMBOL(vr41xx_enable_dsiuint);
280 280
281void vr41xx_disable_dsiuint(uint16_t mask) 281void vr41xx_disable_dsiuint(uint16_t mask)
282{ 282{
283 struct irq_desc *desc = irq_desc + DSIU_IRQ; 283 struct irq_desc *desc = irq_to_desc(DSIU_IRQ);
284 unsigned long flags; 284 unsigned long flags;
285 285
286 raw_spin_lock_irqsave(&desc->lock, flags); 286 raw_spin_lock_irqsave(&desc->lock, flags);
@@ -292,7 +292,7 @@ EXPORT_SYMBOL(vr41xx_disable_dsiuint);
292 292
293void vr41xx_enable_firint(uint16_t mask) 293void vr41xx_enable_firint(uint16_t mask)
294{ 294{
295 struct irq_desc *desc = irq_desc + FIR_IRQ; 295 struct irq_desc *desc = irq_to_desc(FIR_IRQ);
296 unsigned long flags; 296 unsigned long flags;
297 297
298 raw_spin_lock_irqsave(&desc->lock, flags); 298 raw_spin_lock_irqsave(&desc->lock, flags);
@@ -304,7 +304,7 @@ EXPORT_SYMBOL(vr41xx_enable_firint);
304 304
305void vr41xx_disable_firint(uint16_t mask) 305void vr41xx_disable_firint(uint16_t mask)
306{ 306{
307 struct irq_desc *desc = irq_desc + FIR_IRQ; 307 struct irq_desc *desc = irq_to_desc(FIR_IRQ);
308 unsigned long flags; 308 unsigned long flags;
309 309
310 raw_spin_lock_irqsave(&desc->lock, flags); 310 raw_spin_lock_irqsave(&desc->lock, flags);
@@ -316,7 +316,7 @@ EXPORT_SYMBOL(vr41xx_disable_firint);
316 316
317void vr41xx_enable_pciint(void) 317void vr41xx_enable_pciint(void)
318{ 318{
319 struct irq_desc *desc = irq_desc + PCI_IRQ; 319 struct irq_desc *desc = irq_to_desc(PCI_IRQ);
320 unsigned long flags; 320 unsigned long flags;
321 321
322 if (current_cpu_type() == CPU_VR4122 || 322 if (current_cpu_type() == CPU_VR4122 ||
@@ -332,7 +332,7 @@ EXPORT_SYMBOL(vr41xx_enable_pciint);
332 332
333void vr41xx_disable_pciint(void) 333void vr41xx_disable_pciint(void)
334{ 334{
335 struct irq_desc *desc = irq_desc + PCI_IRQ; 335 struct irq_desc *desc = irq_to_desc(PCI_IRQ);
336 unsigned long flags; 336 unsigned long flags;
337 337
338 if (current_cpu_type() == CPU_VR4122 || 338 if (current_cpu_type() == CPU_VR4122 ||
@@ -348,7 +348,7 @@ EXPORT_SYMBOL(vr41xx_disable_pciint);
348 348
349void vr41xx_enable_scuint(void) 349void vr41xx_enable_scuint(void)
350{ 350{
351 struct irq_desc *desc = irq_desc + SCU_IRQ; 351 struct irq_desc *desc = irq_to_desc(SCU_IRQ);
352 unsigned long flags; 352 unsigned long flags;
353 353
354 if (current_cpu_type() == CPU_VR4122 || 354 if (current_cpu_type() == CPU_VR4122 ||
@@ -364,7 +364,7 @@ EXPORT_SYMBOL(vr41xx_enable_scuint);
364 364
365void vr41xx_disable_scuint(void) 365void vr41xx_disable_scuint(void)
366{ 366{
367 struct irq_desc *desc = irq_desc + SCU_IRQ; 367 struct irq_desc *desc = irq_to_desc(SCU_IRQ);
368 unsigned long flags; 368 unsigned long flags;
369 369
370 if (current_cpu_type() == CPU_VR4122 || 370 if (current_cpu_type() == CPU_VR4122 ||
@@ -380,7 +380,7 @@ EXPORT_SYMBOL(vr41xx_disable_scuint);
380 380
381void vr41xx_enable_csiint(uint16_t mask) 381void vr41xx_enable_csiint(uint16_t mask)
382{ 382{
383 struct irq_desc *desc = irq_desc + CSI_IRQ; 383 struct irq_desc *desc = irq_to_desc(CSI_IRQ);
384 unsigned long flags; 384 unsigned long flags;
385 385
386 if (current_cpu_type() == CPU_VR4122 || 386 if (current_cpu_type() == CPU_VR4122 ||
@@ -396,7 +396,7 @@ EXPORT_SYMBOL(vr41xx_enable_csiint);
396 396
397void vr41xx_disable_csiint(uint16_t mask) 397void vr41xx_disable_csiint(uint16_t mask)
398{ 398{
399 struct irq_desc *desc = irq_desc + CSI_IRQ; 399 struct irq_desc *desc = irq_to_desc(CSI_IRQ);
400 unsigned long flags; 400 unsigned long flags;
401 401
402 if (current_cpu_type() == CPU_VR4122 || 402 if (current_cpu_type() == CPU_VR4122 ||
@@ -412,7 +412,7 @@ EXPORT_SYMBOL(vr41xx_disable_csiint);
412 412
413void vr41xx_enable_bcuint(void) 413void vr41xx_enable_bcuint(void)
414{ 414{
415 struct irq_desc *desc = irq_desc + BCU_IRQ; 415 struct irq_desc *desc = irq_to_desc(BCU_IRQ);
416 unsigned long flags; 416 unsigned long flags;
417 417
418 if (current_cpu_type() == CPU_VR4122 || 418 if (current_cpu_type() == CPU_VR4122 ||
@@ -428,7 +428,7 @@ EXPORT_SYMBOL(vr41xx_enable_bcuint);
428 428
429void vr41xx_disable_bcuint(void) 429void vr41xx_disable_bcuint(void)
430{ 430{
431 struct irq_desc *desc = irq_desc + BCU_IRQ; 431 struct irq_desc *desc = irq_to_desc(BCU_IRQ);
432 unsigned long flags; 432 unsigned long flags;
433 433
434 if (current_cpu_type() == CPU_VR4122 || 434 if (current_cpu_type() == CPU_VR4122 ||
@@ -442,45 +442,41 @@ void vr41xx_disable_bcuint(void)
442 442
443EXPORT_SYMBOL(vr41xx_disable_bcuint); 443EXPORT_SYMBOL(vr41xx_disable_bcuint);
444 444
445static void disable_sysint1_irq(unsigned int irq) 445static void disable_sysint1_irq(struct irq_data *d)
446{ 446{
447 icu1_clear(MSYSINT1REG, 1 << SYSINT1_IRQ_TO_PIN(irq)); 447 icu1_clear(MSYSINT1REG, 1 << SYSINT1_IRQ_TO_PIN(d->irq));
448} 448}
449 449
450static void enable_sysint1_irq(unsigned int irq) 450static void enable_sysint1_irq(struct irq_data *d)
451{ 451{
452 icu1_set(MSYSINT1REG, 1 << SYSINT1_IRQ_TO_PIN(irq)); 452 icu1_set(MSYSINT1REG, 1 << SYSINT1_IRQ_TO_PIN(d->irq));
453} 453}
454 454
455static struct irq_chip sysint1_irq_type = { 455static struct irq_chip sysint1_irq_type = {
456 .name = "SYSINT1", 456 .name = "SYSINT1",
457 .ack = disable_sysint1_irq, 457 .irq_mask = disable_sysint1_irq,
458 .mask = disable_sysint1_irq, 458 .irq_unmask = enable_sysint1_irq,
459 .mask_ack = disable_sysint1_irq,
460 .unmask = enable_sysint1_irq,
461}; 459};
462 460
463static void disable_sysint2_irq(unsigned int irq) 461static void disable_sysint2_irq(struct irq_data *d)
464{ 462{
465 icu2_clear(MSYSINT2REG, 1 << SYSINT2_IRQ_TO_PIN(irq)); 463 icu2_clear(MSYSINT2REG, 1 << SYSINT2_IRQ_TO_PIN(d->irq));
466} 464}
467 465
468static void enable_sysint2_irq(unsigned int irq) 466static void enable_sysint2_irq(struct irq_data *d)
469{ 467{
470 icu2_set(MSYSINT2REG, 1 << SYSINT2_IRQ_TO_PIN(irq)); 468 icu2_set(MSYSINT2REG, 1 << SYSINT2_IRQ_TO_PIN(d->irq));
471} 469}
472 470
473static struct irq_chip sysint2_irq_type = { 471static struct irq_chip sysint2_irq_type = {
474 .name = "SYSINT2", 472 .name = "SYSINT2",
475 .ack = disable_sysint2_irq, 473 .irq_mask = disable_sysint2_irq,
476 .mask = disable_sysint2_irq, 474 .irq_unmask = enable_sysint2_irq,
477 .mask_ack = disable_sysint2_irq,
478 .unmask = enable_sysint2_irq,
479}; 475};
480 476
481static inline int set_sysint1_assign(unsigned int irq, unsigned char assign) 477static inline int set_sysint1_assign(unsigned int irq, unsigned char assign)
482{ 478{
483 struct irq_desc *desc = irq_desc + irq; 479 struct irq_desc *desc = irq_to_desc(irq);
484 uint16_t intassign0, intassign1; 480 uint16_t intassign0, intassign1;
485 unsigned int pin; 481 unsigned int pin;
486 482
@@ -540,7 +536,7 @@ static inline int set_sysint1_assign(unsigned int irq, unsigned char assign)
540 536
541static inline int set_sysint2_assign(unsigned int irq, unsigned char assign) 537static inline int set_sysint2_assign(unsigned int irq, unsigned char assign)
542{ 538{
543 struct irq_desc *desc = irq_desc + irq; 539 struct irq_desc *desc = irq_to_desc(irq);
544 uint16_t intassign2, intassign3; 540 uint16_t intassign2, intassign3;
545 unsigned int pin; 541 unsigned int pin;
546 542
diff --git a/arch/mips/vr41xx/common/irq.c b/arch/mips/vr41xx/common/irq.c
index 0975eb72d385..9ff7f397c0e1 100644
--- a/arch/mips/vr41xx/common/irq.c
+++ b/arch/mips/vr41xx/common/irq.c
@@ -62,7 +62,6 @@ EXPORT_SYMBOL_GPL(cascade_irq);
62static void irq_dispatch(unsigned int irq) 62static void irq_dispatch(unsigned int irq)
63{ 63{
64 irq_cascade_t *cascade; 64 irq_cascade_t *cascade;
65 struct irq_desc *desc;
66 65
67 if (irq >= NR_IRQS) { 66 if (irq >= NR_IRQS) {
68 atomic_inc(&irq_err_count); 67 atomic_inc(&irq_err_count);
@@ -71,14 +70,16 @@ static void irq_dispatch(unsigned int irq)
71 70
72 cascade = irq_cascade + irq; 71 cascade = irq_cascade + irq;
73 if (cascade->get_irq != NULL) { 72 if (cascade->get_irq != NULL) {
74 unsigned int source_irq = irq; 73 struct irq_desc *desc = irq_to_desc(irq);
74 struct irq_data *idata = irq_desc_get_irq_data(desc);
75 struct irq_chip *chip = irq_desc_get_chip(desc);
75 int ret; 76 int ret;
76 desc = irq_desc + source_irq; 77
77 if (desc->chip->mask_ack) 78 if (chip->irq_mask_ack)
78 desc->chip->mask_ack(source_irq); 79 chip->irq_mask_ack(idata);
79 else { 80 else {
80 desc->chip->mask(source_irq); 81 chip->irq_mask(idata);
81 desc->chip->ack(source_irq); 82 chip->irq_ack(idata);
82 } 83 }
83 ret = cascade->get_irq(irq); 84 ret = cascade->get_irq(irq);
84 irq = ret; 85 irq = ret;
@@ -86,8 +87,8 @@ static void irq_dispatch(unsigned int irq)
86 atomic_inc(&irq_err_count); 87 atomic_inc(&irq_err_count);
87 else 88 else
88 irq_dispatch(irq); 89 irq_dispatch(irq);
89 if (!(desc->status & IRQ_DISABLED) && desc->chip->unmask) 90 if (!(desc->status & IRQ_DISABLED) && chip->irq_unmask)
90 desc->chip->unmask(source_irq); 91 chip->irq_unmask(idata);
91 } else 92 } else
92 do_IRQ(irq); 93 do_IRQ(irq);
93} 94}
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-30 17:29:41 -0500