diff options
author | Thomas Gleixner <tglx@linutronix.de> | 2011-03-23 17:08:47 -0400 |
---|---|---|
committer | Ralf Baechle <ralf@linux-mips.org> | 2011-03-25 13:45:15 -0400 |
commit | 93f293610446f10fd13de9f18b4d0300f0d89279 (patch) | |
tree | 99d00f9a46fecfc94b8b6b8ad8e688620e307046 /arch/mips | |
parent | 3fb8818bd2ed2030f00678da090adff36739bf20 (diff) |
MIPS: bcm63xx: Convert to new irq_chip functions
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
To: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/2176/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips')
-rw-r--r-- | arch/mips/bcm63xx/irq.c | 77 |
1 files changed, 32 insertions, 45 deletions
diff --git a/arch/mips/bcm63xx/irq.c b/arch/mips/bcm63xx/irq.c index 3be87f2422f0..1691531aa34d 100644 --- a/arch/mips/bcm63xx/irq.c +++ b/arch/mips/bcm63xx/irq.c | |||
@@ -76,88 +76,80 @@ asmlinkage void plat_irq_dispatch(void) | |||
76 | * internal IRQs operations: only mask/unmask on PERF irq mask | 76 | * internal IRQs operations: only mask/unmask on PERF irq mask |
77 | * register. | 77 | * register. |
78 | */ | 78 | */ |
79 | static inline void bcm63xx_internal_irq_mask(unsigned int irq) | 79 | static inline void bcm63xx_internal_irq_mask(struct irq_data *d) |
80 | { | 80 | { |
81 | unsigned int irq = d->irq - IRQ_INTERNAL_BASE; | ||
81 | u32 mask; | 82 | u32 mask; |
82 | 83 | ||
83 | irq -= IRQ_INTERNAL_BASE; | ||
84 | mask = bcm_perf_readl(PERF_IRQMASK_REG); | 84 | mask = bcm_perf_readl(PERF_IRQMASK_REG); |
85 | mask &= ~(1 << irq); | 85 | mask &= ~(1 << irq); |
86 | bcm_perf_writel(mask, PERF_IRQMASK_REG); | 86 | bcm_perf_writel(mask, PERF_IRQMASK_REG); |
87 | } | 87 | } |
88 | 88 | ||
89 | static void bcm63xx_internal_irq_unmask(unsigned int irq) | 89 | static void bcm63xx_internal_irq_unmask(struct irq_data *d) |
90 | { | 90 | { |
91 | unsigned int irq = d->irq - IRQ_INTERNAL_BASE; | ||
91 | u32 mask; | 92 | u32 mask; |
92 | 93 | ||
93 | irq -= IRQ_INTERNAL_BASE; | ||
94 | mask = bcm_perf_readl(PERF_IRQMASK_REG); | 94 | mask = bcm_perf_readl(PERF_IRQMASK_REG); |
95 | mask |= (1 << irq); | 95 | mask |= (1 << irq); |
96 | bcm_perf_writel(mask, PERF_IRQMASK_REG); | 96 | bcm_perf_writel(mask, PERF_IRQMASK_REG); |
97 | } | 97 | } |
98 | 98 | ||
99 | static unsigned int bcm63xx_internal_irq_startup(unsigned int irq) | ||
100 | { | ||
101 | bcm63xx_internal_irq_unmask(irq); | ||
102 | return 0; | ||
103 | } | ||
104 | |||
105 | /* | 99 | /* |
106 | * external IRQs operations: mask/unmask and clear on PERF external | 100 | * external IRQs operations: mask/unmask and clear on PERF external |
107 | * irq control register. | 101 | * irq control register. |
108 | */ | 102 | */ |
109 | static void bcm63xx_external_irq_mask(unsigned int irq) | 103 | static void bcm63xx_external_irq_mask(struct irq_data *d) |
110 | { | 104 | { |
105 | unsigned int irq = d->irq - IRQ_EXT_BASE; | ||
111 | u32 reg; | 106 | u32 reg; |
112 | 107 | ||
113 | irq -= IRQ_EXT_BASE; | ||
114 | reg = bcm_perf_readl(PERF_EXTIRQ_CFG_REG); | 108 | reg = bcm_perf_readl(PERF_EXTIRQ_CFG_REG); |
115 | reg &= ~EXTIRQ_CFG_MASK(irq); | 109 | reg &= ~EXTIRQ_CFG_MASK(irq); |
116 | bcm_perf_writel(reg, PERF_EXTIRQ_CFG_REG); | 110 | bcm_perf_writel(reg, PERF_EXTIRQ_CFG_REG); |
117 | } | 111 | } |
118 | 112 | ||
119 | static void bcm63xx_external_irq_unmask(unsigned int irq) | 113 | static void bcm63xx_external_irq_unmask(struct irq_data *d) |
120 | { | 114 | { |
115 | unsigned int irq = d->irq - IRQ_EXT_BASE; | ||
121 | u32 reg; | 116 | u32 reg; |
122 | 117 | ||
123 | irq -= IRQ_EXT_BASE; | ||
124 | reg = bcm_perf_readl(PERF_EXTIRQ_CFG_REG); | 118 | reg = bcm_perf_readl(PERF_EXTIRQ_CFG_REG); |
125 | reg |= EXTIRQ_CFG_MASK(irq); | 119 | reg |= EXTIRQ_CFG_MASK(irq); |
126 | bcm_perf_writel(reg, PERF_EXTIRQ_CFG_REG); | 120 | bcm_perf_writel(reg, PERF_EXTIRQ_CFG_REG); |
127 | } | 121 | } |
128 | 122 | ||
129 | static void bcm63xx_external_irq_clear(unsigned int irq) | 123 | static void bcm63xx_external_irq_clear(struct irq_data *d) |
130 | { | 124 | { |
125 | unsigned int irq = d->irq - IRQ_EXT_BASE; | ||
131 | u32 reg; | 126 | u32 reg; |
132 | 127 | ||
133 | irq -= IRQ_EXT_BASE; | ||
134 | reg = bcm_perf_readl(PERF_EXTIRQ_CFG_REG); | 128 | reg = bcm_perf_readl(PERF_EXTIRQ_CFG_REG); |
135 | reg |= EXTIRQ_CFG_CLEAR(irq); | 129 | reg |= EXTIRQ_CFG_CLEAR(irq); |
136 | bcm_perf_writel(reg, PERF_EXTIRQ_CFG_REG); | 130 | bcm_perf_writel(reg, PERF_EXTIRQ_CFG_REG); |
137 | } | 131 | } |
138 | 132 | ||
139 | static unsigned int bcm63xx_external_irq_startup(unsigned int irq) | 133 | static unsigned int bcm63xx_external_irq_startup(struct irq_data *d) |
140 | { | 134 | { |
141 | set_c0_status(0x100 << (irq - IRQ_MIPS_BASE)); | 135 | set_c0_status(0x100 << (d->irq - IRQ_MIPS_BASE)); |
142 | irq_enable_hazard(); | 136 | irq_enable_hazard(); |
143 | bcm63xx_external_irq_unmask(irq); | 137 | bcm63xx_external_irq_unmask(d); |
144 | return 0; | 138 | return 0; |
145 | } | 139 | } |
146 | 140 | ||
147 | static void bcm63xx_external_irq_shutdown(unsigned int irq) | 141 | static void bcm63xx_external_irq_shutdown(struct irq_data *d) |
148 | { | 142 | { |
149 | bcm63xx_external_irq_mask(irq); | 143 | bcm63xx_external_irq_mask(d); |
150 | clear_c0_status(0x100 << (irq - IRQ_MIPS_BASE)); | 144 | clear_c0_status(0x100 << (d->irq - IRQ_MIPS_BASE)); |
151 | irq_disable_hazard(); | 145 | irq_disable_hazard(); |
152 | } | 146 | } |
153 | 147 | ||
154 | static int bcm63xx_external_irq_set_type(unsigned int irq, | 148 | static int bcm63xx_external_irq_set_type(struct irq_data *d, |
155 | unsigned int flow_type) | 149 | unsigned int flow_type) |
156 | { | 150 | { |
151 | unsigned int irq = d->irq - IRQ_EXT_BASE; | ||
157 | u32 reg; | 152 | u32 reg; |
158 | struct irq_desc *desc = irq_desc + irq; | ||
159 | |||
160 | irq -= IRQ_EXT_BASE; | ||
161 | 153 | ||
162 | flow_type &= IRQ_TYPE_SENSE_MASK; | 154 | flow_type &= IRQ_TYPE_SENSE_MASK; |
163 | 155 | ||
@@ -199,37 +191,32 @@ static int bcm63xx_external_irq_set_type(unsigned int irq, | |||
199 | } | 191 | } |
200 | bcm_perf_writel(reg, PERF_EXTIRQ_CFG_REG); | 192 | bcm_perf_writel(reg, PERF_EXTIRQ_CFG_REG); |
201 | 193 | ||
202 | if (flow_type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) { | 194 | irqd_set_trigger_type(d, flow_type); |
203 | desc->status |= IRQ_LEVEL; | 195 | if (flow_type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) |
204 | desc->handle_irq = handle_level_irq; | 196 | __irq_set_handler_locked(d->irq, handle_level_irq); |
205 | } else { | 197 | else |
206 | desc->handle_irq = handle_edge_irq; | 198 | __irq_set_handler_locked(d->irq, handle_edge_irq); |
207 | } | ||
208 | 199 | ||
209 | return 0; | 200 | return IRQ_SET_MASK_OK_NOCOPY; |
210 | } | 201 | } |
211 | 202 | ||
212 | static struct irq_chip bcm63xx_internal_irq_chip = { | 203 | static struct irq_chip bcm63xx_internal_irq_chip = { |
213 | .name = "bcm63xx_ipic", | 204 | .name = "bcm63xx_ipic", |
214 | .startup = bcm63xx_internal_irq_startup, | 205 | .irq_mask = bcm63xx_internal_irq_mask, |
215 | .shutdown = bcm63xx_internal_irq_mask, | 206 | .irq_unmask = bcm63xx_internal_irq_unmask, |
216 | |||
217 | .mask = bcm63xx_internal_irq_mask, | ||
218 | .mask_ack = bcm63xx_internal_irq_mask, | ||
219 | .unmask = bcm63xx_internal_irq_unmask, | ||
220 | }; | 207 | }; |
221 | 208 | ||
222 | static struct irq_chip bcm63xx_external_irq_chip = { | 209 | static struct irq_chip bcm63xx_external_irq_chip = { |
223 | .name = "bcm63xx_epic", | 210 | .name = "bcm63xx_epic", |
224 | .startup = bcm63xx_external_irq_startup, | 211 | .irq_startup = bcm63xx_external_irq_startup, |
225 | .shutdown = bcm63xx_external_irq_shutdown, | 212 | .irq_shutdown = bcm63xx_external_irq_shutdown, |
226 | 213 | ||
227 | .ack = bcm63xx_external_irq_clear, | 214 | .irq_ack = bcm63xx_external_irq_clear, |
228 | 215 | ||
229 | .mask = bcm63xx_external_irq_mask, | 216 | .irq_mask = bcm63xx_external_irq_mask, |
230 | .unmask = bcm63xx_external_irq_unmask, | 217 | .irq_unmask = bcm63xx_external_irq_unmask, |
231 | 218 | ||
232 | .set_type = bcm63xx_external_irq_set_type, | 219 | .irq_set_type = bcm63xx_external_irq_set_type, |
233 | }; | 220 | }; |
234 | 221 | ||
235 | static struct irqaction cpu_ip2_cascade_action = { | 222 | static struct irqaction cpu_ip2_cascade_action = { |