diff options
author | Atsushi Nemoto <anemo@mba.ocn.ne.jp> | 2006-02-15 04:25:48 -0500 |
---|---|---|
committer | Ralf Baechle <ralf@linux-mips.org> | 2006-03-21 08:27:45 -0500 |
commit | 37caa934af02bc01d0e1366a49e1c89360fa0f29 (patch) | |
tree | 96f0a41a3edbd0404358a92e5af5c1739ce311ac /arch/mips | |
parent | bbad8123f3a40a7b262e8e52d0bc10da67d719bb (diff) |
[MIPS] sc-rm7k.c cleanup
Use blast_scache_range, blast_inv_scache_range for rm7k scache routine.
Output code should be logically same.
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips')
-rw-r--r-- | arch/mips/mm/sc-rm7k.c | 25 |
1 files changed, 9 insertions, 16 deletions
diff --git a/arch/mips/mm/sc-rm7k.c b/arch/mips/mm/sc-rm7k.c index 9e8ff8badb19..3b6cc9ba1b05 100644 --- a/arch/mips/mm/sc-rm7k.c +++ b/arch/mips/mm/sc-rm7k.c | |||
@@ -9,6 +9,7 @@ | |||
9 | #include <linux/init.h> | 9 | #include <linux/init.h> |
10 | #include <linux/kernel.h> | 10 | #include <linux/kernel.h> |
11 | #include <linux/mm.h> | 11 | #include <linux/mm.h> |
12 | #include <linux/bitops.h> | ||
12 | 13 | ||
13 | #include <asm/addrspace.h> | 14 | #include <asm/addrspace.h> |
14 | #include <asm/bcache.h> | 15 | #include <asm/bcache.h> |
@@ -43,14 +44,7 @@ static void rm7k_sc_wback_inv(unsigned long addr, unsigned long size) | |||
43 | /* Catch bad driver code */ | 44 | /* Catch bad driver code */ |
44 | BUG_ON(size == 0); | 45 | BUG_ON(size == 0); |
45 | 46 | ||
46 | a = addr & ~(sc_lsize - 1); | 47 | blast_scache_range(addr, addr + size); |
47 | end = (addr + size - 1) & ~(sc_lsize - 1); | ||
48 | while (1) { | ||
49 | flush_scache_line(a); /* Hit_Writeback_Inv_SD */ | ||
50 | if (a == end) | ||
51 | break; | ||
52 | a += sc_lsize; | ||
53 | } | ||
54 | 48 | ||
55 | if (!rm7k_tcache_enabled) | 49 | if (!rm7k_tcache_enabled) |
56 | return; | 50 | return; |
@@ -74,14 +68,7 @@ static void rm7k_sc_inv(unsigned long addr, unsigned long size) | |||
74 | /* Catch bad driver code */ | 68 | /* Catch bad driver code */ |
75 | BUG_ON(size == 0); | 69 | BUG_ON(size == 0); |
76 | 70 | ||
77 | a = addr & ~(sc_lsize - 1); | 71 | blast_inv_scache_range(addr, addr + size); |
78 | end = (addr + size - 1) & ~(sc_lsize - 1); | ||
79 | while (1) { | ||
80 | invalidate_scache_line(a); /* Hit_Invalidate_SD */ | ||
81 | if (a == end) | ||
82 | break; | ||
83 | a += sc_lsize; | ||
84 | } | ||
85 | 72 | ||
86 | if (!rm7k_tcache_enabled) | 73 | if (!rm7k_tcache_enabled) |
87 | return; | 74 | return; |
@@ -143,11 +130,17 @@ struct bcache_ops rm7k_sc_ops = { | |||
143 | 130 | ||
144 | void __init rm7k_sc_init(void) | 131 | void __init rm7k_sc_init(void) |
145 | { | 132 | { |
133 | struct cpuinfo_mips *c = ¤t_cpu_data; | ||
146 | unsigned int config = read_c0_config(); | 134 | unsigned int config = read_c0_config(); |
147 | 135 | ||
148 | if ((config & RM7K_CONF_SC)) | 136 | if ((config & RM7K_CONF_SC)) |
149 | return; | 137 | return; |
150 | 138 | ||
139 | c->scache.linesz = sc_lsize; | ||
140 | c->scache.ways = 4; | ||
141 | c->scache.waybit= ffs(scache_size / c->scache.ways) - 1; | ||
142 | c->scache.waysize = scache_size / c->scache.ways; | ||
143 | c->scache.sets = scache_size / (c->scache.linesz * c->scache.ways); | ||
151 | printk(KERN_INFO "Secondary cache size %dK, linesize %d bytes.\n", | 144 | printk(KERN_INFO "Secondary cache size %dK, linesize %d bytes.\n", |
152 | (scache_size >> 10), sc_lsize); | 145 | (scache_size >> 10), sc_lsize); |
153 | 146 | ||